Display substrate, display device and control method

Abstract

The present application discloses a display substrate, a display device and a control method, wherein the display substrate is used for a display device, the display device includes an optical element, the display substrate is arranged on the optical element, the display substrate includes a base substrate, sub-pixels and a light-emitting driving circuit, the base substrate includes a display area and a peripheral area, the driving circuit layer is located on the base substrate, the sub-pixels are located in the display area, the light-emitting driving circuit is located in the peripheral area, and the light-emitting driving circuit is configured to provide a light-emitting control signal to each row of sub-pixels. In a scanning cycle, the duration of the light-emitting control signal provided by the light-emitting driving circuit to the sub-pixels located from the first preset row to the second preset row is greater than the scanning duration from the first preset row to the second preset row. The present application sets the display substrate on the optical element, and avoids interfering with the sampling of the optical element in the process of scanning the sub-pixels from the first preset row to the second preset row, thereby ensuring the normal realization of the function of the optical element and realizing full-screen display at the same time.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display device, and a control method for the display device. Background Art

[0002] Currently, most of the products on the market use technologies such as screen punching or screen notching to install optical components such as cameras and infrared sensors under the screen punching or notching to achieve the corresponding functions. However, this will affect the appearance of the screen and the proportion of the full-screen display. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application provides a display substrate, a display device and a control method of the display device.

[0004] The display substrate provided in the embodiment of the present application is used for a display device, the display device includes an optical element, the display substrate is arranged on the optical element, and the display substrate includes:

[0005] A substrate, comprising a display area and a peripheral area at least located on one side of the display area;

[0006] A plurality of sub-pixels arranged in an array on the display area;

[0007] A light-emitting driving circuit, located in the peripheral area, and configured to provide a light-emitting control signal to each row of the sub-pixels;

[0008] In a scanning cycle, the duration of the light control signal provided by the light driving circuit to the sub-pixels located from the first preset row to the second preset row is a preset duration, and the preset duration is greater than the scanning duration from the first preset row to the second preset row.

[0009] In some embodiments, the display substrate further comprises:

[0010] A gate driving circuit, located in the peripheral area, configured to sequentially provide a gate signal to each row of the sub-pixels;

[0011] The driving chip is located in the peripheral area and is configured to sequentially provide data signals to each column of the sub-pixels.

[0012] In some embodiments, the display substrate further comprises a timer located in the peripheral area, and the timer is respectively connected to the gate driving circuit, the light emitting driving circuit and the driving chip;

[0013] The timer is configured to provide a first driving signal to the gate driving circuit so that the gate driving circuit sequentially provides a gate signal to each row of the sub-pixels; or / and

[0014] The timer is configured to provide a second driving signal to the light emitting driving circuit so that the light emitting driving circuit sequentially provides a light emitting control signal to each row of the sub-pixels; or / and

[0015] The timer is configured to provide a third driving signal to the driving chip so that the driving chip provides a data signal to each column of the sub-pixels in sequence.

[0016] In some embodiments, the display substrate further comprises:

[0017] A plurality of gate signal lines, each of which is connected to a row of sub-pixels and to a gate driving circuit;

[0018] A plurality of light-emitting control lines, each of which is connected to a row of sub-pixels and to a light-emitting driving circuit;

[0019] A plurality of data lines, each of which is connected to a column of the sub-pixels and to a driving chip.

[0020] In some embodiments, the display substrate further includes a power line, the gate signal line includes a first gate signal line, the sub-pixel includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit includes:

[0021] a first light-emitting control module, connected to the power line, the light-emitting control line and the first node respectively, and used to write the driving voltage of the power line into the first node according to the light-emitting control signal of the light-emitting control line;

[0022] a driving module, connected to the first node, the data line, the first gate signal line, the second node and the third node respectively, for writing the data signal of the data line into the second node according to the gate signal provided by the first gate signal line, and generating a driving signal from the driving voltage of the first node according to the voltage of the second node to write into the third node;

[0023] The second light-emitting control module is respectively connected to the light-emitting control line, the third node and the light-emitting element, and is used to transmit the driving signal of the third node to the light-emitting element according to the light-emitting control signal of the light-emitting control line.

[0024] In some embodiments, the first light control module includes:

[0025] A first transistor, a source and a drain of the first transistor are respectively connected to the power line and the first node, and a gate of the first transistor is connected to the light emitting control line.

[0026] In some embodiments, the driving module includes:

[0027] a second transistor, wherein a source and a drain of the second transistor are respectively connected to the data line and the first node, and a gate of the second transistor is connected to the first gate signal line;

[0028] a third transistor, wherein a source and a drain of the third transistor are respectively connected to the first node and the third node, and a gate of the third transistor is connected to the second node;

[0029] A fourth transistor, wherein a source and a drain of the fourth transistor are respectively connected to the second node and the third node, and a gate of the fourth transistor is connected to the first gate signal line.

[0030] In some embodiments, the second light control module includes:

[0031] A fifth transistor, wherein a source and a drain of the fifth transistor are respectively connected to the third node and the light emitting element, and a gate is connected to the light emitting control line.

[0032] In some embodiments, the display substrate further includes an initialization line, the gate signal line includes a second gate signal line, the second gate signal line is located in a row with the first gate signal line, and the pixel driving circuit further includes a reset module, the reset module includes:

[0033] a sixth transistor, wherein a source and a drain of the sixth transistor are respectively connected to the sub-pixel and the initialization line, and a gate of the sixth transistor is connected to the second gate signal line, and is used for writing a reference voltage of the initialization line into the sub-pixel according to a second gate signal of the second gate signal line;

[0034] A seventh transistor, wherein the source and the drain of the seventh transistor are respectively connected to the second node and the initialization line, and the gate is connected to the second gate signal line, and is used to write the reference voltage of the initialization line into the second node according to the second gate signal of the second gate signal line.

[0035] In some embodiments, the pixel driving circuit further includes:

[0036] The charge storage module includes energy storage capacitors, which are respectively connected to the power line and the second node.

[0037] In some embodiments, the display substrate also includes a driving circuit layer and a light-emitting layer stacked sequentially on the base substrate, the pixel driving circuit is formed in the driving circuit layer, the light-emitting element is formed in the light-emitting layer, and the light-emitting layer includes an anode layer, and the anode layer is a transparent electrode layer.

[0038] In some embodiments, the driving circuit layer is a buffer layer, an active layer, a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a passivation layer, a conductive metal layer and a planarization layer stacked in sequence on the base substrate.

[0039] An embodiment of the present application further provides a display device, comprising the display substrate.

[0040] In some embodiments, the display device includes an optical element, and the optical element is located on the side of the base substrate away from the driving circuit layer.

[0041] The present application also provides a control method for the display device, the control method comprising:

[0042] Acquire a target sub-pixel overlapping with the position of the optical element;

[0043] Determine, according to the target sub-pixel, a pixel row where the target sub-pixel is located;

[0044] In each scanning cycle, when the pixel row is scanned along the scanning sequence, the driving extension time is waited for and then the scanning is performed sequentially.

[0045] In the display substrate and display device of the embodiments of the present application, by setting the duration of the light-emitting control signal provided by the light-emitting driving circuit to the sub-pixels located between the first preset row and the second preset row to be greater than the scanning duration from the first preset row to the second preset row, external light can pass through the display substrate into the optical element, thereby ensuring the normal function of the optical element and realizing full-screen display, thereby improving product competitiveness.

[0046] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0048] Figure 1 It is a module schematic diagram of a display substrate according to an embodiment of the present application.

[0049] Figure 2It is a schematic plan view of a display device according to an embodiment of the present application.

[0050] Figure 3 It is a schematic diagram of the signal timing of the display substrate according to the embodiment of the present application.

[0051] Figure 4 Schematic diagram of a pixel driving circuit according to an embodiment of the present application.

[0052] Figure 5 It is a driving timing diagram of the pixel driving circuit according to the embodiment of the present application.

[0053] Figure 6 It is a module schematic diagram of a display device according to an embodiment of the present application.

[0054] Figure 7 It is a schematic cross-sectional view of a display substrate according to an embodiment of the present application.

[0055] Main component reference numbers

[0056] 10 display substrate, 12 sub-pixels;

[0057] 110 substrate, 111 display area, 112 peripheral area, 1121 first peripheral area, 1122 second peripheral area, 1123 third peripheral area;

[0058] 120 pixel circuit layer, 121 pixel driving circuit, 1211 first light emitting control module, T1 first transistor, 1212 driving module, T2 second transistor, T3 third transistor, T4 fourth transistor, 1213 second light emitting control module, T5 fifth transistor, 1214 reset module, T6 sixth transistor, T7 seventh transistor, 1215 charge storage module, C1 storage capacitor;

[0059] S gate signal line, D data line, EM light emitting control line, power line Vdd, initialization line Vin;

[0060] Buffer buffer layer, Active active layer, GI1 first dielectric layer, Gate1 first gate layer, GI2 second dielectric layer, Gate2 second gate layer, ILD passivation layer, PLN planarization layer, SD metal line;

[0061] 130 light emitting layer, 131 sub-pixel, Anode layer;

[0062] 140 gate driving circuit, 150 light emitting driving circuit, 160 driving chip, 170 timer;

[0063] 20 optical elements, 100 display devices. DETAILED DESCRIPTION

[0064] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0065] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0066] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0067] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0068] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0069] In recent years, the self-luminous display technologies of active-matrix organic light-emitting diodes (AMOLED) and quantum dot light-emitting diodes (QLED) have developed rapidly, especially AMOLED display technology. Compared with the commonly used liquid crystal display technology, it has begun to show advantages such as wide color gamut, fast response speed, wide viewing angle, and foldability, which has attracted many manufacturers to invest a lot of money in its research and development. At present, a large number of display products on the market have adopted AMOLED technology, and it is likely to replace LCD and become the next generation of mainstream display.

[0070] AMOLED is gradually developing towards full screen and function integration. At present, under-screen fingerprint recognition has been mass-produced and used in products of major mobile phone manufacturers. However, under-screen cameras and under-screen infrared sensors are still in the technical development stage. Due to the influence of screen transmittance, they are not yet ready for mass production. Currently, most of the products on the market use screen punching or screen groove digging technologies to install the camera and infrared sensor under the screen punching and groove digging to achieve the corresponding functions. However, this will affect the appearance of the screen and the proportion of the full-screen display.

[0071] In view of this, please combine Figure 1 and Figure 3 In one embodiment of the present application, a display substrate 10 is provided for a display device 100. The display device 100 includes an optical element 20. The display substrate 10 is disposed on the optical element 20. The display substrate 10 includes a base substrate 110, a plurality of sub-pixels 12 and a light-emitting driving circuit 150. The base substrate 110 includes a display area 111 and a peripheral area 112 located at least on one side of the display area 111.

[0072] A plurality of sub-pixels 12 are arranged in an array in the display area 111 to form a pixel array. The light emitting driving circuit 150 is located in the peripheral area 112 , and the light emitting driving circuit 150 is configured to provide a light emitting control signal to each row of sub-pixels 12 .

[0073] In a scanning cycle, the duration of the light-emitting control signal provided by the light-emitting driving circuit 150 to the sub-pixels 12 located from the first preset row to the second preset row is the preset duration, which is greater than the scanning duration from the first preset row to the second preset row.

[0074] The embodiment of the present application provides a display device 100, which includes a display substrate 10 provided in the embodiment of the present application. The display device 100 in the embodiment of the present application can display images through the display substrate 10 provided in the embodiment of the present application. The display device 100 in the embodiment of the present application also includes an optical element 20 disposed at the bottom of the display substrate 10, and external light can pass through the display substrate 10 provided in the embodiment of the present application and enter the optical element 20, so that the function of the optical element 20 is realized normally.

[0075] In the display substrate 10 and the display device 100 in the embodiment of the present application, by setting the display substrate on the optical element 20, within one scanning cycle, the duration of the light emitting control signal provided by the light emitting driving circuit 150 to the sub-pixels 12 located from the first preset row to the second preset row is greater than the scanning duration from the first preset row to the second preset row, so that in the process of scanning the sub-pixels 12 from the first preset row to the second preset row, interference with the sampling of the optical element 20 is avoided, thereby ensuring the normal function of the optical element 20, and at the same time achieving full-screen display, thereby improving product competitiveness.

[0076] Please further combine Figures 1 to 7 , the specific structures of the display substrate 10 and the display device 100 are described below.

[0077] In some embodiments, the display device 100 can be a display device 100 that can display images, such as a smart phone, a tablet, a computer, a smart bracelet, a virtual reality device, a personal data terminal, a laptop computer, etc., but is not limited thereto. For example, in this embodiment, the display device 100 can be illustrated as a smart phone.

[0078] The optical element 20 may include, but is not limited to, a camera, an infrared sensor, an infrared rangefinder, and an optical fingerprint reader. The optical element 20 is located below the display substrate 10 , and external light can pass through the display substrate 10 and be sampled by the optical element 200 .

[0079] The display substrate 10 may be an AMOLED display substrate 10. The display substrate 10 includes a base substrate 110, a driving circuit layer 120, and a light emitting layer 130. The base substrate 110, the driving circuit layer 120, and the light emitting layer 130 are stacked in sequence, and the driving circuit layer 120 is located on the side of the base substrate 110 away from the optical element 20. The display substrate 10 is, for example, a motherboard after the preparation of the pixel array is completed in the preparation process and before the cutting process is performed. After the display substrate 10 is subjected to the test process, the circuit units, connecting wires, etc. used in the test stage are cut off to prepare a display panel for the final product.

[0080] The base substrate 110 includes a display area 111 and a peripheral area 112. The peripheral area 112 is located on at least one side of the display area 111. For example, the peripheral area 112 surrounds the display area 111 and occupies the largest area (the area where the most circuit units, connecting lines, etc. are arranged) under the display area 111. The optical element 20 can be located at any position of the display area 111.

[0081] A pixel array is formed on the display area 111, and the pixel array includes a plurality of sub-pixels 12. For example, the plurality of sub-pixels 12 are arranged in an array, including a plurality of rows and a plurality of columns. The number of rows and columns may be m*n, and the specific size of m and n is determined according to the actual needs of the product and is not limited.

[0082] Please combine Figure 2 In some embodiments, the driving circuit layer 120 is further formed with a plurality of gate signal lines S, light emitting control lines EM and data lines D, the plurality of gate signal lines S and the plurality of light emitting control lines EM are arranged in sequence along a first direction, each gate signal line S and light emitting control line EM is connected to a row of sub-pixels 12, the plurality of data lines D are arranged in sequence along a second direction, each data line D is connected to a column of sub-pixels 12, the gate signal line S is configured to transmit a gate signal to the sub-pixel 12, the light emitting control line EM is configured to transmit a light emitting control signal to the sub-pixel 12, and the data line D is configured to transmit a data signal to the sub-pixel 12.

[0083] Specifically, a plurality of gate signal lines S extend in the horizontal direction and are configured to provide gate signals to the sub-pixels 12 to control and drive the plurality of sub-pixels 12 to display the image. The plurality of gate signal lines S are connected to the sub-pixels 12, for example, each of the gate signal lines S is connected to a sub-pixel 12 corresponding to a sub-pixel 12 located in the same row.

[0084] The plurality of light-emitting control lines EM extend in the horizontal direction and are configured to provide light-emitting control signals to the sub-pixels 12, so as to control and drive the plurality of sub-pixels 12 to display the picture. The plurality of light-emitting control lines EM are connected to the sub-pixels 12, for example, each of the light-emitting control lines EM is connected to the sub-pixels 12 corresponding to the sub-pixels 12 located in the same row.

[0085] The plurality of data lines D are located in the display area 111 and extend in the vertical direction. The plurality of data lines D are configured to be electrically connected to the sub-pixels 12 corresponding to the sub-pixels 12 in the plurality of columns, respectively, to provide data signals to the sub-pixels 12 corresponding to the sub-pixels 12 in the plurality of columns, respectively, to control and drive the plurality of sub-pixels 12 to display the picture. For example, each of the plurality of data lines D13 is connected to the sub-pixels 12 in the same column (for example, the column direction refers to the direction of the sub-pixels 12). Figure 2 The sub-pixel 12 corresponds to the sub-pixel 12 in the vertical direction).

[0086] Please combine Figure 1 In some embodiments, the display substrate 10 further includes a gate driving circuit 140, a light-emitting driving circuit 150, and a driving chip 160 located in the peripheral area 112. The gate driving circuit 140 is connected to the gate signal line S for providing a gate signal to the sub-pixel 12 through the gate signal line S. The light-emitting driving circuit 150 is connected to the light-emitting control line EM for providing a light-emitting control signal to the sub-pixel 12 through the light-emitting control line EM. The driving chip 160 is connected to the data line D for providing a data signal to the sub-pixel 12 through the data line D.

[0087] Specifically, the peripheral area 112 may include a first peripheral area 1121, a second peripheral area 1122 and a third peripheral area 1123 connected in sequence, wherein the second peripheral area 1122 may be adjacent to the bottom area of ​​the display area 111, and the first peripheral area 1121 and the third peripheral area 1123 are respectively located on both sides of the display area 111.

[0088] The gate driving circuit 140 may be located in the first peripheral area 1121 and connected to a plurality of gate signal lines S, and used to sequentially provide gate signals to each row of sub-pixels 12 through the plurality of gate signal lines S. The light-emitting driving circuit 150 may be located in the third peripheral area 1123 and connected to a plurality of light-emitting control lines EM, and used to sequentially provide light-emitting control signals to each row of sub-pixels 12 through the plurality of light-emitting control lines EM. The driving chip 160 may be located in the second peripheral area 1122 and connected to a plurality of data lines D, and used to sequentially provide data signals to each column of sub-pixels 12 through the plurality of data lines D.

[0089] In some embodiments, the display substrate 10 further includes a timer 170 (TimingController) located in the peripheral area 112, and the timer 170 is respectively connected to the gate driving circuit 140, the light-emitting driving circuit 150, and the driving chip 160. The timer 170 is configured to provide a first driving signal to the gate driving circuit 140 so that the gate driving circuit 140 sequentially provides a gate signal to each row of sub-pixels 12; and / or, the timer 170 is configured to provide a second driving signal to the light-emitting driving circuit 150 so that the light-emitting driving circuit 150 sequentially provides a light-emitting control signal to each row of sub-pixels 12; and / or, the timer 170 is configured to provide a third driving signal to the driving chip 160 so that the driving chip 160 sequentially provides a data signal to each column of sub-pixels 12.

[0090] Specifically, the timer 170 may be disposed in the second peripheral area 1122, and the timer 170 is used to control the output of the clock signal. The timer 170 may be respectively connected to the gate driving circuit 140, the light emitting driving circuit 150, and the driving chip 160. The timer 170 may provide the first driving signal, the second driving signal, and the third driving signal to the gate driving circuit 140, the light emitting driving circuit 150, and the driving chip 160, respectively, so as to control the gate driving circuit 140, the light emitting driving circuit 150, and the driving chip 160 to provide the corresponding control signal to the sub-pixel 12.

[0091] When the gate driving circuit 140 receives the first driving signal, it can sequentially provide gate signals to the sub-pixels 12 of the corresponding row through the plurality of gate signal lines S according to the first driving signal. When the light driving circuit 150 receives the second driving signal, it can sequentially provide light control signals to the sub-pixels 12 of the corresponding row through the plurality of light control lines EM according to the second driving signal. When the driving chip 160 receives the third driving signal, it can sequentially provide data signals to the sub-pixels 12 of the corresponding column through the plurality of data lines D according to the third driving signal.

[0092] In this way, the timer 170 can provide the first drive signal, the second drive signal and the third drive signal to the gate drive circuit 140, the light emitting drive circuit 150 and the drive chip 160 respectively, so as to control the sub-pixel 12 to emit light to perform the display function of the display area 111.

[0093] Please combine Figure 3 In some embodiments, within a scanning cycle, the duration of the light-emitting control signal provided by the light-emitting driving circuit 150 to the sub-pixels 12 located between the first preset row and the second preset row is a preset duration, and the preset duration is greater than the scanning duration from the first preset row to the second preset row.

[0094] It should be noted that the optical element 20 overlaps with at least part of the sub-pixels 12 in the first preset row to the second preset row. That is, the positions of the first preset row and the second preset row are related to the position of the optical element 20. For example, if the rows where the sub-pixels 12 and the optical element 20 overlap are in the 15th to 75th rows, the first preset row may be the 15th row, and the second preset row may be the 75th row.

[0095] It should also be noted that the duration of the light emitting control signal provided by the light emitting driving circuit 150 to the sub-pixels 12 located in the first preset row to the second preset row is the preset duration, which means that the duration of the light emitting control signal of each sub-pixel 12 in the first preset row to the second preset row is the preset duration.

[0096] Further, the duration of the light-emitting control signal provided by the light-emitting driving circuit 150 to the sub-pixels 12 located from the first preset row to the second preset row is not less than the sum of the scanning duration from the first preset row to the second preset row and the sampling duration of the optical element. For example, the duration of the light-emitting control signal provided by the light-emitting driving circuit 150 to the sub-pixels 12 located from the first preset row to the second preset row is equal to the scanning duration from the first preset row to the second preset row plus the sampling duration of the optical element.

[0097] The scanning time length of scanning from the first preset row to the second preset row refers to the time from the start time of the light-emitting driving circuit 150 providing the light-emitting control signal to the first preset row to the start time of providing the light-emitting control signal to the second preset row. For example, the start time of the light-emitting driving circuit 150 providing the light-emitting control signal to the first preset row is t0, the end time of providing the light-emitting control signal is t2, and the start time of the light-emitting driving circuit 150 providing the light-emitting control signal to the second preset row is t1, then the scanning time length of scanning from the first preset row to the second preset row is t1-t0, and the preset time length is t2-t0. Then the preset time length t2-t0 is greater than the scanning time length t1-t0 of scanning from the first preset row to the second preset row, and the sampling time length of the optical element is t1-t2.

[0098] It can be understood that the sub-pixel 12 will generate downward light to interfere with the optical element 20, and the sub-pixel 12 will emit light after receiving the light-emitting control signal. The sub-pixel 12 does not emit light during the process of receiving the light-emitting control signal. Therefore, the preset time length of the light-emitting control signal located from the first preset row to the second preset row is greater than the scanning time length from the first preset row to the second preset row. This can ensure that when the first preset row is scanned to the second preset row, the sub-pixels 12 in the first preset row and the second preset row do not emit light, thereby avoiding the sub-pixels 12 in the first preset row to the second preset row interfering with the optical element 20 and ensuring the normal sampling operation of the optical element 20.

[0099] Please combine Figure 4In some embodiments, the sub-pixel 12 includes a pixel driving circuit 121 and a light-emitting element 131, the pixel driving circuit 121 is connected to the light-emitting element 131, and is used to drive the light-emitting element 131 to emit light, the gate signal line S includes a first gate signal line Si, and the display substrate 10 also includes a power line Vdd, and the driving voltage can be a high level. The power line Vdd is connected to the pixel driving circuit 121 to provide a driving voltage to the pixel driving circuit 121.

[0100] The pixel driving circuit 121 includes a first light emitting control module 1211 , a driving module 1212 and a second light emitting control module 1213 .

[0101] The first light-emitting control module 1211 is respectively connected to the power line Vdd, the light-emitting control line EM and the first node N1, and is used to write the driving voltage of the power line Vdd into the first node N1 according to the light-emitting control signal of the light-emitting control line EM. The driving module 1212 is respectively connected to the first node N1, the data line D, the first gate signal line S, the second node N2 and the third node N3, and is used to write the data signal of the data line D into the second node N2 according to the gate signal provided by the first gate signal line S, and to generate a driving signal from the driving voltage of the first node N1 according to the voltage of the second node N2 to write into the third node N3. The second light-emitting control module 1213 is respectively connected to the light-emitting control line EM, the third node N3 and the light-emitting element 131, and is used to transmit the driving signal of the third node N3 to the light-emitting element 131 according to the light-emitting control signal of the light-emitting control line EM to drive the light-emitting element 131 to emit light.

[0102] It should be noted that, in this embodiment, the light-emitting control signal, the gate signal and the driving signal are low-level signals. That is, when the light-emitting control signal of the light-emitting control line EM is a low-level signal, the first light-emitting control module 1211 writes the driving voltage of the power line Vdd into the first node N1. When the gate signal provided by the first gate signal line S is a low-level signal, the driving module 1212 writes the data signal of the data line D into the second node N2. When the light-emitting control signal of the light-emitting control line EM is a low-level signal, the second light-emitting control module 1213 transmits the driving signal of the third node N3 to the light-emitting element 131 to drive the light-emitting element 131 to emit light.

[0103] In some embodiments, the first light-emitting control module 1211 includes a first transistor T1, a source and a drain of the first transistor T1 are respectively connected to the power line Vdd and the first node N1, and a gate of the first transistor T1 is connected to the light-emitting control line EM, for writing the driving voltage of the power line Vdd into the first node N1 according to the light-emitting control signal provided by the light-emitting control line EM.

[0104] It should be noted that in the embodiments of the present application, the transistors can be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. The transistors in this embodiment are described by taking P-type transistors as an example, that is, in the embodiments of the present application, when the gate of the transistor receives a low-level signal, the source and drain of the transistor are turned on, and when the transistor receives a high-level signal, the source and drain of the transistor are disconnected.

[0105] It can be understood that based on the description and teaching of the implementation method of P-type transistors in the present disclosure, ordinary technicians in the field can easily think of the implementation method of the present disclosure using N-type transistors without making any creative work. Therefore, these implementation methods are also within the scope of protection of the present disclosure.

[0106] In some embodiments, the driving module 1212 includes a second transistor T2, a third transistor T3, and a fourth transistor T4, wherein the source and drain of the second transistor T2 are respectively connected to the data line D and the first node N1, and the gate is connected to the first gate signal line S. The source and drain of the third transistor T3 are respectively connected to the first node N1 and the third node N3, and the gate of the third transistor T3 is connected to the second node N2; the source and drain of the fourth transistor T4 are respectively connected to the second node N2 and the third node N3, and the gate is connected to the first gate signal line S.

[0107] In some embodiments, the second light emitting control module 1213 includes a fifth transistor T5, a source and a drain of the fifth transistor T5 are respectively connected to the third node N3 and the light emitting element 131, and a gate of the fifth transistor T5 is connected to the light emitting control line EM.

[0108] In some embodiments, the display substrate 10 further includes an initialization line Vin connected to the pixel driving circuit 121, and the initialization line Vin is used to provide a reference voltage to the pixel driving circuit 121. The gate signal line S includes a second gate signal line S, and the second gate signal line S is located on a row above the first gate signal line S. The pixel driving circuit 121 further includes a reset module 1214, and the reset module 1214 includes a sixth transistor T6 and a seventh transistor T7.

[0109] The source and drain of the sixth transistor T6 are respectively connected to the light emitting element 131 and the initialization line Vin. The gate of the sixth transistor T6 is connected to the second gate signal line S for writing the reference voltage of the initialization line Vin into the light emitting element 131 according to the second gate signal of the second gate signal line S.

[0110] The source and drain of the seventh transistor T7 are respectively connected to the second node N2 and the initialization line Vin. The gate of the seventh transistor T7 is connected to the second gate signal line S for writing the reference voltage of the initialization line Vin into the second node N2 according to the second gate signal of the second gate signal line S.

[0111] In some embodiments, the pixel driving circuit 121 further includes a charge storage module 1215 , and the charge storage module 1215 includes a storage capacitor C1 , which is respectively connected to the power line Vdd and the second node N2 .

[0112] The pixel driving circuit 121 of the present application drives the light emitting element 131 to display a frame of picture, which includes a reset phase t1, a compensation phase t2, and a light emitting phase t3. Figure 4 The pixel driving circuit 121 and Figure 5 The driving timing sequence shown is taken as an example to introduce the working process of the pixel driving circuit 121.

[0113] In the reset stage t1 , the light emitting control signal and the second gate signal are high level signals, and the first gate signal is a low level signal.

[0114] At this time, the sixth transistor T6 and the seventh transistor T7 are turned on, and the reference voltage of the initialization line Vin is written into the anode of the light-emitting element 131 and the second node N2 through the sixth transistor T6 and the seventh transistor T7 respectively. The second node N2 and the anode voltage of the light-emitting element 131 are the reference voltages. The third transistor T3 is turned on, and the capacitor of the light-emitting element 131 can be discharged, thereby avoiding insufficient discharge of the capacitor of the light-emitting element 131, resulting in the brightness of the light-emitting element 131 being too bright, affecting the yield at low grayscale and the contrast of the display substrate 10.

[0115] In the compensation stage t2, the light emitting control signal and the first gate signal are high-level signals, and the second gate signal is a low-level signal.

[0116] At this time, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the other transistors are turned off, the data signal of the data line D is written into the second node N2, and the potential of the second node N2 increases. When the potential of the second node N2 is Vdata+Vth, the third transistor T3 is turned off, and the charging is completed.

[0117] In the light emitting stage t3 , the first gate signal and the second gate signal are high level signals, and the light emitting control signal is a low level signal.

[0118] At this time, the third transistor T3, the first transistor T1 and the fifth transistor T5 are turned on, and the remaining transistors are turned off. The driving voltage of the power line Vdd is written from the first transistor T1 to the first node N1. The third transistor T3 generates a driving signal from the potential of the first node N1 according to the potential of the second node N2 and writes it into the third node N3, which is then input from the third node N3 to the light-emitting element 131 to drive the light-emitting element 131 to emit light.

[0119] Please combine Figure 6 In some embodiments, the display substrate 100 further includes a driving circuit layer 120 and a light-emitting layer 130 sequentially stacked on the base substrate 110, a pixel driving circuit 121 is formed on the driving circuit layer 120, a light-emitting element 131 is formed on the light-emitting layer 130, and the light-emitting layer 130 includes an anode layer Anode, and the anode layer Anode can be either a transparent electrode layer or an opaque electrode layer. In the present application, the anode layer Anode can be explained by taking a transparent electrode layer as an example. It can be understood that when the anode layer Anode is a transparent layer, the transmittance of the display substrate 10 can be increased, thereby reducing the sampling effect of the display substrate 10 on the optical element 20, thereby improving the effect of the optical element.

[0120] The light-emitting layer 130 includes an anode layer Anode, an electroluminescent layer and a cathode layer, wherein the anode layer Anode, the electroluminescent layer and the cathode layer are sequentially stacked on the driving circuit layer 120. The anode layer Anode is a transparent electrode layer, that is, light can pass through the anode layer Anode. The anode layer Anode can be made of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0121] Please combine Figure 7 In some embodiments, the driving circuit layer 120 includes a buffer layer Buffer, an active layer Active, a first dielectric layer GI1, a first gate layer Gate1, a second dielectric layer GI2, a second gate layer Gate2, a passivation layer ILD, and a planarization layer PLN stacked in sequence on the base substrate 110.

[0122] Specifically, the substrate 110 can be made of glass or PI, etc., and the specific material is not limited. The buffer layer Buffer is composed of a film layer such as SiN or SiO, which plays a flattening role and blocks the diffusion of impurity components on the substrate 110 from affecting the characteristics of the transistor. The active layer Active can be made of materials such as A-Si, LTPS, and oxide semiconductors, and is used to form the channel of the transistor in the pixel driving circuit 121, and the two sides form the source and drain of the transistor respectively. This application takes LTPS as an example.

[0123] The first dielectric layer GI1 can be composed of SiN or SiO. The first gate layer Gate1 is the gate of the transistor in the pixel driving circuit 121, generally composed of metals such as molybdenum, and the electrode plate of the capacitor. The first dielectric layer GI1 is the dielectric layer of the capacitor, composed of SiN or SiO. The second gate layer Gate2 is another electrode plate of the capacitor, generally composed of metals such as molybdenum. The passivation layer ILD is used to protect the transistor and is composed of SiN or SiO. The planarization layer PLN is generally a PI-type material.

[0124] In addition, in some embodiments, the driving circuit layer 120 further includes a metal line SD of the transistor. The metal line SD is generally composed of metals such as Ti / Al / Ti, and is connected to the source and drain electrodes of the transistor.

[0125] Furthermore, the anode layer Anode may be connected to a metal line SD of the transistor through a via formed on the planarization layer PLN, and the metal line SD is connected to a source electrode and a drain electrode of the transistor through the via.

[0126] In some embodiments, the light emitting layer may further include a pixel definition layer PDL and a support layer PS. The pixel definition layer PDL and the support layer PS are generally PI-based materials.

[0127] In some embodiments, the display substrate may further include a module unit stacked on the light-emitting layer, and the module unit may include but is not limited to functional layers such as TSP, Polarizer, OCA, and Cover Glass.

[0128] The embodiment of the present application further provides a control method, which is used for the above-mentioned display device, and the control method includes:

[0129] 01, obtain the target sub-pixel overlapping with the optical element position;

[0130] 02, determining the pixel row where the target sub-pixel is located according to the target sub-pixel;

[0131] 03. In each scanning cycle, when scanning to the pixel row along the scanning sequence, wait for the drive to extend the time before scanning in sequence.

[0132] In this way, it is possible to prevent the light emitted by the sub-pixel overlapping the optical element from interfering with the sampling of the optical element.

[0133] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0134] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display substrate for a display device, characterized in that: The display device comprises an optical element, the display substrate is arranged on the optical element, and the display substrate comprises: A substrate, comprising a display area and a peripheral area at least located on one side of the display area; A plurality of sub-pixels arranged in an array on the display area; A light-emitting driving circuit, located in the peripheral area, and configured to provide a light-emitting control signal to each row of the sub-pixels; In a scanning cycle, the duration of the light-emitting control signal provided by the light-emitting driving circuit to the sub-pixels located from the first preset row to the second preset row is a preset duration, the optical element overlaps with at least part of the sub-pixels from the first preset row to the second preset row, and the sub-pixels do not emit light during the process of receiving the light-emitting control signal, the preset duration is greater than the scanning duration from the first preset row to the second preset row, and the preset duration is not less than the sum of the scanning duration from the first preset row to the second preset row and the sampling duration of the optical element, and the scanning duration from the first preset row to the second preset row is the starting moment when the light-emitting driving circuit provides the light-emitting control signal to the first preset row to the starting moment when the light-emitting control signal is provided to the second preset row.

2. The display substrate according to claim 1, characterized in that: The display substrate further comprises: A gate driving circuit, located in the peripheral area, configured to sequentially provide a gate signal to each row of the sub-pixels; The driving chip is located in the peripheral area and is configured to sequentially provide data signals to each column of the sub-pixels.

3. The display substrate according to claim 2, characterized in that: The display substrate further comprises a timer located in the peripheral area, and the timer is respectively connected to the gate driving circuit, the light emitting driving circuit and the driving chip; The timer is configured to provide a first driving signal to the gate driving circuit so that the gate driving circuit sequentially provides a gate signal to each row of the sub-pixels; or / and The timer is configured to provide a second driving signal to the light emitting driving circuit so that the light emitting driving circuit sequentially provides a light emitting control signal to each row of the sub-pixels; or / and The timer is configured to provide a third driving signal to the driving chip so that the driving chip provides a data signal to each column of the sub-pixels in sequence.

4. The display substrate according to claim 2, characterized in that: The display substrate further comprises: A plurality of gate signal lines, each of which is connected to a row of sub-pixels and to a gate driving circuit; A plurality of light-emitting control lines, each of which is connected to a row of sub-pixels and to a light-emitting driving circuit; A plurality of data lines, each of which is connected to a column of the sub-pixels and to a driving chip.

5. The display substrate according to claim 4, characterized in that: The display substrate further includes a power supply line, the gate signal line includes a first gate signal line, the sub-pixel includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit includes: a first light-emitting control module, connected to the power line, the light-emitting control line and the first node respectively, and used to write the driving voltage of the power line into the first node according to the light-emitting control signal of the light-emitting control line; a driving module, connected to the first node, the data line, the first gate signal line, the second node and the third node respectively, for writing the data signal of the data line into the second node according to the gate signal provided by the first gate signal line, and generating a driving signal from the driving voltage of the first node according to the voltage of the second node to write into the third node; The second light-emitting control module is respectively connected to the light-emitting control line, the third node and the light-emitting element, and is used to transmit the driving signal of the third node to the light-emitting element according to the light-emitting control signal of the light-emitting control line.

6. The display substrate according to claim 5, characterized in that: The first light control module comprises: A first transistor, a source and a drain of the first transistor are respectively connected to the power line and the first node, and a gate of the first transistor is connected to the light emitting control line.

7. The display substrate according to claim 5, characterized in that: The driving module comprises: a second transistor, wherein a source and a drain of the second transistor are respectively connected to the data line and the first node, and a gate of the second transistor is connected to the first gate signal line; a third transistor, wherein a source and a drain of the third transistor are respectively connected to the first node and the third node, and a gate of the third transistor is connected to the second node; A fourth transistor, wherein a source and a drain of the fourth transistor are respectively connected to the second node and the third node, and a gate of the fourth transistor is connected to the first gate signal line.

8. The display substrate according to claim 5, characterized in that: The second light emitting control module comprises: A fifth transistor, wherein a source and a drain of the fifth transistor are respectively connected to the third node and the light emitting element, and a gate is connected to the light emitting control line.

9. The display substrate according to claim 5, characterized in that: The display substrate further includes an initialization line, the gate signal line includes a second gate signal line, the second gate signal line is located in a row with the first gate signal line, and the pixel driving circuit further includes a reset module, the reset module includes: a sixth transistor, wherein the source and the drain of the sixth transistor are respectively connected to the light emitting element and the initialization line, and the gate is connected to the second gate signal line, and is used for writing the reference voltage of the initialization line into the light emitting element according to the second gate signal of the second gate signal line; A seventh transistor, wherein the source and the drain of the seventh transistor are respectively connected to the second node and the initialization line, and the gate is connected to the second gate signal line, and is used to write the reference voltage of the initialization line into the second node according to the second gate signal of the second gate signal line.

10. The display substrate according to claim 5, characterized in that: The pixel driving circuit further includes: The charge storage module includes energy storage capacitors, which are respectively connected to the power line and the second node.

11. The display substrate according to claim 5, characterized in that: The display substrate also includes a driving circuit layer and a light-emitting layer sequentially stacked on the base substrate, the pixel driving circuit is formed in the driving circuit layer, the light-emitting element is formed in the light-emitting layer, and the light-emitting layer includes an anode layer, which is a transparent electrode layer.

12. The display substrate according to claim 11, characterized in that: The driving circuit layer comprises a buffer layer, an active layer, a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a passivation layer and a planarization layer stacked in sequence on the base substrate.

13. A display device, characterized in that: A display substrate comprising any one of claims 1-12.

14. The display device according to claim 13, characterized in that: The display device comprises an optical element, and the optical element is located on the side of the base substrate away from the driving circuit layer.

15. A control method, used for the display device according to claim 14, characterized in that: The control method comprises: Acquire a target sub-pixel overlapping with the position of the optical element; Determine, according to the target sub-pixel, a pixel row where the target sub-pixel is located; In each scanning cycle, when the pixel row is scanned along the scanning sequence, the driving extension time is waited for and then the scanning is performed sequentially.

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