Write leveling function detection method, device, electronic device and storage medium

Abstract

The present disclosure provides a write-leveling function detection method, device, electronic device and storage medium. The method includes: in the write-leveling mode, obtaining the offset between the rising edge of the current data selection signal and the rising edge of the most recent clock signal before the rising edge of the current data selection signal arrives; comparing the offset with a preset interval, and determining a preset output data signal based on the comparison result; detecting the actual output data signal collected at the moment after the rising edge of the current data selection signal has passed a preset delay time; comparing the preset output data signal and the actual output data signal, and obtaining a write-leveling function detection result based on the comparison result. The present disclosure predicts the output data based on the phase difference between the rising edge of the data selection signal issued during the write-leveling function debugging and the rising edge of the most recent clock signal before it; comparing the predicted output data with the actual output data to determine whether the write-leveling function is normal, thereby realizing automatic detection.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a write leveling function detection method, device, electronic device, and storage medium. Background Art

[0002] Double Data Rate (DDR) memory consists of multiple DRAM (Dynamic Random Access Memory) chips. Due to the topological distribution of these DRAM chips within the memory, phase shifts between control signals like command and clock signals and data signals can occur. For example, a phase shift between the DRAM system clock (CK) and the data strobe (DQS) signal can affect the correct writing of data. Therefore, write-leveling is designed to compensate for these phase shifts.

[0003] In the design, testing and use of DDR memory, it is necessary to verify whether its write leveling function is normal. How to test the write leveling function of the memory is an urgent problem to be solved in this field. Summary of the Invention

[0004] The present disclosure provides a write-leveling function detection method, device, electronic device, and storage medium for detecting the write-leveling function of a memory.

[0005] According to some embodiments, the first aspect of the present disclosure provides a write-leveling function detection method, which enters a write-leveling mode; obtains the offset between the rising edge of the current data selection signal and the rising edge of the clock signal closest to the rising edge of the current data selection signal; compares the offset with a preset interval, and determines a preset output data signal based on the comparison result; detects the actual output data signal collected at the moment after the rising edge of the current data selection signal has passed a preset delay time; compares the preset output data signal and the actual output data signal, and obtains a write-leveling function detection result based on the comparison result. In a feasible implementation, obtaining the offset between the rising edge of the current data selection signal and the rising edge of the clock signal closest to the rising edge of the current data selection signal includes: determining the rising edge of the current data selection signal; obtaining the time interval between the start command of the write-leveling mode and the rising edge of the current data selection signal; and calculating the remainder of the time interval divided by the clock period of the clock signal, where the remainder is the offset.

[0006] In a feasible implementation manner, each equalization debugging in the write equalization mode issues a group of data selection signals, and each group of data selection signals includes two consecutive data selection signals; determining the rising edge of the current data selection signal includes: determining the rising edge of the second data selection signal in the group of data selection signals issued under the current equalization debugging as the rising edge of the current data selection signal.

[0007] In a feasible implementation, the preset interval includes a first interval; the starting point of the first interval is the moment corresponding to the first time length after the rising edge of the clock signal; the end point of the first interval is the moment corresponding to the second time length after the rising edge of the clock signal; wherein the first time length is the write balancing hold time length; the second time length is the difference between half of the clock period of the clock signal and the write balancing hold time length.

[0008] In a feasible implementation, the offset is compared with a preset interval, and a preset output data signal is determined based on the comparison result, including: if the offset falls within a first interval, the preset output data signal is a high level.

[0009] In a feasible implementation, the preset interval also includes a second interval; the starting point of the second interval is the moment corresponding to the third time period after the rising edge of the clock signal; the end point of the second interval is the moment corresponding to the fourth time period after the rising edge of the clock signal; wherein the third time period is the sum of half the clock period of the clock signal and the write equalization hold time period; the fourth time period is the difference between the clock period of the clock signal and the write equalization hold time period.

[0010] In a feasible implementation, the offset is compared with a preset interval, and a preset output data signal is determined based on the comparison result, including: if the offset falls within the second interval, the preset output data signal is a low level.

[0011] In a feasible implementation, a preset output data signal and an actual output data signal are compared, and a write leveling function test result is obtained based on the comparison result, including: if the preset output data signal and the actual output data signal are the same, the write leveling function test result is normal; otherwise, the write leveling function test result is abnormal.

[0012] In a feasible embodiment, the preset interval also includes a third interval; the third interval includes a first sub-interval and a second sub-interval; the starting point of the first sub-interval is the moment corresponding to the fifth time period before the rising edge of the clock signal; the end point of the first sub-interval is the moment corresponding to the fifth time period after the rising edge of the clock signal; wherein the fifth time period is equal to the write equalization hold time period; the starting point of the second sub-interval is the moment corresponding to the sixth time period after the rising edge of the clock signal; the end point of the second sub-interval is the moment corresponding to the seventh time period after the rising edge of the clock signal; the sixth time period is equal to the difference between half of the clock period of the clock signal and the write equalization hold time period; the seventh time period is equal to the sum of the clock period of the clock signal and the write equalization hold time period.

[0013] In a feasible implementation, the write equalization function detection method further includes: according to the debugging timing, sequentially taking the rising edge of the data selection signal of each equalization debugging in the write equalization mode as the rising edge of the current data selection signal; counting the actual output data signals corresponding to each equalization debugging in which the rising edge of the statistical selection signal falls in the third interval, and obtaining the write equalization function detection result based on the statistical result; wherein the statistical result includes the number of actual output data signals that are low level or high level respectively.

[0014] In a feasible implementation manner, the rising edge of the statistical data selection signal falls on the actual output data signals corresponding to each group of data selection signals in the third interval, and the write equalization function detection result is obtained based on the statistical result, including: the rising edge of the statistical data selection signal falls on the actual output data signals corresponding to each group of data selection signals in the first sub-interval, and the first sub-statistical result is obtained; if the number of low-level actual output data signals and the number of high-level actual output data signals in the first sub-statistical result are not zero, then the write equalization function detection result is normal function; otherwise, the write equalization function detection result is abnormal function.

[0015] In a feasible implementation manner, the rising edge of the statistical data selection signal falls on the actual output data signals corresponding to each group of data selection signals in the third interval, and the write equalization function detection result is obtained based on the statistical result, including: the rising edge of the statistical data selection signal falls on the actual output data signals corresponding to each group of data selection signals in the second sub-interval, and the second sub-statistical result is obtained; if the number of low-level actual output data signals and the number of high-level actual output data signals in the second sub-statistical result are both not zero, then the write equalization function detection result is normal function; otherwise, the write equalization function detection result is abnormal function.

[0016] The following is a device, electronic device and storage medium corresponding to a data verification method provided in the first aspect of the present disclosure. The effects thereof can be referred to in the method section.

[0017] According to some embodiments, the second aspect of the present disclosure provides a write leveling function detection device, including: a control module, used to indicate entering a write leveling mode; a first processing module, used to obtain the offset between the rising edge of the current data selection signal and the rising edge of the clock signal most recently before the rising edge of the current data selection signal arrives; the first processing module is also used to compare the offset with a preset interval, and determine a preset output data signal based on the comparison result; the second processing module is used to detect the actual output data signal collected at the moment after a preset delay time from the rising edge of the current data selection signal; a comparison module is used to compare the preset output data signal and the actual output data signal, and obtain a write leveling function detection result based on the comparison result.

[0018] According to some embodiments, the third aspect of the present disclosure provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method of the first aspect.

[0019] According to some embodiments, the present disclosure provides a fourth aspect of a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method of the first aspect.

[0020] The write equalization function detection method, device, electronic device and storage medium provided by the embodiments of the present disclosure include: in the write equalization mode, obtaining the offset between the rising edge of the current data selection signal and the rising edge of the most recent clock signal before the rising edge of the current data selection signal arrives; comparing the offset with a preset interval, and determining the preset output data signal based on the comparison result; detecting the actual output data signal collected at the moment after the rising edge of the current data selection signal has passed a preset delay time; comparing the preset output data signal and the actual output data signal, and obtaining the write equalization function detection result based on the comparison result. The embodiments of the present disclosure predict the output data based on the phase difference between the rising edge of the data selection signal and the rising edge of the most recent clock signal before its arrival when the write equalization function is debugged; comparing the predicted output data with the actual output data, and determining whether the write equalization function is normal based on the comparison result, thereby realizing automatic detection of the write equalization function. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0022] Figure 1 is a schematic diagram of an exemplary DDR memory topology;

[0023] Figure 2 A flowchart of a write leveling function detection method provided by an embodiment of the present disclosure;

[0024] Figure 3 A timing diagram of a write-leveling training mode provided in an embodiment of the present disclosure;

[0025] Figure 4 A timing diagram of another write-leveling training mode provided in an embodiment of the present disclosure;

[0026] Figure 5 A timing diagram of another write equalization training mode provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of dividing a preset interval provided in an embodiment of the present disclosure;

[0028] Figure 7 A flowchart of another write leveling function detection method provided by an embodiment of the present disclosure;

[0029] Figure 8 A schematic structural diagram of a write leveling function detection device provided by an embodiment of the present disclosure;

[0030] Figure 9 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure.

[0031] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0032] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0033] Double Data Rate (DDR) memory includes multiple DRAM (Dynamic Random Access Memory) chips. Due to the topological distribution of signal lines for different signals, there may be phase deviations between control signals such as command signals and clock signals received by the DRAM chips and the data signals. For example, there may be a phase deviation between the DRAM system clock signal (CK) and the data select signal (DQS), which in turn affects the correct writing of data.

[0034] Specifically, the DDR memory includes a controller and multiple DRAM chips, and the controller transmits a clock signal and a data signal to each DRAM chip. Figure 1 The following is a schematic diagram of an exemplary DDR memory topology. Here, the clock signal is transmitted to the first DRAM chip, which then transmits it to the second DRAM chip, and so on. The data signal is transmitted directly from the controller to each DRAM chip. Due to the significant signal transmission time, the clock signal arrives at different times on each DRAM chip, while the data signal arrives at the same time on all DRAM chips. This results in varying degrees of phase deviation between the clock and data signals on all DRAM chips except the first one. Therefore, write leveling is designed to compensate for these phase shifts.

[0035] The write-leveling function adjusts the phase between the system clock signal (CK) and the data strobe signal (DQS) for each DRAM chip. Through multiple adjustments, the clock received by the DRAM chip is synchronized with the write data. Specifically, the controller applies a delay to the data strobe signal (DQS), samples the state of the clock signal (CK) on the rising edge of the data strobe signal (DQS), and feeds back the high or low state of the clock signal (CK) to the controller via the data signal (DQ). Based on this feedback, the controller increases or decreases the delay applied to the data strobe signal (DQS) until it detects a transition from 0 to 1 in the clock signal (CK) feedback, indicating that the phase adjustment between the clock signal (CK) and the data strobe signal (DQS) is complete.

[0036] During the design of the write-leveling function, it is necessary to test the designed write-leveling function and then optimize the design. After the memory with the write-leveling function is processed into a product, its write-leveling function needs to be tested to screen out the memory with normal write-leveling function and ensure product quality. During the use of the memory, it is necessary to automatically detect whether the chip's write-leveling function is working properly to prevent read and write errors.

[0037] Based on this, the present disclosure provides a write leveling function detection method, device, electronic device and storage medium, which can detect the write leveling function of a memory.

[0038] The following specific embodiments are used to describe in detail the technical solution and how it solves the above technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following embodiments are described in conjunction with the accompanying drawings.

[0039] Figure 2 A flowchart of a write leveling function detection method provided in an embodiment of the present disclosure. The method is applied to a memory, and its execution subject may be a write leveling function detection device. The device may be implemented by a computer program, such as application software, etc.; or, the device may also be implemented as a medium storing relevant computer programs, such as a USB flash drive, a cloud disk, etc.; or, the device may also be implemented by a physical device integrated or installed with relevant computer programs, such as a computer, etc. The following description will be made by taking the execution subject as an example of a write leveling function detection device. Figure 2 As shown, the method may include the following steps:

[0040] S100, entering write balancing mode;

[0041] S200, obtaining an offset between a rising edge of a current data strobe signal and a rising edge of a clock signal closest to the rising edge of the current data strobe signal;

[0042] S300, comparing the offset with a preset interval, and determining a preset output data signal according to the comparison result;

[0043] S400, detecting an actual output data signal collected at a moment after a preset delay time from the rising edge of the current data strobe signal;

[0044] S500 : Compare the preset output data signal and the actual output data signal, and obtain a write-leveling function detection result according to the comparison result.

[0045] Specifically, in step S100, a command to enter write-leveling mode may be issued to the DRAM chip being tested. For example, a control signal for entering or exiting write-leveling mode may be provided, wherein a high level of the control signal enters write-leveling mode, and a low level of the control signal exits write-leveling mode. The write-leveling mode is entered by setting the control signal to a high level.

[0046] It should be noted that in write-leveling mode, at the rising edge of the data strobe signal, the state of the acquisition clock signal CK is reflected by the data signal DQ. In actual output, the data signal DQ, which reflects the state of the clock signal CK, is output after a preset delay time. In other words, the actual output data signal in step S400 reflects the state of the clock signal CK corresponding to the rising edge of the current data strobe signal. The preset delay time is a property parameter of the DDR memory product and is related to the specifications of the DDR memory product, and is unrelated to the data signal DQ or the clock signal CK itself.

[0047] Furthermore, the predicted output data signal in step S300 predicts the state of the clock signal CK corresponding to the rising edge of the current data strobe signal. Therefore, by comparing the actual output data signal with the predicted output data signal to see if they are consistent, the write leveling function is detected to see if it is normal.

[0048] In some embodiments, during the execution of the write-leveling function, multiple write-leveling tests are performed, with a data strobe signal being issued during each test. Each data strobe signal is sequentially used as the current data strobe signal, and steps S200 to S500 are executed to detect whether the write-leveling function of the current test is normal. Furthermore, if the test results of each test are normal, it indicates that the DRAM chip being tested has a normal write-leveling function.

[0049] In some embodiments, in step S200, obtaining the offset between the rising edge of the current data strobe signal and the rising edge of the clock signal closest to the rising edge of the current data strobe signal specifically includes:

[0050] S210, determining the rising edge of the current data strobe signal;

[0051] S220, obtaining the time interval between the start command of the write equalization mode and the rising edge of the current data strobe signal;

[0052] S230: Calculate the remainder of the time interval divided by the clock period of the clock signal, where the remainder is the offset.

[0053] Specifically, in a detection scenario where a data strobe signal is issued for each debug, the offset calculation formula in step S230 is: tis = tDQSIS - [tDQSIS ÷ tCK] × tCK. Here, tis represents the offset; tDQSIS represents the time interval between the start command of the write equalization mode and the rising edge of the data strobe signal; tCK represents the clock period of the clock signal; and [] represents the rounding-down operation rule.

[0054] In some embodiments, each equalization debugging in the write equalization mode issues a group of data selection signals, and each group of data selection signals includes two consecutive data selection signals; in step S210, determining the rising edge of the current data selection signal specifically includes: determining the rising edge of the second data selection signal in a group of data selection signals issued under the current equalization debugging as the rising edge of the current data selection signal.

[0055] In this embodiment, each debug session issues two consecutive data strobe signals, i.e., two rising edges. The second rising edge of a set of data strobe signals is used as the rising edge of the current data strobe signal. Accordingly, the actual output data signal reflects the clock signal state corresponding to the second rising edge of the set of data strobe signals. This method improves the accuracy of the collected clock signal and the accuracy of the output data signal feedback.

[0056] Each set of data strobe signals corresponds to an actual output data signal that corresponds one-to-one with the rising edges of the data strobe signals. For example, if each set of data strobe signals includes two rising edges, two actual output data signals can be obtained. Due to the instability of the first rising edge of a set of data strobe signals, it is not possible to accurately capture the state of the corresponding clock signal at the first rising edge of the data strobe signals and accurately feedback the state of the clock signal via the actual output data signal. Therefore, the second actual output data signal can be selected for write-leveling function testing to improve accuracy.

[0057] The second actual output data signal is selected for write equalization function detection, and the calculated offset is the offset corresponding to the second rising edge of each set of data selection signals. In some embodiments, if the offset is calculated directly according to the second rising edge of each set of data selection signals, the calculation formula of the offset is: tis = tDQSIS_2nd-[tDQSIS_2nd÷tCK]×tCK. Among them, tDQSIS_2nd represents the time interval between the start command of the write equalization mode and the second rising edge of each set of data selection signals. In other embodiments, if the offset corresponding to the second rising edge is calculated according to the first rising edge of each set of data selection signals, the calculation formula of the offset is tis = (tDQSIS_1st+tCK)-[(tDQSIS_1st+tCK)÷tCK]×tCK. Among them, tis represents the offset; tDQSIS_1st represents the time interval between the start command of the write equalization mode and the first rising edge of each group of data selection signals; (tDQSIS_1st+tCK) represents the time interval between the start command of the write equalization mode and the second rising edge of each group of data selection signals.

[0058] In some embodiments, the first actual output data signal can also be selected for write-leveling function testing. The calculated offset is the offset corresponding to the first rising edge of each set of data strobe signals. The offset calculation formula is: tis = tDQSIS_1st - [tDQSIS_1st ÷ tCK] × tCK. tDQSIS_1st represents the time interval between the start command of the write-leveling mode and the first rising edge of each set of data strobe signals.

[0059] In some embodiments, a set of data strobe signals issued during each debug session may further include more than two consecutive data strobe signals. The rising edge of one of the data strobe signals is selected as the rising edge of the current data strobe signal to execute steps S200 to S500, thereby detecting the current debug session. When a set of data strobe signals includes multiple rising edges, the actual output data obtained during each debug session must correctly correspond to the rising edges of the data strobe signals.

[0060] In addition, when setting the number of data strobe signals included in each group of data strobe signals, the time interval between two adjacent debugs needs to be considered. A smaller time interval cannot support setting more data strobe signals in each group of data strobe signals.

[0061] The following combination Figures 3 to 5 , in different types of write equalization modes, the time interval tDQSIS between the start command of the write equalization mode and the rising edge of the data selection signal is shown, and the characterization of the data signal DQ to the clock signal.

[0062] Figure 3 A timing diagram of write-leveling mode provided in an embodiment of the present disclosure includes differential clock signals CK_t and CK_c, differential data strobe signals DQS_c and DQS_t, and output data signal DQ. MRW1-WR leveling and MRW2-WR leveling are used to control commands for entering write-leveling mode.

[0063] Figure 3 The time parameters in include: write leveling output delay, Figure 3 The delay time in step S400 is marked with tWLO; and the time between the falling edge of the last data strobe signal in the current debug and the rising edge of the first data strobe signal in the next debug is marked with tDQSL. Figure 3 The above time parameters are attribute parameters of DDR memory products and are related to the specifications of DDR memory products.

[0064] Reference Figure 3 , entering write-leveling mode at the rising edge of the clock signal T3. Taking the example of each debug output containing two consecutive data strobe signals and being able to directly capture the first rising edge of this set of data strobe signals, the two different time intervals tDQSIS1 and tDQSIS2 corresponding to the two debugs are shown.

[0065] Figure 3The first rising edge of the first group of data selection signals is located in the clock cycle before the rising edge Tb0 of the clock signal, and the corresponding clock signal is at a low level. After a preset delay time tWLO from the first rising edge of the first group of data selection signals, the output data signal DQ generates a falling edge and is output as 0.

[0066] However, when the first rising edge of the first set of data strobe signals is unstable, the output data signal DQ may not capture the unstable rising edge, and thus cannot generate a falling edge based on the low level of the clock signal. Therefore, when the first rising edge of the first set of data strobe signals is unstable, the output data signal DQ cannot accurately reflect the state of the corresponding clock signal.

[0067] Furthermore, Figure 3 The second rising edge of the first set of data strobe signals falls between the rising edges Tb0 and Tb1 of the clock signal, and the corresponding clock signal is at a low level. After a preset delay time tWLO from the second rising edge of the first set of data strobe signals, the output data signal DQ generates a falling edge and is output as 0. Typically, the second rising edge of each set of data strobe signals is relatively stable, so the output data signal DQ can accurately reflect the state of the corresponding clock signal.

[0068] It should be noted that whether the output data signal DQ transitions depends on the previous state of the output data signal DQ. Assuming that the output data signal DQ is initially low, after a preset delay time tWLO from the second rising edge of the first set of data strobe signals, the output data signal DQ remains at 0 without transitioning.

[0069] Reference Figure 3 The first rising edge of the second data strobe signal lies between the rising edges Td1 and Td2 of the clock signal, and the corresponding clock signal is at a high level. Therefore, after a preset delay time tWLO from the first rising edge of the second data strobe signal, the output data signal DQ generates a rising edge and is output as 1. However, if the first rising edge of the second data strobe signal is unstable, the output data signal DQ may not capture this unstable rising edge and, consequently, cannot generate a rising edge based on the high level of the clock signal. Therefore, if the first rising edge of the second data strobe signal is unstable, the output data signal DQ cannot accurately reflect the state of the corresponding clock signal.

[0070] Furthermore, the second rising edge of the second set of data selection signals is located between the rising edge Td2 of the clock signal and the rising edge Td3 of the clock signal, and the corresponding clock signal is at a high level; after a preset delay time tWLO from the second rising edge of the second set of data selection signals, the output data signal DQ generates a rising edge and is output as 1.

[0071] It should be noted that whether the output data signal DQ transitions depends on the previous state of the output data signal DQ. Assuming that the previous state of the output data signal DQ is a high level, then after a preset delay time tWLO from the first rising edge of the second set of data strobe signals, the output data signal DQ remains at 1 without transitioning.

[0072] Figure 4 This is a timing diagram of another write leveling mode provided by an embodiment of the present disclosure. Figure 3 tDQSL takes the minimum value, which is half the data strobe signal cycle. Write equalization mode is entered at the rising edge of the clock signal T3. For example, each debug output contains two consecutive data strobe signals, and the first rising edge of the data strobe signal can be directly captured. The three different time intervals tDQSIS3, tDQSIS4, and tDQSIS5 corresponding to three debugs are shown.

[0073] Figure 5 This is a timing diagram of another write-leveling mode provided by an embodiment of the present disclosure, in which the clock signal remains at a low level between the rising edges Tc0 and Td0 of the clock signal. Write-leveling mode is entered at the rising edge T3 of the clock signal. Taking the example of each debug output containing two consecutive data strobe signals and the ability to directly capture the first rising edge of the set of data strobe signals, two different time intervals tDQSIS6 and tDQSIS7 corresponding to the two debugs are shown.

[0074] Figure 6 A schematic diagram of the division of a preset interval provided in an embodiment of the present disclosure. Figure 6 , the prediction interval in step S300 and the corresponding prediction output result are explained.

[0075] Reference Figure 6 The preset interval includes a first interval; the starting point of the first interval is the time corresponding to the first time length after the rising edge of the clock signal (tWLH); the end point of the first interval is the time corresponding to the second time length after the rising edge of the clock signal (tCK / 2-tWLH); wherein the first time length is the write levelinghold time (tWLH for short); the second time length is the difference between half of the clock period of the clock signal and the write leveling hold time tWLH.

[0076] The write-level hold time is a property parameter of DDR memory products and is a target value specified for different DDR products and data rates. For example, for LPDDR4 products, when the data rate is 1600 bits per second (bps), the write-level hold time tWLH is specified as 150 picoseconds (ps); when the data rate is 2400bps, the write-level hold time tWLH is specified as 150ps; when the data rate is 3200bps, the write-level hold time tWLH is specified as 75ps; and when the data rate is 4266bps, the write-level hold time tWLH is specified as 50ps.

[0077] The offset tis reflects the relative position of the rising edge of the data strobe signal relative to the rising edge of the clock signal. The write-leveling hold time tWLH also reflects the target relative position of the rising edge of the data strobe signal relative to the rising edge of the clock signal. Therefore, based on the write-leveling hold time tWLH, the clock signal is divided into multiple intervals.

[0078] In some embodiments, in step S300, the offset is compared with a preset interval, and a preset output data signal is determined based on the comparison result, including: if the offset falls within the first interval, the preset output data signal is a high level. Figure 6 When the offset is in the first interval, the corresponding clock signal CK is 1. That is, when the rising edge of the data strobe signal falls in the first interval, the predicted output data signal is 1.

[0079] In some embodiments, the preset interval also includes a second interval; the starting point of the second interval is the moment corresponding to the third time period after the rising edge of the clock signal (tCK / 2+tWLH); the end point of the second interval is the moment corresponding to the fourth time period after the rising edge of the clock signal (tCK-tWLH); wherein the third time period is the sum of half the clock period of the clock signal and the write-balancing hold time; the fourth time period is the difference between the clock period of the clock signal and the write-balancing hold time.

[0080] In some embodiments, in step S300, the offset is compared with the preset interval, and the preset output data signal is determined based on the comparison result, including: if the offset falls within the second interval, the preset output data signal is low level. Figure 6 When the offset is in the second interval, the corresponding clock signal CK is 0. That is, when the rising edge of the data strobe signal falls in the second interval, the output data signal is predicted to be 0.

[0081] In some embodiments, in step S500, the preset output data signal and the actual output data signal are compared, and a write leveling function test result is obtained based on the comparison result, specifically including: if the preset output data signal and the actual output data signal are the same, then the write leveling function test result is normal function; otherwise, the write leveling function test result is abnormal function.

[0082] In some embodiments, the preset interval further includes a third interval; the third interval includes a first sub-interval and a second sub-interval. The starting point of the first sub-interval is the time (-tWLH) corresponding to the fifth time duration before the rising edge of the clock signal; the ending point of the first sub-interval is the time (tWLH) corresponding to the fifth time duration after the rising edge of the clock signal, which is the starting point of the first interval; wherein the fifth time duration is equal to the write leveling hold time duration.

[0083] The starting point of the second sub-interval is the moment (tCK / 2-tWLH) corresponding to the sixth time period after the rising edge of the clock signal, which is the end point of the first interval; the end point of the second sub-interval is the moment (tCK / 2+tWLH) corresponding to the seventh time period after the rising edge of the clock signal, which is the starting point of the second interval; the sixth time period is equal to the difference between half of the clock period of the clock signal and the write equalization hold time; the seventh time period is equal to the sum of the clock period of the clock signal and the write equalization hold time.

[0084] Since the clock cycle is periodic, the end point of the second interval in the current clock cycle is the starting point of the first sub-interval in the next clock cycle. It can be understood that tCK-tWLH is equivalent to -tWLH.

[0085] in addition, Figure 6 The interval division is performed using the case where tWLH is less than tCK / 2-tWLH as an example. The corresponding predicted output data signal is determined based on the level state of the corresponding clock signal within each interval. In some embodiments, tWLH may be greater than tCK / 2-tWLH. When tWLH is greater than tCK / 2-tWLH, those skilled in the art can divide the interval in a similar manner and derive the predicted output data signal corresponding to each interval.

[0086] Reference Figure 6 , the third interval is in the clock signal CK jump interval, and the collected clock signal CK may be 0 or 1. Based on this, in some embodiments, the write leveling function detection method further includes:

[0087] S600, according to the debugging timing, sequentially taking the rising edge of the data strobe signal of each equalization debugging in the write equalization mode as the rising edge of the current data strobe signal;

[0088] S700, counting the actual output data signals corresponding to each equalization debugging in which the rising edge of the statistical selection signal falls in the third interval, and obtaining the write equalization function detection result according to the statistical result; wherein the statistical result includes the number of actual output data signals being low level or high level respectively.

[0089] For the first subinterval and the second subinterval, the predicted output result may be 0 or 1. During the debugging process, the chip can only meet the requirements if this flip point falls within the range of -tWLH to +tWLH, that is, it falls within the first subinterval. If the write equalization function is normal, both 1 and 0 can be detected in the interval where the flip signal exists. In this embodiment, the actual output data of the third interval where the rising edge of the data selection signal falls during each debugging during the entire execution process of the write equalization function is recorded, and the number of low levels and high levels in these actual output data is counted to realize the verification of the write equalization function. In some embodiments, the write equalization function of each chip is repeatedly tested multiple times to increase the statistical quantity and ensure the referenceability of the statistical results.

[0090] In some embodiments, in step S700, the actual output data signals corresponding to the respective groups of data strobe signals whose rising edges of the statistical strobe signals fall within the third interval are counted, and a write leveling function test result is obtained based on the statistical result, specifically including:

[0091] S710, counting the actual output data signals corresponding to the data strobe signals of each group whose rising edge of the statistical data strobe signal falls within the first sub-interval, to obtain a first sub-statistical result;

[0092] S720: If the number of low-level and high-level output data signals in the first sub-statistical result is not zero, the write leveling function test result is normal; otherwise, the write leveling function test result is abnormal.

[0093] In some embodiments, in step S700, the actual output data signals corresponding to the respective groups of data strobe signals whose rising edges of the statistical strobe signals fall within the third interval are counted, and the write leveling function test results are obtained based on the statistical results, including:

[0094] S730, counting the actual output data signals corresponding to the data strobe signals of each group whose rising edge of the statistical strobe signal falls within the second sub-interval, to obtain a second sub-statistical result;

[0095] S740: If the number of low-level and high-level output data signals in the second sub-statistical result is not zero, the write leveling function test result is normal; otherwise, the write leveling function test result is abnormal.

[0096] In some embodiments, the actual output data of each interval during which the rising edge of the data strobe signal falls can also be recorded during the entire execution of the write-leveling function. If the actual output data of the first interval during which the rising edge of the data strobe signal falls is all high, the write-leveling function test result indicates normal functioning; otherwise, the write-leveling function test result indicates abnormal functioning. If the actual output data of the second interval during which the rising edge of the data strobe signal falls is all low, the write-leveling function test result indicates normal functioning; otherwise, the write-leveling function test result indicates abnormal functioning.

[0097] Figure 7 A flowchart of another write leveling function detection method provided by an embodiment of the present disclosure is provided. First, the offset tis of each debugging is calculated according to the clock cycle and the rising edge of the strobe data signal.

[0098] Determine whether the offset tis is within the first interval. Taking tWLH less than tck / 2-tWLH as an example, the intervals are divided. The first interval is tWLH ≤ tis ≤ tck / 2-tWLH, and the predicted output data corresponding to this first interval is 1. If it is within the first interval, determine whether the actual output data signal is 1. If it is 1, it indicates that the actual output data signal is equal to the predicted output data and the write leveling function is normal. If it is 0, it indicates that the actual output data signal is not equal to the predicted output data and the write leveling function is abnormal.

[0099] If it is not in the first interval, determine whether the offset tis is in the second interval. Similarly, taking tWLH less than tck / 2-tWLH as an example to divide the interval, the second interval is tWLH+tck / 2≤tis≤tck-tWLH. The predicted output data corresponding to this second interval is 0. If it is in the second interval, determine whether the actual output data signal is 0; if it is 0, it indicates that the actual output data signal is equal to the predicted output data and the write equalization function is normal; if it is 1, it indicates that the actual output data signal is not equal to the predicted output data and the write equalization function is abnormal.

[0100] If it is neither in the first interval nor in the second interval, then determine whether the offset tis is in the first sub-interval. Similarly, taking tWLH less than tck / 2 - tWLH as an example to divide the interval, the first sub-interval is -tWLH < tis < tWLH. Here, due to the periodicity of the clock signal, the starting point of the first sub-interval in the current clock cycle is the ending point of the second interval in the previous clock cycle, that is, tCK - tWLH is equivalent to -tWLH. If the offset tis falls within the first sub-interval, count the output data signals of 0 or 1 respectively. Then, determine whether to exit the write equalization mode. If it has exited, then determine whether the counts of 0 and 1 in the output data are both non-zero. If there are both 0 and 1 in the output data, it indicates normal functionality; otherwise, the functionality is abnormal. If it has not exited the write equalization mode, calculate the offset tis according to the data strobe signal issued in the current debugging, and repeat the loop until exiting the write equalization mode.

[0101] If it is neither in the first interval, nor in the second interval, nor in the first sub-interval, then determine whether the offset tis is in the second sub-interval. Similarly, taking tWLH less than tck / 2 - tWLH as an example to divide the interval, the second sub-interval is tck / 2 - tWLH < tis < tck / 2 + tWLH. If the offset tis falls within the second sub-interval, count the output data signals of 0 or 1 respectively. Then determine whether to exit the write equalization mode. If it has exited, then determine whether the counts of 0 and 1 in the output data are both non-zero. If there are both 0 and 1 in the output data, it indicates normal functionality; otherwise, the functionality is abnormal. If it has not exited the write equalization mode, calculate the offset tis according to the data strobe signal issued in the current debugging, and repeat the loop until exiting the write equalization mode.

[0102] The write equalization function detection method provided by the embodiments of the present disclosure includes: in the write equalization mode, obtaining the offset between the rising edge of the current data strobe signal and the rising edge of the nearest clock signal before the rising edge of the current data strobe signal; comparing the offset with a preset interval, and determining a preset output data signal according to the comparison result; detecting the actual output data signal collected at the moment after a preset delay duration from the rising edge of the current data strobe signal; comparing the preset output data signal and the actual output data signal, and obtaining the write equalization function detection result according to the comparison result.

[0103] The embodiments of the present disclosure predict the output data according to the phase difference between the rising edge of the data strobe signal and the rising edge of the nearest clock signal before it when debugging according to the write equalization function; compare the predicted output data with the actual output data, and determine whether the write equalization function is normal according to the comparison result. The embodiments of the present disclosure implement automatic monitoring by using a computer program without human intervention.

[0104] The following provides devices, electronic devices, and storage media corresponding to the data verification method according to the embodiments of the present disclosure. The effects thereof can be referred to in the method section.

[0105] Figure 8 This is a structural diagram of a write leveling function detection device provided by an embodiment of the present disclosure. Figure 8 As shown, the write leveling function detection device includes: a control module 10, which is used to control entry into the write leveling mode; a first processing module 20, which is used to obtain the offset between the rising edge of the current data selection signal and the rising edge of the clock signal closest to the rising edge of the current data selection signal; the first processing module 20 is also used to compare the offset with a preset interval, and determine the preset output data signal based on the comparison result; the second processing module 30 is used to detect the actual output data signal collected at the moment after the rising edge of the current data selection signal has passed a preset delay time; the comparison module 40 is used to compare the preset output data signal and the actual output data signal, and obtain the write leveling function detection result based on the comparison result.

[0106] Specifically, the control module 10 sends a control signal to the memory chip being tested to control the memory chip being tested to enter or exit the write-leveling mode. The control module 10 sends a data strobe signal to the memory chip being tested, and the second processing module 30 detects the actual output data signal generated by the memory chip being tested and sends it to the comparison module 40. The control module 10 sends the data strobe signal and a control signal for controlling entry or exit from the write-leveling mode to the first processing module 20. The first processing module 20 calculates an offset based on the control signal and the data strobe signal, outputs a predicted output data signal based on the offset, and sends it to the comparison module 40. The comparison module 40 compares the preset output data signal with the actual output data signal and outputs the detection result of the write-leveling function.

[0107] In some embodiments, the first processing module 20 is specifically used to determine the rising edge of the current data selection signal; the first processing module 20 is also specifically used to obtain the time interval between the start command of the write equalization mode and the rising edge of the current data selection signal; the first processing module 20 is also specifically used to calculate the remainder of the time interval divided by the clock period of the clock signal, and the remainder is the offset.

[0108] Optionally, each equalization debugging in the write equalization mode sends out a group of data selection signals, and each group of data selection signals includes two consecutive data selection signals; the first processing module 20 is specifically used to determine the rising edge of the second data selection signal in a group of data selection signals issued under the current equalization debugging as the rising edge of the current data selection signal.

[0109] In some embodiments, the preset interval includes a first interval; the starting point of the first interval is the moment corresponding to a first time period after the rising edge of the clock signal; the end point of the first interval is the moment corresponding to a second time period after the rising edge of the clock signal; wherein the first time period is the write balancing hold time period; the second time period is the difference between half of the clock period of the clock signal and the write balancing hold time period.

[0110] Furthermore, the first processing module 20 is specifically configured to preset the output data signal to a high level if the offset falls within the first interval.

[0111] In some embodiments, the preset interval also includes a second interval; the starting point of the second interval is the moment corresponding to the third time period after the rising edge of the clock signal; the end point of the second interval is the moment corresponding to the fourth time period after the rising edge of the clock signal; wherein the third time period is the sum of half the clock period of the clock signal and the write equalization hold time period; the fourth time period is the difference between the clock period of the clock signal and the write equalization hold time period.

[0112] Furthermore, the first processing module 20 is specifically configured to preset the output data signal to a low level if the offset falls within the second interval.

[0113] Furthermore, the comparison module 40 is specifically configured to determine that the write leveling function test result is normal if the preset output data signal and the actual output data signal are the same; otherwise, the write leveling function test result is abnormal.

[0114] In some embodiments, the preset interval further includes a third interval; the third interval includes a first sub-interval and a second sub-interval;

[0115] The starting point of the first subinterval is the time corresponding to the fifth time duration before the rising edge of the clock signal; the ending point of the first subinterval is the time corresponding to the fifth time duration after the rising edge of the clock signal; wherein the fifth time duration is equal to the write leveling hold time duration;

[0116] The starting point of the second sub-interval is the moment corresponding to the sixth time period after the rising edge of the clock signal; the end point of the second sub-interval is the moment corresponding to the seventh time period after the rising edge of the clock signal; the sixth time period is equal to the difference between half of the clock period of the clock signal and the write balancing hold time; the seventh time period is equal to the sum of the clock period of the clock signal and the write balancing hold time.

[0117] In some embodiments, the write-leveling function detection apparatus further includes a statistical module. The control module 10 is further configured to sequentially use the rising edge of the data strobe signal during each equalization debugging in the write-leveling mode as the rising edge of the current data strobe signal according to the debugging timing; the statistical module is further configured to count the actual output data signals corresponding to each equalization debugging in which the rising edge of the data strobe signal falls within the third interval, and obtain a write-leveling function detection result based on the statistical result; wherein the statistical result includes the number of actual output data signals that are low or high.

[0118] Furthermore, the statistical module is specifically configured to count actual output data signals corresponding to each group of data strobe signals whose rising edge of the statistical data strobe signal falls within the first subinterval, to obtain a first sub-statistical result;

[0119] The statistical module is specifically configured to determine that the write-leveling function detection result is normal if the number of low-level and high-level actual output data signals in the first sub-statistical result are both non-zero; otherwise, the write-leveling function detection result is abnormal.

[0120] Furthermore, the statistical module is specifically configured to count the actual output data signals corresponding to the data strobe signals of each group whose rising edge of the statistical data strobe signal falls within the second subinterval, to obtain a second sub-statistical result;

[0121] The statistical module is specifically configured to determine that if the number of low-level and high-level actual output data signals in the second sub-statistical result is not zero, the write-leveling function detection result is normal; otherwise, the write-leveling function detection result is abnormal.

[0122] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure is shown in FIG. Figure 9 As shown, the electronic device includes a processor 291 and a memory 292. It may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call logic instructions in the memory 292 to execute the method of the above embodiment.

[0123] In addition, the logic instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0124] Memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 291 executes the software programs, instructions, and modules stored in memory 292 to perform functional applications and data processing, thereby implementing the methods in the above-mentioned method embodiments.

[0125] Memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Memory 292 may also include high-speed random access memory and non-volatile memory.

[0126] The present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method provided in the embodiment.

[0127] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0128] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A write leveling function detection method, characterized in that: Enter write balancing mode; Acquire an offset between a rising edge of a current data strobe signal and a rising edge of a clock signal closest to the rising edge of the current data strobe signal; Comparing the offset with a preset interval, and determining a preset output data signal based on the comparison result; Detecting an actual output data signal collected at a moment after a preset delay time from the rising edge of the current data strobe signal; The preset output data signal and the actual output data signal are compared, and a write-leveling function detection result is obtained according to the comparison result.

2. The method according to claim 1, characterized in that The obtaining of the offset between the rising edge of the current data strobe signal and the rising edge of the clock signal closest to the rising edge of the current data strobe signal includes: Determining a rising edge of the current data strobe signal; Acquire the time interval between the start command of the write equalization mode and the rising edge of the current data strobe signal; A remainder of the time interval divided by the clock period of the clock signal is calculated and obtained, where the remainder is the offset.

3. The method according to claim 2, characterized in that Each equalization debugging in the write equalization mode sends a group of data strobe signals, and each group of data strobe signals includes two consecutive data strobe signals; Determining the rising edge of the current data strobe signal includes: A rising edge of a second data strobe signal in the group of data strobe signals issued in the current equalization debugging is determined as a rising edge of the current data strobe signal.

4. The method according to claim 1, wherein The preset interval includes a first interval; The starting point of the first interval is a time corresponding to a first time length after the rising edge of the clock signal; the end point of the first interval is a time corresponding to a second time length after the rising edge of the clock signal; The first duration is a write-leveling holding duration; and the second duration is a difference between half a clock period of the clock signal and the write-leveling holding duration.

5. The method according to claim 4, characterized in that The step of comparing the offset with a preset interval and determining a preset output data signal according to the comparison result includes: If the offset falls within the first interval, the preset output data signal is a high level.

6. The method according to claim 1 or 4, characterized in that The preset interval also includes a second interval; The starting point of the second interval is a time corresponding to a third time period after the rising edge of the clock signal; the end point of the second interval is a time corresponding to a fourth time period after the rising edge of the clock signal; The third duration is the sum of half the clock period of the clock signal and the write-balanced holding period; and the fourth duration is the difference between the clock period of the clock signal and the write-balanced holding period.

7. The method according to claim 6, characterized in that The step of comparing the offset with a preset interval and determining a preset output data signal according to the comparison result includes: If the offset falls within the second interval, the preset output data signal is at a low level.

8. The method according to claim 5 or 7, characterized in that The comparing the preset output data signal with the actual output data signal and obtaining the write leveling function detection result according to the comparison result includes: If the preset output data signal and the actual output data signal are the same, the write leveling function detection result is normal; otherwise, the write leveling function detection result is abnormal.

9. The method according to claim 1, 4 or 6, characterized in that The preset interval further includes a third interval; the third interval includes a first sub-interval and a second sub-interval; The starting point of the first subinterval is a time corresponding to the fifth time duration before the rising edge of the clock signal; the ending point of the first subinterval is a time corresponding to the fifth time duration after the rising edge of the clock signal; wherein the fifth time duration is equal to the write leveling hold time duration; The starting point of the second sub-interval is the moment corresponding to the sixth time period after the rising edge of the clock signal; the end point of the second sub-interval is the moment corresponding to the seventh time period after the rising edge of the clock signal; the sixth time period is equal to the difference between half of the clock period of the clock signal and the write balancing hold time period; the seventh time period is equal to the sum of the clock period of the clock signal and the write balancing hold time period.

10. The method according to claim 9, characterized in that The write leveling function detection method further includes: According to the debugging timing, the rising edge of the data strobe signal of each equalization debugging in the write equalization mode is sequentially used as the rising edge of the current data strobe signal; Counting the actual output data signals corresponding to each equalization debugging in which the rising edge of the data selection signal falls within the third interval, and obtaining the write equalization function detection result according to the statistical result; wherein the statistical result includes the number of the actual output data signals being low level or high level respectively.

11. The method according to claim 10, characterized in that The counting of the actual output data signals corresponding to the groups of data strobe signals whose rising edges of the data strobe signals fall within the third interval, and obtaining the write leveling function detection result according to the counting result, includes: Counting the actual output data signals corresponding to the groups of data strobe signals whose rising edges fall within the first sub-interval, to obtain a first sub-statistical result; If the number of low-level and high-level actual output data signals in the first sub-statistical result is not zero, the write leveling function detection result is normal; otherwise, the write leveling function detection result is abnormal.

12. The method according to claim 10, characterized in that The counting of the actual output data signals corresponding to the groups of data strobe signals whose rising edges of the data strobe signals fall within the third interval, and obtaining the write leveling function detection result according to the counting result, includes: Counting the actual output data signals corresponding to each group of the data strobe signals whose rising edges fall within the second sub-interval, to obtain a second sub-statistical result; If the number of low-level and high-level actual output data signals in the second sub-statistical result is not zero, the write leveling function detection result is normal; otherwise, the write leveling function detection result is abnormal.

13. A write leveling function detection device, characterized in that: include: A control module, used for instructing to enter a write balancing mode; A first processing module is configured to obtain an offset between a rising edge of a current data strobe signal and a rising edge of a clock signal closest to the rising edge of the current data strobe signal; The first processing module is further configured to compare the offset with a preset interval and determine a preset output data signal based on the comparison result; A second processing module is used to detect an actual output data signal collected at a moment after a preset delay time from the rising edge of the current data strobe signal; The comparison module is configured to compare the preset output data signal with the actual output data signal, and obtain a write-leveling function detection result according to the comparison result.

14. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 12 when executed by a processor.

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