Semiconductor memory device

Abstract

A semiconductor storage device of one embodiment includes a memory element, a bit line, a sense amplifier, and a potential generation circuit. The memory element includes a capacitor having a first terminal and a second terminal and a first transistor. The first transistor has a third terminal and a fourth terminal, the fourth terminal is connected to the first terminal, and includes an oxide semiconductor. The bit line is connected to the third terminal. The sense amplifier is connected to the bit line, between a first node connected to a first potential and a second node connected to a second potential lower than the first potential. The potential generation circuit is configured to supply a fourth potential different from a third potential that is intermediate between the first potential and the second potential to the second terminal.

Description

[0001] References to related applications

[0002] This application is based on and asserts the priority right of Japanese Patent Application No. 2021-50690, filed on March 24, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The implementation methods generally relate to semiconductor memory devices. Background Technology

[0004] As a storage device, DRAM (Dynamic Random Access Memory) is known. DRAM memory elements include capacitors and transistors. The memory elements retain data based on the charge stored in the capacitors. The potential of the data in the memory element to be read is amplified by a readout amplifier, thereby determining the stored data. Summary of the Invention

[0005] One implementation provides a semiconductor memory device that suppresses malfunctions.

[0006] One embodiment of a semiconductor memory device includes a memory element, a bit line, a sense amplifier, and a potential generation circuit. The memory element includes a capacitor having a first terminal and a second terminal, and a first transistor. The first transistor has a third terminal and a fourth terminal, the fourth terminal being connected to the first terminal, and comprises an oxide semiconductor. The bit line is connected to the third terminal. The sense amplifier is connected to the bit line, and is connected between a first node with a first potential and a second node with a second potential lower than the first potential. The potential generation circuit is configured to supply a fourth potential, different from a third potential that is the midpoint of the difference between the first and second potentials, to the second terminal.

[0007] Based on the above structure, a semiconductor memory device that suppresses malfunctions can be provided. Attached Figure Description

[0008] Figure 1 The functional blocks and associated constituent elements of the semiconductor memory device according to the first embodiment are shown.

[0009] Figure 2 The components of the memory element according to the first embodiment and the connections between the components are shown.

[0010] Figure 3 The leakage current in the memory element of the first embodiment and the memory element for reference is shown.

[0011] Figure 4The diagram shows a portion of the components of the readout amplifier according to the first embodiment, as well as the connections between these components.

[0012] Figure 5 A portion of the potential of the bit line in the first embodiment and the potential output from the potential generation circuit are shown.

[0013] Figure 6 The potentials during data readout of several elements of the semiconductor memory device of the first embodiment are shown along time.

[0014] Figure 7 The potentials of several elements of a reference semiconductor memory device are shown along time.

[0015] Figure 8 The diagram shows a portion of the components of the readout amplifier of the second embodiment, as well as the components that connect and associate the components.

[0016] Figure 9 The components of the potential generation circuit of the second embodiment are shown, as well as the components that connect and associate the components.

[0017] Figure 10 The potentials during data readout of several elements of the semiconductor memory device of the second embodiment are shown along time.

[0018] Figure 11 The potentials of several elements of a reference semiconductor memory device are shown along time.

[0019] Figure 12 The diagram shows the constituent elements of a potential generation circuit in a modified example of the second embodiment, as well as the constituent elements connecting and associating with each other.

[0020] Figure 13 The components of the potential generation circuit of the third embodiment are shown, as well as the components that connect and associate the components. Detailed Implementation

[0021] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having substantially the same function and structure will be given the same reference numerals, and repeated descriptions will sometimes be omitted. Sometimes, in order to distinguish among multiple constituent elements having substantially the same function and structure, numbers or characters will be appended to the end of the reference numerals.

[0022] The description of a particular implementation method applies, unless explicitly or obviously excluded, to the description of the other implementation methods.

[0023] Functional blocks do not need to be differentiated as in the example below. For example, a portion of the functionality could be executed by a different functional block than the one illustrated. Furthermore, the illustrated functional block could be divided into further subdivided functional sub-blocks.

[0024] In this specification and the patent claims, the case where a first element is "connected" to other second elements includes the case where the first element is connected to the second element via an element that is directly or always or selectively conductive.

[0025] 1. First Implementation Method

[0026] 1.1. Construction (Structure)

[0027] Figure 1 Functional blocks of the semiconductor memory device according to the first embodiment are shown. For example... Figure 1 As shown, the semiconductor memory device 1 is controlled by the memory controller 2. The semiconductor memory device 1 includes a memory element array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, a read circuit 17, a potential generation circuit 18, and a sense amplifier 19.

[0028] The memory element array 11 includes multiple memory elements MC, multiple word lines WL, multiple bit lines BL, and plate lines PL. Each memory element MC can store 1 bit of data. Each memory element MC is connected between one bit line BL and one plate line PL, and also connected to one word line WL. The word line WL is associated with a row. The bit line BL is associated with a column. A memory element MC is determined by selecting one row and one column.

[0029] The input / output circuit 12 receives control signals CNT, commands CMD, address signals ADD, and data DAT from the memory controller 2. The input / output circuit 12 then sends the data DAT to the memory controller 2. When data is written to the semiconductor memory device 1, the data DAT is used for writing data. When data is read from the semiconductor memory device 1, the data DAT is used for reading data.

[0030] The control circuit 13 receives the control signal CNT and the command CMD from the input / output circuit 12. The control circuit 13 controls the write circuit 16 and the read circuit 17 according to the control signal CNT and the command CMD.

[0031] The potential generation circuit 18 generates multiple potentials of different magnitudes under the control of the control circuit 13. The potential generation circuit 18 supplies the generated potentials to the memory element array 11, the write circuit 16, and the read circuit 17.

[0032] The write circuit 16 performs processing and control for writing data to the memory element MC. The write circuit 16 receives write data Dw from the input / output circuit 12. Write data Dw is the data written to the memory element MC, the object of the data write. The write circuit 16 receives one or more potentials used in the data write from the potential generation circuit 18. Based on the control of the control circuit 13 and the write data Dw, the write circuit 16 supplies one or more potentials for data writing to the column selection circuit 15.

[0033] The readout circuit 17 performs processing and control for reading data from the memory element MC.

[0034] The readout circuit 17 receives one or more potentials used in data readout from the potential generation circuit 18. Under the control of the control circuit 13, the readout circuit 17 calculates the data stored in the memory element MC using the potentials used for data readout. The calculated data is supplied to the input / output circuit 12 as readout data Dr.

[0035] The row selection circuit 14 receives the address signal ADD from the input / output circuit 12. The row selection circuit 14 supplies the potential received from the potential generation circuit 18 to the memory element array 11, thereby making a word line WL associated with the row determined according to the received address signal ADD selected.

[0036] The column selection circuit 15 receives the address signal ADD from the input / output circuit 12. The column selection circuit 15 supplies the potential received from the potential generation circuit 18 to the memory element array 11, thereby making the bit line BL associated with the column determined according to the received address signal ADD the selected state.

[0037] The sense amplifier 19 includes multiple sense amplifier circuits SAC (not shown). The sense amplifier 19 receives multiple potentials from the potential generation circuit 18 and operates using the received potentials. During data readout, the sense amplifier 19 amplifies the potential on the bit line BL in order to calculate the data stored in the memory element MC to which the data is read out.

[0038] 1.1.1. Memory Elements

[0039] Figure 2 The constituent elements of the memory element according to the first embodiment and the connections between these constituent elements are shown. Figure 2As shown, each memory element MC includes a capacitor CC and an n-type MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) CT. One end of the capacitor CC is connected to the plate line PL, and the other end is connected to one end of the transistor CT. The capacitor CC uses the charge accumulated at the node connected to the transistor CT to store data. The node of the capacitor CC connected to the transistor CT is sometimes referred to as the storage node SN. The state of whether the storage node has accumulated charge corresponds to the state of the memory element MC storing "1" data and the state of storing "0" data. Hereinafter, as an example, the state of the storage node SN having accumulated charge is treated as the state of the memory element MC storing "1" data, and the state of the storage node SN not having accumulated charge is treated as the state of the memory element MC storing "0" data.

[0040] The other end of the transistor CT is connected to a bit line BL, and the gate is connected to a word line WL. The semiconductor constituting part of the transistor CT provides at least a region for forming a channel (channel region). The semiconductor material includes oxide semiconductors, or is substantially composed of oxide semiconductors. In this specification and the patent claims, "substantially constitutes" means that the "substantially constitutes" element may include unintended impurities. An oxide semiconductor is an oxide that has the properties of a semiconductor. Examples of oxide semiconductors are oxides containing one or more of the elements indium (In), gallium (Ga), aluminum (Al), zinc (Zn), and tin (Sn). More specifically, regarding oxide semiconductors, for example, they may contain In, Ga, Zn, and O, or they may contain In, Al, Zn, and O.

[0041] Generally, the band gap of oxide semiconductors is wider than that of silicon. Therefore, the conductivity of oxide semiconductors in the unvoltage state is lower than that of silicon in the unvoltage state. Consequently, transistors containing oxide semiconductors have a higher cutoff characteristic than transistors containing silicon. Hereinafter, transistors containing oxide semiconductors are sometimes referred to as oxide semiconductor transistors, and transistors containing silicon are sometimes referred to as silicon transistors. Because the cutoff characteristic of oxide semiconductor transistors is higher than that of silicon transistors, the leakage current during the cutoff period in oxide semiconductor transistors is lower than that in silicon transistors. Therefore, in memory elements MC, the leakage current from the storage node SN to the transistor CT is less. Consequently, memory elements MC have a higher data retention capability (retention characteristic) than those containing silicon transistors.

[0042] On the other hand, in memory elements MC that include transistors CT containing oxide semiconductors, the following phenomenon may occur. Figure 3 The leakage current in the memory element of the first embodiment and the leakage current in the memory element for reference are shown. Figure 3 The memory element MCR for reference is shown on the left, and the memory element MC of the first embodiment is shown on the right.

[0043] The memory element MCR does not include the transistor CT in the memory element MC, but includes the transistor CTR. The transistor CTR includes silicon transistors. The element capacitor CC may cause current leakage between the storage node SN and the board line PL. See reference... Figure 3 As described, generally speaking, a transistor may generate leakage current from either the source or drain to the back gate. Depending on the semiconductor material, the transistor CTR generates a higher leakage current than the transistor CT. The leakage current in the transistor CTR is greater than the leakage current through the element capacitor CC. Therefore, in the transistor CTR, the outflow of charge from the storage node SN is dominated by the outflow through the transistor CTR to the back gate.

[0044] On the other hand, the leakage current in transistor CT is small, smaller than the leakage current through element capacitor CC. Therefore, in transistor CT, the outflow of charge from storage node SN to plate line PL is dominant.

[0045] 1.1.2. Readout Amplifier

[0046] Figure 4 The diagram shows a portion of the components of the sense amplifier 19 according to the first embodiment, as well as the connections between these components. As described above, the sense amplifier 19 includes a plurality of sense amplifier circuits SAC. Figure 4 A sense amplifier circuit SAC is shown. Figure 4 Additionally, the components associated with the sense amplifier circuit SAC and the connections of these components are shown.

[0047] like Figure 4As shown, the sense amplifier circuit SAC includes p-type MOSFETs TP1 and TP2 and n-type MOSFETs TN1, TN2, TN3, and TN4. The sense amplifier 19 also includes transistors TN5 and TN6. Transistor TP1 is connected between node SAP and node N1. Node SAP is supplied with a potential, for example, from the potential generation circuit 18. Node SAP is supplied with either a power supply potential Vddsa or a dynamically switched potential Vddsa / 2. The power supply potential Vddsa may have the same magnitude as the power supply potential Vdd used in the semiconductor memory device 1, or it may have a different magnitude. The gate of transistor TP1 is connected to node N2. Transistor TP1 has a resistance (on-resistance) Rp of a certain magnitude during conduction.

[0048] Transistor TN1 is connected between node N1 and node SAN. Node SAN is supplied with potential, for example, from potential generation circuit 18. Node SAN is supplied with either potential Vddsa / 2 or ground potential (common potential) Vss (e.g., 0V), which is dynamically switched. The following description is based on an example where Vss is 0V. The gate of transistor TN1 is connected to a bit line BL. Transistor TN1 has an on-resistance Rn.

[0049] Transistor TP2 is connected between node SAP and node N2. The gate of transistor TP2 is connected to node N1. Transistor TP2 has an on-resistance that is substantially the same as its on-resistance Rp. In this specification, "substantially the same" means that it is permissible for two components to be formed with the same goal, but not entirely the same due to unavoidable reasons such as limitations of the technology used to manufacture these components.

[0050] Transistor TN2 is connected between node N2 and node SAN. Transistor TN2 has an on-resistance that is substantially the same as its on-resistance Rn. The gate of transistor TN2 functions as node-BL. Node-BL is sometimes referred to as complementary bit line-BL. Complementary bit line-BL functions as a node with a reference potential (or reference potential). The reference potential is used to calculate the potential presented on bit line BL based on the data stored in the memory element MC to be read when data read begins. Hereinafter, the memory element MC to be read is sometimes referred to as selection memory element MC.

[0051] Transistor TN3 is connected between node N1 and complementary bit line -BL. The gate of transistor TN3 receives signal ISO. Signal ISO is supplied, for example, from a component different from the sense amplifier circuit SAC in sense circuit 17.

[0052] Transistor TN4 is connected between node N2 and bit line BL. The gate of transistor TN4 receives signal ISO. Signal ISO is supplied, for example, from a component different from the sense amplifier circuit SAC in sense circuit 17.

[0053] Transistor TN5 is connected between at least one bit line BL and node NBP. Node NBP receives a precharge potential Vpc from the potential generation circuit 18. The precharge potential Vpc is (Vddsa - Vss) / 2, where Vss is 0V, so it is Vddsa / 2, and it also functions as a reference potential. Hereinafter, the precharge potential Vpc is sometimes referred to as the precharge potential (Vddsa / 2). The gate of transistor TN5 receives the signal EQ. The signal EQ is supplied, for example, from a different component than the sense amplifier circuit SAC in sense circuit 17.

[0054] Transistor TN6 is connected between at least one complementary bit line -BL and node NBP. The gate of transistor TN6 receives the signal EQ.

[0055] Transistors TP1 and TN1 constitute the first inverter circuit, and transistors TP2 and TN2 constitute the second inverter. During the conduction of transistors TN3 and TN4, the first and second inverter circuits are cross-connected. That is, the input and output nodes of the first inverter circuit are connected to the output and input nodes of the second inverter circuit, respectively.

[0056] 1.1.3. Potential Generation Circuit

[0057] The potential generation circuit 18 generates a potential Vpl of a certain magnitude, which is supplied to the board line PL. The potential Vpl has a magnitude determined by the potential variation of the bit line BL connected to the select memory element MC during data readout, due to various reasons. Hereinafter, the bit line BL connected to the select memory element MC is sometimes referred to as the select bit line BL. Additionally, the complementary bit line-BL connected to the sense amplifier circuit SAC connected to the select bit line BL is sometimes referred to as the select complementary bit line-BL.

[0058] Specifically, the potential Vpl can be determined in the following way. For example... Figure 5 As shown in the upper part, and as referenced Figure 6As described later, the select bit line BL is precharged to a precharge potential Vpc, which is between the power supply potential Vddsa and the ground potential Vss (=0V), i.e., Vddsa / 2. After precharging, a potential based on the data stored in the select memory element MC is applied. The potential of the select bit line BL at the end of precharging may vary from Vddsa / 2 for various reasons before the potential based on the data stored in the select memory element MC is applied. The potential Vpl can be determined based on the amount of this variation. A more specific example follows.

[0059] For reference Figure 3 As described, in transistor CT, leakage current is generated between storage node SN and plate line PL, causing a change in the potential of storage node SN. Due to the leakage current, the potential of storage node SN changes in a manner close to the potential of plate line PL. To specifically suppress the rise in the potential of storage node SN due to leakage current for reasons described later, the potential of plate line PL is reduced. Furthermore, at the end of pre-charge, due to the capacitive coupling between the gate electrodes of transistors TN5 and TN6 and the select bit line BL and the select complementary bit line -BL, the potential of the select bit line BL and the select complementary bit line -BL may drop from Vddsa / 2 by a positive magnitude ΔV. Based on this situation, as... Figure 5 As shown in the lower part, the potential Vpl of the plate line PL can be Vddsa / 2-ΔV.

[0060] 1.2. Actions

[0061] Figure 6 The potentials during data readout of several elements of the semiconductor memory device of the first embodiment are shown along time. The word line WL among the elements showing the potentials is the word line WL connected to the select memory element MC, and is hereinafter sometimes referred to as the select word line WL.

[0062] like Figure 6 As shown, the potential of the plate line PL is maintained at potential Vpl.

[0063] exist Figure 6 At the start of the period, the potentials of each element are as follows. The select word line WL is asserted, i.e., it has a power supply potential Vpp. The power supply potential Vpp is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. By applying the power supply potential Vpp, the transistor CT of the select memory element MC is turned on, and the element capacitor CC of the select memory element MC is connected to the select bit line BL.

[0064] The signal EQ is negated, meaning it has a ground potential Vss. Therefore, transistors TN5 and TN6 are cut off, and neither the select bit line BL nor the select complementary bit line -BL is connected to node NBP at the precharge potential Vpc. In other words, the select bit line BL and the select complementary bit line -BL are not precharged.

[0065] The signal ISO is affirmed, i.e., it has a power supply potential Vddiso. The power supply potential Vddiso is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. By applying the power supply potential Vddiso, transistors TN3 and TN4 are turned on, and the select bit line BL and the select complementary bit line -BL are connected to nodes N2 and N1, respectively.

[0066] Node SAP has a power supply potential Vddsa, and node SAN has a ground potential Vss. Therefore, the sense amplifier circuit SAC receives power and is in a state of conduction, meaning it can operate.

[0067] Based on the potential states described above, one of the selection bit line BL and the selection complementary bit line -BL has a power supply potential Vddsa, and the other has a ground potential Vss. Which of the selection bit line BL and the selection complementary bit line -BL has the power supply potential Vddsa depends on whether the selection memory element MC stores "0" data or "1" data. When the selection memory element MC stores "0" data, the selection bit line BL has the ground potential Vss. In this case, the storage node SN also has the ground potential Vss. On the other hand, when the selection memory element MC stores "1" data, the selection bit line BL has the power supply potential Vddsa. In this case, the storage node SN also has the power supply potential Vddsa. Hereinafter, the case where the selection memory element MC stores "0" data is sometimes referred to as the "0" data storage case, and the case where the selection memory element MC stores "1" data is sometimes referred to as the "1" data storage case.

[0068] Accompanying the start of data readout, at time t0, the select word line WL is negated, meaning its potential becomes ground potential Vss. Therefore, the transistor CT of the select memory element MC is turned off, and the element capacitor CC of the select memory element MC is disconnected from the select bit line BL. The potential of the select word line WL continues until time t3. Alternatively, a negative potential Vnn can be applied to the select word line WL instead of ground potential Vss.

[0069] The period from time t1 to time t2 is the equalization period. At time t1, the potential of node SAP becomes Vddsa / 2, and the potential of node SAN also becomes Vddsa / 2. Therefore, the sense amplifier circuit SAC does not receive power and disables its function of amplifying the potential. The potentials of node SAP and node SAN continue until time t4. The potentials applied to node SAP and node SAN, strictly speaking, are (Vddsa + Vss) / 2. However, as mentioned above, based on the example where the ground potential Vss is 0V, the applied potential is Vddsa / 2.

[0070] Furthermore, at time t1, the signal EQ is affirmed, meaning the potential of the signal EQ becomes the power supply potential Vddeq. The power supply potential Vddeq is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With the application of the power supply potential Vddeq, transistors TN5 and TN6 are turned on, and the select bit line BL and the select complementary bit line -BL are connected to node NBP. As a result, the select bit line BL and the select complementary bit line -BL are both equalized to the same potential. Specifically, the select bit line BL and the select complementary bit line -BL are pre-charged to the pre-charge potential Vpc, i.e., potential Vddsa / 2.

[0071] At time t2, signal EQ is negated. This ends the pre-charging of select bit line BL and select complementary bit line -BL. Additionally, signal ISO is negated, meaning its potential becomes ground potential Vss. Consequently, transistors TN3 and TN4 are turned off, and select bit line BL and select complementary bit line -BL are disconnected from nodes N2 and N1 of the sense amplifier circuit SAC, respectively, thus isolating them.

[0072] At time t2, with the end of pre-charge and the start of isolation, the potentials of the selected bit line BL and the selected complementary bit line -BL change from potential Vddsa / 2, specifically becoming Vddsa / 2-ΔV.

[0073] Time intervals t3 to t4 constitute the charge sharing period. At time t3, the select word line WL is affirmed. As a result, charge sharing begins. Through charge sharing, the charge accumulated in the select bit line BL is shared with the charge accumulated in the storage node SN of the select memory element MC. As a result, the potential of the select bit line BL rises or falls depending on the data stored in the select memory element MC. In the case of "0" data storage, the potential of the storage node SN rises towards the potential of the select bit line BL, i.e., Vddsa / 2-ΔV, and the potential of the select bit line BL falls. The storage node SN and the select bit line BL become a state with a potential VB0 equal to the magnitude of the rising potential of the storage node SN and the falling potential of the select bit line BL. The potential of the complementary select bit line -BL is maintained.

[0074] On the other hand, in the "1" data storage scenario, the potential of the storage node SN decreases towards the potential of the select bit line BL, i.e., Vddsa / 2-ΔV, and the potential of the select bit line BL increases. The storage node SN and the select bit line BL become a state with a potential VB1 equal to the magnitude of the decreasing potential of the storage node SN and the increasing potential of the select bit line BL. The potential of the complementary select bit line -BL is maintained.

[0075] Time t4 to time t5 is the read-out period. At time t4, the potential of node SAP becomes the power supply potential Vddsa, and the potential of node SAN becomes the ground potential Vss. As a result, the potential of the select bit line BL rises or falls depending on the data stored in the select memory element MC. Furthermore, depending on the potential of the select bit line BL, the potential of the drain of transistor TN1, which has a gate connected to the select bit line BL, i.e., node N1, also rises or falls. That is, in the case of "0" data storage, transistor TN1 is turned off, and the potential of node N1 rises towards the power supply potential Vddsa. On the other hand, in the case of "1" data storage, transistor TN1 is turned on, and the potential of node N1 falls towards the ground potential Vss.

[0076] The period after time t5 is the readout and restore period. At time t5, the signal ISO is confirmed. Therefore, transistors TN3 and TN4 are turned on, and the sense amplifier circuit SAC amplifies the potential of one of nodes N1 and N2 to the power supply potential Vddsa, and the potential of the other node to the ground potential Vss. Through the amplification of the sense amplifier circuit SAC, in the "0" data storage case, the potential of the selection bit line BL drops to the ground potential Vss, and the potential of the selection complementary bit line -BL rises to the power supply potential Vddsa. On the other hand, in the "1" data storage case, the potential of the selection bit line BL rises to the power supply potential Vddsa, and the potential of the selection complementary bit line -BL drops to the ground potential Vss.

[0077] Figure 6 The action shown is an example; pre-reading and read (recovery) are not limited to... Figure 6 The recorded actions. For example, it is also possible to omit the pre-readout and perform the readout. In this case, at time t5, the potential of node SAP can become the power supply potential Vddsa, and the potential of node SAN can become the ground potential Vss.

[0078] The reference symbols M0 and M1 in the figure will be described later.

[0079] 1.3. Advantages (Effects)

[0080] According to the first embodiment, a semiconductor memory device that suppresses malfunctions can be provided as described below.

[0081] First, for comparison, refer to Figure 7 The semiconductor memory device 100 is described for reference. Figure 7 The potentials of several elements of the reference semiconductor memory device 100 are shown along time. For example... Figure 7 As shown, in the semiconductor memory device 100, the potential of the plate line PL is maintained at a potential Vplr. The potential Vplr has a magnitude of Vddsa / 2. Figure 7 The times t10, t11, t12, t13, and t15 occur respectively with respect to the first embodiment. Figure 6 The actions at times t0, t1, t2, t3, and t5 are equivalent to the actions.

[0082] In the case of a semiconductor memory device 100, if, ideally, the potentials of the selected bit line BL and the selected complementary bit line -BL remain at Vddsa / 2 after pre-charging, then the potential changes of the selected bit line BL and the selected complementary bit line -BL based on charge sharing begin from the potential Vddsa / 2. However, as referred to... Figure 5 As described, the potentials of the selected bit line BL and the selected complementary bit line -BL at the end of pre-charging and the beginning of charge sharing may decrease from Vddsa / 2. Due to this, the following phenomena may occur.

[0083] That is, in the "1" data storage case, the reference potential on the selected complementary bit line -BL has a magnitude of Vddsa / 2 - ΔV, and the selected bit line BL has a potential of a certain magnitude VB1r. The difference between the reference potential on the selected complementary bit line -BL and the potential on the selected bit line BL is a certain magnitude M1r, which functions as a margin in the "1" data storage case and is sometimes referred to as the "1" data storage case margin M1r. The "1" data storage case margin M1r is larger than the "1" data storage case margin in the ideal case (where the selected bit line BL and the selected complementary bit line -BL have a potential of Vddsa / 2 at the beginning of charge sharing). Therefore, the decrease in the potential of the selected bit line BL and the selected complementary bit line -BL from Vddsa / 2 at the beginning of charge sharing leads to an increase in the "1" data storage case margin M1r.

[0084] On the other hand, in the "0" data storage case, the reference potential on the selected complementary bit line -BL has a magnitude of Vddsa / 2 - ΔV, and the selected bit line BL has a potential of a certain magnitude VB0r. The difference between the reference potential on the selected complementary bit line -BL and the potential on the selected bit line BL is a certain magnitude M0r, which functions as a margin in the "0" data storage case, and is sometimes referred to as the "0" data storage case margin M0r. The "0" data storage case margin M0r is smaller than the "0" data storage case margin in the ideal case (where the selected bit line BL and the selected complementary bit line -BL have a potential of Vddsa / 2 at the start of charge sharing). Therefore, the decrease in the potential of the selected bit line BL and the selected complementary bit line -BL from Vddsa / 2 at the start of charge sharing leads to a reduction in the "0" data storage case margin M0r.

[0085] Choosing the difference between the reference potential on the complementary bit line -BL and the potential on the selected bit line BL, i.e., the margin, helps in calculating the accurate data of the sense amplifier circuit SAC. Therefore, in the case of "0" data storage, the small margin M0r may cause the sense amplifier circuit SAC to malfunction.

[0086] Transistor CT is an oxide semiconductor transistor, so as referenced Figure 3 As described, leakage current occurs between the storage node SN and the board line PL, and the potential of the storage node SN changes in a manner close to the decreasing or increasing potential Vpl of the board line PL. Therefore, in the case of "0" data storage, the potential of the storage node SN is higher than in the case where no leakage current occurs. On the other hand, as referred to... Figure 7As described, the potential VB0r of the select bit line BL achieved through charge sharing is equal to the potential of the storage node SN when the potential of the select bit line BL is equal to that of the select bit line BL. Therefore, the potential of the select bit line BL after pre-charging in the "0" data storage case is higher than in the case without leakage current. Consequently, due to leakage current, the margin M0r in the "0" data storage case may be smaller than in the case without leakage current.

[0087] According to the first embodiment, the potential Vpl of the board line PL is set to be lower than the pre-charge potential Vpc, based on the potentials of the select bit line BL and the select complementary bit line -BL after pre-charging. Specifically, the potential Vpl can be a potential that is substantially the same as the magnitude ΔV of the potential drop of the select bit line BL and the select complementary bit line -BL after pre-charging, which is lower than the pre-charge potential (Vddsa / 2). Therefore, the potential Vpl becomes a potential lower than the potential Vplr (=Vddsa / 2) of the board line PL in the reference semiconductor memory device 100. Then, through charge sharing, the potential of the storage node SN rises or falls towards the potential Vpl, and the potentials of the storage node SN and the select bit line BL become substantially the same. The select bit line BL has a potential VB0 of a certain magnitude in the "0" data storage case and a potential VB1 of a certain magnitude in the "1" data storage case. The margin for the "0" data storage case is M0, and the margin for the "1" data storage case is M1. The potential Vpl of the board line PL is lower than the pre-charge potential (Vddsa / 2), thus the potentials VB0 and VB1 of the select bit line BL after charge sharing become lower than the potentials VB0r and VB1r in the semiconductor memory device 100, respectively. Therefore, the margin M0 for "0" data storage in the first embodiment is larger than the margin M0r for "0" data storage in the semiconductor memory device 100. Furthermore, the rise in the potential of the storage node SN in the "0" data storage condition caused by the leakage current of the element capacitor CC is suppressed because the potential Vpl of the board line PL is lower than the pre-charge potential (Vddsa / 2). Therefore, malfunction of the read amplifier circuit SAC in the "0" data storage condition can be suppressed.

[0088] 2. Second Implementation Method

[0089] The second embodiment differs from the first embodiment in the structure of the readout amplifier circuit SAC and the potential generation circuit 18, and in related aspects. Hereinafter, the features that differ from the first embodiment will be mainly described.

[0090] 2.1. Structure

[0091] The sense amplifier circuit SAC and the potential generation circuit 18 of the second embodiment are different from those of the sense amplifier circuit SAC and the potential generation circuit 18 of the first embodiment. Hereinafter, the sense amplifier circuit SAC and the potential generation circuit 18 of the second embodiment are sometimes referred to as sense amplifier circuit SACb and potential generation circuit 18b, respectively, to distinguish them from those of the sense amplifier circuit SAC and the potential generation circuit 18 of the first embodiment. In addition, the semiconductor memory device 1 and the sense circuit 17 of the second embodiment are sometimes referred to as semiconductor memory device 1b, sense circuit 17b, and sense amplifier 19b, respectively, to distinguish them from those of the semiconductor memory device 1, sense circuit 17, and sense amplifier 19 of the first embodiment.

[0092] 2.1.2. Readout Amplifier

[0093] Figure 8 The components of a portion of the readout amplifier 19b of the second embodiment and the connections of the components are shown. Figure 8 A sense amplifier circuit SACb is shown. Figure 8 Additionally, the components associated with the sense amplifier circuit SACb and the connections of these components are shown.

[0094] like Figure 8 As shown, the sense amplifier circuit SACb includes, in addition to the constituent elements included in the sense amplifier circuit SAC of the first embodiment, n-type MOSFETs TN11 and TN12.

[0095] Transistor TN11 is connected between node N1 and the gate of transistor TN1. The gate of transistor TN11 receives signal OC. Signal OC is supplied, for example, from a component different from the sense amplifier circuit SACb in sense circuit 17b.

[0096] Transistor TN12 is connected between node N2 and the gate of transistor TN12. The gate of transistor TN12 receives signal OC.

[0097] 2.1.3. Potential Generation Circuit

[0098] Figure 9 The diagram shows the constituent elements of the potential generation circuit according to the second embodiment, as well as the connections and associations between these constituent elements. For example... Figure 9As shown, the potential generation circuit 18b includes resistors R1 and R2 and an operational amplifier OP. Resistor R1 has a resistance substantially the same as the on-resistance Rp of transistor TP1 (and / or TP2). Resistor R1 is connected between node N11 and node N11, which receives the power supply potential Vddsa. Resistor R1 can be implemented, for example, through impurity diffusion regions in a semiconductor and / or wiring in polysilicon or metal.

[0099] Resistor R2 has a resistance substantially the same as the on-resistance Rn of transistor TN1 (and / or TN2). Resistor R2 is connected between node N11 and the node receiving the ground potential Vss. Resistor R2 can be implemented, for example, using impurity diffusion regions in a semiconductor and / or wiring in polysilicon or metal.

[0100] The non-inverting input terminal of the operational amplifier OP is connected to node N11. The output terminal of the operational amplifier OP is connected to the board line PL and its own inverting input terminal. Through the operation of the operational amplifier OP, the potential Vplb of the board line PL is maintained at the potential of node N11. The potential of node N11 is equal to the voltage division achieved by resistors R1 and R2 of the potential difference Vddsa between the power supply potential Vddsa and the ground potential Vss (in the case of Vss = 0V). That is, the potential of node N11 is equal to the product of the potential difference Vddsa and the ratio of resistor R2 to the sum of resistors R1 and R2. Therefore, the potential Vplb of the board line PL is maintained at a magnitude equal to the voltage division achieved by the ratio of the on-resistances Rp and Rn of the potential difference Vddsa. More specifically, the potential Vplb of the board line PL has a magnitude of Vddsa / 2 - (ΔV1 + ΔV2) / 2. ΔV1, as described below, is the amount of potential decrease of either the select bit line BL or the select complementary bit line -BL after precharging. ΔV2, as described below, is the amount of potential decrease of either the select bit line BL or the select complementary bit line -BL caused by the end of precharging.

[0101] 2.2. Actions

[0102] Figure 10 The potentials during data readout of several elements of the semiconductor memory device of the second embodiment are shown along time.

[0103] For reference Figure 9 As described and as Figure 10 As shown, the potential of the plate line PL is maintained at potential Vplb.

[0104] Figure 10 Regarding the addition of signal OC and the potentials of the selection bit line BL and the selection complementary bit line -BL, it differs from the first embodiment. Figure 6 different.

[0105] exist Figure 10 At the beginning of the period, signal OC is negated, i.e., it has a ground potential Vss. Therefore, transistors TN11 and TN12 in the readout amplifier circuit SACb are turned off. Consequently, the gate of transistor TN1 is cut off from node N1, and the gate of transistor TN2 is cut off from node N2.

[0106] At time t1, signal OC is affirmed, meaning its potential becomes the power supply potential Vddoc. The power supply potential Vddoc is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. By applying the power supply potential Vddoc, transistors TN11 and TN12 are turned on; transistor TN1 is diode-connected, and transistor TN2 is diode-connected. Additionally, node N1 is connected to the select bit line BL via transistor TN11. Furthermore, node N2 is connected to the select complementary bit line -BL via transistor TN12. The potential of signal OC is maintained until time t3.

[0107] Time t2 to time t3 is the offset cancellation period. Through isolation at time t2, the connection between node N1 via transistor TN3 and the select complementary bit line -BL, and the connection between node N2 via transistor TN4 and the select bit line BL, are severed. On the other hand, as described above, nodes N1 and N2 are connected to the select bit line BL and the complementary select bit line -BL, respectively, using transistors TN11 and TN12. Therefore, the potentials of nodes N1 and N2 are transferred to the select bit line BL and the complementary select bit line -BL, respectively.

[0108] At time t2, the potential of node SAP becomes the power supply potential Vddsa, and the potential of node SAN becomes the ground potential Vss. As a result, the readout amplifier circuit SAC becomes capable of amplifying the potential. Furthermore, with the end of pre-charge and the start of isolation at time t2, the potentials of the selection bit line BL and the selection complementary bit line -BL change from the pre-charge potential (Vddsa / 2). During this change, offset cancellation is achieved through the action of the conducting transistors TN11 and TN12. That is, transistor TN1 is turned on by transistor TN11, thus forming the on-resistance of transistor TN1 between node N1 and node SAN. Similarly, transistor TN2 is turned on by transistor TN12, thus forming the on-resistance of transistor TN2 between node N2 and node SAN. Therefore, a potential based on the ratio of the on-resistance of transistor TP1 to the on-resistance of transistor TN1 is generated at node N1, and a potential based on the ratio of the on-resistance of transistor TP2 to the on-resistance of transistor TN2 is generated at node N2. Generally, p-type MOSFETs and n-type MOSFETs have different on-resistances, with the n-type MOSFET having a lower on-resistance than the p-type MOSFET. Therefore, the potentials of node N1 and node N2 are not the midpoint of the potential difference between node SAP and node SAN, but rather lower than the midpoint. Due to the potential changes in nodes N1 and N2 caused by offset cancellation, the potential of one of the selected bit lines BL and -BL drops by a positive magnitude ΔV1 from Vddsa / 2, while the potential of the other drops by a positive magnitude ΔV2 from Vddsa / 2. The difference between ΔV1 and ΔV2 arises from the deviation (offset) between the on-resistances of transistors TP1 and TP2 and the on-resistances of transistors TN1 and TN2.

[0109] As described above, the difference between ΔV1 and ΔV2 is based on the difference (offset) between the on-resistances of transistors TP1 and TP2 and the on-resistances of transistors TN1 and TN2. Therefore, at the beginning of charge sharing, nodes N1 and N2 have a potential difference based on the difference between the on-resistances Rp of transistors TP1 and TP2 and the on-resistances Rn of transistors TN1 and TN2. Then, the select bit line BL and the select complementary bit line -BL are charged in response to this potential difference between nodes N1 and N2. Readouts are performed based on the potentials of the select bit line BL and the select complementary bit line -BL, which are charged at such potentials. The potential difference between node N1 and node N2, generated by the difference between the on-resistances Rp of transistors TP1 and TP2 and the on-resistances Rn of transistors TN1 and TN2, causes a deviation between the potential of the select bit line BL and the potential of the select complementary bit line -BL. In contrast, by offset cancellation, the potential difference between node N1 and node N2, generated by the difference between the on-resistance Rp of transistors TP1 and TP2 and the on-resistance Rn of transistors TN1 and TN2, can be equivalently eliminated (compensated). As a result, during offset cancellation, the imbalance between the potential difference (margin) between the select bit line BL and the reference potential when the select bit line BL has a high potential and the potential difference between the select bit line BL and the reference potential when the select bit line BL has a low potential is improved.

[0110] At time t3, the potential of node SAP becomes potential Vddsa / 2, and the potential of node SAN also becomes potential Vddsa / 2. As a result, the sense amplifier circuit SAC becomes unable to amplify the potential. Through charge sharing from time t3, in the "0" data storage case, the selected bit line BL becomes a state with a potential of a certain magnitude VB0b. The potential of the selected complementary bit line -BL is maintained. On the other hand, in the "1" data storage case, the potential of the selected bit line BL becomes a state with a potential of a certain magnitude VB1b. The potential of the selected complementary bit line -BL is maintained.

[0111] The reference symbols M0b and M1b in the figure will be described later.

[0112] 2.3. Advantages

[0113] According to the second embodiment, similarly to the first embodiment, the potential Vpl of the board line PL is set to be lower than the pre-charge potential Vpc, based on the magnitudes of the potentials of the selected bit line BL and the selected complementary bit line -BL after the pre-charge is completed. Therefore, the same advantages as those of the first embodiment can be obtained.

[0114] Furthermore, according to the second embodiment, by applying offset elimination, as described below, the imbalance between the "0" data storage margin and the "1" data storage margin is suppressed.

[0115] Figure 11 The potentials of several elements of the reference semiconductor memory device 200 are shown along time. In the semiconductor memory device 200, similar to the semiconductor memory device 100, the potential Vpl of the plate line PL has a magnitude of Vddsa / 2. Offset cancellation is performed from time t12, and charge sharing is performed from time t13. Due to offset cancellation, the potentials of the select bit line BL and the select complementary bit line -BL decrease. As a result, the potential of the select bit line BL after charge sharing is lower than the potential of the select bit line BL without offset cancellation. Furthermore, in the "0" data storage case, due to the increase in the potential of the storage node SN caused by leakage current between the storage node SN and the plate line PL, the potential of the select bit line BL is higher than in the case without leakage current, having a potential of a certain magnitude VB0br. On the other hand, in the "1" data storage case, due to the decrease in the potential of the storage node SN caused by leakage current, the potential of the select bit line BL is lower than in the case without leakage current, having a potential of a certain magnitude VB1br. Therefore, in the case of "0" data storage, the complementary bit line -BL is chosen to have a low potential, resulting in a small margin M0rb for "0" data storage. In the case of "1" data storage, the complementary bit line -BL is chosen to have a low potential, resulting in a large margin M1rb for "1" data storage. As a result, a difference occurs between the margin M0rb for "0" data storage and the margin M1rb for "1" data storage.

[0116] "1" Data storage margin M1rb is compared to the margin M1r without offset elimination (refer to...) Figure 7 The offset M0rb in the "0" data storage case is smaller than the offset M0r in the case without offset elimination. That is, the imbalance, or difference, between the offset M0rb in the "0" data storage case and the offset M1rb in the "1" data storage case is smaller. Figure 7 The difference is small. However, the difference between the margin M0rb for "0" data storage and the margin M1rb for "1" data storage is still large.

[0117] According to the second embodiment, by applying offset cancellation, the effect of offset (the difference between the on-resistance of transistors TP1 and TP2 and the on-resistance of transistors TN1 and TN2) in the sense amplifier circuit SACb can be suppressed.

[0118] According to the second embodiment, a potential generation circuit 18b is provided, which maintains the potential Vplb of the board line PL at a magnitude equal to the voltage division based on the ratio of the on-resistance Rp and Rn based on the potential difference Vddsa. Due to the difference in on-resistance Rp and Rn, the amount of potential drop ΔV1 and ΔV2 of the select bit line BL and complementary select bit line -BL based on offset elimination are also different. The potential of the storage node SN rises or falls towards the potential Vplb of the board line PL due to leakage current. Therefore, the potential Vplb is set precisely to be between the potential of the select bit line BL after pre-charging and the potential of the complementary select bit line -BL. Therefore, the imbalance between the difference between the "0" data storage margin M0rb and the "1" data storage margin M1rb, which results from the rise or fall of the potential of the storage node SN towards the potential Vpl of the board line PL, can be suppressed. That is, it can suppress the imbalance between the difference between the "0" data storage margin M0rb and the "1" data storage margin M1rb, which reflects the difference between the on-resistance Rp and Rn.

[0119] 2.4. Variations

[0120] Figure 12 The constituent elements of the potential generation circuit of a modified example of the second embodiment and the connections of the constituent elements are shown. Figure 12 As shown, the potential generation circuit 18b2 of the modified example does not include resistors R1 and R2 in the potential generation circuit 18b, but includes p-type MOSFET TP21 and n-type MOSFETs TN21 and TN22 respectively.

[0121] Transistor TP21 has a substantially the same on-resistance Rp as transistor TP1 (and / or TP2). For this purpose, as an example, transistor TP21 can have a gate length and gate width substantially the same as those of transistor TP1, and an impurity concentration substantially the same as that of the channel region of transistor TP1.

[0122] Transistor TP21 is connected between node N11 and node Vddsa at the power supply potential Vddsa. The gate of transistor TP21 is connected to node N11 and is diode-connected.

[0123] Transistor TN21 has a substantially the same on-resistance Rn as transistor TN1 (and / or TN2). For this purpose, as an example, transistor TN21 can have a gate length and gate width substantially the same as those of transistor TN1, and a substantially the same impurity concentration in the channel region as those of transistor TN1. Transistor TN21 is connected between node N11 and a node at ground potential Vss.

[0124] Transistor TN22 is connected between node N11 and the gate of transistor TN21. The gate of transistor TN22 receives signal OC. During the period when signal OC is received, transistor TN22 is turned on, thereby diode-connecting transistor TN21.

[0125] According to the variation, during the offset cancellation period, the potential of node N11 is based on the on-resistance of transistor TP21 and transistor TN21, which are substantially the same as the on-resistance Rp of transistor TP1 and the on-resistance Rn of transistor TN1, respectively. Therefore, during the offset cancellation period, the potential Vplb of board line PL is maintained at substantially the same magnitude as the potential of bit line BL. Since the on-resistances of transistors TP21 and TN21, which determine the potential of node N11, are substantially the same as the on-resistances Rp and Rn of transistors TP1 and TN1, which determine the potential of bit line BL, this maintenance accuracy is high.

[0126] 3. Third Implementation Method

[0127] The third embodiment differs from the first and second embodiments in that the potential generation circuit 18 is different. Hereinafter, the features that differ from the first and second embodiments will be mainly described.

[0128] The potential generation circuit 18 of the third embodiment differs from the potential generation circuits 18 of other embodiments. Hereinafter, the potential generation circuit 18 of the third embodiment will sometimes be referred to as potential generation circuit 18c in order to distinguish it from the potential generation circuits 18 of other embodiments.

[0129] The third embodiment can be applied to any of the first and second embodiments. The third embodiment can also be applied to variations of the second embodiment.

[0130] Figure 13 The diagram shows the constituent elements of the potential generation circuit according to the third embodiment, as well as the connections and associations between these constituent elements. For example... Figure 13 As shown, the potential generation circuit 18c includes the structure of the potential generation circuit 18 of the first embodiment and the structure of the potential generation circuit 18b of the second embodiment, as well as an n-type MOSFET TN31. Figure 13As an example, a third embodiment is shown where the second embodiment is used as the basis. A transistor TN31 is connected between the board line PL and the bit line BL. The gate of transistor TN31 receives the signal BLEQ. The signal BLEQ is supplied from a component in the readout circuit 17. The signal BLEQ, for example, has the same logic level as the signal OC. Therefore, during offset cancellation, the board line PL is connected to the select bit line BL using the conducting transistor TN31.

[0131] According to the third embodiment, similar to the first embodiment, the potential Vpl of the plate line PL has a magnitude based on the potentials of the selected bit line BL and the selected complementary bit line -BL after the pre-charge is completed, and is lower than the pre-charge potential Vpc. Therefore, the same advantages as those of the first embodiment can be obtained.

[0132] Furthermore, according to the third embodiment, the potential generation circuit 18c includes a transistor TN31 between the board line PL and the bit line BL, and the transistor TN31 is turned on during the offset elimination period. Therefore, during the offset elimination period, the board line PL and the bit line BL are connected. Thus, the function of making the potential Vpl of the board line PL substantially the same as the potential of the bit line BL is higher than that in the first and second embodiments. Therefore, the imbalance between the "0" data storage margin M0 and the "1" data storage margin M1 can be suppressed with higher accuracy than in the first and second embodiments.

[0133] Furthermore, the third embodiment, based on the second embodiment, provides a structure for offset elimination in the same manner as the second embodiment. Therefore, it is possible to obtain the same advantages as the second embodiment.

[0134] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the invention described in the patent claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A memory element (MC) includes a capacitor (CC) and a first transistor (CT), the capacitor (CC) having a first terminal (SN) and a second terminal (PL), the first transistor (CT) having a third terminal, i.e., a drain, and a fourth terminal, i.e., a source, the fourth terminal being connected to the first terminal, the first transistor (CT) comprising an oxide semiconductor. Bit line (BL) is connected to the third terminal; A sense amplifier (SAC), connected to the bit line, is connected between a first node (SAP) at a first potential (Vddsa) and a second node (SAN) at a second potential (Vss) lower than the first potential; and The potential generation circuit (18) is configured to supply a fourth potential (Vpl), which is different from the third potential, i.e., the pre-charge potential (Vddsa / 2), which is the midpoint of the difference between the first potential and the second potential, to the second terminal. The fourth potential (Vpl) is lower than the third potential (Vddsa / 2). The sense amplifier (SAC) is also configured to make the bit line (BL) the third potential (Vddsa / 2) during the reading of data from the memory element (MC). During the data readout period, while the first transistor (CT) is off, the bit line drops from the third potential. The fourth potential (Vpl) is based on the amount by which the bit line drops from the third potential.

2. A semiconductor memory device comprising: A memory element (MC) includes a capacitor (CC) and a first transistor (CT), the capacitor (CC) having a first terminal (SN) and a second terminal (PL), the first transistor (CT) having a third terminal, i.e., a drain, and a fourth terminal, i.e., a source, the fourth terminal being connected to the first terminal, the first transistor (CT) comprising an oxide semiconductor. Bit line (BL) is connected to the third terminal; A sense amplifier (SAC), connected to the bit line, is connected between a first node (SAP) at a first potential (Vddsa) and a second node (SAN) at a second potential (Vss) lower than the first potential; and The potential generation circuit (18) is configured to supply a fourth potential (Vpl), which is different from the third potential, i.e., the pre-charge potential (Vddsa / 2), which is the midpoint of the difference between the first potential and the second potential, to the second terminal. The fourth potential (Vpl) is lower than the third potential (Vddsa / 2). The sense amplifier (SAC) is also configured to make the bit line (BL) the third potential (Vddsa / 2) during the reading of data from the memory element (MC). During the data readout period, while the first transistor (CT) is off, the bit line drops from the third potential to the fourth potential (Vpl), i.e., the equalized BL potential = PL potential.

3. A semiconductor memory device comprising: A memory element (MC) includes a capacitor (CC) and a first transistor (CT), the capacitor (CC) having a first terminal (SN) and a second terminal (PL), the first transistor (CT) having a third terminal, i.e., a drain, and a fourth terminal, i.e., a source, the fourth terminal being connected to the first terminal, the first transistor (CT) comprising an oxide semiconductor. Bit line (BL) is connected to the third terminal; A sense amplifier (SAC), connected to the bit line, is connected between a first node (SAP) at a first potential (Vddsa) and a second node (SAN) at a second potential (Vss) lower than the first potential; and The potential generation circuit (18) is configured to supply a fourth potential (Vpl), which is different from the third potential, i.e., the pre-charge potential (Vddsa / 2), which is the midpoint of the difference between the first potential and the second potential, to the second terminal. The sense amplifier (SAC) includes: The second transistor (TP1) of the first conductivity type, i.e. p-type, between the first node (SAP) and the third node (N1). The third transistor (TN1) of the second conductivity type, i.e., n-type, between the third node and the second node (SAN); The fourth transistor (TN11) is located between the third node and the gate of the third transistor. The first conductivity type, i.e., the p-type fifth transistor (TP2), is connected between the first node and the fourth node (N2) connected to the gate of the second transistor, wherein the gate of the fifth transistor is connected to the third transistor; The sixth transistor (TN2) of the second conductivity type, i.e., type n, between the fourth node and the second node; and The seventh transistor (TN12) is located between the fourth node and the gate of the sixth transistor.

4. The semiconductor memory device according to claim 3, wherein, The second transistor (TP1) has a first on-resistance (Rp). The third transistor (TN1) has a second on-resistance (Rn). The first potential (Vddsa) and the second potential (Vss) have a first potential difference. The fourth potential (Vpl) is equal to the product of the first potential difference and the ratio of the second on-resistance to the sum of the first on-resistance and the second on-resistance.

5. The semiconductor memory device according to claim 3, wherein, The second transistor (TP1) has a first on-resistance (Rp). The third transistor (TN1) has a second on-resistance (Rn). The potential generation circuit (18) includes: The first resistor (R1) has the same value as the first on-resistance; The second resistor (R2) has a fifth terminal (N11) connected to the first resistor, and its size is substantially the same as that of the second on-resistance; as well as An operational amplifier (OP) circuit has a non-inverting input terminal connected to the fifth terminal and an inverting input terminal and an output terminal connected to the second terminal (PL).

6. The semiconductor memory device according to claim 5, wherein, The first resistor (R1) includes the eighth transistor (TP21) of the first conductivity type, i.e., p-type. The second resistor (R2) includes the 9th transistor (TN21) of the second conductivity type, i.e., n-type.

7. The semiconductor memory device according to claim 1 or 2, wherein, The semiconductor memory device also includes a 10th transistor (TN31) between the second terminal (PL) and the bit line (BL).

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