Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and a method of operating the same. A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data stored in the selected memory cell by applying a read voltage to a selected word line among word lines connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and the peripheral circuit is configured to transmit a boost prevention voltage to a pass region in the cell string while applying an equalization voltage to the word lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0040474, filed on March 29, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This application relates to electronic devices, and more specifically, to semiconductor memory devices and methods of operating the semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be formed in a two-dimensional structure (where strings are arranged horizontally on a semiconductor substrate) or a three-dimensional structure (where strings are stacked vertically on a semiconductor substrate). Three-dimensional memory devices are memory devices designed to address the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0005] According to one embodiment of this disclosure, a semiconductor memory device includes a cell string and peripheral circuitry. The cell string includes at least one drain-select transistor connected to a bit line, at least one source-select transistor connected to a common source line, and a plurality of memory cells connected between the drain-select transistor and the source-select transistor. The peripheral circuitry performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuitry is configured to read data stored in the selected memory cell by applying a read voltage to the selected word line among the word lines connected to the plurality of memory cells and by applying a pass voltage to the unselected word lines. The peripheral circuitry is also configured to transmit a boost prevention voltage to a channel region in the cell string while applying an equalization voltage to the word line.

[0006] According to another embodiment of this disclosure, a method of operating a semiconductor memory device includes a cell string, the cell string including at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor, the method including: applying a read voltage to selected word lines among a plurality of word lines respectively connected to the plurality of memory cells, and applying a pass voltage to unselected word lines; and transmitting a boost prevention voltage to a channel region in the cell string while applying equalizing voltages to the plurality of word lines. Attached Figure Description

[0007] Figure 1This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is a diagram. Figure 1 A block diagram of one embodiment of the memory cell array 110.

[0009] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0010] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0011] Figure 5 It is a diagram. Figure 1 A circuit diagram of an embodiment of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0012] Figure 6 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 7 It is a diagram. Figure 6 A flowchart of an embodiment of step S130.

[0014] Figure 8 The diagram is based on Figure 7 Timing diagram of a method for operating a semiconductor memory device.

[0015] Figure 9 The diagram is based on Figure 7 Another timing diagram of a method for operating a semiconductor memory device.

[0016] Figure 10 It is a diagram. Figure 6 A flowchart of another embodiment of step S130.

[0017] Figure 11 The diagram is based on Figure 10 Timing diagram of a method for operating a semiconductor memory device.

[0018] Figure 12 It is a diagram. Figure 6 A flowchart of another embodiment of step S130.

[0019] Figure 13 The diagram is based on Figure 12 Timing diagram of a method for operating a semiconductor memory device.

[0020] Figure 14 This is a block diagram of a memory system 1000, which includes... Figure 1 Semiconductor memory device 100.

[0021] Figure 15 It is a diagram. Figure 14 A block diagram of an application example of a memory system.

[0022] Figure 16 This is a block diagram illustrating a computing system, which includes a reference... Figure 15 The memory system described. Detailed Implementation

[0023] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are provided for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0024] The embodiments of this disclosure are intended to provide a semiconductor memory device capable of preventing read disturbances, and a method for operating the semiconductor memory device.

[0025] This technology can provide a semiconductor memory device that can prevent read disturbances, and a method for operating the semiconductor memory device.

[0026] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0027] refer to Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, and a voltage generator 150.

[0028] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz may include multiple memory cells. As one embodiment, the multiple memory cells may be non-volatile memory cells and may be configured using non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional memory cell array. According to one embodiment, the memory cell array 110 may be configured as a three-dimensional memory cell array. Furthermore, each memory cell among the multiple memory cells included in the memory cell array may store at least one bit of data. In one embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each memory cell in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each memory cell in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to one embodiment, the memory cell array 110 may include a plurality of memory cells, each storing five or more bits of data.

[0029] The address decoder 120, read and write circuitry 130, and voltage generator 150 can operate as peripheral circuitry driving the memory cell array 110. In this case, the peripheral circuitry can operate under the control of control logic 140. The address decoder 120 can be connected to the memory cell array 110 via word line WL. The address decoder 120 can be configured to operate in response to the control logic 140. The address decoder 120 can receive addresses via an input / output buffer (not shown) within the semiconductor memory device 100.

[0030] Address decoder 120 can be configured to decode block addresses among received addresses. Address decoder 120 can select at least one memory block based on the decoded block address. Furthermore, during a read voltage application operation, address decoder 120 can apply a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines. Similarly, during a program verification operation, address decoder 120 can apply a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines.

[0031] Address decoder 120 can be configured to decode the column address in the received address. Address decoder 120 can transmit the decoded column address to read and write circuitry 130.

[0032] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line based on the block and row addresses. The column address can be decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0033] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0034] The read and write circuit 130 may include multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, while continuously supplying sensing current to the bit lines connected to the memory cell, the multiple page buffers PB1 to PBm can sense changes in the amount of current flowing according to the programming state of the corresponding memory cell via sensing nodes, and can latch the sensed changes as sensed data. The read and write circuit 130 can operate in response to a page buffer control signal output from control logic 140.

[0035] During a read operation, the read and write circuit 130 can sense data in the memory cell, temporarily store the read data, and output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. As an exemplary embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include column select circuitry, etc.

[0036] Control logic 140 can be connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can be configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110. Control logic can control voltage generator 150 to generate various voltages used during programming operations of memory cell array 110. Furthermore, control logic 140 can control address decoder 120 to transmit the voltages generated by voltage generator 150 via global lines to local lines of the memory block targeted for operation. Simultaneously, during a read operation, control logic 140 can control read and write circuit 130 to read data from the selected page of the memory block via bit lines BL1 to BLm, and store the data in page buffers PB1 to PBm. Furthermore, during a programming operation, control logic 140 can control read and write circuit 130 to program the data stored in page buffers PB1 to PBm into the selected page.

[0037] In response to a control signal output from control logic 140, voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and in response to control by control logic 140, generate multiple voltages by selectively activating these multiple pump capacitors.

[0038] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on control logic 140.

[0039] During a typical read operation in a semiconductor memory device, a floating channel may be formed in the cell string, and thus, by applying a read voltage V to the word line... READ Or through voltage V PASS Discharging may result in a negative boost in the channel voltage. While restoring the negative boost in the channel voltage, a positive boost may occur for the word line. Consequently, the threshold voltage distribution of the memory cell may shift in the positive direction, and thus, read disturbances may occur during subsequent read operations.

[0040] According to the semiconductor memory device and method of operating the semiconductor memory device according to embodiments of the present disclosure, a boost prevention voltage can be transmitted to the cell string during an equalization period after a read operation. The boost prevention voltage can be a voltage transmitted to maintain the channel voltage in the cell string. Accordingly, negative boosts occurring in the channel region of the cell string are minimized, and positive boosts occurring in the word lines during subsequent recovery steps are also minimized. As a result, according to the present disclosure, the impact of read disturbances can be reduced by minimizing the shift width of the threshold voltage distribution of the memory cells.

[0041] Figure 2 It is a diagram. Figure 1 A block diagram of one embodiment of the memory cell array 110.

[0042] refer to Figure 2 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. Such multiple memory cells may be arranged along the +X, +Y, and +Z directions. (Reference) Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0043] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0044] refer to Figure 3 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., the +X direction). Figure 3 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0045] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0046] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, a pillar for providing the channel layer may be provided in each cell string. As one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film.

[0047] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0048] As one embodiment, source select transistors in cell strings arranged in the same row can be connected to source select lines extending in the row direction, and source select transistors in cell strings arranged in different rows can be connected to different source select lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m can be connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row can be connected to the second source selection line SSL2.

[0049] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0050] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0051] The first memory cells MC1 to the nth memory cell MCn can be divided into: the first memory cells MC1 to the pth memory cells MCp, and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp can be arranged sequentially in the direction opposite to the +Z direction and can be connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn can be arranged sequentially in the +Z direction and can be connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn can be connected to each other via the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0052] The gate of the pipe transistor PT in each cell string can be connected to the pipe line PL.

[0053] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0054] A string of cells arranged in the column direction can be connected to a bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0055] Memory cells connected to the same word line in a cell string arranged in the row direction are configured as a page. For example, memory cells in cell strings CS11 to CS1m in the first row, connected to the first word line WL1, are configured as a page. Memory cells in cell strings CS21 to CS2m in the second row, connected to the first word line WL1, can be configured as another page. A cell string arranged in a row direction can be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0056] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0057] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKa can be improved. However, the size of memory block BLKa may increase. With fewer dummy memory cells provided, the size of memory block BLKa can be reduced. However, the reliability of operation for memory block BLKa may decrease.

[0058] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0059] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0060] refer to Figure 4 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may extend along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may include, on a substrate (not shown) stacked below the memory block BLKb: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0061] The source select transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row can be connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row can be connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row can be connected to the second source select line SSL2. As another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a common source select line.

[0062] The first memory cell MC1 to the nth memory cell MCn in each cell string can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0063] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0064] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb has the same Figure 3 The equivalent circuit of the memory block BLKa is similar to the equivalent circuit.

[0065] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0066] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKb can be improved. However, the size of memory block BLKb may increase. With fewer dummy memory cells provided, the size of memory block BLKb can be reduced. However, the reliability of operation for memory block BLKb may decrease.

[0067] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0068] Figure 5 It is a diagram. Figure 1 A circuit diagram of an embodiment of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0069] refer to Figure 5 The memory block BLKc may include multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm may be connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm may include at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0070] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, a pillar for providing the channel layer may be provided in each cell string. As one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film.

[0071] The source selection transistor SST of each cell string can be connected between the common source line CSL and the memory cells MC1 to MCn.

[0072] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0073] The drain selection transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn.

[0074] Memory cells connected to the same word line are configured as a page. Cell strings CS1 to CSm can be selected by selecting the drain select line DSL. A page within the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0075] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. The even-numbered cell strings among the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0076] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a three-dimensional memory cell array. Furthermore, as... Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a two-dimensional memory cell array.

[0077] Figure 6 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0078] refer to Figure 6 A method of operating a semiconductor memory device according to an embodiment of the present disclosure may include: applying a read voltage V to a selected word line. READ And apply a pass voltage V to the unselected word line. PASS (S110), and while applying equalization voltage to the word line, transmit boost prevention voltage to the channel of the cell string (S130).

[0079] In step S110, a read voltage V can be applied to the selected word line. READ The selected word line is connected to the memory cell selected as the target of the read operation, and a pass voltage V can be applied to the remaining unselected word lines. PASSAccordingly, data stored in the memory cell selected as the target of the read operation can be read. After the read data is temporarily stored in page buffers PB1 to PBm, the read data can be output through the input / output buffers (not shown) of the semiconductor memory device 100. (See reference...) Figure 8 The operation of the semiconductor memory device 100 performed in step S110 is described in more detail.

[0080] In step S130, the read voltage V applied to the selected word line in step S110 can be made... READ and the pass voltage V applied to the unselected word line PASS Discharge. To this end, in step S130, an equalization voltage V can be applied to the selected word line and the unselected word line. EQ Simultaneously, in step S130, an equalization voltage V is applied to the word line. EQ Simultaneously, a boost protection voltage can be transmitted to the channel to prevent the channel voltage of the cell string from rising. As described above, with the read voltage V applied to the word line... READ and the pass voltage V applied to the unselected word line PASS Discharging may cause a negative boost in the channel voltage within the cell string. Furthermore, while the negative boost in the channel voltage is being restored, a positive boost may occur for the word line. Consequently, the threshold voltage distribution of the memory cell may shift in the positive direction, and thus, read disturbances may occur during subsequent read operations.

[0081] According to an embodiment of the semiconductor memory device and method of operating the semiconductor memory device, by transmitting a boost prevention voltage to the channel of the cell string in step S130, the negative boost of the channel voltage of the cell string can be minimized. Therefore, the positive boost that occurs in the word line during the recovery step can be minimized. As a result, the shift width of the threshold voltage distribution of the memory cells can be minimized, and thus, the effects of read disturbances can be reduced.

[0082] Refer to later Figure 7 , Figure 10 and Figure 12 To describe Figure 6 An exemplary embodiment of step S130.

[0083] Figure 7 It is a diagram. Figure 6 A flowchart of an embodiment of step S130.

[0084] refer to Figure 7 , Figure 6 Step S130 may include: applying a turn-on voltage V to the drain select line DSL connected to the cell string.ON And apply a turn-off voltage V to the source selection line SSL OFF (S211) A boost protection voltage is transmitted to the drain selection transistor DST through the bit lines BL1 to BLm connected to the cell string respectively (S231), and an equalization voltage V is applied to the selected word line and the unselected word line. EQ (S251).

[0085] In step S211, due to the on-state voltage V ON The voltage V is applied to the drain selection line DSL and turned off. OFF A source select line SSL is applied, so the drain select transistor DST of the cell string can be turned on and the source select transistor SST can be turned off. Subsequently, in step S231, a boost protection voltage can be transmitted to the drain select transistor DST via the bit line. Because the drain select transistor DST is turned on, the boost protection voltage can be transmitted to the channel region in the cell string.

[0086] Subsequently, in step S251, an equalization voltage V can be applied to the word line. EQ Equalizing voltage V EQ It can be greater than the reading voltage V READ The voltage. Simultaneously, because step S231 prevents voltage transfer to the channel region in the cell string by boosting the voltage, even the equalized voltage V... EQ The equalization voltage V of word lines WL1 to WLn is applied thereafter. EQ It can be discharged, and the phenomenon of negative boosting of the channel voltage of the cell string can be minimized. Therefore, the operation of transferring boost voltage prevention to the drain selection transistor via the bit line in step S231 can be maintained until the word line equalization voltage V... EQ Discharged. Furthermore, the operation of applying a conduction voltage to the drain selection line DSL in step S211 can be maintained until the word line's equalization voltage V. EQ It was discharged.

[0087] Figure 8 The diagram is based on Figure 7 Timing diagram of a method for operating a semiconductor memory device.

[0088] refer to Figure 8 This shows the reading time period P. READ and equilibrium period P EQ Timing diagrams related to the voltages of the following items during the period: bit lines BL1 and BL2, drain select line DSL, unselected word line WL, selected word line WL, source select line SSL, and common source line CSL. Figure 8An example is shown in which the off cell in the memory cell selected as the read target is connected to the first bit line BL1, and the on cell is connected to the second bit line BL2.

[0089] During the reading period P READ In this process, bit lines BL1 and BL2 can be pre-charged. Accordingly, the voltages of bit lines BL1 and BL2 can be increased to the pre-charge voltage V. PRCH Meanwhile, during the reading period P READ In the middle, the conduction voltage V ON It can be applied to the drain select line DSL and the source select line SSL. The ground voltage VSS can be applied to the common source line CSL.

[0090] Within the word lines, through voltage V PASS It can be applied to an unselected word line and the voltage V can be read. READ It can be applied to the selected word line (S110). Read voltage V READ It can be less than the voltage V. PASS Therefore, data stored in the memory cell connected to the selected word line can be read.

[0091] For example, because the cell string connected to bit line BL1 can include turn-off cells, during the read period P READ The initial applied pre-charge voltage V PRCH It can be maintained. Meanwhile, because the cell string connected to bit line BL2 includes conduction cells, during the read period P... READ The initial applied pre-charge voltage V PRCH It can be reduced. As mentioned above, based on the pre-charge voltage V PRCH Whether it is reduced or not can distinguish the data stored in the connected memory cells.

[0092] During the reading period P READ After it ends, during the equilibrium period P EQ In the middle, a conduction voltage V can be applied to the drain selection line DSL. ON Furthermore, a turn-off voltage V can be applied to the source select line SSL. OFF (S211). Additionally, during the equilibrium period P... EQ In this process, a boost protection voltage can be applied to bit lines BL1 and BL2 (S231). Figure 8 In the embodiment, the pre-charge voltage V PRCH It can be used as a boost converter to prevent voltage spikes.

[0093] Meanwhile, during the equilibrium period P EQ In this process, a balanced voltage V can be applied to both the unselected and selected word lines. EQ(S251). In one embodiment, such as Figure 8 As shown, the equalization voltage V EQ It can be greater than the reading voltage V READ And less than the voltage V PASS The voltage. In another embodiment, the equalization voltage V EQ It can be related to the voltage V. PASS Voltages with the same amplitude.

[0094] like Figure 8 As shown, due to the equilibrium period P EQ During the period, the on-voltage V ON The voltage V is applied to the drain selection line DSL and turned off. OFF An application is made to the source-select line SSL, so the drain-select transistor DST can be turned on and the source-select transistor SST can be turned off. Furthermore, due to the equalization period P... EQ During this period, a boost prevention voltage is applied to bit lines BL1 and BL2 (S231), so the boost prevention voltage can be transmitted to the channel region of the cell string through the drain-select transistor DST. Because the boost prevention voltage is transmitted to the channel region in the cell string, even if the equalization voltage V... EQ The voltage V is applied to word lines WL1 to WLn (S251), and thereafter, the equalization voltage V of the word lines is... EQ Discharging can also minimize the phenomenon of negative boosting of the channel voltage of the cell string. Therefore, the positive boost that occurs in the word line during the recovery step can be minimized. As a result, the shift width of the threshold voltage distribution of the memory cell can be minimized, and thus, the effect of read disturbances can be reduced.

[0095] Figure 9 The diagram is based on Figure 7 Another timing diagram of a method for operating a semiconductor memory device. Similar to... Figure 8 ,exist Figure 9 The figure shows the reading time period P. READ and equilibrium period P EQ Timing diagrams related to the voltages of the following items during the period: bit lines BL1 and BL2, drain select line DSL, unselected word line WL, selected word line WL, source select line SSL, and common source line CSL. In the following text, terms related to... Figure 8 The description is a repetitive description.

[0096] refer to Figure 9 Reading time period P READ Operations and References Figure 8 The described operations are the same. Additionally, besides the magnitude of the voltage applied to the bit line, the equalization period P... EQ Operations and References Figure 8 The operations described are the same.

[0097] That is, according to Figure 9 In the embodiment, during the equilibrium period P EQ In, greater than the pre-charge voltage V PRCH Boost voltage prevents voltage V BP1 It can be applied to bit lines BL1 and BL2. Due to the boost prevent voltage V... BP1 The increased amplitude can further reduce the phenomenon of negative boosting in the channel area of ​​the unit string. Figure 8 This shows the use of a pre-charge voltage V. PRCH As an example of voltage boosting prevention, and Figure 9 This shows the use of a voltage greater than the pre-charge voltage V. PRCH Boost voltage prevents voltage V BP1 This is one example, but the disclosure is not limited thereto. That is, a voltage less than the pre-charge voltage V can also be used. PRCH The boost voltage prevents voltage.

[0098] Figure 10 It is a diagram. Figure 6 A flowchart of another embodiment of step S130.

[0099] refer to Figure 10 , Figure 6 Step S130 may include: applying a forward voltage V to the source select line SSL connected to the cell string. ON And apply a turn-off voltage V to the drain-select line DSL. OFF (S213) A boost protection voltage is transferred to the source selection transistor SST via the common source line CSL connected to the cell string (S233), and an equalization voltage V is applied to the selected word line and the unselected word line. EQ (S253).

[0100] In step S213, due to the on-state voltage V ON A source select line SSL is applied and a turn-off voltage V is applied. OFF A voltage is applied to the drain select line DSL, so the source select transistor SST of the cell string can be turned on, and the drain select transistor DST can be turned off. Subsequently, in step S233, a boost protection voltage can be transmitted to the source select transistor SST via the source select line CSL. Because the source select transistor SST is turned on, the boost protection voltage can be transmitted to the channel region in the cell string.

[0101] Subsequently, in step S253, an equalization voltage V can be applied to the word line. EQ Equalizing voltage V EQ It can be greater than the reading voltage V READThe voltage. Simultaneously, because the boost prevents the voltage from being transmitted to the channel region in the cell string via step S233, even the equalized voltage V... EQ The equalization voltage V of word lines WL1 to WLn is applied thereafter. EQ Discharging can also minimize the phenomenon of negative boosting of the channel voltage of the cell string. Therefore, the operation of transferring boost voltage prevention to the source selection transistor SST via the common source line CSL in step S233 can be maintained until the word line equalization voltage V... EQ Discharged. Furthermore, the operation of applying a conduction voltage to the source selection line SSL in step S213 can also be maintained until the word line's equalization voltage V. EQ It was discharged.

[0102] Figure 11 The diagram is based on Figure 10 Timing diagram of a method for operating a semiconductor memory device. Similar to... Figure 8 and Figure 9 ,exist Figure 11 The figure shows the reading time period P. READ and equilibrium period P EQ Timing diagrams related to the voltages of the following items during the period: bit lines BL1 and BL2, drain select line DSL, unselected word line WL, selected word line WL, source select line SSL, and common source line CSL. In the following text, terms related to... Figure 8 Or a description that is repeated in the 9 figures.

[0103] refer to Figure 11 Reading time period P READ Operations and References Figure 8 and Figure 9 The operations described are the same. Meanwhile, the equilibrium period P is described below. EQ The operations within.

[0104] During the reading period P READ After it ends, during the equilibrium period P EQ In the middle, a conduction voltage V can be applied to the source selection line SSL. ON Furthermore, a turn-off voltage V can be applied to the drain-select line DSL. OFF (S213). Furthermore, during the equilibrium period P... EQ In this case, a boost protection voltage V can be applied to the common source line CSL. BP2 (S233).

[0105] Meanwhile, during the equilibrium period P EQ In this process, a balanced voltage V can be applied to both the unselected and selected word lines. EQ (S253). In one embodiment, such as Figure 11 As shown, the equalization voltage V EQ It can be greater than the reading voltage V READ And less than the voltage V PASS The voltage. In another embodiment, the equalization voltage V EQ It can be related to the voltage V. PASS Voltages with the same amplitude.

[0106] like Figure 11 As shown, during the equilibrium period P EQ During this period, a turn-on voltage V is applied to the source selection line SSL. ON And apply a turn-off voltage V to the drain-select line DSL. OFF This allows the source selection transistor SST to be turned on and the drain selection transistor DST to be turned off (S213). Additionally, during the equalization period P... EQ During this period, a boost protection voltage V is applied to the common source line CSL. BP2 (S233) Therefore, the boost protection voltage can be transmitted to the channel region of the cell string through the source selection transistor SST. Because the boost protection voltage is transmitted to the channel region in the cell string, even if the equalization voltage V... EQ The equalization voltage V of the word lines is applied to word lines WL1 to WLn (S253), and thereafter... EQ Discharging can also minimize the phenomenon of negative boosting of the channel voltage of the cell string. Therefore, the positive boost that occurs in the word line during the recovery step can be minimized. As a result, the shift width of the threshold voltage distribution of the memory cell can be minimized, and thus, the effect of read disturbances can be reduced.

[0107] According to the reference Figures 7 to 9 In the described embodiment, the boost prevents voltage from being transmitted from the bit line to the channel region in the cell string through the drain select transistor. On the other hand, according to the reference... Figure 10 and Figure 11 In the described embodiment, the boost converter prevents voltage from being transmitted from the common source line to the channel region in the cell string via the source selection transistor.

[0108] Figure 12 It is a diagram. Figure 6 A flowchart of another embodiment of step S130.

[0109] refer to Figure 12 , Figure 6 Step S130 may include: applying a forward voltage V to the drain select line DSL and the source select line SSL connected to the cell string. ON(S215); A first boost protection voltage is transmitted to the drain select transistor DST via bit lines BL1 to BLm connected to the cell string, and a second boost protection voltage is transmitted to the source select transistor SST via the common source line CSL connected to the cell string (S235); and an equalization voltage V is applied to the selected word line and the unselected word line. EQ (S255).

[0110] In step S215, due to the on-state voltage V ON A drain select line DSL and a source select line SSL are applied, so the drain select transistor DST and the source select transistor SST of the cell string can be turned on. Subsequently, in step S235, a first boost protection voltage can be transmitted to the drain select transistor DST via the bit line, and a second boost protection voltage can be transmitted to the source select transistor SST via the common source line CSL. Because the drain select transistor DST is turned on, the first boost protection voltage can be transmitted to the channel region in the cell string. Simultaneously, because the source select transistor SST is turned on, the second boost protection voltage can also be transmitted to the channel region in the cell string. In one embodiment, the first boost protection voltage may have the same magnitude as the second boost protection voltage. In another embodiment, the first boost protection voltage and the second boost protection voltage may have different magnitudes.

[0111] Subsequently, in step S255, an equalization voltage V can be applied to the word line. EQ Because the first boost protection voltage and the second boost protection voltage are transmitted to the channel region in the cell string through step S235, even if the equalization voltage V EQ The equalization voltage V of word lines WL1 to WLn is applied thereafter. EQ Discharging can also minimize the phenomenon of negative boosting of the channel voltage of the cell string. Therefore, in step S235, the operation of transferring the first boost protection voltage to the drain select transistor via the bit line and the operation of transferring the second boost protection voltage to the source select transistor SST via the common source line CSL can be maintained until the word line equalization voltage V... EQ Discharged. Furthermore, the operation of applying turn-on voltage to the drain select line DSL and the source select line SSL in step S215 can also be maintained until the word line equalization voltage V. EQ It was discharged.

[0112] Figure 13 The diagram is based on Figure 12 Timing diagram of a method for operating a semiconductor memory device.

[0113] Similar to Figure 8 , Figure 9 and Figure 11,exist Figure 13 The figure shows the reading time period P. READ and equilibrium period P EQ Timing diagrams related to the voltages of the following items during the period: bit lines BL1 and BL2, drain select line DSL, unselected word line UnselectedWL, selected word line SelectedWL, source select line SSL, and common source line CSL. In the following text, terms related to... Figure 8 , Figure 9 or Figure 11 The description is a repetitive description.

[0114] refer to Figure 13 Reading time period P READ Operations and References Figure 8 , Figure 9 and Figure 11 The operations described are the same. Meanwhile, the equilibrium period P is described below. EQ The operations within.

[0115] During the reading period P READ After it ends, during the equilibrium period P EQ In the middle, a conduction voltage V can be applied to the drain select line DSL and the source select line SSL. ON (S215). Furthermore, during the equilibrium period P... EQ In the middle, a first boost protection voltage V can be applied to bit lines BL1 and BL2. BPa Furthermore, a second boost protection voltage V can be applied to the common source line CSL. BPb (S235).

[0116] Meanwhile, during the equilibrium period P EQ In this process, a balanced voltage V can be applied to both the unselected and selected word lines. EQ (S255). In one embodiment, such as Figure 13 As shown, the equalization voltage V EQ It can be greater than the reading voltage V READ And less than the voltage V PASS The voltage. In another embodiment, the equalization voltage V EQ It can be related to the voltage V. PASS Voltages with the same amplitude.

[0117] like Figure 13 As shown, during the equilibrium period P EQ During this period, a turn-on voltage V is applied to the drain select line DSL and the source select line SSL. ON This allows the drain-select transistor DST and the source-select transistor SST (S215) to be turned on. Furthermore, due to the equalization period P... EQ During the first boost voltage prevention voltage VBPa The voltage is applied to bit lines BL1 and BL2 (S235), so the first boost prevents the voltage V. BPa The signal can be transferred to the channel region of the cell string via the drain-select transistor (DST). Meanwhile, during the equalization period P... EQ During the period, the second boost prevents voltage V BPb The second boost protection voltage V is applied to the common source line CSL (S235). BPb The voltage can be transferred to the channel region of the cell string via the source-select transistor SST. This is because the first boost prevents the voltage V... BPa Second boost prevent voltage V BPb It is transmitted to the channel area in the cell string, so even the equalization voltage V EQ The voltage V is applied to word lines WL1 to WLn (S255), and thereafter, the equalization voltage V of the word lines is... EQ Discharging can also minimize the phenomenon of negative boosting of the channel voltage of the cell string. Therefore, the positive boost that may occur in the word line during the recovery step can be minimized. As a result, the shift width of the threshold voltage distribution of the memory cell can be minimized, and thus, the impact of read disturbances can be reduced.

[0118] According to the reference Figures 7 to 9 In the described embodiment, the boost prevention voltage can be transferred from the bit line to the channel region in the cell string via a drain-select transistor. On the other hand, according to the reference... Figure 10 and Figure 11 In the described embodiment, the boost protection voltage can be transmitted from the common source line to the channel region in the cell string via a source-select transistor. According to the reference... Figure 12 and Figure 13 In the described embodiment, the first boost protection voltage and the second boost protection voltage can be transmitted from both sides of the bit line and the common source line to the channel region in the cell string via the drain selection transistor and the source selection transistor, respectively.

[0119] Figure 14 This is a block diagram of a memory system 1000, which includes... Figure 1 Semiconductor memory device 100.

[0120] refer to Figure 14 The memory system 1000 may include a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 The semiconductor memory device described. Repeated descriptions are omitted below.

[0121] Memory controller 1100 can connect to a host and semiconductor memory device 100. Memory controller 1100 can be configured to access semiconductor memory device 100 in response to requests from the host. For example, memory controller 1100 can be configured to control read, write, erase, and background operations of semiconductor memory device 100. Memory controller 1100 can be configured to provide an interface between semiconductor memory device 100 and host. Memory controller 1100 can be configured to drive firmware for controlling semiconductor memory device 100.

[0122] The memory controller 1100 may include random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 may be used as at least one of the following: operating memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 can control the overall operation of the memory controller 1100. Furthermore, during write operations, the memory controller 1100 may temporarily store programming data provided from the host.

[0123] The host interface 1130 may include protocols for performing data exchange between the host and the memory controller 1100. As an exemplary embodiment, the memory controller 1100 may be configured to communicate with the host via at least one of a variety of interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0124] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface 1140 may include a NAND interface or a NOR interface.

[0125] Error correction block 1150 can be configured to detect and correct errors in data received from semiconductor memory device 100 using error correction codes (ECC). As an exemplary embodiment, the error correction block can be provided as a component of memory controller 1100.

[0126] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As an exemplary embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), or universal flash storage (UFS).

[0127] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) can include a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0128] As another example, the memory system 1000 is provided as one of a variety of components of an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, web tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3D TV, digital recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, and digital video player, device capable of transmitting and receiving information in a wireless environment, one of a variety of electronic devices for configuring a home network, one of a variety of electronic devices for configuring a computer network, one of a variety of electronic devices for configuring a telematics network, RFID device, or one of a variety of components for configuring a computing system.

[0129] As an exemplary embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in methods such as: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processed stacked package (WSP).

[0130] Figure 15 It is a diagram. Figure 14 A block diagram of an application example of a memory system.

[0131] refer to Figure 15 The memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0132] exist Figure 15 In this context, the multiple groups can communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is similarly configured and operated.

[0133] Each group can be configured to communicate with the memory controller 2200 via a shared channel. The memory controller 2200 can be connected to a reference... Figure 14 The memory controller 1100 described is similarly configured and can be configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0134] Figure 16 This is a block diagram illustrating a computing system, which includes a reference... Figure 15 The memory system described.

[0135] The computing system 3000 may include a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0136] The memory system 2000 can be electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 can be stored in the memory system 2000.

[0137] exist Figure 16 In this configuration, the semiconductor memory device 2100 can be connected to the system bus 3500 via the memory controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the memory controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

[0138] exist Figure 16 The reference is provided in the middle. Figure 15 The memory system 2000 is described. However, the memory system 2000 can be described using references. Figure 14 The memory system 1000 described herein is used instead. As an exemplary embodiment, the computing system 3000 may be configured to include a reference... Figure 14 and Figure 15 The memory systems described are 1000 and 2000.

Claims

1. A semiconductor memory device comprising: a cell string including at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor; and a peripheral circuit configured to perform a read operation on a selected memory cell among the plurality of memory cells, wherein the peripheral circuit is configured to: read data stored in the selected memory cell by applying a read voltage to a selected word line among word lines connected to the plurality of memory cells, and by applying a pass voltage to unselected word lines; apply an on voltage to a drain select line connected to the drain select transistor; apply an off voltage to a source select line connected to the source select transistor while the on voltage is applied to the drain select line; and apply a boost prevention voltage to the bit line while an equalization voltage is applied to the word lines.

2. The semiconductor memory device according to claim 1, wherein the boost prevention voltage is a same voltage as a precharge voltage applied to the bit line at a start of the read operation.

3. The semiconductor memory device according to claim 1, wherein the boost prevention voltage is a voltage greater than a precharge voltage applied to the bit line at a start of the read operation.

4. The semiconductor memory device according to claim 1, wherein the equalization voltage is greater than the read voltage and less than the pass voltage.

5. The semiconductor memory device according to claim 1, wherein the equalization voltage is a same voltage as the pass voltage.

6. A semiconductor memory device comprising: a cell string including at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor; and a peripheral circuit configured to perform a read operation on a selected memory cell among the plurality of memory cells, wherein the peripheral circuit is configured to: read data stored in the selected memory cell by applying a read voltage to a selected word line among word lines connected to the plurality of memory cells, and by applying a pass voltage to unselected word lines; apply an on voltage to a source select line connected to the source select transistor; apply an off voltage to a drain select line connected to the drain select transistor while the on voltage is applied to the source select line; and apply a boost prevention voltage to the common source line while an equalization voltage is applied to the word lines.

7. A method of operating a semiconductor memory device, the semiconductor memory device including a cell string including at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor, the method comprising: applying a read voltage to a selected word line among a plurality of word lines respectively connected to the plurality of memory cells, and applying a pass voltage to unselected word lines; applying a turn-on voltage to a drain select line connected to the drain select transistor; applying a turn-off voltage to a source select line connected to the source select transistor; transferring a boost prevention voltage to the drain select transistor through the bit line; and applying an equalization voltage to the plurality of word lines.

8. The method of claim 7, further comprising, before applying the read voltage to the selected word line among the plurality of word lines respectively connected to the plurality of memory cells, and applying the pass voltage to the unselected word lines: applying a pre-charge voltage to the bit line, wherein the boost prevention voltage is the same voltage as the pre-charge voltage.

9. The method of claim 7, further comprising, before applying the read voltage to the selected word line among the plurality of word lines respectively connected to the plurality of memory cells, and applying the pass voltage to the unselected word lines: applying a pre-charge voltage to the bit line, wherein the boost prevention voltage is greater than the pre-charge voltage.

10. The method of claim 7, wherein the equalization voltage is greater than the read voltage and less than the pass voltage.

11. The method of claim 7, wherein the equalization voltage is the same voltage as the pass voltage.

12. A method of operating a semiconductor memory device, the semiconductor memory device including a cell string including at least one drain select transistor connected to a bit line, at least one source select transistor connected to a common source line, and a plurality of memory cells connected between the drain select transistor and the source select transistor, the method comprising: applying a read voltage to a selected word line among a plurality of word lines respectively connected to the plurality of memory cells, and applying a pass voltage to unselected word lines; applying a turn-on voltage to a source select line connected to the source select transistor; applying a turn-off voltage to a drain select line connected to the drain select transistor; transferring a boost prevention voltage to the source select transistor through the common source line; and applying an equalization voltage to the plurality of word lines.

13. The method of claim 12, further comprising, before applying the read voltage to the selected word line among the plurality of word lines respectively connected to the plurality of memory cells, and applying the pass voltage to the unselected word lines: applying a pre-charge voltage to the bit line, wherein the boost prevention voltage is the same voltage as the pre-charge voltage.

14. The method of claim 12, further comprising, before applying the read voltage to the selected word line among the plurality of word lines respectively connected to the plurality of memory cells, and applying the pass voltage to the unselected word lines: applying a pre-charge voltage to the bit line, wherein the boost prevention voltage is greater than the pre-charge voltage.

15. The method of claim 12, wherein the equalization voltage is greater than the read voltage and less than the pass voltage.

16. The method of claim 12, wherein the equalization voltage is the same voltage as the pass voltage.

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