Method of manufacturing an electronic device

Abstract

A method of fabricating an electronic device includes providing a substrate including a non-discarded portion and a discarded portion adjacent to the non-discarded portion. A first test lead is formed extending through the non-discarded portion and the discarded portion. The substrate is cut in alignment with a target line, where the target line aligns a boundary between the non-discarded portion and the discarded portion. A first conduction test is performed on the first test lead. When a result of the first conduction test is a short circuit, it is determined that the substrate is in an off-target cut state, or when the result of the first conduction test is an open circuit, it is determined that the substrate is in a target cut state.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing an electronic device, and more particularly to a method for manufacturing an electronic device capable of detecting the results of cutting and grinding during the manufacturing process. Background Technology

[0002] Modern electronic devices often feature tiling display panels to provide information to users. A tiling display panel consists of multiple interconnected individual display panels with a borderless design to minimize gaps between adjacent panels. Therefore, the manufacturing process of these individual display panels requires scribe / break (SB) and grinding steps to remove the borders. Furthermore, after slicing and grinding, the display panels must be inspected to ensure they meet specifications. Currently, this is done by personnel using an optical microscope (OM), which is time-consuming and increases the possibility of human error. Summary of the Invention

[0003] One embodiment of this disclosure provides a method for manufacturing an electronic device, comprising the following steps: Providing a substrate, wherein the substrate includes a non-discarded portion and a discarded portion adjacent to the non-discarded portion. Forming a first test wire extending through the non-discarded portion and the discarded portion. Cutting the substrate with a target line aligned to the boundary between the non-discarded portion and the discarded portion. Performing a first conductivity test on the first test wire. Determining that the substrate is in a deviated-from-target-cut state when the result of the first conductivity test is a short circuit, or determining that the substrate is in a target-cut state when the result of the first conductivity test is an open circuit. Attached Figure Description

[0004] Figure 1 The diagram shown is a top view of the substrate of an electronic device that has not been cut or polished in the first embodiment of this disclosure.

[0005] Figure 2 The diagram shown is a top view of the substrate of the cut electronic device in the first embodiment of this disclosure.

[0006] Figure 3 The image shown is a top view of the substrate of the polished electronic device in the first embodiment of this disclosure.

[0007] Figure 4 The diagram shows a flowchart of the steps involved in manufacturing an electronic device according to the first embodiment of this disclosure.

[0008] Figure 5 The diagram shown is a top view of the substrate of an electronic device that has not been cut or ground, according to the second embodiment of this disclosure.

[0009] Figure 6 The diagram shows a schematic of a substrate of a portion of an electronic device that has been cut and polished according to the third embodiment of this disclosure.

[0010] Figure 7 The image shown is a top view of the substrate of an electronic device that has not been cut or ground, according to the fourth embodiment of this disclosure.

[0011] Figure 8 The diagram shown is a schematic representation of a substrate of a portion of an electronic device that has been cut and polished according to the fifth embodiment of this disclosure.

[0012] Figure 9 The image shown is a top view of the substrate of an electronic device that has not been cut or ground, according to the sixth embodiment of this disclosure.

[0013] Figure 10 The diagram shown is a top view of the substrate of the electronic device that has been cut and polished according to the sixth embodiment of this disclosure.

[0014] Explanation of reference numerals in the attached drawings: 10 – Electronic device; 100 – Substrate; 1001-1004, 1011, 1013, 1221-1224 – Edge; 100F, 100R – Surface; 100S1-100S3 – Side surface; 1021-1024, 1041-1044 – Target line; 1061-1066, 1341-1346 – Specification line; 1081, 1083, 1085, 1087, 1141, 1143, 1145, 1147 – Test leads; 1101-110 3. 1161-1163, 1261-1263, 1301-1303 ~ wires; 1121-1122, 1181-1182, 1281-1282, 1321-1322 ~ test pads; 1201-1204, 1241-1242, 1361-1363 ~ line segments; AA ~ display area; BD ~ boundary; DP ~ discarded portion; NDP ~ non-discarded portion; OLB ~ external pin connection portion; PA ~ peripheral area; S100-S116 ~ steps; X, Y, Z ~ directions. Detailed Implementation

[0015] This disclosure can be understood by referring to the following detailed description and accompanying drawings. It should be noted that, for ease of understanding and to keep the drawings concise, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0016] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0017] It should be understood that when an element or membrane is referred to as being "on," "set on," or "connected to" another element or membrane, it can be directly on or directly connected to that other element or membrane, or there may be an inserted element or membrane between them (in the indirect case). Conversely, when an element is referred to as being "directly on," "directly set on," or "directly connected to" another element or membrane, there may be no inserted element or membrane between them. Furthermore, the arrangement relationships between different elements can be interpreted according to the contents of the drawings.

[0018] Electrical connections can be direct or indirect. An electrical connection between two components can be a direct contact for transmitting electrical signals, with no other components between them. An electrical connection between two components can also be a bridge between them for transmitting electrical signals. An electrical connection can also be called a coupling.

[0019] Although the terms first, second, third… can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by first, second, third… in the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0020] It should be understood that the technical features of several different embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure.

[0021] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, touch display devices, curved display devices, or free-shape display devices. The electronic devices may be bendable or flexible. The electronic devices may include, for example, light-emitting diodes (LEDs), liquid crystals, fluorescent, phosphorescent, other suitable display media, or combinations thereof, but are not limited to these. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), mini-light-emitting diodes (mini LEDs), micro-light-emitting diodes (micro-LEDs), quantum dot (QDs) LEDs (e.g., QLEDs, QDLEDs), other suitable materials, or any arrangement or combination thereof, but are not limited to these. Display devices may include, for example, video wall display devices, but are not limited to these. The concepts or principles disclosed herein can also be applied to non-self-emissive liquid crystal displays (LCDs), but are not limited thereto.

[0022] The antenna device may be, for example, a liquid crystal antenna or other types of antenna, but is not limited thereto. The antenna device may include, for example, a splicing antenna device, but is not limited thereto. It should be noted that the electronic device may be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, control system, light source system, shelf system, etc., to support the display device, antenna device, or splicing device. The following description uses a display device as an example of an electronic device to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0023] The following diagram illustrates a direction X, a direction Y, and a direction Z. Direction Z may be perpendicular to surface 100F of substrate 100, while directions X and Y may be parallel to surface 100F of substrate 100. Direction Z may be perpendicular to directions X and Y, and direction X may be perpendicular to direction Y. The following diagram describes the spatial relationships of the structure based on directions X, Y, and Z.

[0024] Please refer to Figure 1The diagram shows a top view of the substrate of an electronic device without cutting and grinding, according to the first embodiment of this disclosure. The electronic device 10 in this embodiment uses a display device as an example, but is not limited thereto. Generally, a display device may include two opposing substrates and a display medium layer disposed between the two substrates. To highlight the technical features of this disclosure and to make the drawings more easily understood, the following figures only show one substrate, omitting the display medium layer and the other substrate. In other possible embodiments, the display device may include a substrate and a display medium layer disposed on the substrate.

[0025] Please also refer to Figure 1 and Figure 4 ,in Figure 4 The diagram shown is a flowchart illustrating the steps of a method for manufacturing an electronic device according to the first embodiment of this disclosure. Figure 4 First, step S100 is performed, providing a substrate, wherein the substrate includes a non-discarded portion and a discarded portion adjacent to the non-discarded portion. For example... Figure 1 The substrate 100 may be, for example, an array substrate of a display device, and may include, but is not limited to, a plurality of thin-film transistors for controlling the display medium layer, as well as signal lines and control circuits for controlling these thin-film transistors. The display medium layer may include the light-emitting elements described in the preceding paragraphs. In this embodiment, the display medium layer may include micro light-emitting diodes, and the light-emitting diodes may be disposed on the substrate 100, but are not limited thereto. However, for the sake of simplicity, the light-emitting diodes, thin-film transistors, signal lines, and control circuits are not shown in the figures.

[0026] In some other embodiments, substrate 100 may also be, for example, a color filter substrate for a display device, but is not limited thereto. Furthermore, the base layer material of substrate 100 may include glass, quartz, sapphire, polymers (such as polyimide (PI), polyethylene terephthalate (PET)) and / or other suitable materials to serve as a flexible or rigid substrate, but is not limited thereto.

[0027] The substrate 100 may include an edge 1001, an edge 1002, an edge 1003, and an edge 1004, and these edges may be connected to each other to form a rectangle. In the method disclosed herein, a target line 1021, a target line 1022, a target line 1023, and a target line 1024 may be pre-determined on a surface 100F of the substrate 100. These target lines may serve as target lines for a scribe / break (SB) process, and these target lines may be connected to each other to form a rectangle. Furthermore, a target line 1041, a target line 1042, a target line 1043, and a target line 1044 may be pre-determined on the surface 100F of the substrate 100. These target lines may serve as target lines for a grinding process, and these target lines may also be connected to each other to form a rectangle.

[0028] The substrate 100 may have a display area AA and a peripheral area PA surrounding the display area AA. To achieve a borderless design, the rectangular area formed by the target lines 1041, 1042, 1043, and 1044 of the grinding process may correspond to or approximately correspond to the display area AA of the display device. The target lines 1021, 1022, 1023, and 1024 of the cutting process may be located within the peripheral area PA of the display device, but are not limited thereto.

[0029] like Figure 1 Target line 1021 may be located between edge 1001 and target line 1041; target line 1022 may be located between edge 1002 and target line 1042; target line 1023 may be located between edge 1003 and target line 1043; and target line 1024 may be located between edge 1004 and target line 1044. Edges 1001, 1003, target lines 1021, 1023, 1041, and / or target line 1043 may be parallel to or substantially parallel to direction Y. Additionally, edges 1002, 1004, target lines 1022, 1024, 1042, and / or target line 1044 may be parallel to or substantially parallel to direction X.

[0030] To effectively control the results of the cutting and grinding processes, a specification line 1061 and a specification line 1062 can be defined based on the target line 1021, and a specification line 1063 can be defined based on the target line 1041. Specification line 1061 can be the lower specification limit (LSL) of the cutting process, and specification line 1062 can be the upper specification limit (USL) of the cutting process, with the target line 1021 located between specification lines 1061 and 1062. Furthermore, specification line 1063 can be the upper specification limit of the grinding process, with the target line 1041 located between specification lines 1062 and 1063.

[0031] Similarly, target line 1023 is located between specification line 1064 and specification line 1065, and target line 1043 is located between specification line 1065 and specification line 1066. Specification line 1064 can be the lower limit of the cutting process specification, specification line 1065 can be the upper limit of the cutting process specification, and specification line 1066 can be the upper limit of the grinding process specification.

[0032] like Figure 1 In direction X, the area of ​​the substrate to the right of target line 1021 or to the left of target line 1023, or the area of ​​the substrate between target line 1021 and target line 1023, can be defined as a non-discardable portion NDP. Furthermore, in direction X, the area of ​​the substrate to the left of target line 1021 or to the right of target line 1023, or the area of ​​the substrate between target line 1021 and edge 1001, or the area of ​​the substrate between target line 1023 and edge 1003, can be defined as a discardable portion DP. In other words, target line 1021 or target line 1023 can be defined as a boundary BD between the non-discardable portion NDP and the discardable portion DP. Moreover, the discardable portion DP can be removed after the cutting and polishing process, while at least a portion of the non-discardable portion NDP can be retained after the cutting and polishing process.

[0033] like Figure 4 Next, step S102 is performed to form a first test wire extending through the non-discarded portion and the discarded portion. For example... Figure 1 Test leads 1081 and / or test leads 1083 (both may also be referred to as first test leads) may be formed on the non-discarded portion NDP and the discarded portion DP, and test leads 1081 and test leads 1083 may have the same or similar structures. In this embodiment, test lead 1081 may be set corresponding to edge 1001 (such as the short side), and test lead 1083 may be set corresponding to edge 1003 (such as the short side), but is not limited thereto.

[0034] Test lead 1081 or test lead 1083 may include a lead 1101 (which may be referred to as a first lead), a lead 1102 (which may be referred to as a second lead), a lead 1103 (which may also be referred to as a second lead), a test pad 1121 (which may be referred to as a first test pad), and a test pad 1122 (which may also be referred to as a first test pad), but is not limited thereto.

[0035] Wire 1101 may be disposed on the discard portion DP or within the surrounding area PA, and may extend along the boundary BD (i.e., target line 1021 or target line 1023) between the non-discard portion NDP and the discard portion DP. The extension direction of wire 1101 may be parallel to direction Y, but is not limited thereto. Wires 1102 and 1103 may extend through the non-discard portion NDP and the discard portion DP, and the extension directions of wires 1102 and 1103 may be parallel to direction X, but are not limited thereto. Therefore, the extension directions of at least a portion of wire 1102 and at least a portion of wire 1103 are different from the extension direction of wire 1101. Furthermore, one end of wire 1101 may be connected to one end of wire 1102, and the other end of wire 1101 may be connected to one end of wire 1103.

[0036] Test pads 1121 and 1122 can be disposed on the non-discardable portion NDP or within the display area AA. Test pad 1121 can be connected to the other end of wire 1102, and test pad 1122 can be connected to the other end of wire 1103. Therefore, test pad 1121 can be electrically connected to wire 1101 via wire 1102, and test pad 1122 can be electrically connected to wire 1101 via wire 1103. Thus, the method disclosed herein can measure the conductivity of test wire 1081 or test wire 1083 using test pads 1121 and 1122.

[0037] Conductors 1101, 1102, 1103, test pads 1121 and 1122 may be formed on the surface 100F of the substrate 100, but are not limited thereto. Conductors 1101, 1102, 1103, test pads 1121 and 1122 may include metals, transparent conductive materials, and other suitable types of conductive materials. In this embodiment, conductors 1101, 1102, and 1103 may include transparent conductive materials (such as indium tin oxide (ITO)), but are not limited thereto. Furthermore, the structure of test conductor 1081 and / or the structure of test conductor 1083 disclosed herein are not limited to this embodiment and may have other variations.

[0038] like Figure 4Next, step S104 is performed, aligning the substrate with a target line for cutting, wherein the target line is aligned with a boundary between the non-discarded portion and the discarded portion. In the cutting process, the target line can be used as the default cutting line, and the substrate can be cut by aligning with the cutting line. However, due to limitations in the machine's alignment accuracy, the actual cutting line on the substrate may not perfectly coincide with the target line. Therefore, the target line can be an ideal cutting line. Furthermore, the term "align" can mean that the target line coincides with the boundary.

[0039] like Figure 1 A cutting process can be performed, and the substrate 100 can be cut according to target lines 1021 and / or 1023. During the cutting process, suitable cutting tools such as a cutting wheel or laser can be used to cut the substrate 100. Since the cutting position or direction may deviate during the cutting process, upper specification limits (such as specification lines 1062 or 1065) and lower specification limits (such as specification lines 1061 or 1064) are typically set to provide a permissible range for the process.

[0040] Please refer to Figure 1 and Figure 2 ,in Figure 2 The image shown is a top view of a cut electronic device substrate according to the first embodiment of this disclosure. Figure 2 When the cutting process is along the Y direction and corresponding Figure 1 After cutting substrate 100 using target lines 1021 and 1023. Figure 1 The portion of substrate 100 to the left of target line 1021 can be removed. Figure 1 A portion of the substrate 100 to the right of the target line 1023 can be removed, and wires 1101 in test wires 1081 and 1083 can also be removed, exposing an edge 1011 and an edge 1013 of the substrate 100. Alternatively, Figure 1 Taking the test lead 1081 as an example, after the cutting process cuts the substrate 100 along the Y direction and at the position between the lead 1101 and the specification line 1062 (the upper limit of the specification of the cutting process), the lead 1101 and a portion of the substrate 100 can be removed together.

[0041] Based on the above situation, such as Figure 2 The conductive path between test pads 1121 and 1122 in test lead 1081 is cut off after the cutting process, thus electrically isolating test pads 1121 and 1122. Furthermore, the above description also applies to test lead 1083, and will not be repeated here.

[0042] like Figure 4 Next, step S106 is performed to conduct a first conductivity test on the first test wire. For example... Figure 2A first conductivity test can be performed on test wire 1081 or test wire 1083 using test pads 1121 and 1122. Next, [further steps are taken]. Figure 4 In step S108, when the result of the first conductivity test is a short circuit, it is determined that the substrate is in a state deviating from the target cutting state, or when the result of the first conductivity test is an open circuit, it is determined that the substrate is in a target cutting state.

[0043] like Figure 1 and Figure 2 When the first conductivity test results in a short circuit, the conductive path between test pads 1121 and 1122 is not severed. This indicates that the cutting position in the cutting process may fall within the range between specification line 1061 (the lower limit of the cutting process specification) and the edge 1001 of substrate 100, or that the cutting process is not performed along the Y direction. Therefore, it can be determined that substrate 100 is deviating from the target cutting state, and this substrate can be determined to be a controlled product. If the substrate is determined to be a controlled product, it means that in the subsequent polishing process, the exposed edges after cutting need to be polished for a longer time, and the first conductivity test should be repeated after the polishing process.

[0044] like Figure 2 When the result of the first conductivity test is an open circuit, the conductive path between test pad 1121 and test pad 1122 is broken. This means that the cutting position of the cutting process falls within the range between wire 1101 and specification line 1062 (the upper limit of the specification of the cutting process), or it means that the cutting process may be cutting substrate 100 corresponding to target line 1021. Therefore, it can be determined that substrate 100 is in the target cutting state, and this substrate can be determined to be a qualified product.

[0045] like Figure 4 Next, step S110 is performed to form a second test lead on the non-discarded portion. For example... Figure 1 or Figure 2 Test leads 1141 and / or test leads 1143 (both may also be referred to as second test leads) may be formed on the non-discarded portion NDP, and test leads 1141 and test leads 1143 may have the same or similar structures. In this embodiment, test lead 1141 may be provided corresponding to edge 1001 (such as the short side), and test lead 1143 may be provided corresponding to edge 1003 (such as the short side), but is not limited thereto.

[0046] Test lead 1141 or test lead 1143 may include a lead 1161 (which may be referred to as a third lead), a lead 1162 (which may be referred to as a fourth lead), a lead 1163 (which may also be referred to as a fourth lead), a test pad 1181 (which may be referred to as a second test pad), and a test pad 1182 (which may also be referred to as a second test pad), but is not limited thereto.

[0047] Conductor 1161 may be disposed on the non-discarded portion NDP or within the display area AA, and may extend along the boundary BD (i.e., target line 1021 or target line 1023) between the non-discarded portion NDP and the discarded portion DP. The extension direction of conductor 1161 may be parallel to direction Y, but is not limited thereto. Conductors 1162 and 1163 may be disposed on the non-discarded portion NDP or within the display area AA, and conductors 1162 and 1163 may each include a line segment 1201 and a line segment 1202, but are not limited thereto. The extension direction of line segment 1201 may be parallel to direction X, and the extension direction of line segment 1202 may be parallel to direction Y, and one end of line segment 1201 may be connected to one end of line segment 1202, but is not limited thereto. Therefore, the extension directions of at least a portion of conductor 1162 and at least a portion of conductor 1163 are different from the extension direction of conductor 1161.

[0048] Furthermore, one end of wire 1161 can be connected to one end of wire 1162, and the other end of wire 1161 can be connected to one end of wire 1163. For example... Figure 1 One end of wire 1161 can be connected to one end of segment 1201 of wire 1162, and the other end of wire 1161 can be connected to one end of segment 1201 of wire 1163.

[0049] Test pads 1181 and 1182 can be placed on the non-discardable portion of the NDP or within the display area AA. Test pad 1181 can be connected to the other end of wire 1162, while test pad 1182 can be connected to the other end of wire 1163. For example... Figure 1 or Figure 2 Test pad 1181 can be connected to one end of segment 1202 of wire 1162, and test pad 1182 can be connected to one end of segment 1202 of wire 1163. Therefore, test pad 1181 can be electrically connected to wire 1161 via wire 1162, and test pad 1182 can be electrically connected to wire 1161 via wire 1163. Therefore, the method disclosed herein can measure the conductivity of test wire 1141 or test wire 1143 using test pads 1181 and 1182.

[0050] Conductors 1161, 1162, 1163, test pads 1181 and 1182 may be formed on the same surface (i.e., surface 100F) of the non-discarded portion NDP of substrate 100, but are not limited thereto. Conductors 1161, 1162, 1163, test pads 1181 and 1182 may include metals, transparent conductive materials, and other suitable types of conductive materials. In this embodiment, conductors 1161, 1162, and 1163 may include transparent conductive materials (such as indium tin oxide (ITO)), but are not limited thereto. Furthermore, the structure of test conductor 1141 and / or the structure of test conductor 1143 disclosed herein are not limited to this embodiment and may have other variations.

[0051] like Figure 4 Next, step S112 is performed to polish an edge exposed after the substrate has been cut. For example... Figure 2 The edges 1011 and / or 1013 exposed after the cutting process can be polished. For example, any suitable polishing tool can be used to polish the substrate 100. Taking into account the error in the polishing process, a specification upper limit (such as specification line 1063 or specification line 1066) can be set to provide a range that is permissible in the process.

[0052] Please refer to Figure 2 and Figure 3 ,in Figure 3 The image shown is a top view of the substrate of the polished electronic device according to the first embodiment of this disclosure. Figure 3 When the grinding process will Figure 2 After the edges 1011 and / or 1013 of the middle substrate 100 are ground to the target lines 1041 and / or 1043, Figure 2 A portion of the substrate 100 to the left of the target line 1041 can be removed. Figure 2 A portion of the substrate 100 to the right of the target line 1043 can be removed, along with a portion of the conductive lines 1102 and 1103, exposing one edge 1221 and one edge 1223 of the substrate 100. After the cutting and polishing process, the remaining non-discardable portion NDP of the substrate 100 can be retained, and edges 1221 and 1223 can substantially correspond to the edges of the display area AA to achieve a borderless design.

[0053] In other embodiments, Figure 2 The edges 1011 and / or 1013 of the intermediate substrate 100 may be ground to specification lines 1063 and / or 1066. At this time, Figure 3 The edge 1221 of the intermediate substrate 100 can be roughly aligned with the outer edge of the wire 1161 of the test wire 1141, or Figure 3 The edge 1223 of the middle substrate 100 is approximately aligned with the outer edge of the wire 1161 of the test wire 1143.

[0054] like Figure 4 Next, step S114 is performed to conduct a second conductivity test on the second test wire. For example... Figure 3 A second conductivity test can be performed on test wire 1141 or test wire 1143 using test pads 1181 and 1182. Next, proceed with... Figure 4 In step S116, when the result of the second conductivity test is an open circuit, it is determined that the substrate is in a state deviating from the target polishing state, or when the result of the second conductivity test is a short circuit, it is determined that the substrate is in a target polishing state.

[0055] like Figure 3 When the second conductivity test result is an open circuit, the conductive path between test pad 1181 and test pad 1182 is broken. This result indicates that the polishing process may have polished the edge of substrate 100 beyond specification line 1063 or specification line 1066, causing wire 1161 to potentially have been removed. Therefore, it can be determined that substrate 100 is deviating from the target polishing state, and this substrate can be determined to be a defective product.

[0056] like Figure 3 When the result of the second conductivity test is a short circuit, the conductive path between test pad 1181 and test pad 1182 is not broken. This indicates that the polishing process did not polish the edge of substrate 100 beyond specification line 1063 or specification line 1066, or that the polishing process may have polished the edge of substrate 100 to target line 1041 or target line 1043. Therefore, it can be determined that substrate 100 is in the target polishing state, and this substrate can be determined to be a qualified product.

[0057] It should also be noted that if the substrate 100 shows a short circuit in the first conductivity test, then after the polishing process, in addition to performing the second conductivity test, the first conductivity test must be repeated. If both the first and second conductivity tests show a short circuit, the substrate 100 must still be deemed a defective product. This is because it indicates that the discarded portion of the substrate 100 was not removed after the cutting and polishing processes, making it impossible to achieve a borderless design when using this substrate 100 for subsequent splicing processes.

[0058] Therefore, the electronic device manufacturing method of this embodiment eliminates the need to wait until the display module is manufactured before having personnel use an optical microscope (OM) to verify whether the frame or cutting and grinding results meet specifications. In the electronic device manufacturing method of this embodiment, a simple conductivity test can be conducted during the manufacturing process to determine whether the cutting or grinding results meet specifications, which can significantly shorten the inspection time and reduce the probability of human error.

[0059] Furthermore, in existing display devices, test pads are typically placed within the peripheral area PA, and various tests may have to wait until the display module is manufactured, resulting in the bezel width not being effectively reduced. However, in the manufacturing method of the electronic device in this embodiment, the test pad can be placed within the display area AA (e.g., the rectangular area formed by target lines 1041, 1042, 1043, and 1044), allowing the bezel to be effectively reduced to the edge of the display area AA, thereby achieving a borderless design.

[0060] In this embodiment (e.g.) Figure 1 Test leads 1081, 1083, 1141, and 1143 may be formed on the substrate 100 before the dicing process, but are not limited thereto. In some embodiments, test leads 1081 and 1083 may be formed on the substrate 100 before the dicing process, while test leads 1141 and 1143 may be formed on the substrate 100 after the dicing process and before the polishing process, but are not limited thereto.

[0061] Figure 4 The steps shown in the method for manufacturing an electronic device may not be exhaustive; other steps may be performed before, after, or between any of the shown steps. Furthermore, some steps may be performed in a different order. The method for manufacturing an electronic device in this embodiment may include steps S100 to S116. In some embodiments, the method for manufacturing an electronic device may include steps S100 to S108. Furthermore, the first conductivity test and the second conductivity test of this embodiment may also be applied to other embodiments.

[0062] The method of manufacturing the electronic device disclosed herein is not limited to the embodiments described above. Other embodiments of this disclosure will continue to be disclosed below; however, in order to simplify the description and highlight the differences between the embodiments, the same reference numerals are used to refer to the same elements, and repeated parts will not be described again.

[0063] Please refer to Figure 5 The diagram shown is a top view of the substrate of an electronic device without cutting and polishing, according to the second embodiment of this disclosure. This embodiment differs from the first embodiment (e.g., Figure 1The difference lies in that, in this embodiment, the test pads 1121 and 1122 of the test leads 1081 or 1083 can be disposed on an external lead bonding portion OLB and a non-discarded portion NDP within the peripheral area PA of the substrate 100. The external lead bonding portion OLB can be disposed on at least one side of the display area AA, such as... Figure 5 The external lead bonding portion OLB may be located on both sides of the display area AA in the Y direction, but is not limited thereto. It should be noted that the external lead bonding portion OLB may be removed after subsequent cutting and grinding of the edge 1002 and / or edge 1004 (such as the long side), but is not limited thereto.

[0064] Conductors 1102 and 1103 may each include a segment 1241 and a segment 1242, but are not limited thereto. The extension direction of segment 1241 may be parallel to direction X, and the extension direction of segment 1242 may be parallel to direction Y. One end of segment 1241 may be connected to one end of segment 1242, but is not limited thereto. Therefore, at least a portion of conductors 1102 and at least a portion of conductors 1103 have extension directions different from the extension direction of conductor 1101. Furthermore, one end of conductor 1101 may be connected to one end of segment 1241 of conductor 1102, and the other end of conductor 1101 may be connected to one end of segment 1241 of conductor 1103.

[0065] Test pad 1121 can be connected to one end of segment 1242 of wire 1102, and test pad 1122 can be connected to one end of segment 1242 of wire 1103. Therefore, test pad 1121 can be electrically connected to wire 1101 via wire 1102, and test pad 1122 can be electrically connected to wire 1101 via wire 1103. The remaining features of this embodiment are the same as those of the first embodiment and achieve the same effects, and will not be described again.

[0066] Please refer to Figure 6 The diagram shows a schematic representation of a substrate of a portion of an electronic device that has been cut and polished according to the third embodiment of this disclosure. To highlight the technical features of this embodiment and to make the drawings more easily understood, Figure 6 The substrate 100 corresponding to a portion of the test lead 1141 is shown, omitting the test lead 1143, as well as any remaining portions of the cut and polished test lead 1081 or test lead 1083. Figure 6 The substrate 100 (or the non-discarded portion NDP of the substrate 100) may include a surface 100F (or may be referred to as a first surface) and a surface 100R (or may be referred to as a second surface), and the surfaces 100F and 100R may be two surfaces of the substrate 100 that are opposite to each other in the Z direction. This embodiment differs from the first embodiment (e.g.) Figure 1The difference is that, in this embodiment, the wire 1161 can be formed on surface 100F while the test pads 1181 and 1182 can be formed on surface 100R.

[0067] Line segment 1202 of wire 1162 may extend in the Y direction to one edge of surface 100F of substrate 100, while line segment 1202 of wire 1163 may extend in the Y direction to the other edge of surface 100F of substrate 100, but is not limited thereto. In this embodiment, wire 1162 and wire 1163 may each include a line segment 1203 and a line segment 1204, but are not limited thereto. Line segment 1203 of wire 1162 may be formed on one side 100S1 of substrate 100 (or non-discarded portion NDP of substrate 100), and line segment 1203 of wire 1163 may be formed on one side 100S2 of substrate 100 (or non-discarded portion NDP of substrate 100), and line segment 1203 may extend in the Z direction, but is not limited thereto. Side 100S1 and side 100S2 can be two sides of substrate 100 that are opposite each other in the Y direction, and side 100S1 and side 100S2 can be connected to surface 100F and surface 100R.

[0068] Segment 1204 of conductors 1162 and 1163 may be formed on surface 100R, and segment 1204 may extend in direction Y, but is not limited thereto. One end of segment 1203 may be connected to one end of segment 1202 on surface 100F, and the other end of segment 1203 may be connected to one end of segment 1204 on surface 100R, and the other end of segment 1204 may be connected to test pad 1181 or test pad 1182.

[0069] Line segments 1203, 1204, test pads 1181 and 1182 can be formed after the cutting and grinding processes. Line segment 1203 can be formed on side surfaces 100S1 and 100S2 via a side printing process, but is not limited thereto. Therefore, test pads 1181 and 1182 can be electrically connected to the wire 1161 on surface 100F via a side printing process. Furthermore, wire 1161, line segments 1201 and 1202 can be formed before the grinding process, but is not limited thereto. The remaining features of this embodiment are the same as those of the above embodiments and achieve the same effects, and will not be repeated here.

[0070] Please refer to Figure 7 The diagram shown is a top view of the substrate of an electronic device without cutting and polishing, according to the fourth embodiment of this disclosure. This embodiment differs from the first embodiment (as shown in the diagram). Figure 1The difference lies in that, in this embodiment, edges 1002 and / or 1004 (such as long edges) can be cut and ground. In this embodiment, a specification line 1341 and a specification line 1342 can be defined based on target line 1022 (target line of the cutting process), and a specification line 1343 can be defined based on target line 1042 (target line of the grinding process). Specification line 1341 can be the lower limit of the specification of the cutting process, specification line 1342 can be the upper limit of the specification of the cutting process, and target line 1022 is located between specification line 1341 and specification line 1342. Furthermore, specification line 1343 can be the upper limit of the specification of the grinding process, and target line 1042 is located between specification line 1342 and specification line 1343.

[0071] Similarly, target line 1024 (the target line for the cutting process) is located between specification line 1344 and specification line 1345, and target line 1044 (the target line for the grinding process) is located between specification line 1345 and specification line 1346. Specification line 1344 can be the lower specification limit for the cutting process, specification line 1345 can be the upper specification limit for the cutting process, and specification line 1346 can be the upper specification limit for the grinding process.

[0072] like Figure 7 In the Y direction, the area of ​​the substrate below target line 1022 or above target line 1024, or the area of ​​the substrate between target line 1022 and target line 1024, can be defined as the non-discarded portion NDP. Furthermore, in the Y direction, the area of ​​the substrate above target line 1022 or below target line 1024, or the area of ​​the substrate between target line 1022 and edge 1002, or the area of ​​the substrate between target line 1024 and edge 1004, can be defined as the discarded portion DP. In other words, target line 1022 or target line 1024 can be defined as the boundary BD between the non-discarded portion NDP and the discarded portion DP.

[0073] Furthermore, the first test lead in this embodiment may include at least one test lead 1085 and / or at least one test lead 1087, and the second test lead may include at least one test lead 1145 and / or at least one test lead 1147. For example... Figure 7 Two test leads 1085 and two test leads 1145 can be set to correspond to edge 1002 (such as the long side), while two test leads 1087 and two test leads 1147 can be set to correspond to edge 1004 (such as the long side). The number of test leads is not fixed. Figure 7 The above is the limit.

[0074] Test lead 1085 or test lead 1087 may include a lead 1261 (which may be referred to as a first lead), a lead 1262 (which may be referred to as a second lead), a lead 1263 (which may also be referred to as a second lead), a test pad 1281 (which may be referred to as a first test pad) and a test pad 1282 (which may also be referred to as a first test pad), but is not limited thereto.

[0075] Wire 1261 can be disposed on the discarded portion DP or within the surrounding area PA, and can extend along the boundary BD (i.e., target line 1022 or target line 1024). The extension direction of wire 1261 can be parallel to direction X, but is not limited thereto. Wires 1262 and 1263 can extend through the non-discarded portion NDP and the discarded portion DP, and the extension directions of wires 1262 and 1263 can be parallel to direction Y, but are not limited thereto. Furthermore, one end of wire 1261 can be connected to one end of wire 1262, and the other end of wire 1261 can be connected to one end of wire 1263.

[0076] Test pads 1281 and 1282 can be disposed on the non-discardable portion NDP or within the display area AA. Test pad 1281 can be connected to the other end of wire 1262, and test pad 1282 can be connected to the other end of wire 1263. Therefore, test pad 1281 can be electrically connected to wire 1261 via wire 1262, and test pad 1282 can be electrically connected to wire 1261 via wire 1263.

[0077] Taking test lead 1085 as an example, when the result of the first conductivity test is a short circuit, the conductive path between test pad 1281 and test pad 1282 is not cut off. This indicates that the cutting position of the cutting process may fall within the range between specification line 1341 (the lower limit of the cutting process specification) and the edge 1002 of substrate 100, or the cutting process is not performed along direction X. Therefore, it can be determined that substrate 100 is deviating from the target cutting state, and this substrate can be determined to be a defective product.

[0078] When the result of the first conductivity test is an open circuit, the conductive path between test pad 1281 and test pad 1282 is broken. This means that the cutting position of the cutting process falls within the range between wire 1261 and specification line 1342 (the upper limit of the specification of the cutting process), or it means that the cutting process may be cutting substrate 100 corresponding to target line 1022. Therefore, it can be determined that substrate 100 is in the target cutting state, and this substrate can be determined to be a qualified product.

[0079] In this embodiment, wires 1261, 1262, 1263, test pads 1281 and 1282 may be formed on the surface 100F of the substrate 100, but are not limited thereto. Wires 1261, 1262, 1263, test pads 1281 and 1282 may include metals, transparent conductive materials, and other suitable types of conductive materials. In this embodiment, wires 1261, 1262, and 1263 may include transparent conductive materials (such as indium tin oxide), but are not limited thereto. Furthermore, the structure of the test wire 1085 and / or the structure of the test wire 1087 disclosed herein are not limited to this embodiment and may have other variations.

[0080] Test lead 1145 or test lead 1147 may include, but is not limited to, a lead 1301 (which may be referred to as a third lead), a lead 1302 (which may be referred to as a fourth lead), a lead 1303 (which may also be referred to as a fourth lead), a test pad 1321 (which may be referred to as a second test pad) and a test pad 1322 (which may also be referred to as a second test pad).

[0081] Wire 1301 may be disposed on the non-discardable portion NDP or within the display area AA, and may extend along the boundary BD (i.e., target line 1022 or target line 1024). The extension direction of wire 1301 may be parallel to direction X, but is not limited thereto. Wires 1302 and 1303 may be disposed on the non-discardable portion NDP or within the display area AA, and the extension directions of wires 1302 and 1303 may be parallel to direction Y, but are not limited thereto. Therefore, the extension directions of at least a portion of wires 1302 and at least a portion of wires 1303 are different from the extension direction of wire 1301. Furthermore, one end of wire 1301 may be connected to one end of wire 1302, and the other end of wire 1301 may be connected to one end of wire 1303.

[0082] Test pads 1321 and 1322 can be disposed on the non-discardable portion NDP or within the display area AA. Test pad 1321 can be connected to the other end of wire 1302, and test pad 1322 can be connected to the other end of wire 1303. Therefore, test pad 1321 can be electrically connected to wire 1301 via wire 1302, and test pad 1322 can be electrically connected to wire 1301 via wire 1303.

[0083] When the second conductivity test result is an open circuit, the conductive path between test pad 1321 and test pad 1322 is broken. This result indicates that the polishing process may have polished the edge of substrate 100 beyond specification line 1343 or specification line 1346, causing wire 1301 to possibly have been removed. Therefore, it can be determined that substrate 100 is deviating from the target polishing state, and this substrate can be determined to be a defective product.

[0084] When the result of the second conductivity test is a short circuit, the conductive path between test pad 1321 and test pad 1322 is not broken. This indicates that the polishing process did not polish the edge of substrate 100 beyond specification line 1343 or specification line 1346, or that the polishing process may have polished the edge of substrate 100 to target line 1042 or target line 1044. Therefore, it can be determined that substrate 100 is in the target polishing state, and this substrate can be determined to be a qualified product.

[0085] In this embodiment, wires 1301, 1302, 1303, test pad 1321, and test pad 1322 may be formed on the same surface (i.e., surface 100F) of the non-discarded portion NDP of substrate 100, but are not limited thereto. Wires 1301, 1302, 1303, test pad 1321, and test pad 1322 may include metals, transparent conductive materials, and other suitable types of conductive materials. In this embodiment, wires 1301, 1302, and 1303 may include transparent conductive materials (such as indium tin oxide), but are not limited thereto. Furthermore, the structure of test wire 1145 and / or the structure of test wire 1147 disclosed herein are not limited to this embodiment and may have other variations. The steps and remaining features of the manufacturing method in this embodiment are the same as in the first embodiment and can achieve the same effects as in the first embodiment, and will not be repeated here.

[0086] In this embodiment, multiple signal lines can be arranged in the peripheral area PA located on both sides of the display area AA in the Y direction. Therefore, the size (e.g., area) of the test wire 1085 or test wire 1087 can be smaller than the size of the test wire 1081 or test wire 1083 in the first embodiment, or the size of the test wire 1145 or test wire 1147 can be smaller than the size of the test wire 1141 or test wire 1143 in the first embodiment. For example, the length of the wire 1261 of the test wire 1085 or test wire 1087 can be smaller than the length of the wire 1101 of the test wire 1081 or test wire 1083, or the length of the wire 1301 of the test wire 1145 or test wire 1147 can be smaller than the length of the wire 1161 of the test wire 1141 or test wire 1143, but this is not a limitation.

[0087] Therefore, excessive signal line placement space occupied by test leads within the peripheral PA area can be avoided, and electrical interference from test leads to signal lines can be reduced. On the other hand, the number of test leads 1085 or 1087 can be greater than the number of test leads 1081 or 1083, or the number of test leads 1145 or 1147 can be greater than the number of test leads 1141 or 1143, to improve the accuracy of the detection results of the substrate 100 after the cutting and grinding process.

[0088] Please refer to Figure 8 The diagram shows a schematic representation of a substrate of a portion of an electronic device that has been cut and polished according to the fifth embodiment of this disclosure. To highlight the technical features of this embodiment and to make the drawings more easily understood, Figure 8 The substrate 100 corresponding to a portion of the test lead 1145 is shown, omitting the test lead 1147, as well as any remaining portions of the cut and polished test lead 1085 or test lead 1087. This embodiment differs from the fourth embodiment (e.g.) Figure 7 The difference is that, in this embodiment, the wire 1301 can be formed on surface 100F, while the test pads 1321 and 1322 can be formed on surface 100R.

[0089] In this embodiment, wires 1302 and 1303 may each include a line segment 1361, a line segment 1362, and a line segment 1363. The line segment 1361 of wires 1302 and 1303 may extend in the Y direction to an edge of the surface 100F of the substrate 100. One end of wire 1301 may be connected to one end of line segment 1361 of wire 1302, and the other end of wire 1301 may be connected to one end of line segment 1361 of wire 1303.

[0090] In wires 1302 and 1303, line segment 1362 may be formed on one side 100S3 of substrate 100 (or the non-discarded portion NDP of substrate 100), and line segment 1362 may extend along direction Z. Figure 8 For example, side 100S3 can be a side formed by grinding the substrate 100 to the target line 1042 of the grinding process, but is not limited thereto.

[0091] In wires 1302 and 1303, segment 1363 may be formed on surface 100R, and segment 1363 may extend in the direction Y, but is not limited thereto. One end of segment 1362 may be connected to one end of segment 1361 on surface 100F, and the other end of segment 1362 may be connected to one end of segment 1363 on surface 100R, and the other end of segment 1363 may be connected to test pad 1321 or test pad 1322.

[0092] Line segments 1362, 1363, test pad 1321, and test pad 1322 can be formed after the cutting and grinding processes, wherein line segment 1362 can be formed on side surface 100S3 through a side printing process, but is not limited thereto. Furthermore, wire 1301 and line segment 1361 can be formed before the grinding process, but are not limited thereto. The remaining features of this embodiment can be compared with those of the fourth embodiment (e.g., Figure 7 The same as the first embodiment, and can achieve the same effect, will not be described again.

[0093] Please refer to Figure 9 and Figure 10 , Figure 9 The image shown is a top view of the substrate of the electronic device in the sixth embodiment of this disclosure, undone and unpolished. Figure 10 The image shown is a top view of the substrate of an electronic device that has been cut and polished according to the sixth embodiment of this disclosure. Figure 9 As shown, this embodiment can be derived from the first embodiment (such as...). Figure 1 ) and the fourth embodiment (such as Figure 7 The first test lead in this embodiment may include test lead 1081 and test lead 1083 of the first embodiment and test lead 1085 and test lead 1087 of the fourth embodiment, while the second test lead in this embodiment may include test lead 1141 and test lead 1143 of the first embodiment and test lead 1145 and test lead 1147 of the fourth embodiment.

[0094] Test leads 1081 and 1141 can be set to correspond to edge 1001 (such as the short side), test leads 1083 and 1143 can be set to correspond to edge 1003 (such as the short side), two test leads 1085 and two test leads 1145 can be set to correspond to edge 1002 (such as the long side), and two test leads 1087 and two test leads 1147 can be set to correspond to edge 1004 (such as the long side), but are not limited thereto.

[0095] Therefore, for the cutting and grinding process, the first and second conductivity tests can be performed on the first and second test wires using the method described in the first embodiment to detect the cutting and grinding status of the four edges of the substrate 100. In this embodiment, the substrate 100 after cutting and grinding can be as follows: Figure 10 As shown, one edge 1221, one edge 1222, one edge 1223, and one edge 1224 of the substrate 100 can be aligned or substantially aligned with the edge of the display area AA of the display device, thereby achieving a borderless design. The remaining features of this embodiment are the same as those of the first and fourth embodiments, and can achieve the same effects as the first embodiment, and will not be described again.

[0096] In summary, in the manufacturing method of the electronic device disclosed herein, a first test lead and a second test lead are disposed on a substrate, and a first conductivity test and a second conductivity test are performed through test pads in the first and second test leads. Compared with existing inspection methods, the method disclosed herein can determine whether the cutting or grinding results meet specifications through a simple conductivity test during the manufacturing process, which can significantly shorten the inspection time and reduce the probability of human error. Furthermore, the test pads can be disposed within the display area, allowing the bezel to be effectively reduced to the edge of the display area, thus achieving a bezel-less design.

[0097] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for manufacturing an electronic device, characterized in that, include: A substrate is provided, wherein the substrate includes a non-discarded portion and a discarded portion adjacent to the non-discarded portion, the substrate having a first surface, a second surface opposite to the first surface, a first side surface connecting the first surface and the second surface, and a second side surface connecting the first surface and the second surface, wherein the second side surface is opposite to the first side surface; A first test lead is formed and extends through the non-discarded portion and the discarded portion; A second test lead is formed on the non-discarded portion, wherein the second test lead includes a first lead, a second lead, a third lead, a first test pad, and a second test pad, wherein the first test pad is electrically connected to the first lead through the second lead, and the second test pad is electrically connected to the first lead through the third lead, wherein the extension of the first lead does not overlap with the second lead and the third lead; The substrate is cut along a target line, wherein the target line is aligned with a boundary between the non-discarded portion and the discarded portion; A first conductivity test is performed on the first test wire; When the result of the first conductivity test is a short circuit, the substrate is determined to be in a state deviating from the target cutting state; or when the result of the first conductivity test is an open circuit, the substrate is determined to be in a target cutting state. Grind an edge of the substrate exposed after the cutting, wherein an extension direction of the first wire is parallel to the edge; A second conductivity test is performed on the second test wire; as well as When the result of the second conductivity test is an open circuit, the substrate is determined to be in a state deviating from the target polishing state; or when the result of the second conductivity test is a short circuit, the substrate is determined to be in a target polishing state. The second conductor includes a first segment disposed on the first surface, a second segment disposed on the first side surface, and a third segment disposed on the second surface. The third conductor includes a fourth segment disposed on the first surface, a fifth segment disposed on the second side surface, and a sixth segment disposed on the second surface.

2. The method for manufacturing an electronic device as described in claim 1, characterized in that, The first test lead includes a fourth lead and a third test pad. The fourth lead is disposed on the discarded portion and extends along the boundary. The third test pad is disposed on the non-discarded portion and is electrically connected to the fourth lead.

3. The method for manufacturing an electronic device as described in claim 2, characterized in that, The first test lead further includes a fifth lead extending through the non-discarded portion and the discarded portion, the third test pad being electrically connected to the fourth lead via the fifth lead, and at least a portion of the fifth lead having an extension direction different from that of the fourth lead.

4. The method for manufacturing an electronic device as described in claim 1, characterized in that, The substrate includes a display area and an external pin engagement portion disposed on at least one side of the display area. The first test lead includes a fourth lead and a third test pad. The fourth lead is disposed on the discard portion and extends along the boundary. The third test pad is disposed on the external pin engagement portion and the non-discard portion, and the third test pad is electrically connected to the fourth lead.

5. The method for manufacturing an electronic device as described in claim 1, characterized in that, The first conductor extends along the boundary.

6. The method for manufacturing an electronic device as described in claim 5, characterized in that, The first wire is formed on the first surface and the second test pad is formed on the second surface.

7. The method for manufacturing an electronic device as described in claim 5, characterized in that, The second test pad is electrically connected to the first wire via a side printing process.

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