Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: conformally covering a gate dielectric layer and a first work function material layer in a gate opening, after forming the first work function material layer in the gate opening, conformally covering a protection layer on the first work function material layer, in a step of forming a shielding layer covering a first region and exposing a second region, the protection layer protects the first work function material layer in the second region from being easily modified, in a step of removing the first work function material layer in the second region, the first work function material layer on a top of a fin in the second region and the first work function material layer on a sidewall of a bottom of the fin in the second region have a consistent removal rate, accordingly, the top of the fin in the second region is not easily exposed too quickly, so that after removing the first work function material layer in the second region, the top of the fin in the second region is not easily damaged, and when the semiconductor structure is working, the uniformity of the device performance is improved, and the reliability of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also shortened accordingly. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate structure on the channel is also deteriorated, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, i.e. the so-called short-channel effects (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the decrease of feature size, semiconductor technology gradually begins to transition from planar MOSFET to three-dimensional transistor with higher efficiency, such as FinFET. In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides, compared with planar MOSFET, the control ability of the gate structure on the channel is stronger, and the short-channel effects can be well suppressed; the gate structure also changes from the original polysilicon gate structure to the metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.

[0004] The existing method for forming a semiconductor structure still has deficiencies, and the reliability of the semiconductor structure needs to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a method for forming a semiconductor structure to improve the reliability of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region and a second region which are adjacent to each other, the substrate comprises a substrate, a fin which is separated from the substrate, an isolation layer which is located on the substrate and covers part of the sidewall of the fin, a dummy gate structure which is located on the isolation layer and crosses the fin, a sidewall layer which covers the sidewall of the dummy gate structure, and an interlayer dielectric layer which covers the sidewall of the sidewall layer and exposes the top of the dummy gate structure; removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; forming a gate dielectric layer which conformally covers the gate opening; forming a first work function material layer which conformally covers the gate dielectric layer in the gate opening; conformally covering the first work function material layer with a protective layer; after the protective layer is formed, forming a shielding layer which covers the first region and exposes the second region; removing the protective layer of the second region by taking the shielding layer as a mask; after the protective layer of the second region is removed, removing the first work function material layer of the second region by taking the shielding layer as a mask, and the remaining first work function material layer is used as a first work function layer.

[0007] Optionally, the material of the protective layer comprises silicon oxide.

[0008] Optionally, the protective layer is formed by using an atomic layer deposition process or a low-temperature oxidation process.

[0009] Optionally, in the step of conformally covering the first work function material layer with a protective layer, the thickness of the protective layer is 0.5-2 nm.

[0010] Optionally, the step of forming the shielding layer which covers the first region and exposes the second region comprises the following steps: forming a shielding material layer which covers the first region and the second region; forming a mask layer on the shielding material layer; removing the shielding material layer of the second region by taking the mask layer as a mask, and the remaining shielding material layer which is located in the first region is used as the shielding layer.

[0011] Optionally, the shielding material layer of the second region is removed by using a plasma dry etching process by taking the mask layer as a mask.

[0012] Optionally, in the step of removing the shielding material layer of the second region to form the shielding layer by taking the mask layer as a mask, the material of the mask layer is the same as that of the protective layer; and in the step of removing the protective layer of the second region by taking the shielding layer as a mask, the mask layer is removed.

[0013] Optionally, in the step of removing the protective layer of the second region by taking the shielding layer as a mask, a wet etching process is used.

[0014] ​Optionally, in the step of removing the protective layer of the second region by taking the shielding layer as a mask, a wet etching solution used in the step includes diluted hydrogen fluoride.

[0015] Optionally, in the step of removing the first work function material layer of the second region by taking the shielding layer as a mask, a wet etching process is used.

[0016] Optionally, the method for forming the semiconductor structure further includes: before conformally covering the first work function material layer in the gate opening, forming an etching stop layer conformally covering the gate opening.

[0017] Optionally, in the step of forming the etching stop layer, the etching stop layer is formed on the gate dielectric layer.

[0018] Optionally, the method for forming the semiconductor structure further includes: after removing the first work function material layer of the second region, removing the shielding layer.

[0019] Optionally, a dry etching process is used to remove the shielding layer.

[0020] Optionally, the method for forming the semiconductor structure further includes: after removing the shielding layer, removing the remaining protective layer.

[0021] Optionally, an isotropic dry etching process is used to remove the remaining protective layer.

[0022] Optionally, the isotropic dry etching process includes a Siconi etching process.

[0023] Optionally, the method for forming the semiconductor structure further includes: after removing the remaining protective layer, forming a second work function layer conformally covering the second region.

[0024] Optionally, the method for forming the semiconductor structure further includes: after forming the second work function layer conformally covering the second region, forming a gate layer on the second work function layer.

[0025] Optionally, a material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0026] Optionally, the sidewall layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0027] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0028] In the method for forming the semiconductor structure provided by the embodiment of the present application, the gate dielectric layer is conformally covered; the first work function material layer is formed in the gate opening and conformally covers the gate dielectric layer; after the first work function material layer is formed in the gate opening, the protection layer is conformally covered on the first work function material layer; in the step of forming the shielding layer covering the first region and exposing the second region, the protection layer protects the first work function material layer of the second region, so that the first work function material layer is not easily modified, and thus in the step of removing the first work function material layer of the second region, the removal rate of the first work function material layer at the top of the fin and the first work function material layer of the sidewall at the bottom of the fin in the second region is easily consistent, and correspondingly, the first work function material layer at the top of the fin in the second region is not easily exposed too fast, and thus after the first work function material layer of the second region is removed, the top of the fin in the second region is not easily damaged, which is beneficial to improving the uniformity of the device performance and improving the reliability of the semiconductor structure when the semiconductor structure works.

[0029] In an optional solution, the method for forming the semiconductor structure further includes, before the first work function material layer is conformally covered in the gate opening, forming an etching stop layer conformally covering the gate opening. In the step of forming the shielding layer covering the first region and exposing the second region, because the protection layer protects the first work function material layer of the second region, so that the first work function material layer is not easily modified, in the step of removing the first work function material layer of the second region, the removal rate of the first work function material layer at the top of the fin and the first work function material layer of the sidewall at the bottom of the fin in the second region is easily consistent, and correspondingly, the etching stop layer below the first work function material layer at the top of the fin in the second region is not easily exposed too fast, and thus after the first work function material layer of the second region is removed, the etching stop layer at the top of the fin in the second region is not easily damaged, and subsequently, the second work function layer is formed in the second region, and the ions in the second work function layer are not easily diffused into the top of the fin in the second region through the etching stop layer, and thus when the semiconductor structure works, the leakage current at the top of the fin in the second region is not easily generated, which is beneficial to improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figures 1 to 6 It is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0031] Figures 7 to 18 It is a structure diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The reliability of the currently formed semiconductor structure needs to be improved. The reasons for the poor performance of the semiconductor structure are analyzed in combination with a method for forming a semiconductor structure.

[0033] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0034] like Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 In the cross-sectional view at AA, a substrate is provided, the substrate including a first region I and a second region II adjacent to the first region I, the substrate including a substrate 1 and a fin 2 located on the substrate 1; an isolation layer 3 is formed on the substrate 1 where the fin 2 is exposed, the isolation layer 3 covering a portion of the sidewalls of the fin 2; a pseudo-gate structure (not shown) is formed on the isolation layer 3, spanning the fin 2 and covering a portion of the top wall and a portion of the sidewalls of the fin 2; a sidewall layer 7 is formed on the sidewalls of the pseudo-gate structure; after forming the sidewall layer 7, an interlayer dielectric layer 4 is formed on the side of the pseudo-gate structure, the interlayer dielectric layer 4 covering the fin 2 and the sidewalls of the pseudo-gate structure; the pseudo-gate structure is removed, and a gate opening 5 is formed in the interlayer dielectric layer 4; a gate dielectric layer (not shown), an etch stop layer 8 located on the gate dielectric layer, and a first work function material layer 6 located on the etch stop layer 8 are formed in the gate opening 5.

[0035] like Figure 3 As shown, a shielding layer 9 is formed that covers the first region I and exposes the second region II, with the top of the shielding layer 9 exceeding the interlayer dielectric layer 4. The steps for forming the shielding layer 9 include: forming a shielding material layer (not shown) covering the first region I and the second region II; forming a mask layer 10 on the shielding material layer, the mask layer 10 covering the first region I and exposing the second region II; etching the shielding material layer using the mask layer 10 as a mask, with the remaining shielding material layer serving as the shielding layer 9.

[0036] like Figure 4 As shown, after forming the masking layer 9, the masking layer 10 is removed.

[0037] like Figure 5 As shown, after removing the mask layer 10, the first work function material layer 6 exposed by the shielding layer 9 is removed, and the remaining first work function material layer 6 located in the first region I is used as the first work function layer 11.

[0038] like Figure 6 As shown, after forming the first function layer 11, the occlusion layer 9 is removed.

[0039] In the step of forming the shielding layer 9, the shielding material layer is etched using a plasma dry etching process. The plasma in the plasma dry etching process enters the first work function material layer 6, causing material modification of the first work function material layer 6 exposed by the shielding layer 9. This is because, during the formation of the shielding layer 9, the first work function material layer 6 at the top of the fin 2 is exposed first. Figure 6 (circled in the middle) Therefore, the degree of modification of the first work function material layer 6 at the top of fin 2 is greater than that of the first work function material layer 6 in the other areas of fin 2. In addition, due to the tip effect of the etching process, the first work function material layer 6 at the top of fin 2 is more damaged by the plasma dry etching process. As a result, during the removal of the first work function material layer 6 exposed by the shielding layer 9, the removal rate of the first work function material layer 6 at the top of fin 2 is faster than that at the bottom sidewall of fin 2. Correspondingly, the etching stop layer 8 at the top of fin 2 in the second region II is exposed prematurely. After the first work function material layer 6 on fin 2 in the second region II is completely removed, the etching stop layer at the top of fin 2 in the second region II is easily damaged. During the subsequent formation of the semiconductor structure, a second work function layer is formed in the second region II. Ions in the second work function layer can easily pass through the damaged etching stop layer and diffuse into fin 2 in the second region II. When the semiconductor structure is working, the leakage current at the top of fin 2 in the second region is large, which leads to a decrease in the reliability of the semiconductor structure.

[0040] In extreme cases, the top of the fin 2 in the second region may be damaged, resulting in poor performance uniformity of the semiconductor structure during operation and reducing its reliability.

[0041] To address the aforementioned technical problem, a substrate is provided, comprising an adjacent first region and a second region. The substrate includes a substrate, fins discretely disposed on the substrate, an isolation layer located on the substrate and covering a portion of the sidewalls of the fins, a pseudo-gate structure located on the isolation layer spanning the fins, and an interlayer dielectric layer covering the sidewalls of the pseudo-gate structure. The pseudo-gate structure is removed, and a gate opening is formed in the interlayer dielectric layer. A first work function material layer is conformally covered in the gate opening. A protective layer is conformally covered on the first work function material layer. A shielding layer is formed covering the first region and exposing the second region. The protective layer of the second region is removed using the shielding layer as a mask. After removing the protective layer of the second region, the first work function material layer of the second region is removed using the shielding layer as a mask, with the remaining first work function material layer serving as the first work function layer.

[0042] The embodiment of the present application provides a semiconductor structure forming method, after a first work function material layer is formed in a gate opening, a conformal protection layer is covered on the first work function material layer, in a step of forming a shielding layer covering the first region and exposing the second region, the protection layer protects the first work function material layer of the second region, so that the first work function material layer is not easily modified, thereby in a step of removing the first work function material layer of the second region, the removal rate of the first work function material layer on the top of the fin and the first work function material layer on the sidewall of the bottom of the fin in the second region is easily consistent, correspondingly, the top of the fin in the second region is not easily exposed too fast, and then after the first work function material layer of the second region is removed, the top of the fin in the second region is not easily damaged, when the semiconductor structure works, the uniformity of the device performance is improved, and the reliability of the semiconductor structure is improved.

[0043] In order to make the above-mentioned purpose, characteristics and advantages of the embodiment of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0044] Figures 7 to 18 It is a structure schematic diagram corresponding to each step in the embodiment of the semiconductor structure forming method of the present application.

[0045] Reference Figure 7 And Figure 8 , Figure 8 For Figure 7 The cross-sectional view at BB provides a substrate, the substrate includes adjacent first region I and second region II, the substrate includes a substrate 100, a fin 101 separated on the substrate 100, an isolation layer 102 located on the substrate 100 and covering part of the sidewall of the fin 101, a dummy gate structure 103 located on the isolation layer 102 and crossing the fin 101, a sidewall layer 105 covering the sidewall of the dummy gate structure 103, and an interlayer dielectric layer 104 (not shown in the figure) covering the sidewall of the sidewall layer 105 and exposing the top of the dummy gate structure 103.

[0046] In the embodiment, the second region II is located between the first region I. In the embodiment, the first region I is a PMOS (Positive Channel Metal Oxide Semiconductor) device region, and the second region II is an NMOS (Negative channel Metal Oxide Semiconductor) device region. In other embodiments, the first region can also be an NMOS device region, and the second region can also be a PMOS device region.

[0047] The substrate 100 provides a process platform for forming a semiconductor structure. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0048] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100. Accordingly, the material of the fin 101 is silicon.

[0049] The isolation layer 102 is used to achieve electrical isolation between the fins 101.

[0050] In this embodiment, the material of the isolation layer 102 is a dielectric material. Specifically, the material of the isolation layer 102 includes one or more of silicon nitride, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride and boron carbon nitride. In this embodiment, the material of the isolation layer 102 includes silicon oxide.

[0051] The dummy gate structure 103 occupies process space for forming a gate structure.

[0052] In this embodiment, the dummy gate structure 103 is a stacked structure. Specifically, the dummy gate structure 103 includes a gate oxide layer (not shown in the figure) and a gate layer (not shown in the figure) on the gate oxide layer.

[0053] In this embodiment, the material of the gate oxide layer is silicon oxide and the material of the gate layer is polysilicon (poly).

[0054] It should be noted that the extension direction of the dummy gate structure 103 is the same as the extension direction of the junction between the first region I and the second region II.

[0055] It should be noted that in the step of providing the substrate, the substrate further includes a first source / drain doped layer (not shown in the figure) in the fin 101 on both sides of the dummy gate structure 103 in the first region I. When the semiconductor structure is in operation, the first source / drain doped layer 107 applies compression stress to the channel under the gate structure, thereby improving the migration rate of the carriers in the channel.

[0056] It should be noted that in the step of providing the substrate, the substrate further includes a second source / drain doped layer (not shown in the figure) in the fin 101 on both sides of the dummy gate structure 103 in the second region II. When the semiconductor structure is in operation, the second source / drain doped layer applies tensile stress to the channel under the gate structure, thereby improving the migration rate of the carriers in the channel.

[0057] In the step of providing the substrate, a sidewall layer 105 is further formed on the sidewall of the dummy gate structure 103.

[0058] The sidewall layer 105 is used to define the forming area of the first source / drain doped layer and the second source / drain doped layer, and is also used to reduce the capacitive coupling effect between the dummy gate structure 103 and the first source / drain doped layer and the second source / drain doped layer, thereby improving the electrical performance of the semiconductor structure.

[0059] In this embodiment, the material of the sidewall layer 105 includes silicon nitride. In other embodiments, the material of the sidewall layer includes one or more of silicon oxide, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitride oxide, boron nitride, and boron carbon nitride.

[0060] The interlayer dielectric layer 104 is used to electrically isolate adjacent devices. In a subsequent step, the dummy gate structure 103 is removed, and a gate opening is formed in the interlayer dielectric layer 104.

[0061] In this embodiment, the material of the interlayer dielectric layer 104 is an insulating material. Specifically, the material of the interlayer dielectric layer 104 includes silicon oxide.

[0062] Referring to Figure 9 , the dummy gate structure 103 is removed, and a gate opening 106 is formed in the interlayer dielectric layer 104.

[0063] The gate opening 106 is prepared for the subsequent formation of a gate structure.

[0064] In this embodiment, a wet etching process is used to remove the dummy gate structure 103.

[0065] In this embodiment, the dummy gate structure 103 includes a gate oxide layer and a gate layer on the gate oxide layer, the material of the gate oxide layer is silicon oxide, and the material of the gate layer is polysilicon. Correspondingly, the wet etching solution includes tetramethylammonium hydroxide (TMAH) and hydrogen fluoride solution.

[0066] Referring to Figure 10 , the method for forming the semiconductor structure includes forming a gate dielectric layer (not shown in the figure) conformally covering the gate opening 106.

[0067] The gate dielectric layer is used to electrically isolate the fin 101 and the subsequently formed gate structure. It should be noted that the material of the gate dielectric layer is a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0068] In this embodiment, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer can also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0069] In this embodiment, the gate dielectric layer is formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

[0070] With reference to the above Figure 10 A conformal etch stop layer 108 is formed on the isolation layer 102 and the fin 101 exposed by the gate opening 106, and the etch stop layer 108 is formed on the gate dielectric layer.

[0071] In the subsequent formation of the semiconductor structure, the etch stop layer 108 is used to protect the fin 101 from damage.

[0072] In this embodiment, the etch stop layer 108 is a stacked structure. In other embodiments, the etch stop layer can also be a single film layer. Specifically, the etch stop layer 108 includes a TiSiN layer and a TaN layer on the TiSiN layer.

[0073] In this embodiment, the etch stop layer 108 is formed by an atomic layer deposition process. The atomic layer deposition process has good step coverage, so that the etch stop layer 108 can be formed on the sidewall and top wall of the fin 101, as well as on the isolation layer 102. In other embodiments, the etch stop layer can also be formed by a chemical vapor deposition process.

[0074] In this embodiment, the etch stop layer 108 also functions as a barrier layer, which is used to block the diffusion of ions in the first work function layer and the second work function layer formed subsequently into the gate dielectric layer and the fin 101.

[0075] It should be noted that the etching stop layer 108 is not too thick or too thin. The etching stop layer 108 will remain in the semiconductor structure. If the etching stop layer 108 is too thick, it will affect the adjustment of the threshold voltage of the semiconductor structure, so that the threshold voltage of the semiconductor structure cannot meet the process requirements, and the etching stop layer 108 is too thick, which will also compress the forming space of the remaining film layer. Subsequently, the first work function material layer is conformally covered in the gate opening, and the first work function material layer in the second region is removed, and the remaining first work function material layer is used as the first work function layer. If the etching stop layer 108 is too thin, the etching stop layer 108 cannot play the role of etching stop, the gate dielectric layer is easy to be damaged, and the gate dielectric layer cannot well electrically isolate the fin 102 and the subsequently formed gate structure, resulting in poor electrical performance of the semiconductor structure. In addition, if the etching stop layer 108 is too thin, the etching stop layer 108 cannot well block the ions in the subsequently formed gate structure from diffusing into the gate dielectric layer, so that the gate dielectric layer cannot well electrically isolate the fin 101 and the subsequently formed gate structure. In the extreme case, the ions in the gate structure are also easy to diffuse into the fin 101 through the etching stop layer 108. When the semiconductor structure works, the leakage current at the top of the fin 101 in the second region II is large, which reduces the reliability of the semiconductor structure. Even in a more extreme case, the top of the fin 101 in the second region II is damaged, and when the semiconductor structure works, the performance uniformity of the semiconductor structure is poor, which reduces the reliability of the semiconductor structure. In the embodiment, the thickness of the etching stop layer 108 is 5-15 nm. to

[0076] It should be noted that because the etching stop layer 108 includes a TiSiN layer and a TaN layer on the TiSiN layer, it can also play a role in adjusting the threshold voltage of the semiconductor structure.

[0077] Continuing to refer to Figure 10 In the gate opening 106, a first work function material layer conformally covering the gate dielectric layer is formed. Specifically, the first work function material layer 107 conformally covers the etching stop layer 108.

[0078] The first work function material layer 107 prepares for the subsequent formation of the first work function layer.

[0079] Specifically, the first work function layer is used as the work function metal of the first region I (i.e., the PMOS device region). Correspondingly, the material of the first work function material layer 107 includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide. In the embodiment, the material of the first work function material layer 107 includes titanium nitride.

[0080] In this embodiment, the first work function material layer 107 is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0081] It should be noted that the surface of the first work function material layer 107 is prone to oxidation during the formation of the first work function material layer 107. In this embodiment, the material of the first work function material layer 107 includes titanium nitride, and accordingly, the surface of the first work function material layer 107 will form titanium nitride oxide (TiON).

[0082] Reference Figure 11 The protective layer 109 is conformally covered on the first work function material layer 107.

[0083] Subsequently, a shielding material layer covering the first region I and the second region II is formed, and the shielding material layer in the second region II is removed to form a shielding layer covering the first region I and exposing the second region II. In the step of forming the shielding layer, the protective layer 109 protects the first work function material layer 107 in the second region II, so that the first work function material layer 107 is not easily modified, thereby making the removal rate of the first work function material layer 107 on the top of the fin 101 and the sidewall of the bottom of the fin 101 in the second region II consistent in the step of removing the first work function material layer 107 in the second region II. Accordingly, the top of the fin 101 in the second region II is not easily exposed too quickly, and thus the top of the fin 101 in the second region II is not easily damaged after the first work function material layer 107 in the second region II is removed. When the semiconductor structure is working, it is beneficial to improve the uniformity of device performance and improve the reliability of the semiconductor structure.

[0084] In the step of forming the shielding layer covering the first region I and exposing the second region II, because the protective layer 109 protects the first work function material layer 107 of the second region II from being modified, in the step of removing the first work function material layer 107 of the second region II, the removal rate of the first work function material layer 107 at the top of the fin 101 and the first work function material layer 107 at the sidewall of the bottom of the fin 101 in the second region II is easy to be consistent, and the etching stop layer 108 under the first work function material layer 107 at the top of the fin 101 in the second region II is not easy to be exposed too fast. After the first work function material layer 107 of the second region II is removed, the etching stop layer 108 at the top of the fin 101 in the second region II is not easy to be damaged. Accordingly, in the subsequent step of forming the second work function layer in the second region II, the ions in the second work function layer are not easy to diffuse into the top of the fin 101 in the second region II through the etching stop layer 108. When the semiconductor structure works, the top of the fin 101 in the second region II is not easy to have a leakage current, which is beneficial to improve the reliability of the semiconductor structure.

[0085] In the embodiment, the material of the protective layer 109 is an insulating material. In the step of removing the shielding material layer of the second region II by using a plasma dry etching process to form the shielding layer, compared with the case that the material of the protective layer 109 contains metal, the plasma is more difficult to pass through the insulating material, so that the first work function material layer 107 is more difficult to be modified.

[0086] In the embodiment, the material of the protective layer 109 includes silicon oxide. The Si-O bond in silicon oxide has a large bond energy and is difficult to be modified. In addition, silicon oxide is a commonly used dielectric material in the process and has a low cost, and has a high process compatibility. In the subsequent step of removing the protective layer 109, it is easy to remove the residual.

[0087] In the embodiment, the protective layer 109 is formed by using a low temperature oxidation process. The low temperature oxidation process has a good step coverage, so that the protective layer 109 can uniformly cover the first work function material layer 107, and the thickness uniformity of the protective layer 109 in each region of the first work function material layer 107 is high. In the subsequent process of forming the shielding layer covering the first region I and exposing the second region II, the protective layer 109 can well protect the first work function material layer 107 of the second region II, and the first work function material layer 107 is not easy to be modified. In other embodiments, the protective layer can also be formed by using an atomic layer deposition process.

[0088] It should be noted that in the step of conformally covering the first work function material layer 107 with a protective layer 109, the protective layer 109 should not be too thick or too thin. If the protective layer 109 is too thick, it will take too much process time to form the protective layer 109, and then it will take too much process time to remove the remaining protective layer 109. If the protective layer 109 is too thin, in the process of removing the shielding material layer of the second region II and forming a shielding layer covering the first region I and exposing the second region II, the protective layer 109 cannot well protect the top of the fin 101 of the second region II, resulting in the first work function material layer 107 at the top of the fin 101 being easily modified. In the subsequent step of removing the first work function material layer 107 of the second region II, the removal rate of the first work function material layer 107 at the top of the fin 101 of the second region II is faster than that of the first work function material layer 107 at the bottom sidewall of the fin 101. Accordingly, the etching stop layer 108 at the top of the fin 101 of the second region II is easily exposed too fast. After removing the first work function material layer 107 of the second region II, the etching stop layer 108 at the top of the fin 101 of the second region II is easily damaged. In the subsequent step of forming a second work function layer in the second region II, ions in the second work function layer are likely to pass through the damaged etching stop layer 108 and diffuse into the fin 101. When the semiconductor structure is working, the leakage current at the top of the fin 101 of the second region II is large, which reduces the reliability of the semiconductor structure. In the extreme case, the top of the fin 101 of the second region II is damaged, and when the semiconductor structure is working, the uniformity of the performance of the semiconductor structure is poor. In this embodiment, the thickness of the protective layer 109 is 5-50 nm. to

[0089] Referring to Figure 12 and Figure 13 , a shielding layer 111 covering the first region I and exposing the second region II is formed (as shown in Figure 13 ).

[0090] In the step of forming the shielding layer 111 covering the first region I and exposing the second region II, the protective layer 109 protects the first work function material layer 107 of the second region II from being modified. In the step of removing the first work function material layer 107 of the second region II, the removal rate of the first work function material layer 107 at the top of the fin 101 and the first work function material layer 107 at the sidewall of the bottom of the fin 101 in the second region II is consistent. Accordingly, the top of the fin 101 in the second region II is not easily exposed too fast, so that the top of the fin 101 in the second region II is not easily damaged after the first work function material layer 107 of the second region II is removed. When the semiconductor structure is working, the uniformity of the device performance is improved, and the reliability of the semiconductor structure is improved. Because the protective layer 109 protects the first work function material layer 107 of the second region II from being modified, the removal rate of the first work function material layer 107 at the top of the fin 101 and the first work function material layer 107 at the sidewall of the bottom of the fin 101 in the second region II is consistent. Accordingly, the etching stop layer 108 below the first work function material layer 107 at the top of the fin 101 in the second region II is not easily exposed too fast, so that the etching stop layer 108 at the top of the fin 101 in the second region II is not easily damaged after the first work function material layer 107 of the second region II is removed. Subsequently, a second work function layer is formed in the second region II. The ions in the second work function layer are not easily diffused into the top of the fin 101 in the second region II through the etching stop layer 108. When the semiconductor structure is working, the top of the fin 101 in the second region II is not easily subject to leakage current, which is beneficial to improve the reliability of the semiconductor structure.

[0091] The shielding layer 111 serves as a mask for subsequently removing the protective layer 109 and the first work function material layer 107 of the second region II.

[0092] In this embodiment, the material of the shielding layer 111 includes an anti-reflective coating (BARC). The anti-reflective coating has better filling property, which is beneficial to prevent voids from existing in the shielding layer 111 and improve the formation quality of the shielding layer 111.

[0093] The step of forming the shielding layer 111 covering the first region I and exposing the second region II includes: Figure 12 As shown, a shielding material layer 110 covering the first region I and the second region II is formed; a mask layer 112 is formed on the shielding material layer 110; and Figure 13 As shown, the shielding material layer 110 of the second region II is removed to form the shielding layer 111 covering the first region I and exposing the second region II.

[0094] In the embodiment, the spin coating process is used to form the shielding material layer 110. The spin coating process has the characteristics of mild process conditions and simple operation, and has remarkable effects in reducing pollution, saving energy and improving cost performance.

[0095] It should be noted that in the step of forming the shielding material layer 110, the thickness of the shielding material layer 110 is greater than the depth of the gate opening 106, so that the shielding material layer 110 is formed on the interlayer dielectric layer 104 while completely filling the gate opening 106. In the step of etching the shielding material layer 110 in the second region II to form the shielding layer 111, the top of the interlayer dielectric layer 104 in the first region I is not easily damaged.

[0096] In the step of forming the mask layer 112 on the shielding material layer 110, the mask layer 112 is a laminated structure, and the mask layer 112 includes a hard mask material layer 1121 and a photoresist layer 1122 located on the hard mask material layer 1121, and the photoresist layer 1122 has an opening 113 exposing the second region.

[0097] In the embodiment, the material of the hard mask material layer 1121 is the same as that of the protective layer 109.

[0098] In the embodiment, the material of the hard mask material layer 1121 includes low temperature oxide (LTO), which is formed by a low temperature oxidation process. Therefore, the hard mask material layer 1121 has a higher density and is more resistant to etching as an etching mask. In addition, silicon oxide is a commonly used dielectric material with low cost and high process compatibility, which is beneficial to reduce the process difficulty and cost of forming the hard mask material layer 1121.

[0099] In the embodiment, the low temperature oxidation process is used to form the hard mask material layer 1121. In other embodiments, the atomic layer deposition process can also be used to form the hard mask material layer.

[0100] The forming step of the photoresist layer 1122 includes: forming a photoresist material layer (not shown in the figure) on the hard mask material layer 1121; and performing exposure treatment on the photoresist material layer to form the photoresist layer 1122 with the opening 113.

[0101] In the embodiment, the spin coating process is used to form the photoresist material layer.

[0102] In the embodiment, the second region II is removed by using the mask layer 112 as a mask and adopting a plasma dry etching process to remove the shielding material layer 110 in the second region II, and the shielding material layer 110 in the first region I remains as a shielding layer 111. The plasma dry etching process has an anisotropic etching characteristic and good etching profile control, so that the morphology quality of the sidewall of the shielding layer 111 is good. In addition, by using the dry etching process, the shielding material layer 110 and the hard mask material layer 1121 can be etched in the same etching equipment by changing the etching gas.

[0103] In the step of removing the shielding material layer 110 in the second region II by using the plasma dry etching process, the etching gas includes one or more of hydrogen, nitrogen and CH4.

[0104] In the embodiment, the material of the hard mask material layer 1121 is the same as that of the protective layer 109, and correspondingly, the material of the hard mask layer 114 is the same as that of the protective layer 109. In the step of removing the protective layer 109 in the second region II by using the shielding layer 111 as a mask, the hard mask layer 114 is also removed. Therefore, in the subsequent process, the hard mask layer 114 does not need to be removed by additionally setting a process flow, which is beneficial to simplify the forming method of the semiconductor structure.

[0105] In the embodiment, in the step of removing the shielding material layer 110 in the second region II by using the mask layer 112 as a mask to form the shielding layer 111, the material of the mask layer 112 is the same as that of the protective layer 109. That is, in the step of removing the shielding material layer 110 in the second region II by using the mask layer 112 as a mask and adopting a plasma dry etching process, the photoresist layer 1122 in the mask layer 112 is completely removed, and the hard mask material layer 1121 is etched to form a hard mask layer 114.

[0106] It should be noted that, because the protective layer 109 conformally covers the first work function material layer 107, in the step of removing the shielding material layer 110 in the second region II by using a plasma dry etching process, hydrogen ions and nitrogen ions generated in the plasma etching process are not easy to penetrate into the first work function material layer 107 through the protective layer 109, and correspondingly, the first work function material layer 107 at the top of the fin 101 is not easy to be modified, so that in the subsequent step of removing the first work function material layer 107 exposed by the shielding layer 111, the removal rate of the first work function material layer 107 at the top of the fin 101 and the first work function material layer 107 on the sidewall of the bottom of the fin 101 in the second region II is easy to be consistent.

[0107] As Figure 14The protection layer 109 of the second region II is removed by taking the shielding layer 111 as a mask.

[0108] The protection layer 109 of the second region II is removed, and the first work function material layer 107 of the second region II is exposed, which is prepared for the subsequent removal of the first work function material layer 107 of the second region II.

[0109] In this embodiment, the protection layer 109 of the second region II is removed by taking the shielding layer 111 as a mask and using an isotropic etching process. The isotropic etching process can have an approximately same etching rate for the protection layer 109 on the sidewall of the fin 101 and on the top of the fin 101. Compared with the case of removing the protection layer of the second region II by using a dry etching process, the etching stop layer 108 on the top of the fin 101 is less likely to be damaged.

[0110] In this embodiment, the protection layer 109 of the second region II is removed by using a wet etching process. The wet etching process has a high etching rate, is simple to operate, and has a low process cost.

[0111] Specifically, in the step of removing the protection layer 109 of the second region II by using a wet etching process, the wet etching solution used includes a diluted hydrogen fluoride (DHF) solution.

[0112] It should be noted that in the step of removing the protection layer 109 of the second region II by using a hydrogen fluoride solution, the hydrogen fluoride solution can also remove the titanium nitride oxide (TiON) on the surface of the first work function material layer 107, which facilitates the subsequent removal of the first work function material layer 107 of the second region II.

[0113] It should be noted that in the step of removing the protection layer 109 of the second region II by taking the shielding layer 111 as a mask, the mask layer 112 is removed. Because in the formation of the shielding layer 111, the photoresist layer 1122 in the mask layer 112 is consumed, and the hard mask material layer 1121 is etched to form the hard mask layer 114. Here, removing the mask layer 112 refers to removing the hard mask layer 114.

[0114] The materials of the hard mask layer 114 and the protection layer 109 both include silicon oxide, and the hard mask layer 114 and the protection layer 109 of the second region II are removed simultaneously in one step, which is beneficial to simplify the formation process of the semiconductor structure.

[0115] Reference Figure 15 After the protection layer 109 of the second region II is removed, the first work function material layer 107 of the second region II is removed by taking the shielding layer 111 as a mask, and the remaining first work function material layer serves as a first work function layer 115.

[0116] The first work function material layer 107 in the second region II is removed to prepare for forming a second work function layer in the second region II later.

[0117] In this embodiment, the first work function material layer 107 in the second region II is removed by using a wet etching process with the shielding layer 111 as a mask. The wet etching process has a high etching rate, is simple to operate, and has low process cost.

[0118] Reference Figure 16 After the first work function material layer 107 in the second region II is removed, the shielding layer 111 is removed.

[0119] The shielding layer 111 is removed to expose the gate opening 106 to prepare for removing the remaining protective layer 109 later.

[0120] In this embodiment, the shielding layer 111 is removed by using an ashing process or a wet adhesive removal process.

[0121] Reference Figure 17 After the shielding layer 111 is removed, the remaining protective layer 109 is removed.

[0122] The remaining protective layer 109 is removed to expose the gate opening 106 to prepare for forming a second work function layer later.

[0123] In this embodiment, the remaining protective layer 109 is removed by using an isotropic dry etching process. The isotropic etching process can have approximately the same etching rate for the protective layer 109 on the sidewall of the fin 101 and the top of the fin 101 in the first region I. Compared with the case of removing the protective layer by using a dry etching process, the etching stop layer 108 on the top of the fin 101 in the first region I is less likely to be damaged.

[0124] In this embodiment, the isotropic dry etching process includes a Siconi etching process.

[0125] Reference Figure 18 After the remaining protective layer 109 is removed, a second work function layer 116 conformally covering the second region II is formed.

[0126] The second work function layer 116 is used to adjust the threshold voltage of a device formed in the second region II.

[0127] In this embodiment, the second region II is used to form an NMOS, and the material of the second work function layer 116 includes one or more of titanium aluminide, tantalum carbide, and titanium carbide.

[0128] It should be noted that in the step of forming the second work function layer 116 conformally covering the second region II, the second work function layer 116 is also formed on the first region I.

[0129] The method for forming the semiconductor structure further comprises: after forming the second work function layer 116 conformally covering the second region II, forming a gate layer 117 on the second work function layer 116.

[0130] In this embodiment, the material of the gate layer 117 comprises one or more of W, Cu, Ti, Ag, Pt and Ni.

[0131] It should be noted that the first work function layer 115 and the gate layer 117, and the second work function layer 116 and the gate layer 117 are all gate structures.

[0132] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate comprising a first region and a second region adjacent to the first region, the substrate comprising a substrate, fins on the substrate, an isolation layer on the substrate covering sidewalls of the fins, a dummy gate structure on the isolation layer across the fins, a sidewall layer covering sidewalls of the dummy gate structure, and an interlayer dielectric layer covering sidewalls of the sidewall layer and exposing top portions of the dummy gate structure; removing the dummy gate structure to form gate openings in the interlayer dielectric layer; forming a gate dielectric layer conformally covering the gate openings; forming a first work function material layer conformally covering the gate dielectric layer in the gate openings; forming an etching stop layer conformally covering the gate openings before conformally covering the first work function material layer in the gate openings, the etching stop layer being formed on the gate dielectric layer; forming a protection layer conformally covering the first work function material layer on the first work function material layer, the protection layer protecting the first work function material layer of the second region from being modified; after forming the protection layer, forming a blocking layer covering the first region and exposing the second region, the blocking layer having a hard mask layer formed thereon; removing the protection layer of the second region using the blocking layer as a mask, the material of the protection layer being the same as the material of the hard mask layer; after removing the protection layer of the second region, removing the first work function material layer of the second region using the blocking layer as a mask, the remaining first work function material layer serving as a first work function layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The material of the protection layer comprises silicon oxide.

3. The method of forming a semiconductor structure of claim 1, wherein The protection layer is formed by an atomic layer deposition process or a low-temperature oxidation process.

4. The method of forming a semiconductor structure of claim 1, wherein, In the step of conformally covering a protective layer on the first work function material layer, the thickness of the protective layer is to 5. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the blocking layer covering the first region and exposing the second region comprises: forming a blocking material layer covering the first region and the second region; forming a mask layer on the blocking material layer; removing the blocking material layer of the second region using the mask layer as a mask, the remaining blocking material layer in the first region serving as the blocking layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The blocking material layer of the second region is removed using a plasma dry etching process with the mask layer as a mask.

7. The method of forming a semiconductor structure of claim 5, wherein, The material of the mask layer is the same as the material of the protection layer in the step of removing the blocking material layer of the second region to form the blocking layer. The mask layer is removed in the step of removing the protection layer of the second region using the blocking layer as a mask.

8. The method of forming a semiconductor structure of claim 1, wherein, A wet etching process is used in the step of removing the protection layer of the second region using the blocking layer as a mask.

9. The method of forming a semiconductor structure of claim 8, wherein, The wet etching solution used in the step of removing the protection layer of the second region using the blocking layer as a mask comprises diluted hydrogen fluoride.

10. The method of forming a semiconductor structure of claim 1, wherein, The first work function material layer of the second region is removed using a wet etching process with the blocking layer as a mask.

11. The method of forming a semiconductor structure of claim 1, wherein, The method further comprises removing the blocking layer after removing the first work function material layer of the second region.

12. The method of forming a semiconductor structure of claim 11, wherein, The blocking layer is removed using an ashing process.

13. The method of forming a semiconductor structure of claim 11, wherein, The method further comprises removing the remaining protection layer after removing the blocking layer.

14. The method of forming a semiconductor structure of claim 13, wherein, The remaining protection layer is removed using an isotropic dry etching process.

15. The method of forming a semiconductor structure of claim 14, wherein, The isotropic dry etching process includes a Siconi etching process.

16. The method of forming a semiconductor structure of claim 13, wherein, The method for forming the semiconductor structure further includes, after the remaining protective layer is removed, forming a second work function layer conformally covering the second region.

17. The method of forming a semiconductor structure of claim 16, wherein, The method for forming the semiconductor structure further includes, after the second work function layer conformally covering the second region is formed, forming a gate layer on the second work function layer.

18. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the first work function material layer conformally covering the gate dielectric layer, the material of the first work function material layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide. In the step of forming the first work function material layer conformally covering the gate dielectric layer, the material of the first work function material layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

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