Array substrate and manufacturing method thereof, display panel and display device

Abstract

The present application relates to an array substrate and a manufacturing method thereof, a display panel and a display device, wherein the array substrate comprises: a substrate; a source-drain electrode layer, which is arranged on one side of the substrate and is used to provide a source electrode and a drain electrode to a photosensitive thin film transistor and a driving thin film transistor; a first semiconductor layer and a second semiconductor layer, which are arranged on a side of the source-drain electrode layer away from the substrate and are used to provide an active layer to the driving thin film transistor and the photosensitive thin film transistor, respectively, and the material of the first semiconductor layer comprises polycrystalline silicon, and the material of the second semiconductor layer comprises amorphous silicon; a first gate layer and a second gate layer, which are respectively arranged on a side of the first semiconductor layer and the second semiconductor layer away from the source-drain electrode layer, and are used to provide a gate electrode to the driving thin film transistor and the photosensitive thin film transistor, respectively, so that when the array substrate is applied to a display panel, the display panel can simultaneously achieve excellent photosensitivity and good display effects.

Description

Technical field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device. [Background Technology]

[0002] In the current display industry, in addition to continuously improving display quality, the addition of human-computer interaction has become a key development direction for new display technologies. For example, touch functions are increasingly being integrated into LCD, OLED, and other display panels of various sizes. The addition of various sensors has opened up more possibilities for different types of human-computer interaction functions.

[0003] Currently, the use of lasers is a solution for remote interaction, and the integration of light sensors into display panels provides the foundation for this solution. However, existing display panels struggle to achieve both excellent light sensitivity and good display quality, a key technical issue that urgently needs to be addressed. [Summary of the invention]

[0004] The purpose of the present application is to provide an array substrate and a manufacturing method thereof, a display panel and a display device, so as to solve the problem that it is difficult for a display panel to simultaneously achieve excellent photosensitivity and good display effects.

[0005] In order to solve the above problems, an embodiment of the present application provides an array substrate, which includes a substrate and a thin film transistor layer arranged on one side of the substrate, the thin film transistor layer includes a photosensitive unit and a driving unit, the photosensitive unit includes a photosensitive thin film transistor, the driving unit includes a driving thin film transistor, and wherein the thin film transistor layer specifically includes: a source and drain electrode layer, which is arranged on one side of the substrate and is used to provide a source and a drain electrode to the photosensitive thin film transistor and the driving thin film transistor; a first semiconductor layer and a second semiconductor layer, which are arranged on the side of the source and drain electrode layer away from the substrate, the second semiconductor layer is used to provide an active layer for the photosensitive thin film transistor, the first semiconductor layer is used to provide an active layer for the driving thin film transistor, and the material of the second semiconductor layer includes amorphous silicon, and the material of the first semiconductor layer includes polycrystalline silicon; a first gate layer and a second gate layer, the second gate layer is arranged on the side of the second semiconductor layer away from the source and drain electrode layer, and is used to provide a gate for the photosensitive thin film transistor, and the first gate layer is arranged on the side of the first semiconductor layer away from the source and drain electrode layer, and is used to provide a gate for the driving thin film transistor.

[0006] Among them, the photosensitive unit also includes a reading thin film transistor, and the source and drain layer is also used to provide a source and a drain for the reading thin film transistor, the first semiconductor layer is also used to provide an active layer for the reading thin film transistor, and the first gate layer is also used to provide a gate for the reading thin film transistor.

[0007] The thin film transistor layer further includes: a first light shielding layer, which is arranged between the substrate and the first semiconductor layer and covers the source and drain of the reading thin film transistor and the source and drain of the driving thin film transistor.

[0008] Among them, the thin film transistor layer also includes: a gate insulating layer, which is arranged on the side of the first semiconductor layer and the second semiconductor layer away from the substrate, and the first gate layer and the second gate layer are arranged on the side of the gate insulating layer away from the substrate; a passivation layer, which is arranged on the side of the source and drain layer away from the substrate, and covers the first semiconductor layer, the second semiconductor layer, the gate insulating layer, and the first gate layer, and the second gate layer is arranged on the side of the passivation layer away from the substrate.

[0009] The thin film transistor layer further includes: an electrical connection layer, which is arranged on the side of the passivation layer away from the substrate and is used to electrically connect the source or drain of the photosensitive thin film transistor to the gate of the reading thin film transistor.

[0010] Among them, the thin film transistor layer also includes: a second shading layer, which is arranged on the side of the passivation layer away from the substrate, and the orthographic projection of the second shading layer on the substrate includes the orthographic projection of the channel region in the active layer of the reading thin film transistor on the substrate, and the orthographic projection of the channel region in the active layer of the driving thin film transistor on the substrate.

[0011] In order to solve the above problems, an embodiment of the present application also provides a method for manufacturing an array substrate, which includes: providing a substrate; forming a thin film transistor layer on one side of the substrate, the thin film transistor layer including a photosensitive unit and a driving unit, the photosensitive unit including a photosensitive thin film transistor, the driving unit including a driving thin film transistor, and wherein the thin film transistor layer specifically includes: a source and drain electrode layer, which is arranged on one side of the substrate and is used to provide a source and a drain electrode to the photosensitive thin film transistor and the driving thin film transistor; a first semiconductor layer and a second semiconductor layer, which are arranged on the side of the source and drain electrode layer away from the substrate, the second semiconductor layer is used to provide an active layer for the photosensitive thin film transistor, the first semiconductor layer is used to provide an active layer for the driving thin film transistor, and the material of the second semiconductor layer includes amorphous silicon, and the material of the first semiconductor layer includes polycrystalline silicon; a first gate layer and a second gate layer, the second gate layer is arranged on the side of the second semiconductor layer away from the source and drain electrode layer, and is used to provide a gate for the photosensitive thin film transistor, and the first gate layer is arranged on the side of the first semiconductor layer away from the source and drain electrode layer, and is used to provide a gate for the driving thin film transistor.

[0012] Among them, the photosensitive unit also includes a reading thin film transistor, and the source and drain layer is also used to provide a source and a drain for the reading thin film transistor, the first semiconductor layer is also used to provide an active layer for the reading thin film transistor, and the first gate layer is also used to provide a gate for the reading thin film transistor.

[0013] In order to solve the above problems, an embodiment of the present application further provides a display panel, which includes any one of the above array substrates.

[0014] In order to solve the above problems, an embodiment of the present application further provides a display device, which includes any one of the display panels described above.

[0015] The beneficial effect of the present application is: different from the existing technology, the array substrate and its manufacturing method, display panel and display device provided by the present application integrate the photosensitive unit and the driving unit in the array substrate at the same time, and make the active layer of the photosensitive thin film transistor in the photosensitive unit be made of amorphous silicon and other semiconductor materials with excellent photosensitivity, and make the active layer of the driving thin film transistor in the driving unit be made of polycrystalline silicon and other semiconductor materials with high carrier mobility, so that it is possible to ensure that the photosensitive thin film transistor in the array substrate has good photosensitivity characteristics while ensuring that the driving thin film transistor in the array substrate has good carrier mobility, and then when the array substrate is applied to the display panel, the display panel can simultaneously achieve excellent photosensitivity characteristics and good display effects.

Brief Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic cross-sectional structural diagram of an array substrate provided in an embodiment of the present application;

[0018] Figure 2 is another cross-sectional structural diagram of an array substrate provided in an embodiment of the present application;

[0019] Figure 3 Schematic diagram of the circuit structure of the photosensitive unit provided in an embodiment of the present application;

[0020] Figure 4 1 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0021] Figure 5 2 is a schematic diagram of the cross-sectional structure after S121 is completed according to an embodiment of the present application;

[0022] Figure 6 Schematic diagram of the cross-sectional structure after step A provided in the embodiment of the present application is completed;

[0023] Figure 7 Schematic diagram of the cross-sectional structure after step B is completed provided in the embodiment of the present application;

[0024] Figure 8 1 is a schematic diagram of the cross-sectional structure after S122 is completed provided in an embodiment of the present application;

[0025] Figure 9 Schematic diagram of the cross-sectional structure after step C is completed provided in the embodiment of the present application;

[0026] Figure 10 Schematic diagram of the cross-sectional structure after step D is completed according to the embodiment of the present application;

[0027] Figure 11 1 is a schematic diagram of the cross-sectional structure after S124 is completed according to an embodiment of the present application;

[0028] Figure 12 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0029] Figure 13 It is a structural schematic diagram of the display device provided in an embodiment of the present application. [Specific implementation method]

[0030] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only intended to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and not all examples. All other examples obtained by those of ordinary skill in the art without creative work are intended to fall within the scope of protection of this application.

[0031] See also Figure 1 , Figure 1 : is a schematic diagram of the cross-sectional structure of the array substrate provided in the embodiment of the present application. Figure 1 As shown, the array substrate 10 includes a substrate 11 and a thin film transistor layer provided on one side of the substrate 11. The thin film transistor layer includes a photosensitive unit and a driving unit. The photosensitive unit includes a photosensitive thin film transistor Tp, and the driving unit includes a driving thin film transistor Td.

[0032] The thin film transistor layer specifically includes a source-drain electrode layer 12, a first semiconductor layer 13, a second semiconductor layer 14, a first gate layer 15, and a second gate layer 16. Furthermore, the source-drain electrode layer 12 is disposed on one side of the substrate 11 and is used to provide a source electrode S2 and a drain electrode D2 for the photosensitive thin film transistor Tp in the array substrate 10, and to provide a source electrode S1 and a drain electrode D1 for the driving thin film transistor Td in the array substrate 10.

[0033] The first semiconductor layer 13 and the second semiconductor layer 14 are disposed on a side of the source / drain layer 12 facing away from the substrate 11. Furthermore, the second semiconductor layer 14 can be used to provide an active layer for the photosensitive thin film transistor Tp in the array substrate 10. The active layer of the photosensitive thin film transistor Tp in the array substrate 10 can include a channel region 14A and a source region 14B and a drain region 14C located on either side of the channel region 14A. The first semiconductor layer 13 can be used to provide an active layer for the driving thin film transistor Td in the array substrate 10. The active layer of the driving thin film transistor Td in the array substrate 10 can include a channel region 13A and a source region 13B and a drain region 13C located on either side of the channel region 13A.

[0034] The second gate layer 16 is disposed on a side of the second semiconductor layer 14 away from the source-drain electrode layer 12 and can be used to provide a gate G2 for the photosensitive thin film transistor Tp in the array substrate 10. The first gate layer 15 is disposed on a side of the first semiconductor layer 13 away from the source-drain electrode layer 12 and can be used to provide a gate G1 for the driving thin film transistor Td in the array substrate 10.

[0035] In this embodiment, the material of the above-mentioned second semiconductor layer 14 may include semiconductor materials with excellent photosensitivity such as amorphous silicon, and the material of the above-mentioned first semiconductor layer 13 may include semiconductor materials with high carrier mobility such as polycrystalline silicon, so as to ensure that the photosensitive thin film transistor Tp in the above-mentioned array substrate 10 has good photosensitivity characteristics while ensuring that the driving thin film transistor Td in the above-mentioned array substrate 10 has good carrier mobility, and further, when the above-mentioned array substrate 10 is applied to a display panel, the display panel can simultaneously achieve excellent photosensitivity characteristics and good display effects.

[0036] It can be understood that, compared with the solution in which the active layers of the photosensitive thin film transistor and the driving thin film transistor in some array substrates are made of amorphous silicon or polycrystalline silicon, the active layer of the photosensitive thin film transistor Tp of the array substrate 10 in this embodiment is made of amorphous silicon or other semiconductor materials with excellent photosensitivity, and the active layer of the driving thin film transistor Td is made of polycrystalline silicon or other semiconductor materials with high carrier mobility. This solution can overcome the problem that the active layers of the photosensitive thin film transistor and the driving thin film transistor in the array substrate are made of amorphous silicon, resulting in the array substrate being unable to meet the backplane requirements of higher-end products due to the low carrier mobility of amorphous silicon. It can also overcome the problem that the active layers of the photosensitive thin film transistor and the driving thin film transistor in the array substrate are made of polycrystalline silicon, resulting in poor photosensitivity of the array substrate due to the poor photosensitivity of polycrystalline silicon.

[0037] Moreover, compared with other array substrates in which the active layer of the photosensitive thin film transistor is made of amorphous silicon, and the active layer of the driving thin film transistor is made of indium gallium zinc oxide (IGZO), the active layer of the photosensitive thin film transistor Tp of the array substrate 10 in this embodiment is made of amorphous silicon or other semiconductor materials with excellent photosensitivity, and the active layer of the driving thin film transistor Td is made of polycrystalline silicon or other semiconductor materials with high carrier mobility. Because the compatibility between the amorphous silicon process and the polycrystalline silicon process is better than that between the amorphous silicon process and the IGZO process, it is more conducive to reducing the process cost.

[0038] In a specific embodiment, Figure 2 As shown, the above-mentioned photosensitive unit can also include a reading thin film transistor Tr, and the above-mentioned source and drain layer 12 can also be used to provide a source S3 and a drain D3 to the reading thin film transistor Tr in the above-mentioned array substrate 10, the above-mentioned first gate layer 15 can also be used to provide a gate G3 to the reading thin film transistor Tr in the above-mentioned array substrate 10, and the above-mentioned first semiconductor layer 13 can also be used to provide an active layer to the reading thin film transistor Tr in the above-mentioned array substrate 10, and the active layer of the reading thin film transistor Tr can include a channel region 13D and a source region 13E and a drain region 13F respectively located on both sides of the channel region 13D.

[0039] Specifically, if Figure 1 and Figure 2 As shown, the thin film transistor layer may further include a buffer layer 19. The buffer layer 19 and the source / drain electrode layer 12 may be disposed on the same side of the substrate 11. The buffer layer 19 may cover the source / drain electrode layer 12, and the first semiconductor layer 13 and the second semiconductor layer 14 may be disposed on a side of the buffer layer 19 facing away from the substrate 11. Thus, the first semiconductor layer 13 and the source / drain electrode layer 12 in the array substrate 10 may be separated by the buffer layer 19, and the second semiconductor layer 14 and the source / drain electrode layer 12 in the array substrate 10 may be separated by the buffer layer 19.

[0040] Furthermore, in specific implementation, Figure 1 and Figure 2As shown, the source region 14B and the drain region 14C of the photosensitive thin film transistor Tp in the above-mentioned array substrate 10 can be electrically connected to the source S2 and the drain D2 of the photosensitive thin film transistor Tp in the above-mentioned array substrate 10 respectively through the interlayer vias passing through the above-mentioned buffer layer 19, the source region 13B and the drain region 13C of the driving thin film transistor Td in the above-mentioned array substrate 10 can be electrically connected to the source S1 and the drain D1 of the driving thin film transistor Td in the above-mentioned array substrate 10 respectively through the interlayer vias passing through the above-mentioned buffer layer 19, and the source region 13E and the drain region 13F of the reading thin film transistor Tr in the above-mentioned array substrate 10 can be electrically connected to the source S3 and the drain D3 of the reading thin film transistor Tr in the above-mentioned array substrate 10 respectively through different interlayer vias passing through the above-mentioned buffer layer 19.

[0041] In some specific embodiments, Figure 1 and Figure 2 As shown, the thin film transistor layer may further include a first light shielding layer 21, which is provided between the substrate 11 and the first semiconductor layer 13 and covers the source S3 and drain D3 of the read thin film transistor Tr in the array substrate 10 and the source S1 and drain D1 of the drive thin film transistor Td in the array substrate 10, and may be covered by the buffer layer 19. Thus, when the first semiconductor layer 13 is formed by amorphous silicon laser annealing crystallization or other crystallization methods, the high energy during the crystallization process that causes the source and drain layer 12 located directly below the first semiconductor layer 13 to melt can be avoided or reduced, thereby improving the yield and reliability of the product.

[0042] Specifically, the first light-shielding layer 21 may be a metal layer resistant to high temperature corrosion, and its material may be Mo or Si which are resistant to high temperature and have good light-shielding performance, or may be a Mo / Si laminate or other metal materials.

[0043] In some specific embodiments, Figure 1 and Figure 2 As shown, the thin film transistor layer may further include a gate insulating layer 17, which is provided on a side of the first semiconductor layer 13 and the second semiconductor layer 14 facing away from the substrate 11, and the first gate layer 15 and the second gate layer 16 are provided on a side of the gate insulating layer 17 facing away from the substrate 11. Thus, the gate G2 of the photosensitive thin film transistor Tp in the array substrate 10 can be electrically isolated from the active layer by the gate insulating layer 17, the gate G1 of the driving thin film transistor Td in the array substrate 10 can be electrically isolated from the active layer by the gate insulating layer 17, and the gate G3 of the reading thin film transistor Tr in the array substrate 10 can be electrically isolated from the active layer by the gate insulating layer 17.

[0044] Specifically, if Figure 1 and Figure 2As shown, the gate insulating layer 17 may include a first gate insulating layer 17A, a second gate insulating layer 17B and a third gate insulating layer 17C, wherein the first gate insulating layer 17A may be provided between the active layer and the gate G1 of the driving thin film transistor Td to achieve electrical isolation between the active layer and the gate G1 of the driving thin film transistor Td, the second gate insulating layer 17B may be provided between the active layer and the gate G2 of the photosensitive thin film transistor Tp to achieve electrical isolation between the active layer and the gate G2 of the photosensitive thin film transistor Tp, and the third gate insulating layer 17C may be provided between the active layer and the gate G3 of the reading thin film transistor Tr to achieve electrical isolation between the active layer and the gate G3 of the reading thin film transistor Tr.

[0045] In some specific embodiments, Figure 1 and Figure 2 As shown, the orthographic projection of the gate G1 in the above-mentioned driving thin film transistor Td on the above-mentioned substrate 11 can be located within the orthographic projection of the above-mentioned first gate insulating layer 17A on the above-mentioned substrate 11, the orthographic projection of the gate G2 in the above-mentioned photosensitive thin film transistor Tp on the above-mentioned substrate 11 can be located within the orthographic projection of the above-mentioned second gate insulating layer 17B on the above-mentioned substrate 11, and the orthographic projection of the gate G3 in the above-mentioned reading thin film transistor Tr on the above-mentioned substrate 11 can be located within the orthographic projection of the above-mentioned third gate insulating layer 17C on the above-mentioned substrate 11.

[0046] In the above embodiment, the material of the substrate 11 can be glass or hard resin, or any organic polymer such as polyimide, polycarbonate, polyethylene terephthalate, polyethersulfone substrate. The material of the source and drain layer 12 can be Mo, Mo / Al stacking, Mo / Cu stacking, MoTi / Cu stacking, MoTi / Cu / MoTi stacking, Ti / Al / Ti stacking, Ti / Cu / Ti stacking, Mo / Cu / IZO stacking, IZO / Cu / IZO stacking, or Mo / Cu / ITO stacking. The material of the first gate layer 15 can be Mo, Mo / Al stacking, Mo / Cu stacking, MoTi / Cu stacking, MoTi / Cu / MoTi stacking, Ti / Al / Ti stacking, Ti / Cu / Ti stacking, Mo / Cu / IZO stacking, IZO / Cu / IZO stacking, or Mo / Cu / ITO stacking, or other conductive materials. The second gate layer 16 may be made of a transparent conductive material such as ITO, IZO, or AZO. The gate insulation layer 17 may be made of an insulating material such as SiOx, SiNx, an Al2O3 / SiNx / SiOx stack, or a SiOx / SiNx / SiOx stack. The buffer layer 19 may be made of an insulating material such as SiOx, SiNx, a SiNx / SiOx stack, or SiNOx.

[0047] In some specific embodiments, Figure 1 and Figure 2 As shown, the thin film transistor layer may further include a passivation layer 18, which is disposed on a side of the source and drain electrode layer 12 facing away from the substrate 11 and covers at least the first semiconductor layer 13, the second semiconductor layer 14, the gate insulating layer 17, and the first gate layer 15. The passivation layer 18 may be made of an insulating material such as SiOx, SiNx, SiNx / SiOx, or SiNOx.

[0048] Specifically, the second gate layer 16 may be directly formed on the surface of the gate insulating layer 17 (or the second gate insulating layer 17B) facing away from the substrate 11 and covered by the passivation layer 18. In other embodiments, as Figure 1 and Figure 2 As shown, the second gate layer 16 may also be provided on the side of the passivation layer 18 facing away from the substrate 11 .

[0049] In some specific embodiments, Figure 2 As shown, the thin film transistor layer may further include an electrical connection layer 20, which is provided on the side of the passivation layer 18 facing away from the substrate 11 and can be used to electrically connect the source S2 or drain D2 of the photosensitive thin film transistor Tp in the array substrate 10 to the gate G3 of the reading thin film transistor Tr in the array substrate 10. In addition, in a specific implementation, as shown in FIG. Figure 2 As shown, the electrical connection layer 20 can be electrically connected to the drain D2 of the photosensitive thin film transistor Tp in the array substrate 10 and the gate G3 of the reading thin film transistor Tr in the array substrate 10 through different interlayer vias penetrating the passivation layer 18.

[0050] Specifically, the electrical connection layer 20 may be made of a transparent conductive material such as ITO, IZO, or AZO. In one embodiment, the material of the electrical connection layer 20 may be the same as that of the second gate layer 16. Furthermore, when the second gate layer 16 is disposed on the side of the passivation layer 18 facing away from the substrate 11, the second gate layer 16 and the electrical connection layer 20 may be disposed on the same layer and may be manufactured through the same patterning process, thereby reducing process steps and thereby lowering production costs.

[0051] In some specific embodiments, Figure 1 and Figure 2As shown, the above-mentioned thin film transistor layer may further include a second light-shielding layer 22, which may be provided on the side of the above-mentioned passivation layer 18 away from the substrate 11, and the orthographic projection of the second light-shielding layer 22 on the above-mentioned substrate 11 may at least include the orthographic projection of the channel region 13D of the active layer in the above-mentioned read thin film transistor Tr on the above-mentioned substrate 11, and / or the orthographic projection of the channel region 13D of the active layer in the above-mentioned drive thin film transistor Td on the above-mentioned substrate 11, so as to effectively prevent external light from irradiating the channel region 13D of the active layer in the above-mentioned read thin film transistor Tr and / or the channel region 13A of the active layer in the above-mentioned drive thin film transistor Td, thereby avoiding the problem of unstable performance of the above-mentioned read thin film transistor Tr and / or the above-mentioned drive thin film transistor Td due to the active layer being irradiated by external light.

[0052] Specifically, the second light shielding layer 22 may be made of black organic photoresist material to absorb at least part of the external light directed toward the active layer of the driving thin film transistor Td and / or at least part of the external light directed toward the active layer of the reading thin film transistor Tr.

[0053] In the above embodiment, when the above array substrate 10 is applied to a display panel, the number of driving units in the above array substrate 10 can be multiple, and the multiple driving units can be arranged in an array, each driving unit can correspond to a pixel unit in the above display panel, and can be used to drive its corresponding pixel unit to emit light.

[0054] In some embodiments, the array substrate 10 may include multiple photosensitive units, and the multiple photosensitive units may be arranged in an array, so as to position and sense the external light irradiated to the array substrate 10, so as to realize remote laser pen interaction.

[0055] Specifically, if Figure 3 As shown, each photosensitive unit may include a photosensitive thin film transistor Tp and a read thin film transistor Tr, and the drain electrode D2 of the photosensitive thin film transistor Tp in each photosensitive unit may be electrically connected to the gate electrode G3 of the read thin film transistor Tr in each photosensitive unit. Furthermore, each photosensitive unit may also include a first signal line L1, a second signal line L2, and a third signal line L3, and the source electrode S2 of the photosensitive thin film transistor Tp in each photosensitive unit and the source electrode S3 of the read thin film transistor Tr in each photosensitive unit may be electrically connected to the second signal line L2 in each photosensitive unit, the gate electrode G2 of the photosensitive thin film transistor Tp in each photosensitive unit may be electrically connected to the third signal line L3 in each photosensitive unit, and the drain electrode D3 of the read thin film transistor Tr in each photosensitive unit may be electrically connected to the first signal line L1 in each photosensitive unit.

[0056] Moreover, when the photosensitive unit is working, a preset voltage (e.g., VDD) can be connected to the second signal line L2. When there is no external light (e.g., laser light emitted by an external laser pen), the source S2 and the drain D2 of the photosensitive thin-film transistor Tp are not conductive. When there is external light, the leakage current between the source S2 and the drain D2 of the photosensitive thin-film transistor Tp increases, thereby increasing the voltage on the gate G3 of the read thin-film transistor Tr, and thereby causing the source S2 and the drain D2 of the read thin-film transistor Tr to be conductive. Thus, the voltage on the source S3 of the read thin-film transistor Tr can be transmitted to the drain D3 of the read thin-film transistor Tr, and can be output to the external circuit through the first signal line L1, so as to realize the positioning sensing of the external light irradiated to the photosensitive unit.

[0057] From the above, it can be seen that the array substrate provided by this embodiment integrates the photosensitive unit and the driving unit into the array substrate at the same time, and makes the active layer of the photosensitive thin film transistor in the photosensitive unit be made of semiconductor materials with excellent photosensitivity such as amorphous silicon, and makes the active layer of the driving thin film transistor in the driving unit be made of semiconductor materials with high carrier mobility such as polycrystalline silicon. Therefore, it is possible to ensure that the photosensitive thin film transistor in the array substrate has good photosensitivity characteristics while ensuring that the driving thin film transistor in the array substrate has good carrier mobility. Therefore, when the array substrate is applied to a display panel, the display panel can simultaneously achieve excellent photosensitivity characteristics and good display effects.

[0058] See also Figure 4 , Figure 4 For a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application, please also refer to Figure 1 and Figure 2 , Figure 1 and Figure 2 This is a schematic structural diagram of an array substrate 10 manufactured by the method for manufacturing an array substrate provided in an embodiment of the present application. Figure 1 、 Figure 2 and Figure 4 As shown, the specific process of the method for manufacturing the array substrate 10 provided in this embodiment can be as follows:

[0059] S11: providing a substrate 11.

[0060] S12: forming a thin film transistor layer on one side of the substrate 11, the thin film transistor layer including a photosensitive unit and a driving unit, the photosensitive unit including a photosensitive thin film transistor Tp, the driving unit including a driving thin film transistor Td, and wherein the thin film transistor layer specifically includes: a source-drain electrode layer 12, provided on one side of the substrate 11, and used to provide a source electrode S1 / S2 and a drain electrode D1 / D2 to the photosensitive thin film transistor Tp and the driving thin film transistor Td; a first semiconductor layer 13 and a second semiconductor layer 14, provided on a side of the source-drain electrode layer 12 away from the substrate 11, the second semiconductor layer 14 It is used to provide an active layer for the photosensitive thin film transistor Tp, and the first semiconductor layer 13 is used to provide an active layer for the driving thin film transistor Td, and the material of the second semiconductor layer 14 includes amorphous silicon, and the material of the first semiconductor layer 13 includes polycrystalline silicon; the first gate layer 15 and the second gate layer 16, the second gate layer 16 is arranged on the side of the second semiconductor layer 14 away from the source and drain layer 12, and is used to provide a gate G2 for the photosensitive thin film transistor Tp, the first gate layer 15 is arranged on the side of the first semiconductor layer 13 away from the source and drain layer 12, and is used to provide a gate G1 for the driving thin film transistor Td.

[0061] In a specific embodiment, Figure 2 As shown, the above-mentioned photosensitive unit can also include a reading thin film transistor Tr, and the above-mentioned source and drain layer 12 can also be used to provide a source S3 and a drain D3 to the reading thin film transistor Tr in the above-mentioned array substrate 10, the above-mentioned first gate layer 15 can also be used to provide a gate G3 to the reading thin film transistor Tr in the above-mentioned array substrate 10, and the above-mentioned first semiconductor layer 13 can also be used to provide an active layer to the reading thin film transistor Tr in the above-mentioned array substrate 10.

[0062] In some specific embodiments, the above S12 may specifically include:

[0063] S121 : forming a source-drain layer 12 on one side of the substrate 11 .

[0064] The cross-sectional structure diagram after the completion of S121 can be as follows: Figure 5 shown.

[0065] Specifically, a source-drain electrode material layer may be formed on the substrate 11 , and the source-drain electrode material layer may be patterned to form the source-drain electrode layer 12 .

[0066] S122 : forming a first semiconductor layer 13 and a second semiconductor layer 14 on a side of the source / drain electrode layer 12 facing away from the substrate 11 .

[0067] Before the above S122, the following steps may also be included:

[0068] Step A: Form a first light-shielding layer 21. The first light-shielding layer 21 and the source-drain layer 12 are arranged on the same side of the substrate 11, and the first light-shielding layer 21 covers the source S3 and drain D3 of the reading thin-film transistor Tr in the above-mentioned array substrate 10 and the source S1 and drain D1 of the driving thin-film transistor Td in the above-mentioned array substrate 10.

[0069] The cross-sectional structure diagram after the above step A is completed can be as follows: Figure 6 shown.

[0070] Specifically, a first light-shielding material layer covering the source-drain electrode layer 12 may be formed on the substrate 11 , and the first light-shielding material layer may be patterned to form the first light-shielding layer 21 .

[0071] Step B: forming a buffer layer 19 . The buffer layer 19 and the source / drain electrode layer 12 are disposed on the same side of the substrate 11 . The buffer layer 19 covers the source / drain electrode layer 12 and the first light shielding layer 21 , and an interlayer via V1 is disposed on the buffer layer 19 .

[0072] The cross-sectional structure diagram after the above step B is completed can be as follows: Figure 7 shown.

[0073] Specifically, a buffer material layer covering the source and drain layer 12 and the first light-shielding layer 21 can be formed on the substrate 11 through a thin film deposition process (e.g., a chemical vapor deposition process), and the buffer material layer can be patterned to form the buffer layer 19 having the interlayer via V1.

[0074] Accordingly, the above S122 may specifically include: forming the above first semiconductor layer 13 and the second semiconductor layer 14 on the side of the above buffer layer 19 away from the substrate 11. And, the cross-sectional structure diagram after the above S122 is completed may be as follows: Figure 8 shown.

[0075] Specifically, an amorphous silicon layer can be formed on the side of the buffer layer 19 facing away from the substrate 11, and the amorphous silicon layer can be patterned to form a first amorphous silicon layer and a second amorphous silicon layer (i.e., the second semiconductor layer 14). Then, the first amorphous silicon layer can be converted into a polycrystalline silicon layer (i.e., the first semiconductor layer 13) through an amorphous silicon crystallization process such as a laser annealing process (e.g., a blue light laser annealing process).

[0076] S123 : forming a first gate layer 15 on a side of the first semiconductor layer 13 facing away from the substrate 11 .

[0077] Before the above S123, the following steps may also be included:

[0078] Step C: forming a gate insulating layer 17 on the side of the first semiconductor layer 13 and the second semiconductor layer 14 facing away from the substrate 11 .

[0079] The cross-sectional structure diagram after the completion of step C can be as follows: Figure 9 shown.

[0080] Specifically, a gate insulating material layer can be formed on the side of the first semiconductor layer 13 and the second semiconductor layer 14 facing away from the substrate 11, and the gate insulating material layer can be patterned to form the gate insulating layer 17 including the first gate insulating layer 17A, the second gate insulating layer 17B and the third gate insulating layer 17C.

[0081] Accordingly, the above-mentioned S123 may specifically include: forming the above-mentioned first gate layer 15 on the side of the above-mentioned first gate insulating layer 17A and the third gate insulating layer 17C facing away from the substrate 11 .

[0082] In some specific embodiments, after forming the above-mentioned gate insulating layer 17, the above-mentioned method may further include: performing doping treatment on the source region 14B and the drain region 14C of the active layer in the above-mentioned photosensitive thin film transistor Tp, the source region 13B and the drain region 13C of the active layer in the above-mentioned driving thin film transistor Td, and the source region 13E and the drain region 13F of the active layer in the above-mentioned reading thin film transistor Tr, wherein the doping treatment may be doping with phosphorus ions or doping with boron ions.

[0083] S124 : forming a second gate layer 16 on a side of the second semiconductor layer 14 facing away from the substrate 11 .

[0084] Before the above S124, the following steps may also be included:

[0085] Step D: forming a passivation layer 18 on the side of the buffer layer 19 facing away from the substrate 11 , the passivation layer 18 covers the first semiconductor layer 13 , the second semiconductor layer 14 , the gate insulating layer 17 and the first gate layer 15 , and an interlayer via V2 is provided on the passivation layer 18 .

[0086] The cross-sectional structure diagram after the above step D is completed can be as follows: Figure 10 shown.

[0087] Specifically, a passivation material layer covering the first semiconductor layer 13, the second semiconductor layer 14, the gate insulation layer 17 and the first gate layer 15 can be formed on the side of the buffer layer 19 facing away from the substrate 11 through a thin film deposition process (for example, a chemical vapor deposition process), and the passivation material layer is patterned to form the passivation layer 18 having the interlayer via V2.

[0088] Accordingly, the above S124 may specifically include: forming the above second gate layer 16 on the side of the above passivation layer 18 away from the substrate 11. And, the cross-sectional structural diagram after the above S124 is completed may be as follows: Figure 11 shown.

[0089] In some specific embodiments, after forming the passivation layer 18, the method may further include forming an electrical connection layer 20 on a side of the passivation layer 18 facing away from the substrate 11. Furthermore, during implementation, a transparent conductive material layer may be formed on a side of the passivation layer 18 facing away from the substrate 11, and the transparent conductive material layer may be patterned to form the second gate layer 16 and the electrical connection layer 20.

[0090] In some specific embodiments, after forming the passivation layer 18, the method may further include forming a second light-shielding layer 22 on a side of the passivation layer 18 facing away from the substrate 11. Furthermore, in a specific implementation, a black organic photoresist layer may be formed by coating the side of the passivation layer 18 facing away from the substrate 11, and the black organic photoresist layer may be patterned and thermally baked in sequence to form the second light-shielding layer 22.

[0091] It should be noted that the specific structure of the array substrate in this embodiment can refer to the specific implementation in the above-mentioned embodiment of the array substrate, so it will not be repeated here.

[0092] From the above, it can be seen that the manufacturing method of the array substrate provided in this embodiment integrates the photosensitive unit and the driving unit into the array substrate at the same time, and makes the active layer of the photosensitive thin film transistor in the photosensitive unit be made of amorphous silicon and other semiconductor materials with excellent photosensitivity, and makes the active layer of the driving thin film transistor in the driving unit be made of polycrystalline silicon and other semiconductor materials with high carrier mobility. In this way, it is possible to ensure that the photosensitive thin film transistor in the array substrate has good photosensitivity characteristics while ensuring that the driving thin film transistor in the array substrate has good carrier mobility. Therefore, when the array substrate is applied to a display panel, the display panel can simultaneously achieve excellent photosensitivity characteristics and good display effects.

[0093] See also Figure 12 , Figure 12 Schematic diagram of the structure of the display panel provided in the embodiment of the present application. Figure 12 As shown, the display panel 100 includes the array substrate 101 of any of the above embodiments.

[0094] The array substrate 101 includes a substrate and a thin film transistor layer provided on one side of the substrate. The thin film transistor layer includes a photosensitive unit and a driving unit. The photosensitive unit includes a photosensitive thin film transistor, and the driving unit includes a driving thin film transistor.

[0095] Furthermore, the thin film transistor layer specifically includes a source-drain electrode layer, a first semiconductor layer, a second semiconductor layer, a first gate layer, and a second gate layer. The source-drain electrode layer is arranged on one side of the substrate and is used to provide a source electrode and a drain electrode for the photosensitive thin film transistor and the driving thin film transistor. The first semiconductor layer and the second semiconductor layer are arranged on the side of the source-drain electrode layer away from the substrate, wherein the second semiconductor layer is used to provide an active layer for the photosensitive thin film transistor, and the first semiconductor layer is used to provide an active layer for the driving thin film transistor, and the material of the second semiconductor layer includes amorphous silicon, and the material of the first semiconductor layer includes polycrystalline silicon. The second gate layer is arranged on the side of the second semiconductor layer away from the source-drain electrode layer, and is used to provide a gate for the photosensitive thin film transistor. The first gate layer is arranged on the side of the first semiconductor layer away from the source-drain electrode layer, and is used to provide a gate for the driving thin film transistor.

[0096] From the above, it can be seen that the display panel provided by this embodiment integrates the photosensitive unit and the driving unit into the array substrate at the same time, and makes the active layer of the photosensitive thin film transistor in the photosensitive unit be made of semiconductor materials with excellent photosensitivity such as amorphous silicon, and makes the active layer of the driving thin film transistor in the driving unit be made of semiconductor materials with high carrier mobility such as polycrystalline silicon. In this way, it is possible to ensure that the photosensitive thin film transistor in the array substrate has good photosensitivity characteristics while ensuring that the driving thin film transistor in the array substrate has good carrier mobility, thereby enabling the display panel to simultaneously achieve excellent photosensitivity characteristics and good display effects.

[0097] See also Figure 13 , Figure 13 Schematic diagram of the structure of the display device provided in the embodiment of the present application. Figure 13 As shown, the display device 200 includes a display panel 201 according to any of the above embodiments, and may further include a driving circuit for providing a driving voltage to the display panel 201 .

[0098] It should be noted that the display device in the embodiment of the present application has the same beneficial effects as the above-mentioned display panel because it is provided with the display panel provided in the embodiment of the present application.

[0099] The embodiments of the present application do not impose any specific restrictions on the applicability of the display device, which can be any product or component with display function, such as a television, a laptop computer, a tablet computer, a wearable display device (such as a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, a car display, an advertising light box, etc.

[0100] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The device comprises a substrate and a thin film transistor layer provided on one side of the substrate, wherein the thin film transistor layer comprises a photosensitive unit and a driving unit, wherein the photosensitive unit comprises a photosensitive thin film transistor, and the driving unit comprises a driving thin film transistor, and wherein the thin film transistor layer specifically comprises: a source-drain electrode layer, provided on one side of the substrate and used to provide a source electrode and a corresponding drain electrode for the photosensitive thin film transistor, and to provide a source electrode and a corresponding drain electrode for the driving thin film transistor; a first semiconductor layer and a second semiconductor layer disposed in the same layer, and disposed on a side of the source and drain electrode layer facing away from the substrate, the second semiconductor layer being used to provide an active layer for the photosensitive thin film transistor, and the first semiconductor layer being used to provide an active layer for the driving thin film transistor, wherein the second semiconductor layer is made of amorphous silicon, and the first semiconductor layer is made of polycrystalline silicon; a first gate layer and a second gate layer, wherein the second gate layer is provided on a side of the second semiconductor layer away from the source-drain electrode layer and is used to provide a gate for the photosensitive thin film transistor, and the first gate layer is provided on a side of the first semiconductor layer away from the source-drain electrode layer and is used to provide a gate for the driving thin film transistor; a gate insulating layer, disposed on a side of the first semiconductor layer and the second semiconductor layer facing away from the substrate, and the first gate layer and the second gate layer are disposed on a side of the gate insulating layer facing away from the substrate; Among them, the gate insulation layer includes a first gate insulation layer and a second gate insulation layer arranged in the same layer, the first gate insulation layer is arranged between the active layer of the driving thin film transistor and the corresponding gate, and the second gate insulation layer is arranged between the active layer of the photosensitive thin film transistor and the corresponding gate.

2. The array substrate according to claim 1, wherein: The photosensitive unit also includes a reading thin film transistor, and the source and drain layer is also used to provide a source and a drain for the reading thin film transistor, the first semiconductor layer is also used to provide an active layer for the reading thin film transistor, and the first gate layer is also used to provide a gate for the reading thin film transistor.

3. The array substrate according to claim 2, wherein: The thin film transistor layer further includes: The first light shielding layer is provided between the substrate and the first semiconductor layer and covers the source and drain of the reading thin film transistor and the source and drain of the driving thin film transistor.

4. The array substrate according to claim 2, wherein: The thin film transistor layer further includes: A passivation layer is provided on a side of the source and drain layer away from the substrate and covers the first semiconductor layer, the second semiconductor layer, the gate insulating layer, and the first gate layer, and the second gate layer is provided on a side of the passivation layer away from the substrate.

5. The array substrate according to claim 4, wherein: The thin film transistor layer further includes: The electrical connection layer is provided on the side of the passivation layer away from the substrate and is used to electrically connect the source or drain of the photosensitive thin film transistor to the gate of the reading thin film transistor.

6. The array substrate according to claim 4, wherein: The thin film transistor layer further includes: A second light-shielding layer is provided on the side of the passivation layer facing away from the substrate, and the orthographic projection of the second light-shielding layer on the substrate includes the orthographic projection of the channel region in the active layer of the reading thin film transistor on the substrate and the orthographic projection of the channel region in the active layer of the driving thin film transistor on the substrate.

7. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; A thin film transistor layer is formed on one side of the substrate, the thin film transistor layer includes a photosensitive unit and a driving unit, the photosensitive unit includes a photosensitive thin film transistor, the driving unit includes a driving thin film transistor, and wherein the thin film transistor layer specifically includes: a source-drain electrode layer, which is provided on one side of the substrate and is used to provide a source electrode and a corresponding drain electrode to the photosensitive thin film transistor, and to provide a source electrode and a corresponding drain electrode to the driving thin film transistor; a first semiconductor layer and a second semiconductor layer arranged in the same layer, which are provided on the side of the source-drain electrode layer away from the substrate, the second semiconductor layer is used to provide an active layer for the photosensitive thin film transistor, the first semiconductor layer is used to provide an active layer for the driving thin film transistor, and the material of the second semiconductor layer includes amorphous silicon, and the material of the first semiconductor layer includes polycrystalline silicon. Silicon; a first gate layer and a second gate layer, the second gate layer is arranged on the side of the second semiconductor layer away from the source and drain layer, and is used to provide a gate for the photosensitive thin film transistor, the first gate layer is arranged on the side of the first semiconductor layer away from the source and drain layer, and is used to provide a gate for the driving thin film transistor; a gate insulating layer, arranged on the side of the first semiconductor layer and the second semiconductor layer away from the substrate, and the first gate layer and the second gate layer are arranged on the side of the gate insulating layer away from the substrate; wherein the gate insulating layer includes a first gate insulating layer and a second gate insulating layer arranged in the same layer, the first gate insulating layer is arranged between the active layer of the driving thin film transistor and the corresponding gate, and the second gate insulating layer is arranged between the active layer of the photosensitive thin film transistor and the corresponding gate.

8. The method for manufacturing an array substrate according to claim 7, wherein: The photosensitive unit also includes a reading thin film transistor, and the source and drain layer is also used to provide a source and a drain for the reading thin film transistor, the first semiconductor layer is also used to provide an active layer for the reading thin film transistor, and the first gate layer is also used to provide a gate for the reading thin film transistor.

9. A display panel, characterized in that: Comprising the array substrate according to any one of claims 1 to 6.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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