Isolator

Abstract

The isolator of the embodiment includes: a ΔΣ analog-to-digital converter that converts an analog signal into a 1-bit digital signal and transmits it as normal data; a time-division multiplexing circuit that performs time-division multiplexing, and in the time-division multiplexing, alternately performs processing of converting the normal data into a digital differential signal and transmitting it, and processing of transmitting a special signal different from the normal data; and an insulation transmission circuit that transmits the digital differential signal and the special signal transmitted from the time-division multiplexing circuit via an insulating layer.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2021-50719 (filing date: March 24, 2021). This application includes all the contents of the basic application by reference. Technical Field

[0003] Embodiments relate to isolators. Background Art

[0004] When a control device controls a target device such as a motor, the motor and the control device are connected via an isolator. The isolator has an insulating layer between the input side and the output side, and safely transmits signals such as current and voltage detected by the motor to the control device.

[0005] The isolator is divided into a primary circuit on the input side and a secondary circuit on the output side through an insulating layer. The primary circuit digitizes the analog signal input from the target device and transmits it to the insulating layer after modulation. The secondary circuit demodulates the data transmitted through the insulating layer and outputs it to the control device side.

[0006] At this time, in the primary circuit of the isolator, a ΔΣ analog-to-digital converter (ΔΣADC) is used as a structure for digitizing the analog input signal. The ΔΣADC is a circuit that quantizes the analog signal by oversampling and ΔΣ modulation, thereby converting it into a pulse train corresponding to the amplitude of the analog signal and outputting it. The output signal of the ΔΣADC is ΔΣ modulated to bias the quantization noise to the high frequency side, so the quantization noise can be well removed by applying a low-pass filter.

[0007] However, in an isolator, when an abnormal state occurs, such as an over-large input, it is desirable to stop the operation of the target device as quickly as possible. However, the output of the ΔΣADC is a 1-bit data string, and it is impossible to determine whether the amplitude of the input signal is large unless multiple bits of data are obtained. On the other hand, if a dedicated transmission path is provided in the isolator for transmitting data indicating that it is an abnormal state, the circuit area and current consumption will increase. Summary of the invention

[0008] The embodiment provides an isolator capable of transmitting data other than normal data with a short delay time without providing a dedicated transmission path.

[0009] The isolator of the embodiment includes: a ΔΣ analog-to-digital converter that converts an analog input signal into a 1-bit digital signal and transmits it as normal data; a time-division multiplexing circuit that performs time-division multiplexing, which is time-division multiplexing that alternately performs processing of converting the normal data from the ΔΣ analog-to-digital converter into a digital differential signal and transmitting it, and processing of transmitting a special signal different from the output of the ΔΣ analog-to-digital converter; and an insulation transmission circuit that transmits the digital differential signal and the special signal transmitted from the time-division multiplexing circuit via an insulating layer. Description of the Drawings

[0010] Figure 1 It is a diagram showing the structure of the isolator of the first comparative example.

[0011] Figure 2 It is a diagram showing the structure of the isolator of the second comparative example.

[0012] Figure 3 It is a diagram showing the structure of the isolator of the first embodiment.

[0013] Figure 4 It is a timing diagram for explaining signal transmission in the signal primary circuit and the insulation primary circuit of the isolator of the first embodiment.

[0014] Figure 5 It is a timing diagram for explaining signal transmission in the insulation primary circuit and the insulation secondary circuit of the isolator of the first embodiment.

[0015] Figure 6 It is a timing diagram for explaining the output of the isolator of the first embodiment at the time of an excessive input.

[0016] Figure 7 Relating to the second embodiment, it is a diagram for explaining a technique for reducing the folding back of quantization noise biased toward the high-frequency side included in the output of the ΔΣ ADC to the low-frequency side when performing interval rejection (sampling data) on the output of the ΔΣ ADC by time-direction coding.

[0017] Figure 8 It is a diagram showing a structural example of the high-speed feedback processing circuit (FFB) of the second embodiment.

[0018] Figure 9 Relating to the third embodiment, it is a diagram for explaining a technique for further reducing the folding back of quantization noise biased toward the high-frequency side included in the output of the ΔΣ ADC1b to the low-frequency side when performing interval rejection on the output of the ΔΣ ADC1b by time-direction coding.

[0019] Figure 10It is a diagram showing a first configuration example of a high-speed feedback processing circuit (FFB) according to the third embodiment.

[0020] Figure 11 It is a diagram showing a second configuration example of the high-speed feedback processing circuit (FFB) according to the third embodiment.

[0021] Figure 12 It is a diagram showing a third configuration example of the high-speed feedback processing circuit (FFB) according to the third embodiment.

[0022] Figure 13 The third embodiment is shown Figure 12 A diagram showing an example of the structure of a logic unit of a high-speed feedback processing circuit (FFB).

[0023] Figure 14 The first to third embodiments are described as follows: no thinning (14A), simple thinning (14B), and the second embodiment. Figure 8 The structure (14C) of the third embodiment Figure 9 A graph of the simulation results of the structure (14D). DETAILED DESCRIPTION

[0024] Before describing the embodiment with reference to the drawings, a comparative example will be described first.

[0025] (First Comparative Example)

[0026] Figure 1 It is a diagram showing the structure of an isolator according to a first comparative example.

[0027] The isolator is an insulating amplifier including a primary circuit 101 on the input side and a secondary circuit 102 on the output side via an insulating layer. The primary circuit 101 includes a signal primary circuit 101S on the input side and an insulating primary circuit 101I on the insulating side. The secondary circuit 102 includes an insulating secondary circuit 102I on the insulating side and a signal secondary circuit 102S on the output side.

[0028] In addition, Figure 1 and the following Figure 2 , Figure 3 In the example, the primary circuit is composed of two chips, namely the signal primary circuit and the insulating primary circuit, and the secondary circuit is composed of two chips, namely the signal secondary circuit and the insulating secondary circuit, but the present invention is not limited to this. For example, the entire primary circuit can be composed of one chip, and the entire secondary circuit can be composed of one chip.

[0029] Although the illustration is omitted, the isolator is connected to an object device such as a motor (object device) to be detected for current / voltage, etc. on the input side. In addition, a control device for controlling the object device is connected to the output side of the isolator via, for example, an external low-pass filter or the like.

[0030] An analog input signal from the object device is input to the input terminals INP and INN of the signal primary circuit 101S of the isolator. Usually, the negative input terminal INN is grounded, so the signal representing the state of the object device is input to the positive input terminal INP. The analog input signals from the input terminals INP and INN are amplified by a preamplifier (INPUT) 101a of the input stage to a predetermined gain multiple. The analog input signal amplified by the input stage preamplifier 101a is input to a delta-sigma (ΔΣ) type analog-to-digital converter (ΔΣADC) 101b. The ΔΣADC 101b performs ΔΣ modulation on the analog input signal to digitize it and outputs it as a 1-bit data string. The 1-bit data output from the ΔΣADC 101b is output from the output buffer (BUF1) 101c of the signal primary circuit 101S to the insulation primary circuit 101I.

[0031] The insulation primary circuit 101I obtains the 1-bit data output from the signal primary circuit 101S from the signal detector (SD I1 ) 101d and modulates it through a data modulator (DATA Mod) 101e. The data modulator 101e performs data modulation for transmitting the 1-bit data from the insulation primary circuit 101I to the insulation secondary circuit 102I. The modulated data obtained by modulating the 1-bit data through the data modulator 101e is output to the transformer primary coil 101g through a driver (DRI D ) 101f. The transformer primary coil 101g transmits the magnetic signal corresponding to the modulated data to the secondary circuit 102 side.

[0032] In addition, in Figure 1 and those described later Figure 2 , Figure 3 etc., examples of wireless signal transmission in the insulating layer by a magnetic insulation method using a coil are described, but it is not limited thereto. Wireless signal transmission in the insulating layer can be performed, for example, by a capacitive insulation method using a capacitor, or by an optical insulation method using a light-emitting element and a phototransistor.

[0033] The secondary circuit 102 receives the magnetic signal from the transformer primary coil 102a of the insulation secondary circuit 102I through the transformer secondary coil 102a and converts it into an electrical signal. The modulated data converted into an electrical signal is passed through an amplifier (AMP D)102b is amplified and demodulated into 1-bit data by a demodulator (Comp / Dec) 102c. The demodulated 1-bit data is output to a signal secondary circuit 102S via a buffer (BUF D )102d.

[0034] The signal secondary circuit 102S obtains the 1-bit data output from the isolation secondary circuit 102I through a signal detector (SD S2 )102e. An output control circuit 102f determines whether the 1-bit data obtained by the signal detector (SD S2 )102e is normal output data (normal data) or output data with an abnormality such as a detected excessive input. The output control circuit 102f also adjusts the timing according to the determination result and outputs the 1-bit data to a low-pass filter circuit (LPF) 102g. The LPF 102g analogizes the string of 1-bit data demodulated by the demodulator 102c and applies a prescribed low-pass filter, and outputs the analog signal after passing through the low-pass filter from output terminals OUTP and OUTN.

[0035] In an isolator, for example, in the presence of an abnormal state such as an excessive input, it is desired to stop the operation of the target device as short a time as possible. However, the output of the ΔΣADC 101b is a string of 1-bit data, and it is impossible to determine whether the amplitude of the input signal is large unless multiple-bit data is obtained. At Figure 1 the subsequent stage of the output terminals OUTP and OUTN of the isolator shown, a signal detector using a narrowband filter is usually configured to obtain a high signal-to-noise ratio (SNR). This signal detector requires a delay time of about several tens of μs, for example, when making a determination. As a signal detector, if both a high-SNR detector using a narrowband filter and a low-SNR detector not using a narrowband filter are prepared, the delay time until determination can be shortened to about 2 μs, for example, by using the low-SNR detector. However, devices using silicon carbide (SiC) etc. with a high dielectric breakdown electric field strength, saturated electron velocity, thermal conductivity, etc. are sometimes damaged within several μs due to an excessive input, and thus it is desired that the delay time of the isolator be 1 μs or less.

[0036] (Second Comparative Example)

[0037] Figure 2 is a diagram showing the structure of the isolator of the second comparative example. Figure 2 The structure is an example of transmitting information on an abnormal state such as an excessive input within a short delay time inside the isolator.

[0038] The isolator of the second comparative example includes: a primary circuit 201 including a signal primary circuit 201S and an insulated primary circuit 201I; and a secondary circuit 202 including an insulated secondary circuit 2020I and a signal secondary circuit 202S. An analog input signal is input from input terminals INP and INN to the primary circuit 201. The secondary circuit 202 outputs an analog signal from output terminals OUTP and OUTN.

[0039] The signal primary circuit 201S includes an input-stage preamplifier (INPUT), an abnormality detection circuit 201a, a ΔΣADC 201b, an output buffer 201c, and an output buffer 201h. The ΔΣADC 201b and the output buffer 201c are respectively Figure 1 configured in the same manner as the ΔΣADC 101b and the output buffer 201c.

[0040] The insulated primary circuit 201I includes a signal detector 201d, a data modulator 201e, a driver 201f, a primary transformer coil 201g, a signal detector 201i, a data modulator 201j, a driver 201k, and a primary transformer coil 201m. The signal detector 201d, the data modulator 201e, the driver 201f, and the primary transformer coil 201g are respectively Figure 1 configured in the same manner as the signal detector 101d, the data modulator 101e, the driver 101f, and the primary transformer coil 101g.

[0041] The insulated secondary circuit 202I includes a secondary transformer coil 202a, an amplifier 202b, a demodulator 202c, a buffer 202d, a secondary transformer coil 202h, an amplifier 202i, a demodulator 202j, and a buffer 202k. The secondary transformer coil 202a, the amplifier 202b, the demodulator 202c, and the buffer 202d are respectively Figure 1 configured in the same manner as the secondary transformer coil 102a, the amplifier 102b, the demodulator 102c, and the buffer 102d.

[0042] The signal secondary circuit 202S includes a signal detector 202e, an output control circuit 202f, a low-pass filter circuit 202g, and a signal detector 202m. The signal detector 202e is Figure 1 configured in the same manner as the signal detector 102e.

[0043] The input-stage preamplifier and the abnormality detection circuit 201a of the signal primary circuit 201S not only operate as an input-stage preamplifier but also determine whether the analog input signal from the input terminals INP and INN is an excessive input, and generate and output a determination signal. The determination of an excessive input (for example, excessive voltage) is performed, for example, by comparing the amplitude (for example, voltage) of the analog input signal with a threshold value.

[0044] The determination signal output from the input-stage preamplifier and the abnormality detection circuit 201a is output to the isolation primary circuit 201I via the output buffer 201h. Therefore, the determination signal is transmitted to the isolation primary circuit 201I without passing through the ΔΣADC 201b. The isolation primary circuit 201I obtains the determination signal output from the signal primary circuit 201S from the signal detector 201i and modulates it through the data modulator 201j. The data modulator 201j performs data modulation on the determination signal for transmission from the isolation primary circuit 201I to the isolation secondary circuit 202I. The determination signal modulated by the data modulator 201j (the modulated determination signal) is output to the transformer primary coil 201m by the driver 201k. The transformer primary coil 201m transmits the magnetic signal corresponding to the modulated determination signal to the secondary circuit 202 side.

[0045] The secondary circuit 202 receives the magnetic signal from the transformer primary coil 201m through the transformer secondary coil 202h of the isolation secondary circuit 202I and converts it into an electrical signal. The modulated determination signal converted into an electrical signal is amplified by the amplifier 202i and demodulated into a determination signal by the demodulator 202j. The demodulated determination signal is output to the signal secondary circuit 202S via the buffer 202k.

[0046] The signal secondary circuit 202S obtains the determination signal output from the isolation secondary circuit 202I through the signal detector 202m. The output control circuit 202f inputs the determination signal obtained by the signal detector 202m and identifies it as an excessive input when the determination signal is a signal indicating an excessive input. Then, the output control circuit 202f controls the low-pass filter circuit 202g to output an analog signal indicating an excessive input from the low-pass filter circuit 202g to the output terminals OUTP and OUTN. Alternatively, dedicated output terminals different from the output terminals OUTP and OUTN may be provided in the secondary circuit 202, and the output control circuit 202f outputs an analog signal indicating an excessive input from the dedicated output terminals.

[0047] In this way, in Figure 2 the structure, in addition to the transmission path for transmitting normal data through the ΔΣADC 201b, a transmission path for transmitting the determination signal from the signal primary circuit 201S to the signal secondary circuit 202S is also provided. The determination signal does not pass through the ΔΣADC 201b, so that the determination signal can be transmitted from the signal primary circuit 201S to the signal secondary circuit 202S with a shorter delay time. However, Figure 2 the isolator of the structure requires two systems of transmission paths, so compared with the isolator of the Figure 1 structure, the circuit area and power consumption are significantly increased.

[0048] Therefore, an isolator that transmits data different from normal data with a delay time shorter than that of normal data without significantly increasing the circuit area and current consumption will be described in the following embodiments.

[0049] (First Embodiment)

[0050] Figure 3 FIG. is a diagram showing the structure of the isolator according to the first embodiment. Figure 3 and Figure 1 and Figure 2 Comparing, it can be seen that the isolator of this embodiment does not provide two systems of transmission paths such as the isolator of Figure 2 and, like the isolator of Figure 1 , a single system of transmission path is basic. Therefore, Figure 3 Most of the isolator of Figure 1 is configured in the same manner as the isolator of

[0051] That is, the isolator of this embodiment is an isolation amplifier having a primary circuit 1 on the input side and a secondary circuit 2 on the output side with an insulating layer therebetween. The primary circuit 1 includes a signal primary circuit 1S on the input side and an insulating primary circuit 1I on the insulating side. The secondary circuit 2 includes an insulating secondary circuit 2I on the insulating side and a signal secondary circuit 2S on the output side. The insulating primary circuit 1I and the insulating secondary circuit 2I constitute an insulating transmission circuit and transmit the differential signal from the signal primary circuit 1S via the insulating layer. As described above, in this embodiment, it is assumed that the signal primary circuit 1S, the insulating primary circuit 1I, the insulating secondary circuit 2I, and the signal secondary circuit 2S are each composed of one chip, but it is not limited thereto.

[0052] Referring to Figures 4 to 6 the timing chart of Figure 3 the structure of the isolator shown will be described. Figure 4 is a timing chart for explaining the signal transmission in the signal primary circuit 1S and the insulating primary circuit 1I of the isolator according to this embodiment. Figure 5 is a timing chart for explaining the signal transmission in the insulating primary circuit 1I and the insulating secondary circuit 2I of the isolator according to this embodiment. Figure 6 is a timing chart for explaining the output of the isolator according to this embodiment during an excessive input.

[0053] The analog signal output from an object device such as a motor is input to the input terminals INP and INN of the signal primary circuit 1S of the isolator. The analog input signals from the input terminals INP and INN are determined whether they are over-inputs by the input-stage preamplifier (INPUT) and the abnormality detection circuit 1a. As described above, since the input terminal INN on the negative side is usually grounded, the input-stage preamplifier and the abnormality detection circuit 1a determine normal operation when the amplitude of the signal input from the input terminal INP on the positive side is below the over-input threshold Th, and determine it as an over-input when it is greater than the over-input threshold Th (refer to Figure 6 INP). When it is determined as normal operation, the input-stage preamplifier and the abnormality detection circuit 1a generate L (low level) (digital value "0") as the determination signal S FFB and output it. If it is determined as an over-input, H (high level) (digital value "1") is generated as the determination signal S FFB and output (refer to Figures 4 to 6 S_FFB).

[0054] In addition, the input-stage preamplifier and the abnormality detection circuit 1a amplify the analog input signals from the input terminals INP and INN by a specified gain factor. The analog input signal amplified by the input-stage preamplifier and the abnormality detection circuit 1a is input to a ΔΣ (ΔΣ) type analog-to-digital converter (ΔΣADC) 1b. The ΔΣADC 1b performs ΔΣ modulation on the analog input signal and digitizes it into a 1-bit data string and outputs it. The two outputs A and B of the ΔΣADC 1b are digital differential signals. If one is H, the other is L (H / L), and if one of the two outputs is L, the other is H (L / H) (refer to Figures 4 to 6 ΔΣOUT). The 1-bit signal output from the ΔΣADC 1b is input to the high-speed feedback processing circuit (FFB) 1c.

[0055] FFB 1c inputs the determination signal S from the input-stage preamplifier and the abnormality detection circuit 1a FFB . FFB 1c directly outputs the output of the ΔΣADC 1b as it is to the output buffer (BUF1) 1d when the determination signal S FFB is L (indicating normal operation). Therefore, the two outputs C and D of the output buffer 1d become H / L or L / H (refer to the part corresponding to S_FFB being L in Figures 4 to 6 BUF1OUT).

[0056] On the other hand, FFB 1c when the determination signal S FFBWhen it is H (indicating an excessive input), the normal data of ΔΣADC1b and special data (special signal) different from the output of ΔΣADC1b (which cannot be the output of ΔΣADC1b) are alternately output at each clock. Here, the two outputs of the normal data of ΔΣADC1b are H / L or L / H. Therefore, FFB1c outputs L / L or H / H as special data that is neither H / L nor L / H (hereinafter, an example where the special data is L / L will be described, but it can also be H / H instead of L / L). As a result, the two outputs C and D of the output buffer 1d alternately become normal data and special data at each clock (refer to BUF1OUT corresponding to the part where S_FFB in Figures 4 to 6 is H).

[0057] The determination signal S FFB is directly input to FFB1c from the input - stage pre - amplifier and the abnormality detection circuit 1a without passing through ΔΣADC1b. When the determination signal S FFB is H, special data is inserted between the normal data at every other clock for transmission. Therefore, the transmission of special data when it is determined to be an excessive input bypasses ΔΣADC1b.

[0058] In addition, data other than normal data is used for abnormality detection in the isolator. For example, when the power supply of the signal primary circuit 1S is in the off state, the two outputs C and D of the output buffer 1d are continuously L / L, and the two inputs I and J of the signal detector (SD S2 ) 2e of the signal secondary circuit 2S are L / L. Similarly, when the isolation primary circuit 1I or the isolation secondary circuit 2I is in the power - off state, the two inputs I and J of the signal detector 2e of the signal secondary circuit 2S are also L / L.

[0059] Therefore, when the signal secondary circuit 2S receives the first L / L as inputs I and J, the output control circuit 2f cannot determine whether it indicates that the power supply of one or more of the signal primary circuit 1S, the isolation primary circuit 1I, and the isolation secondary circuit 2I is in the off state, or whether it indicates that the signal primary circuit 1S has detected an excessive input.

[0060] However, when H / L or L / H is received as inputs I and J at the next clock, the signal secondary circuit 2S can determine that the signal primary circuit 1S has detected an excessive input. On the other hand, when L / L continues to be received as inputs I and J at the next clock, the signal secondary circuit 2S can determine that the power supply of one or more of the signal primary circuit 1S, the isolation primary circuit 1I, and the isolation secondary circuit 2I is in the off state.

[0061] Further, if H / H is used as special data, it can be determined at the moment of initially receiving H / H that it is not that one or more of the power supplies in the signal primary circuit 1S, the insulation primary circuit 1I, and the insulation secondary circuit 2I are in the off state (L / L), but rather that the signal primary circuit 1S has detected an excessive input.

[0062] In this way, FFB1c generates an L / L signal (or an H / H signal) at every one clock in the time direction, so as to be able to distinguish an excessive input from the power-off states of the signal primary circuit 1S, the insulation primary circuit 1I, and the insulation secondary circuit 2I. The technique of multiplexing and transmitting multiple signals in this time-division manner (i.e., in the time direction) (time-direction signal multiplexing technique) is called time-direction coding. FFB1c is a time-direction multiplexing circuit that performs time-direction multiplexing.

[0063] The signal transmission between the chips of the signal primary circuit 1S and the insulation primary circuit 1I, and the signal transmission between the chips of the insulation secondary circuit 2I and the signal secondary circuit 2S are carried out by wire. In addition, the signal transmission between the chips of the insulation primary circuit 1I and the insulation secondary circuit 2I is carried out wirelessly via a transformer. Between chips, in the case of signal transmission using any of these wired and wireless methods, when transmitting normal data, a differential signal with two complementary inputs and two outputs (so-called differential signal with two pins) is used, which is a condition for using time-direction coding. That is, this is because by using an H / L or L / H differential signal as normal data, L / L or H / H as special data can be transmitted through time-direction coding.

[0064] In addition, from the perspective of power consumption, it is not necessarily required to transmit differential signals within the chip. However, when differential signals are not transmitted within the chip, the number of pins in the chip-to-chip interface increases, and the power consumption of the interface portion becomes larger. Therefore, it is preferable to transmit differential signals through the same transmission path within the chip as well.

[0065] Time-direction coding can generally transmit two or more types of data Di (i represents the type of data, i = 1, 2,...) in a time-division manner. For example, when i = 2, if k is set as the number representing the operation clock, then like D1(k), D2(k + 1), D1(k + 2), D2(k + 3)..., the first type of data D1 and the second type of data D2 are alternately transmitted at each operation clock. At this time, the data that cannot be sent through time division, here D2(k), D1(k + 1), D2(k + 2), D1(k + 3)... for example, is directly discarded.

[0066] When the data D1 of the first type is normal data, for example, when transmitting two types of data, the data D2(k + 1), D2(k + 3),... of the second type that are periodically repeated are special data. By detecting the special data at regular intervals, it is possible to determine that two types of data have been transmitted.

[0067] The same applies when transmitting three or more types of data. Let m be an integer greater than or equal to 2, and assume that there are m types of the above special data. At this time, the time-division multiplexing circuit alternately performs the process of converting normal data into a digital differential signal and transmitting it with one operation clock, and the process of transmitting m types of special data with m operation clocks. The m types of special data are transmitted in a specified order. In this case, since i = (m + 1), data transmission is performed in the order of D1(k), D2(k + 1), D3(k + 2),..., D(m + 1)(k + m), D1(k + m + 1), D2(k + m + 2)....

[0068] In this way, in the present embodiment, normal data D1 is transmitted when the input is not excessive, and when it is necessary to transmit two or more types of data such as excessive input, two or more types of data Di (i = 1, 2,...) are transmitted by time-division encoding.

[0069] The output buffer 1d outputs the signal input from the FFB1c to the isolation primary circuit 1I.

[0070] The isolation primary circuit 1I obtains the signal output from the signal primary circuit 1S from the signal detector (SD I1 ) 1e. Here, the two inputs E and F of the isolation primary circuit 1I are delayed by the time required for inter-chip transmission compared to the two outputs C and D of the signal primary circuit 1S, but it is described as having no delay in Figure 5 .

[0071] The data modulator (DATA Mod) 1f performs data modulation on the signal obtained from the signal detector 1e for transmission from the isolation primary circuit 1I to the isolation secondary circuit 2I. The modulated data obtained by modulating the signal obtained from the signal detector 1e by the data modulator 1f is output to the transformer primary coil 1h through the driver (DRI D ) 1g. The transformer primary coil 1h transmits a magnetic signal corresponding to the modulated data to the secondary circuit 2 side.

[0072] In addition, in the case of signal transmission from the insulated primary circuit 1I to the insulated secondary circuit 2I via a transformer, when the signal detector 1e receives L / L, if the insulated primary circuit 1I does not send data to the insulated secondary circuit 2I, the insulated secondary circuit 2I substantially receives an L / L signal. Therefore, a receiver that interprets as receiving an L / L signal when no signal from the insulated primary circuit 1I is detected within a specified time can also be installed in the actual insulated secondary circuit 2I.

[0073] The secondary circuit 2 receives a magnetic signal from the transformer primary coil 1h through the transformer secondary coil 2a of the insulated secondary circuit 2I and converts it into an electrical signal. The modulated data converted into an electrical signal is amplified by an amplifier (AMP D ) 2b and demodulated into the original data by a demodulator (Comp / Dec) 2c. The demodulated data is output to the signal secondary circuit 2S via a buffer (BUF D ) 2d.

[0074] Two outputs G and H (see Figure 5 and Figure 6 BUFDOUT) of the insulated secondary circuit 2I are obtained by delaying two input E and F (see Figure 5 and Figure 6 SD1IN) of the insulated primary circuit 1I by two clock amounts. That is, the insulated secondary circuit 2I transfers the signal to the signal secondary circuit 2S while maintaining the state of time-direction encoding.

[0075] The signal secondary circuit 2S obtains the data output from the insulated secondary circuit 2I through a signal detector (SD S2 ) 2e. The output control circuit 2f outputs the data obtained from the signal detector 2e to a low-pass filter circuit (LPF) 2g via a data transmission path. In addition, the output control circuit 2f and the LPF 2g are connected through a signal transmission path (notification line) different from this data transmission path.

[0076] The output control circuit 2f determines which of the normal data of H / L or L / H and the special data of L / L the data obtained from the signal detector 2e is. When it is determined that the data is normal data, the output control circuit 2f notifies the LPF 2g via the notification line of the determination result indicating that the data is normal data.

[0077] On the other hand, when the output control circuit 2f determines that the data obtained from the signal detector 2e is special data (L / L), it further determines the data obtained at the next clock. That is, when the data obtained at the next clock is H / L or L / H, the output control circuit 2f determines that it is an excessive input, and when it is L / L, it determines that it is an abnormal state other than this (the power supply of one or more of the signal primary circuit 1S, the insulation primary circuit 1I, and the insulation secondary circuit 2I is in the off state). In this way, the determination of excessive input performed by the output control circuit 2f when special data is detected uses the data of two consecutive clocks.

[0078] When the output control circuit 2f determines that it is an excessive input, it sends a determination result indicating that it is an excessive input to the LPF 2g via the notification line.

[0079] The LPF 2g analogizes the data (a 1-bit data string) received from the output control circuit 2f via the data transmission path and applies a prescribed low-pass filter. When the LPF 2g receives a determination result indicating that it is normal data, it outputs the analog signal after passing through the low-pass filter as a positive (+) signal from the output terminal OUTP and as a negative (+) signal from the output terminal OUTN. The signal output from the output terminal OUTP and the signal output from the output terminal OUTN have the same in-phase voltage except for the positive and negative of the signal.

[0080] When the LPF 2g receives a determination result indicating that it is an excessive input from the output control circuit 2f, it simultaneously shifts the in-phase voltage of the signals output from the output terminals OUTP and OUTN by, for example, an appropriate + voltage (refer to Figure 6 OUTP and OUTN).

[0081] In Figure 6 the shown timing diagram, an example is shown in which when the LPF 2g receives H / L or L / H after receiving L / L, the in-phase signal is shifted at the moment when the rising edge of the received H / L or L / H is detected. However, depending on the design of the LPF 2g, there may also be a case where, after receiving H / L or L / H, the shift of the in-phase signal is further delayed by one clock due to the signal processing delay of the designed circuit. In addition, the shift of the in-phase voltage based on the LPF 2g is generally performed as the rise of the voltage based on a prescribed time constant, but in Figure 6 an example of a steep rise without considering the time constant is illustrated. In addition, Figure 6 the threshold Th' indicated by the signal for the output terminal OUTP in

[0082] According to the first embodiment, by performing time-direction encoding, it is possible to transmit special data other than normal data without providing a transmission path dedicated to special data in the isolator. As a result, a significant increase in the circuit area and current consumption of the isolator can be suppressed.

[0083] At this time, when the input-stage preamplifier and the abnormality detection circuit 1a detect an excessive input, the determination signal S is transmitted without passing through the ΔΣADC1b, so that data indicating that it is an excessive input can be transmitted with a short delay time. FFB to the FFB1c, so that data indicating that it is an excessive input can be transmitted with a short delay time.

[0084] In addition, when an excessive input is detected, the in-phase signal output from the LPF2g is shifted, so that a signal indicating that it is an excessive input can be output from the output terminals OUTP and OUTN, and no additional dedicated output terminals need to be provided.

[0085] (Second Embodiment)

[0086] Figure 7 Regarding the second embodiment, it is a diagram for explaining a technique for reducing the folding of quantization noise biased toward the high-frequency side in the output of the ΔΣADC1b to the low-frequency side when performing interval removal on the output of the ΔΣADC1b by time-direction encoding. In the second embodiment, the same reference numerals are assigned to the same parts as those in the first embodiment and the description thereof is omitted, and mainly the differences are described.

[0087] The ΔΣADC1b is a circuit that quantizes an analog signal by oversampling and performing ΔΣ modulation, and then converts it into a pulse train corresponding to the amplitude of the analog signal and outputs it. Since the quantization noise is biased toward the high-frequency side by ΔΣ modulation, the quantization noise can be removed well by applying a low-pass filter.

[0088] However, in the first embodiment, when an excessive input is detected, the FFB1c inserts special data every one clock, so that the normal data output from the ΔΣADC1b becomes data with every one clock interval removed. Then, the frequency of the normal data becomes half, and the quantization noise on the high-frequency side folds back to the low-frequency side and overlaps with the signal frequency band on the low-frequency side close to direct current (DC). After the interval-removed normal data is transmitted through the insulating layer, for example, the same data is output continuously for two clocks at the original frequency by 0 insertion and filtering processing (appropriately referred to as stretching processing), thereby performing data stretching. However, even if a low-pass filter is applied after data stretching, the quantization noise folded back in the signal frequency band on the low-frequency side cannot be removed, and the signal-to-noise ratio (SNR) is significantly reduced. The change in the input signal to the ΔΣADC1b is slow, and the significant reduction in the SNR is the same (also refer to the followingFigure 14 )。

[0089] However, a significant reduction in SNR occurs when the input signal to ΔΣADC1b is within the ADC range, that is, when the data output from ΔΣADC1b contains both H / L and L / H. In contrast, when the input signal to ΔΣADC1b is outside the ADC range, the data output from ΔΣADC1b is all H / L continuous or all L / H continuous. Therefore, no quantization error is generated in the data output from ΔΣADC1b, and even if every other clock is removed, the quantization noise does not fold back and superimpose. Furthermore, if the data is stretched after being transmitted through the insulating layer, the data output from ΔΣADC1b is directly restored, and as a result, the result is not affected by the removal of every other clock. Therefore, even when the input signal applied to ΔΣADC1b is within the ADC range, the technique for reducing quantization noise performed in this second embodiment (and the third embodiment described later) is effective when the input-stage preamplifier and the abnormality detection circuit 1a are set to detect an excessive input.

[0090] Hereinafter, the output signal of ΔΣADC1b is denoted as ΔΣ(k), and the signal obtained by removing every other one of ΔΣ(k) is denoted as ΔΣ dcm (2j + 1). Here, k represents the clock number, k = (2j + 1) (where j is an integer). And ΔΣ(k) is a signal obtained by converting an input signal within the ADC range, and is a signal in which the quantization noise is biased toward the high-frequency side of the signal frequency band as shown by the shaded area in the curve graph G1 in Figure 7 . In addition, in each of the curve graphs G1, G3 to G6, G8, the horizontal axis represents frequency, and the vertical axis represents the relative value of power. Instead of adding the values of the signal and the noise, the signal and the noise are arranged (in a way that the noise can be seen on the front side) and recorded. In addition, in the curve graphs G2, G7, the horizontal axis represents frequency, and the vertical axis represents the passing characteristic (relative passing rate).

[0091] Refer to Figure 7 to describe the technique for reducing the folding back of the quantization noise that has been biased toward the high-frequency side due to the removal of every other one.

[0092] ΔΣADC1b oversamples the analog input signal at 20 Mbps (the signal component is 10 MHz or less), performs ΔΣ modulation and quantization, and outputs a 1-bit pulse train signal ΔΣ(k) at a frequency of 10 MHz, for example.

[0093] The FFB1c of this embodiment includes a low-pass filter circuit (LPF) 11 as a noise suppression filter, a removal circuit 12 for removing every other one, and a quantizer 13.

[0094] The signal ΔΣ(k) from the ΔΣ ADC 1b is input to the LPF 11 of the FFB 1c. The band-pass characteristic of the LPF 11 is a characteristic in which the signal that passes through as shown in the graph G2 attenuates from the low-frequency side toward the high-frequency side. As the LPF 11 that realizes such a characteristic, for example, a circuit structure that performs simple processing such as moving average can be used. However, since addition, subtraction, etc. are performed in the circuit of the LPF 11 for the moving average, if n is set to an integer greater than 1, the number of bits of the signal output from the LPF 11 is n bits.

[0095] The spectrum of the signal output from the LPF 11 is a spectrum in which the quantization noise that is biased toward the high-frequency side in the graph G1 is reduced as shown in the graph G3.

[0096] The decimation circuit 12 outputs the signal output from the LPF 11 every 1 bit, and the bits that are not output are discarded, thereby performing a decimation process of 1 / 2. Through this decimation process, the quantization noise remaining in the high-frequency domain of the signal ΔΣ dcm (2j + 1) folds back as shown in the graph G4, but the remaining amount of the quantization noise after passing through the LPF 11 is small, so the SNR does not decrease significantly compared to the case without the LPF 11.

[0097] The quantizer 13 quantizes an n-bit signal having a frequency of, for example, 5 MHz output from the decimation circuit 12 and converts it into a 1-bit data string signal of 10 Mbps (the signal component is 5 MHz or less). The 1-bit signal converted by the quantizer 13 is denoted as ΔΣ RQdcm (2j + 1). Here, the reason for returning to the 1-bit signal again by the quantizer 13 is that if inter-chip transmission is performed while maintaining n bits, an interface of n bits is required and the current consumption increases.

[0098] The spectrum of the signal output from the quantizer 13 is as shown in the graph G5, and becomes a spectrum obtained by adding frequency-flat quantization noise to the decimated spectrum shown in the graph G4. Therefore, the SNR of the signal output from the quantizer 13 is lower than the SNR of the signal output from the decimation circuit 12. However, compared to the case where the output signal from the ΔΣ ADC 1b is directly decimated by the decimation circuit 12 without passing through the LPF 11, the SNR can be maintained at a higher level.

[0099] In addition, in Figure 7 , the decimation circuit 12 is arranged in the front stage and the quantizer 13 is arranged in the rear stage, but the order can also be reversed, with the quantizer 13 arranged in the front stage and the decimation circuit 12 arranged in the rear stage.

[0100] As described in the first embodiment, data transfer between chips is performed through a signal that is formed by alternately arranging, for each clock of 10 MHz, special data L / L (e.g., 5 MHz) indicating an over-large input and normal data (e.g., 5 MHz) of a 1-bit data string output from the quantizer 13.

[0101] The 5-MHz signal ΔΣ transmitted between chips RQdcm (2j + 1) For example, through the stretching circuit 21 provided in the output control circuit 2f, the above-mentioned 0 insertion and stretching processing based on filtering processing are performed. Here, the stretching processing is specifically a process of outputting a signal of the same bit value, such as "0", every two clocks in synchronization with a 10-MHz clock. The sampling frequency of the signal after the stretching processing returns to 20 MHz, which is the same as the frequency of the output signal from the ΔΣADC1b, and is denoted as ΔΣ RQ (j). Through this stretching processing, as shown in the graph G6, the quantization noise on the high-frequency side is stretched and the peak value becomes lower.

[0102] The 1-bit signal output from the stretching circuit 21 is subjected to low-pass filtering processing by the LPF2g with an operating clock of 20 MHz. The band-pass characteristic of the LPF2g is, for example, a characteristic that allows only the signal in the low-frequency side signal band close to direct current (DC) to pass as shown in the graph G7, and substantially cuts off the signals in the higher-frequency side band than the signal band.

[0103] For the multi-bit signal that has been subjected to low-pass filtering processing by the LPF2g with such a characteristic, as shown in the graph G8, the quantization noise in the signal band remains, but almost all other quantization noises are suppressed. The SNR of this processing result is higher than that in the case where the output signal from the ΔΣADC1b is directly subjected to interval rejection by the interval rejection circuit 12 without passing through the LPF11.

[0104] Figure 8 FIG. shows a structural example of the high-speed feedback processing circuit (FFB) 1c of this embodiment.

[0105] The LPF11 includes an adder 11a, a delay element 11b, and a 1 / 2 multiplier element 11c. The delay element 11b is arranged on a branch path branched from the transmission path from the ΔΣADC1b to the adder 11a. The output of the delay element 11b is input to the adder 11a. The 1 / 2 multiplier element 11c is arranged in series with the adder 11a after the adder 11a.

[0106] The 1-bit signal ΔΣ(k) output from ΔΣADC1b is input to adder 11a and delay element 11b. Delay element 11b delays the input signal by 1 clock and outputs it. Therefore, adder 11a outputs a 2-bit signal {ΔΣ(k)+ΔΣ(k - 1)} obtained by adding the signal ΔΣ(k) at the current clock and the signal ΔΣ(k - 1) at the previous clock of the current clock. The 1 / 2 multiplier 11c halves the addition signal {ΔΣ(k)+ΔΣ(k - 1)} output from adder 11a by bit shifting. That is, Figure 8 The LPF11 shown becomes a structural example that performs low-pass filtering processing based on moving average.

[0107] The 2-bit signal of 20 Mbps output from the 1 / 2 multiplier 11c of LPF11 is input to the decimation circuit 12, and passes through switch 12a that is turned on / off synchronously with a 10 MHz clock, so that every other one is decimated and becomes a 2-bit signal of 10 Mbps.

[0108] The 2-bit data string output from the decimation circuit 12 is input to quantizer 13 configured as a 1-bit quantizer and is quantized into a 1-bit signal ΔΣ RQdcm (2j + 1). After FFB1c, the signal ΔΣ RQdcm (2j + 1) is transmitted alternately with L / L.

[0109] According to the second embodiment, it has substantially the same effect as the above-described first embodiment, and by providing LPF11 before the decimation circuit 12, it is possible to reduce the quantization noise after decimation and suppress the degradation of the quality of the data to be transmitted.

[0110] (Third Embodiment)

[0111] Figure 9 Regarding the third embodiment, it is a diagram for explaining a technique for further reducing the folding of quantization noise biased toward the high-frequency side included in the output of ΔΣADC1b to the low-frequency side when performing decimation on the output of ΔΣADC1b by time-direction encoding. In the third embodiment, the same reference numerals are given to the same parts as in the first and second embodiments and the description thereof is omitted, and mainly the differences are described.

[0112] Figure 9 The structure shown is Figure 7 a structure in which the quantizer 13 of FFB1c in the structure shown is replaced with a noise shaping circuit 14.

[0113] The noise shaping circuit 14 will be described later with reference to Figure 10This will be described in detail later. Similar to ΔΣ modulation, it is a circuit that biases quantization noise to the high-frequency side by performing a process of adding the remainder (quantization error) when quantizing the input n-bit signal into a 1-bit signal to the next input signal.

[0114] From Figure 7 The spectrum of the signal output from the quantizer 13 is a spectrum obtained by adding quantization noise that is flat in frequency, as shown in the graph G5. In contrast, the spectrum of the signal output from Figure 9 the noise shaping circuit 14 is as shown in the graph G5', and the biasing rate of the quantization noise to the high-frequency side becomes higher. As a result, the quantization noise in the low-frequency side signal band shown in the graph G5' is reduced compared to Figure 7 the graph G5.

[0115] As a result, the 1-bit signal output from the stretching circuit 21 is as shown in the graph G6', and the quantization noise in the low-frequency side signal band is reduced compared to Figure 7 the graph G6. Therefore, the signal that has undergone low-pass filtering by the LPF 2g is as shown in the graph G8', and the quantization noise is further reduced compared to Figure 7 the curve G8, and the SNR becomes higher.

[0116] Figure 10 FIG. is a diagram showing a first structural example of the high-speed feedback processing circuit (FFB) 1c of the present embodiment.

[0117] In the FFB 1c, the noise shaping circuit 14 disposed at the subsequent stage of the interval rejection circuit 12 includes an adder 14a, a subtractor 14b, a quantizer 14c, and a delay element 14d. The input to the noise shaping circuit 14 is connected to the adder 14a. The output of the adder 14a is connected to the subtractor 14b and the quantizer 14c. The quantizer 14c outputs a signal to the outside of the FFB 1c and also outputs a signal to the subtractor 14b. The subtractor 14b subtracts the output of the quantizer 14c from the output of the adder 14a and outputs it to the delay element 14d. The delay element 14d is connected to the adder 14a.

[0118] With such a circuit structure, the 2-bit signal input from the interval rejection circuit 12 is input to the quantizer 14c and the subtractor 14b via the adder 14a. The quantizer 14c performs bit shifting on the 2-bit signal and quantizes it into a 1-bit signal. The subtractor 14b subtracts the signal quantized by the quantizer 14c from the signal before quantization by the quantizer 14c. Thus, the subtractor 14b outputs the remainder (quantization error) based on the quantization by the quantizer 14c to the delay element 14d. The delay element 14d delays the quantization error input from the subtractor 14b by 1 clock and then outputs it to the adder 14a. The adder 14a adds the quantization error of the previous clock input from the delay element 14d to the newly input signal from the interval rejection circuit 12 and outputs the result.

[0119] In this way, the quantization error generated by the quantizer 14c is calculated by the subtractor 14b and fed back, and thus shaping processing is performed in the same manner as the principle of ΔΣ modulation. The quantization noise is biased toward the high-frequency side and becomes smaller on the low-frequency side.

[0120] In addition, Figure 10 The structure shown is an example of performing first-order noise shaping, but it can also be configured to perform higher-order noise shaping, so that the quantization noise is biased more significantly toward the high-frequency side, further reducing the quantization noise in the signal band.

[0121] Figure 11 FIG. is a diagram showing a second structural example of the high-speed feedback processing circuit (FFB) 1c of the present embodiment. Figure 11 is to Figure 10 The circuit is obtained by deforming the circuit topology with the circuit structure as a prototype.

[0122] Figure 11 The FFB1c of Figure 10 includes the LPF interval rejection circuit 15 and the noise shaping circuit 14. The LPF interval rejection circuit 15 is a circuit obtained by aggregating the LPF 11 and the interval rejection circuit 12 connected in series in Figure 11 into one. In Figure 10 the same circuit elements as those in

[0123] The LPF interval rejection circuit 15 includes an adder 11a, delay elements 11b, a 1 / 2 multiplier element 11c, a switch 12a, and a subtractor 15a. The input from the ΔΣADC 1b to the LPF interval rejection circuit 15 is connected to the adder 11a. The output of the adder 11a is connected to the switch 12a and the subtractor 15a via terminal a. The switch 12a switches between on and off for each clock. The output of the switch 12a is connected to the 1 / 2 multiplier element 11c and the subtractor 15a via terminal b. The subtractor 15a subtracts the input via terminal b from the input via terminal a. The output of the subtractor 15a is output to the delay element 11b via terminal c. The delay element 11b delays the input by one clock and then outputs it. The output of the delay element 11b is connected to the adder 11a via terminal d. The adder 11a adds the input from the ΔΣADC 1b and the input via terminal d. The 1 / 2 multiplier element 11c halves the input via terminal b by bit shifting.

[0124] The operation of the LPF interval rejection circuit 15 with such a structure will be described below. In addition, for simplicity of notation, in Figure 11 the description of the operation of the LPF interval rejection circuit 15, the output signal ΔΣ(k) of the ΔΣADC 1b is denoted as ΔΣ(k)=Ak. The clock number k is k = 1, 2, 3, 4,.... In addition, the signal values at the clock number k of terminals a, b, c, and d are denoted as ak, bk, ck, and dk.

[0125] At k = 1, the switch 12a is open, the value of terminal b is 0 (b1 = 0), and the value of terminal d is 0 (d1 = 0). Since d1 = 0, the value of terminal a, which receives A1 from the ΔΣADC 1b, is A1 (a1 = A1). Since a1 = A1 and b1 = 0, the value of terminal c is A1 (c1 = A1). Since b1 = 0, the output of the 1 / 2 multiplier element 11c is 0.

[0126] At k = 2, the switch 12a is closed, and the values of terminal a and terminal b are equal (a2 = b2). Since a2 = b2, the value of terminal c is 0 (c2 = 0). Since the value of terminal d is c1 (= A1) one clock earlier, d2 = A1. The value of terminal a, which receives A2 from the ΔΣADC 1b, is a2=(A1 + A2), and the value of terminal b is also b2=(A1 + A2) the same as a2. Since b2=(A1 + A2), the output of the 1 / 2 multiplier element 11c is (A1 + A2) / 2.

[0127] When k = 3, switch 12a opens again. At this time, the value of terminal b is set to 0 (b3 = 0). Since the value of terminal d is c2 (= 0) one clock before, d3 = 0. The value of terminal a to which A3 is input from ΔΣADC1b is a3 = A3. The value of terminal c is c3 = a3 - b3 = A3. Since b3 = 0, the output of the 1 / 2 - fold element 11c is 0.

[0128] When k = 4, switch 12a closes again. At this time, the value of terminal a is equal to the value of terminal b (a4 = b4). Since a4 = b4, the value of terminal c is 0 (c4 = 0). Since the value of terminal d is c3 (= A3) one clock before, d4 = A3. The value of terminal a to which A4 is input from ΔΣADC1b is a4 = (A3 + A4), and the value of terminal b is also b4 = (A3 + A4) which is the same as a4. Since b4 = (A3 + A4), the output of the 1 / 2 - fold element 11c is (A3 + A4) / 2.

[0129] After that, the above operations are performed in the same way. Thus, the LPF interleaved cancellation circuit 15 interleavedly cancels the average value of the outputs of two consecutive clocks of ΔΣADC1b every other one and outputs it to the noise shaping circuit 14. Therefore, Figure 11 the LPF interleaved cancellation circuit 15 is equivalent to the circuit obtained by combining Figure 10 the LPF 11 and the interleaved cancellation circuit 12.

[0130] Figure 12 FIG. is a diagram showing a third structural example of the high - speed feedback processing circuit (FFB) 1c of the present embodiment. Figure 12 is a circuit obtained by further deforming the Figure 11 circuit topology.

[0131] Figure 12 The FFB 1c of Figure 11 includes an LPF interleaved cancellation noise shaping circuit 16. The LPF interleaved cancellation noise shaping circuit 16 is a circuit obtained by integrating the vertically - connected LPF interleaved cancellation circuit 15 and the noise shaping circuit 14 in Figure 12 into one. In Figure 10 and Figure 11 the same circuit elements are labeled with the same reference numerals.

[0132] The LPF interval rejection noise shaping circuit 16 includes an adder 11a, delay elements 11b, 1 / 2 multiplier element 11c, a switch 12a, a quantizer 14c', and a subtractor 15a. The input from the ΔΣADC 1b to the LPF interval rejection noise shaping circuit 16 is connected to the adder 11a. The output of the adder 11a is connected to the switch 12a and the subtractor 15a via a terminal a. The switch 12a switches between on and off for each clock. The output of the switch 12a is connected to the quantizer 14c'. The quantizer 14c' quantizes the signal by, for example, combining right shift and left shift to set the value of the lower bits to 0. Here, the quantized signal keeps 2 bits unchanged. The quantizer 14c' is connected to the 1 / 2 multiplier element 11c and the subtractor 15a via a terminal b'. The subtractor 15a subtracts the input via the terminal b' from the input via the terminal a. The signal before quantization is input from the terminal a, and the quantized signal is input from the terminal b'. Therefore, the subtractor 15a calculates the quantization remainder (quantization error) and outputs it. The output of the subtractor 15a is output to the delay element 11b via a terminal c. The delay element 11b delays the input by 1 clock and outputs it. The output of the delay element 11b is connected to the adder 11a via a terminal d. The adder 11a adds the input from the ΔΣADC 1b and the input via the terminal d. Therefore, the quantization error output by the subtractor 15a is added to the input signal of the next clock by the adder 11a. The 1 / 2 multiplier element 11c makes the input via the terminal b' half by bit shift and outputs it as a 1-bit signal.

[0133] Figure 12 The operation of the LPF interval rejection noise shaping circuit 16 with the structure of Figure 11 is based on the operation of Figure 12 and is therefore briefly described. In the

[0134] description, it is also described that ΔΣ(k) = Ak.

[0135] If the switch 12a is open at k = 1, A1 input to the adder 11a is held by the delay element 11b, and the output of the 1 / 2 multiplier element 11c is 0.

[0136] If the switch 12a is closed at k = 2, A2 input to the adder 11a and A1 from the delay element 11b are added, quantized by the quantizer 14c', bit-shifted (averaged) by the 1 / 2 multiplier element 11c, and then output. In addition, the subtractor 15a calculates the quantization error after subtracting the quantized (A1 + A2) from the pre-quantization (A1 + A2) and holds it in the delay element 11b.

[0136] If the switch 12a is open at k = 3, A3 input to the adder 11a is held by the delay element 11b, and the output of the 1 / 2 multiplier element 11c is 0.

[0137] If the switch 12a is closed when k = 4, A4 input to the adder 11a and A3 from the delay element 11b are added. After quantization by the quantizer 14c', bit shifting (averaging) is performed by the 1 / 2 times element 11c and then output. In addition, the quantization error obtained by calculating (A3 + A4) before quantization minus (A3 + A4) after quantization by the subtractor 15a is held in the delay element 11b.

[0138] In this way, the quantization error generated in the quantizer 14c' is calculated by the subtractor 15a and fed back, and thus shaping processing is performed in the same manner as the principle of ΔΣ modulation. The quantization noise is biased to the high frequency side and becomes smaller on the low frequency side.

[0139] Figure 13 It represents Figure 12 FIG. showing a logic unit-based structural example of the high-speed feedback processing circuit (FFB) 1c.

[0140] The input stage preamplifier and anomaly detection circuit 1a includes a voltage detector 1a-1.

[0141] The voltage detector 1a-1 determines whether the analog input signal is over-input. When an over-input is detected, it generates 1 as the determination signal S FFB and outputs it to the latch 31. When no over-input is detected, it generates 0 as the determination signal S FFB and outputs it to the latch 31.

[0142] The determination signal from the voltage detector 1a-1 and the internal clock (operation clock) are input to the latch 31. The latch 31 outputs the determination signal to the frequency divider by two 32, the three-input AND gate 44, the AND gate 45, and the selector 48 in synchronization with the internal clock. In addition, the internal clock is also input to the ΔΣADC 1b, the latches 46 and 47 in the LPF interval rejection noise shaping circuit 16, and the frequency divider by two 32.

[0143] When the determination signal from the latch 31 is 1, the frequency divider by two 32 halves the frequency of the internal clock and outputs it. Otherwise, when the determination signal from the latch 31 is 0, the frequency divider by two 32 is always reset and outputs 0.

[0144] The selector 48 is composed of a multiplexer, for example. When the determination signal from the latch 31 is 0, it directly outputs the input from the ΔΣADC 1b as it is. When the determination signal from the latch 31 is 1, it outputs the signal noise-shaped by the LPF interval rejection noise shaping circuit 16.

[0145] The differential output amplifier 34 converts the single-ended input from the selector 48 into a digital differential signal and outputs it. The differential output amplifier 34 outputs 1 / 0 (H / L) when the output from the selector 48 is 1, and outputs 0 / 1 (L / H) when it is 0.

[0146] The selector 33 is constituted by, for example, a multiplexer. When the output of the frequency divider 32 is 0 (when it is not an excessive input), it directly outputs as it is the signal of the ΔΣADC1b that has been converted into a digital differential signal by the differential output amplifier 34.

[0147] In addition, when the output of the frequency divider 32 is a divided-by-two clock (when it is an excessive input), the selector 33 alternately outputs the output from the differential output amplifier 34 and 0, 0. That is, the selector 33 outputs 0, 0 (the L / L signal of the above-mentioned special data) when the output of the frequency divider 32 is 1 (H), and outputs the data signal after re-noise shaping from the differential output amplifier 34 (that is, after noise shaping by the ΔΣADC1b and further noise shaping by the noise shaping circuit 16) when the output of the frequency divider 32 is 0 (L).

[0148] The LPF interval rejection noise shaping circuit 16 includes an AND gate 41, an exclusive-OR gate (XOR gate) 42, an exclusive-OR gate 43, a three-input AND gate 44, an AND gate 45, a latch 46, and a latch 47.

[0149] The output of the ΔΣADC1b is input to the selector 48, the AND gate 41, and the exclusive-OR gate 42. The output of the AND gate 41 is input to the exclusive-OR gate 43. The output of the exclusive-OR gate 43 is input to the selector 48 and the three-input AND gate 44. The output of the three-input AND gate 44 is delayed by 1 clock by the latch 46 that functions as a delay element 11b and then output to the exclusive-OR gate 43. The output of the exclusive-OR gate 42 is input to the AND gate 45. The output of the AND gate 45 is delayed by 1 clock by the latch 47 that functions as a delay element 11b and then output to the AND gate 41 and the exclusive-OR gate 42.

[0150] The AND gate 41 processes the high-order bit when making a 1-bit input from the ΔΣADC1b into 2 bits. The exclusive-OR gate 42 processes the low-order bit when making a 1-bit input from the ΔΣADC1b into 2 bits.

[0151] The AND gate 41 outputs 1 when the input from the ΔΣADC1b is 1 and the output of the AND gate 45 in the previous 1 clock is 1, and outputs 0 in other cases. The exclusive-OR gate 42 outputs 1 when either the input from the ΔΣADC1b or the output of the AND gate 45 in the previous 1 clock is 1, and outputs 0 in other cases.

[0152] That is, it represents (AND gate 41 output, XOR gate 42 output) of (upper bit, lower bit). When the input from ΔΣADC1b is 0, if the output of AND gate 45 in the previous clock is 0, it is (0, 0); if the output of AND gate 45 in the previous clock is 1, it is (0, 1).

[0153] In addition, (AND gate 41 output, XOR gate 42 output) when the input from ΔΣADC1b is 1, if the output of AND gate 45 in the previous clock is 0, it is (0, 1); if the output of AND gate 45 in the previous clock is 1, it is (1, 0).

[0154] As will be described later, the output of AND gate 45 in the previous clock is the quantization error. Therefore, it can be seen that AND gate 41 and XOR gate 42 function as adder 11a that two - bitizes the 1 - bit input from ΔΣADC1b and adds the fed - back quantization error.

[0155] XOR gate 43 functions as quantizer 14c’ and 1 / 2 - multiplier 11c. It outputs 1 when either the output of AND gate 41 or the output of latch 46 in the previous clock is 1, and outputs 0 otherwise. XOR gate 43 that processes the high - order bit of the 2 - bit signal is connected to selector 48, and the low - order bit is not connected to selector 48, thus functioning as 1 / 2 - multiplier 11c.

[0156] Three - input AND gate 44 outputs 1 when the input from XOR gate 43 is 1, the determination signal from latch 31 is 1, and the output of frequency divider 32 is 1, and outputs 0 otherwise. The divided - by - two clock of frequency divider 32 input to three - input AND gate 44 that processes the high - order bit of LPF interval rejection noise - shaping circuit 16 is for performing subtraction operation during noise shaping. Three - input AND gate 44 outputs the input from XOR gate 43 at a ratio of once every two clocks of the internal clock when detecting an excessive input (the determination signal from latch 31 is 1).

[0157] AND gate 45 outputs 1 when the input from XOR gate 42 is 1 and the determination signal from latch 31 is 1, and outputs 0 otherwise. Therefore, when AND gate 45 detects an excessive input (the determination signal from latch 31 is 1), it outputs the input from XOR gate 42 (that is, the low - order bit of the output of adder 11a). The output of XOR gate 42 is the low - order bit of the 2 - bit signal obtained by adding the output of ΔΣADC1b and the quantization error of the previous clock fed back from latch 47. Therefore, the output of XOR gate 42 becomes the quantization error in the current clock. In such a structure, the quantization error is fed back to adder 11a composed of AND gate 41 and XOR gate 42.

[0158] Figure 14 It represents the simulation result curves of non-interleaved rejection (14A), simple interleaved rejection (14B), the structure (14C) of the second embodiment, and the structure (14D) of the third embodiment. Figure 8 The horizontal axis of the Figure 9 represents the clock number (time), and the vertical axis represents the relative signal amplitude (normalizing the maximum value of the signal amplitude to 1). Figure 14 When obtaining the

[0159] simulation result, the ΔΣADC is set to a 1st-order ΔΣADC, and the Figure 14 final-stage LPF of the Figure 9 is set to a 2nd-order CIC (Cascaded Integrator Comb) filter. Additionally, Figure 14 the simulation result of the

[0160] Figure 14 is an example when a graph signal (a signal considering the frequency characteristics within a specified frequency band) whose frequency gradually increases over time is used as the input signal. Therefore, the part with a small clock number represents the result of the low-frequency part close to direct current (DC), and the part with a large clock number represents the result of a higher-frequency part. Figure 7 and Figure 8 B shows the simulation result based on simple interleaved rejection when the LPF11 and quantizer 13 provided in the structure of the FFB1b shown in Figure 14 are not provided. Observing Figure 14 B, it can be seen that especially in the low-frequency part close to DC, compared with the non-interleaved rejection of

[0161] A, the SNR is significantly reduced. That is, for the output of the ΔΣADC1b with simple interleaved rejection performed every 1 clock, since the data of the clock after being interleaved rejected by the LPF2g is replaced with the data of the previous clock to generate the output to the output terminals OUTP and OUTN, a particularly large distortion is generated in the signal in the low-frequency part close to DC where the input signal changes slowly. Figure 14 It can be known that the simulation result in the case of using the Figure 8 FFB1c shown in Figure 14 C is also the same as Figure 14 B. In the low-frequency part close to DC, compared with the non-interleaved rejection of

[0162] On the other hand, when using the Figure 14 FFB1c shown in Figure 9 D, the simulation result shows that from the low-frequency part to the high-frequency part, the SNR is higher than that of Figure 14 B andFigure 14 C is high.

[0163] According to the third embodiment, it has substantially the same effect as the above-described second embodiment. Moreover, since the quantizer 13 in the second embodiment is replaced with the noise shaping circuit 14, the quantization noise is further biased toward the high-frequency side, reducing the quantization noise in the signal band. As a result, the deterioration of the signal accuracy can be suppressed to a smaller extent.

[0164] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

Claims

1. An isolator, comprising: A ΔΣ analog-to-digital converter that converts an analog input signal into a 1-bit digital signal and transmits it as normal data; A time-division multiplexing circuit that performs time-division multiplexing. In the time-division multiplexing, it alternately performs processing of converting the normal data from the ΔΣ analog-to-digital converter into a digital differential signal having a level difference between two outputs and transmitting it, and processing of transmitting a special signal that does not have a level difference between two outputs and cannot be used as the digital differential signal; and An insulation transmission circuit that transmits the digital differential signal and the special signal transmitted from the time-division multiplexing circuit via an insulating layer.

2. The isolator according to claim 1, wherein When m is an integer of 2 or more, there are m types of the special signals, The time-division multiplexing circuit alternately performs processing of converting the normal data into a digital differential signal and transmitting it with 1 operation clock, and processing of transmitting the m types of special signals with m operation clocks.

3. The isolator according to claim 1, wherein It further includes an abnormality detection circuit that determines whether the amplitude of the analog input signal exceeds an excessive input threshold and generates a determination signal indicating the determination result, The time-division multiplexing circuit, Receives the determination signal, When the determination signal indicates that it does not exceed the excessive input threshold, converts the normal data from the ΔΣ analog-to-digital converter into a digital differential signal and transmits it to the insulation transmission circuit, When the determination signal indicates that it exceeds the excessive input threshold, transmits the time-division multiplexed digital differential signal and the special signal to the insulation transmission circuit.

4. The isolator according to claim 1, wherein The time-division multiplexing circuit includes: A low-pass filter circuit that performs low-pass filtering on the normal data from the ΔΣ analog-to-digital converter; and An interval rejection circuit and a quantizer that perform the following processing in any order: processing of performing interval rejection on the multi-bit normal data after the low-pass filtering by the interval rejection circuit, and processing of quantizing it to 1 bit by the quantizer.

5. The isolator according to claim 1, wherein The time-division multiplexing circuit includes: A low-pass filter circuit that performs low-pass filtering on the normal data from the ΔΣ analog-to-digital converter; An interval rejection circuit that performs interval rejection on the multi-bit normal data after the low-pass filtering; And A noise shaping circuit that performs noise shaping processing. In this noise shaping processing, the multi-bit normal data after interval rejection by the interval rejection circuit is quantized to 1 bit, and the quantization error during quantization is added to the next multi-bit normal data to shift the quantization noise to the high-frequency side.

6. The isolator according to claim 5, wherein The noise shaping circuit includes: An adder, to which the multi-bit normal data after interval elimination by the interval elimination circuit is input; A quantizer, which quantizes the output of the adder; A subtractor, which subtracts the output quantized by the quantizer from the output of the adder; And A delay element, which delays the output of the subtractor, The output of the delay element is input to the adder, and through the adder, it is added to the multi-bit normal data.

7. The isolator according to claim 3, wherein The time-direction multiplexing circuit includes: A frequency divider, to which the determination signal is input, and when the determination signal indicates exceeding the excessive input threshold, sets the frequency of the operation clock to 1 / 2 times and outputs it; A first AND gate, to which the normal data from the ΔΣ analog-to-digital converter is input; A first exclusive-OR gate, which is connected in parallel with the first AND gate, and to which the normal data from the ΔΣ analog-to-digital converter is input; A second exclusive-OR gate, to which the output of the first AND gate is input; A three-input AND gate, to which the output of the second exclusive-OR gate, the output of the frequency divider, and the determination signal are input; A second AND gate, to which the output of the first exclusive-OR gate and the determination signal are input; A first latch, to which the output of the three-input AND gate and the operation clock are input; And A second latch, to which the output of the second AND gate and the operation clock are input, The output of the first latch is input to the second exclusive-OR gate, The output of the second latch is input to the first AND gate and the first exclusive-OR gate.

8. The isolator according to claim 7, wherein The time-direction multiplexing circuit further includes a first selector, which is connected to the normal data from the ΔΣ analog-to-digital converter, the output of the second exclusive-OR gate, and the determination signal, The first selector, When the determination signal indicates not exceeding the excessive input threshold, selects the normal data from the ΔΣ analog-to-digital converter and outputs it, When the determination signal indicates exceeding the excessive input threshold, selects the output of the second exclusive-OR gate and outputs it.

9. The isolator according to claim 8, wherein The time-direction multiplexing circuit further includes: A differential output amplifier, which converts the output from the first selector into the digital differential signal; and A second selector, which is connected to the digital differential signal from the differential output amplifier, the special signal, and the output of the frequency divider, The frequency divider is always reset and outputs 0 when the determination signal indicates not exceeding the excessive input threshold, The second selector, When the output of the frequency divider is 0, outputs the digital differential signal from the differential output amplifier, When the output of the frequency divider is the output with the frequency of the operation clock set to 1 / 2 times, alternately outputs the digital differential signal from the differential output amplifier and the special signal.

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