Method, device, processor and storage medium for obtaining audio data

Abstract

The present application relates to a method, device, processor, storage medium and computer program product for obtaining audio data. The method is applied to a processor, the processor is provided with a frequency division interface and an SPI interface, the SPI interface is connected to the I2S interface of an external audio device; the processor is powered on and started, the SPI interface is configured according to preset configuration parameters, an initial clock signal is generated through the SPI interface, and a synchronization message is sent to the I2S interface, the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters; the initial clock signal is divided through the frequency division interface to obtain a frequency division clock signal; the frequency division clock signal and the initial clock signal are transmitted to the I2S interface; the audio data sent by the external audio device through the I2S interface is received, compared with the current method of reading audio data through analog signals, the situation of data misalignment is reduced, the data of two channels can be received at the same time, the accuracy of the audio data is guaranteed, the generation of noise is reduced, and the applicability is strong.

Description

Technical Field

[0001] The present application relates to the field of smart home technology, and in particular to a method, device, processor, storage medium and computer program product for acquiring audio data. Background Art

[0002] With the development of artificial intelligence technology, more and more scenarios are required for voice collection, which puts forward requirements for the voice collection capabilities of MCU (Microcontroller Unit). Usually, the demand for audio collection is met by MCU with audio interface. Many MCU manufacturers that do not have audio interface also hope to obtain audio data by matching the characteristics of audio interface, so as to expand the application areas of their own chips.

[0003] Currently, chip manufacturers and industry developers that do not have audio interfaces have proposed some solutions, but some of these methods rely on specific resources such as pulse counters and timers of the chip itself and do not have universal scalability. Some use GPIO simulation timing to consume a lot of MCU resources, and the obtained voice is distorted or noisy. Summary of the invention

[0004] Based on this, it is necessary to provide a method, device, processor, computer-readable storage medium and computer program product for obtaining audio data with strong applicability and accurate audio data transmission in response to the above technical problems.

[0005] In a first aspect, the present application provides a method for obtaining audio data, which is applied to a processor, wherein the processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to an I2S interface of an external audio device. The method comprises:

[0006] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0007] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0008] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0009] Receive audio data sent by external audio devices through the I2S interface.

[0010] In one of the embodiments, the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0011] In one embodiment, the SPI interface includes a MOSI interface; generating the initial clock signal through the SPI interface includes: generating the initial clock signal through the MOSI interface; after generating the initial clock signal through the SPI interface, further includes: transmitting the initial clock signal to the frequency division interface.

[0012] In one embodiment, generating the initial clock signal through the MOSI interface includes: writing the initial clock signal to the MOSI interface through a write queue of the SPI interface.

[0013] In one of the embodiments, receiving the audio data sent by the external audio device through the I2S interface includes: receiving the audio data sent by the external audio device through the I2S interface through a read queue of the SPI interface.

[0014] In one of the embodiments, the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; receiving audio data sent by an external audio device through an I2S interface through a read queue of the SPI interface includes: controlling the DMA controller to trigger a read interrupt thread; executing the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0015] In a second aspect, the present application also provides a device for acquiring audio data, which is applied to a processor, wherein the processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to an I2S interface of an external audio device. The device comprises:

[0016] A configuration module is used for power-on startup, configuring the SPI interface according to preset configuration parameters, generating an initial clock signal through the SPI interface, and sending a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0017] A frequency division module, used to divide the frequency of the initial clock signal through the frequency division interface to obtain a frequency-divided clock signal;

[0018] A transmission module, used for transmitting the divided clock signal and the initial clock signal to the I2S interface;

[0019] The receiving module is used to receive audio data sent by an external audio device through the I2S interface.

[0020] In a third aspect, the present application further provides a processor. The processor includes a memory, a frequency division interface and an SPI interface, and the SPI interface is connected to an I2S interface of an external audio device. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0021] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0022] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0023] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0024] Receive audio data sent by external audio devices through the I2S interface.

[0025] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0026] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0027] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0028] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0029] Receive audio data sent by external audio devices through the I2S interface.

[0030] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0031] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0032] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0033] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0034] Receive audio data sent by external audio devices through the I2S interface.

[0035] The above-mentioned method, device, processor, storage medium and computer program product for obtaining audio data are applied to a processor, the processor is provided with a frequency division interface and an SPI interface, the SPI interface is connected to the I2S interface of an external audio device; the processor is powered on and started, the SPI interface is configured according to preset configuration parameters, an initial clock signal is generated through the SPI interface, and a synchronization message is sent to the I2S interface, the synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters; the initial clock signal is divided through the frequency division interface to obtain a frequency division clock signal; the frequency division clock signal and the initial clock signal are transmitted to the I2S interface; and the audio data sent by the external audio device through the I2S interface is received. The whole scheme generates a clock signal through the frequency division interface and the SPI interface of the processor and sends it to the I2S interface, the processor and the external audio device are synchronized in timing, the audio data generated by the external audio device is obtained through the SPI interface in the processor, and the data of two channels can be received at the same time, the accuracy of the audio data is ensured, the generation of noise is reduced, and it is simple, efficient and highly applicable. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A diagram of an application environment of a method for obtaining audio data in one embodiment;

[0037] Figure 2 A schematic diagram of a flow chart of a method for obtaining audio data in one embodiment;

[0038] Figure 3 A schematic diagram of a process of generating an initial clock signal in one embodiment;

[0039] Figure 4 A signal timing diagram of a method for acquiring audio data in one embodiment;

[0040] Figure 5 A schematic flow chart of a method for acquiring audio data in another embodiment;

[0041] Figure 6 A schematic flow chart of a method for obtaining audio data in yet another embodiment;

[0042] Figure 7 is a structural block diagram of a device for acquiring audio data in an embodiment;

[0043] Figure 8 FIG. 4 is a diagram showing the internal structure of a processor in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] The method for obtaining audio data provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the processor 102 communicates with the external audio device 104 through a data line. The processor 102 is provided with a frequency division interface (i.e., a frequency division circuit) and an SPI (Serial Peripheral Interface) interface, the SPI interface is connected to the I2S (Inter-IC Sound, integrated circuit built-in audio bus) interface of the external audio device, the MOSI (Master Output / Slave Input) pin of the SPI interface of the processor is externally connected to the frequency division interface, the output of the frequency division interface is connected to the LRCK (Left and right channel clock) of the I2S interface, the MOSI pin of the SPI interface is also connected to the BCLK (Bit clock) of the I2S interface, and the MISO (Master Input / Slave Output) pin of the SPI interface is connected to the ASDOUT (Serial Data OUT) pin of the I2S interface. Among them, the processor 102 can be a processor with an SPI interface but not an I2S interface, such as a processor that can be an MCU (Microcontroller Unit), a SOC (System on Chip), etc., which is not limited in this application.

[0046] In one embodiment, Figure 2 As shown, a method for obtaining audio data is provided, and the method is applied to Figure 1 The processor 102 in the embodiment is taken as an example to illustrate, and the following steps are included:

[0047] Step 202, power on and start, configure the SPI interface according to preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface, the synchronization message carrying the preset configuration parameters.

[0048] The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters. The preset configuration parameters are clock polarity and phase polarity. For the SPI interface, its working mode is Master mode, and for the I2S interface, it is Slave mode and left-aligned mode. The configuration of the SPI interface and the I2S interface are completed by the processor.

[0049] Specifically, the processor is powered on and started, and the preset configuration parameters shared by the SPI interface and the I2S interface are obtained, and the SPI interface is configured according to the values ​​of the clock polarity and phase polarity in the preset configuration parameters. The initial clock signal and synchronization message are generated through the SPI interface, and the synchronization message is sent to the I2S interface. The synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters. The I2S interface in the audio device can be configured based on the same clock polarity and phase polarity as the SPI interface, so that the SPI interface and the I2S interface are synchronized based on the same clock signal and phase signal.

[0050] Step 204, dividing the frequency of the initial clock signal through the frequency division interface to obtain a divided clock signal.

[0051] The frequency division interface can be specifically a 16 / 20 / 32 frequency division circuit. The corresponding data sampling accuracy is configured as a 16 / 20 / 32bit left-aligned mode. The frequency division coefficient of the frequency division circuit is consistent with the sampling accuracy of the configuration parameter. For example, the sampling data accuracy of the configuration parameter corresponding to the 16-frequency division circuit is 16 bits, and the sampling data accuracy of the configuration parameter corresponding to the 20-frequency division circuit is 20 bits.

[0052] Specifically, the processor transmits the initial clock signal generated by the SPI interface to the frequency division interface (frequency division circuit), and divides the frequency of the initial clock signal through the frequency division circuit to obtain a divided clock signal.

[0053] Step 206: Transmit the divided clock signal and the initial clock signal to the I2S interface.

[0054] Specifically, the processor transmits the divided clock signal to the I2S interface of the external audio device and transmits the initial clock signal to the I2S interface of the external audio device.

[0055] Step 208: receiving audio data sent by an external audio device through the I2S interface.

[0056] Specifically, when the LRCK pin of the I2S interface receives the divided clock signal transmitted by the SPI interface and the BCLK pin of the I2S interface receives the initial clock signal transmitted by the SPI interface, it starts working based on the same timing as the SPI interface and transmits the audio data of the external audio device to the MISO pin of the SPI interface through the ASDOUT pin of the I2S interface.

[0057] In the above method for obtaining audio data, the processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to the I2S interface of the external audio device; the processor is powered on and started, and the SPI interface is configured according to the preset configuration parameters, and the initial clock signal is generated through the SPI interface, and a synchronization message is sent to the I2S interface, and the synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters; the initial clock signal is divided through the frequency division interface to obtain a frequency division clock signal; the frequency division clock signal and the initial clock signal are transmitted to the I2S interface; and the audio data sent by the external audio device through the I2S interface is received. The whole scheme generates a clock signal through the frequency division interface and the SPI interface of the processor and sends it to the I2S interface. The processor and the external audio device are synchronized in timing, and the audio data generated by the external audio device is obtained through the SPI interface in the processor. The data of two channels can be received at the same time, which reduces the situation of data dislocation, ensures the accuracy of the audio data, reduces the generation of noise, and is simple, efficient and highly applicable.

[0058] In an optional embodiment, the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0059] Specifically, the working mode of the processor is the Master mode, the working mode of the external audio device is the Slave mode, and the preset configuration parameters are that the clock polarity and the phase polarity are both 0.

[0060] When two devices communicate, the party responsible for providing the clock (i.e. BCLK signal) and left and right channel signals (i.e. LRCK signal) is called the Master, and the party receiving the clock signal and left and right channel signals is called the Slave. Here, the clock and left and right channel signals of the Master are realized by the logic circuit inside the chip according to the timing of the SPI interface, and the timing of the I2S interface is generated by the clock of the processor's SPI interface in the Master mode and combined with its own timer and pulse counter.

[0061] The I2S interface has multiple working modes according to the polarity and phase of the data in the clock. When the clock polarity of the I2S interface is 0 and the phase is 0, the signal required by it as a slave device is completely consistent with the timing of the SPI interface, so the data output on the I2S can be accurately received by the SPI interface.

[0062] In this embodiment, the I2S interface of the external audio device is completely consistent with the SPI interface of the processor in terms of timing, so there is no delay between the pin signals during data transmission, and the data will not shift, thereby improving the accuracy of audio data transmission.

[0063] In an optional embodiment, if Figure 3 As shown, the SPI interface includes a MOSI interface; generating an initial clock signal through the SPI interface includes:

[0064] Step 302: Generate an initial clock signal through the MOSI interface.

[0065] Specifically, the output pin MOSI of the SPI interface of the processor generates a transmission initial clock signal. The waveform of the initial clock signal is consistent with the waveform of the bit clock signal of the BCLK pin of the I2S interface, and can be used as the bit clock of the I2S interface.

[0066] like Figure 4 As shown in the figure, taking the sampling accuracy of 16 bits as an example, after the processor's initial clock signal is divided by the frequency division circuit, the divided clock signal obtained is consistent with the standard LRCK signal of the I2S interface. Therefore, in terms of timing, it can work together with the ASDOUT and BCLK signals of the I2S interface to ensure the normal operation of the I2S interface.

[0067] After the initial clock signal is generated through the SPI interface, the method further includes: step 304, transmitting the initial clock signal to the frequency division interface.

[0068] Specifically, the processor transmits the initial clock signal to the frequency division interface, divides the frequency through the frequency division circuit to obtain the divided clock signal, and transmits the divided clock signal to the LRCK pin of the I2S interface of the external audio device as the frame clock of the I2S interface. The initial clock signal is transmitted to the BCLK pin of the I2S interface of the external audio device as the bit clock of the I2S interface.

[0069] In an optional embodiment, generating the initial clock signal through the MOSI interface includes: writing the initial clock signal to the MOSI interface through a write queue of the SPI interface.

[0070] Specifically, the processor continuously writes 0x55 (01010101b) to the write queue of the SPI interface, triggering the SPI write interrupt thread, and the SPI write interrupt thread writes 0x55 (01010101b) in the write queue to the MOSI interface. At this time, the waveform of the output of the MOSI pin of the SPI interface is consistent with the waveform of the bit clock signal of the BCLK pin of the I2S interface, and can be used as the bit clock of the I2S interface. Moreover, after the processor's 0x55 (01010101b) is divided by the frequency division circuit, the obtained frequency division clock signal is consistent with the standard LRCK signal of the I2S interface, so in terms of timing, it can work together with the ASDOUT and BCLK signals of the I2S interface to ensure the normal operation of the I2S interface.

[0071] In an optional embodiment, receiving the audio data sent by the external audio device through the I2S interface includes: receiving the audio data sent by the external audio device through the I2S interface through a read queue of the SPI interface.

[0072] Specifically, the processor is provided with an audio buffer area, the processor triggers the SPI read interrupt thread, receives the audio data of the external audio device through the FIFO read queue of the SPI interface, the audio data is output to the MISO pin of the SPI interface through the ASDOUT pin of the I2S interface, the SPI read queue reads the audio data from the MISO pin, and writes the read audio data into the audio buffer area.

[0073] like Figure 5 As shown in the figure, after the processor is powered on, the working mode of the SPI interface is configured as the Master mode, the clock polarity and phase polarity of the SPI interface are 0, and at the same time, the initial values ​​of the data write buffer of the SPI interface are all 0x55. Through the synchronization message, the I2S interface is configured as the Slave mode, the working mode is the left-aligned mode, the audio data sampling accuracy is the same as the frequency division coefficient of the frequency division circuit, and the clock polarity and phase polarity of the I2S interface are 0. The write interrupt thread of the SPI interface writes the initial clock signal 0x55 (01010101b) in the write queue to the MOSI interface. After the frequency division circuit divides the frequency, the divided clock signal is obtained, and the divided clock signal and the initial clock signal are transmitted to the I2S interface. The read queue of the SPI read interrupt thread obtains the left and right channel audio data sent by the external audio device, and writes the audio data into the audio buffer, so the collected audio data is more complete.

[0074] In an optional embodiment, the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; receiving audio data sent by an external audio device through an I2S interface through a read queue of the SPI interface includes: controlling the DMA controller to trigger a read interrupt thread; executing the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0075] The audio buffer includes an audio read buffer and an audio write buffer, and the DMA controller is connected to the audio buffer and the SPI interface during initialization.

[0076] Specifically, Figure 6 As shown, the processor can be provided with a DMA controller. During initialization, the DMA controller and the processor are set to a memory-peripheral association mode, the SPI interface is set to a peripheral of the DMA controller, the DMA working mode is configured to an LLI (Link List Item) mode, and in the LLI mode, the cache for receiving data is set to ping_r and pong_r, and the cache for receiving data is set to ping_w and pong_w. The write cache values ​​of ping_w and pong_w are all initialized to 0x55.

[0077] Configure the SPI interface to work in Master mode, and the clock polarity and phase polarity of the SPI interface are 0. Use synchronization messages to configure the I2S interface to Slave mode, the working mode is left-aligned mode, the audio data sampling accuracy is the same as the frequency division factor of the frequency division circuit, and the clock polarity and phase polarity of the I2S interface are 0.

[0078] If the processor writes the initial clock signal data into the audio write buffer, the DMA controller triggers the write interrupt thread, the DMA's ping_w and pong_w buffers read the initial clock signal from the audio write buffer, and transmit the initial clock signal to the frequency division circuit for frequency division to obtain the frequency division clock signal, and transmit the frequency division clock signal to the LRCK pin of the I2S interface as the frame clock of the I2S interface, and transmit the initial clock signal to the BCLK pin of the I2S interface of the external audio device as the bit clock of the I2S interface. The DMA controller is controlled to trigger the read interrupt thread; the processor executes the read interrupt thread, the audio data sent by the external audio device on the DMA's ping_r and pong_r buffers are read, and the processor writes the audio data on the DMA's ping_r and pong_r buffers into the audio read buffer.

[0079] In this embodiment, the LLI mode of DMA can ensure uninterrupted data transmission, which can improve the integrity of audio data transmission. In addition, the working principle of DMA is to use hardware to transmit data, so it can save processor resources and save the processor from data operation on the FIFO queue of the SPI interface when an interrupt occurs, greatly improving the transmission efficiency of audio data.

[0080] In order to facilitate understanding of the technical solution provided in the embodiment of the present application, the method for obtaining audio data provided in the embodiment of the present application is briefly described with a complete process of obtaining audio data:

[0081] (1) Power on and start up. Configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters.

[0082] (2) Writing the initial clock signal to the MOSI interface through the write queue of the SPI interface, generating the initial clock signal through the MOSI interface; and transmitting the initial clock signal to the frequency division interface.

[0083] (3) The initial clock signal is divided through a frequency division interface to obtain a divided clock signal.

[0084] (4) Transmit the divided clock signal and the initial clock signal to the I2S interface.

[0085] (5) Control the DMA controller to trigger the read interrupt thread; execute the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer area.

[0086] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0087] Based on the same inventive concept, the embodiment of the present application also provides a device for obtaining audio data for implementing the method for obtaining audio data involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more embodiments of the device for obtaining audio data provided below can refer to the limitations of the method for obtaining audio data above, and will not be repeated here.

[0088] In one embodiment, Figure 7 As shown, a device for obtaining audio data is provided, which is applied to a processor, wherein the processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to an I2S interface of an external audio device. The device includes: a configuration module 702, a frequency division module 704, a transmission module 706 and a receiving module 708, wherein:

[0089] Configuration module 702 is used for power-on startup, configures the SPI interface according to preset configuration parameters, generates an initial clock signal through the SPI interface, and sends a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters.

[0090] The frequency division module 704 is used to divide the frequency of the initial clock signal through the frequency division interface to obtain a frequency-divided clock signal.

[0091] The transmission module 706 is used to transmit the divided clock signal and the initial clock signal to the I2S interface.

[0092] The receiving module 708 is used to receive audio data sent by an external audio device through the I2S interface.

[0093] In an optional embodiment, the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0094] In an optional embodiment, the SPI interface includes a MOSI interface; the configuration module 602 is further configured to generate an initial clock signal through the MOSI interface; and transmit the initial clock signal to the frequency division interface.

[0095] In an optional embodiment, the configuration module 702 is further configured to write the initial clock signal into the MOSI interface through the write queue of the SPI interface.

[0096] In an optional embodiment, the receiving module 708 is further configured to receive, through a read queue of the SPI interface, audio data sent by an external audio device through an I2S interface.

[0097] In an optional embodiment, the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; the receiving module 708 is also used to control the DMA controller to trigger a read interrupt thread; the read interrupt thread is executed to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0098] Each module in the above-mentioned device for obtaining audio data can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0099] In one embodiment, a processor is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 8 As shown. The processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to the I2S interface of the external audio device. The processor is used to provide computing and control capabilities. The memory of the processor includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the processor is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for transmitting audio data using an SPI interface is implemented.

[0100] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0101] In one embodiment, a processor is provided, wherein the processor is provided with a frequency division interface, an SPI interface, and a memory, wherein the SPI interface is connected to an I2S interface of an external audio device, and a computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0102] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0103] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0104] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0105] Receive audio data sent by external audio devices through the I2S interface.

[0106] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0107] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the SPI interface includes a MOSI interface; generating an initial clock signal through the SPI interface includes: generating an initial clock signal through the MOSI interface; after generating the initial clock signal through the SPI interface, it also includes: transmitting the initial clock signal to the frequency division interface.

[0108] In one embodiment, when the processor executes the computer program, the following steps are further implemented: generating the initial clock signal through the MOSI interface includes: writing the initial clock signal to the MOSI interface through the write queue of the SPI interface.

[0109] In one embodiment, when the processor executes the computer program, the following steps are further implemented: receiving audio data sent by the external audio device through the I2S interface includes: receiving the audio data sent by the external audio device through the I2S interface through the read queue of the SPI interface.

[0110] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; receiving audio data sent by an external audio device through an I2S interface through a read queue of the SPI interface includes: controlling the DMA controller to trigger a read interrupt thread; executing the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0111] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0112] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0113] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0114] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0115] Receive audio data sent by external audio devices through the I2S interface.

[0116] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0117] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the SPI interface includes a MOSI interface; generating an initial clock signal through the SPI interface includes: generating an initial clock signal through the MOSI interface; after generating the initial clock signal through the SPI interface, it also includes: transmitting the initial clock signal to the frequency division interface.

[0118] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: generating the initial clock signal through the MOSI interface includes: writing the initial clock signal to the MOSI interface through the write queue of the SPI interface.

[0119] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving audio data sent by the external audio device through the I2S interface includes: receiving the audio data sent by the external audio device through the I2S interface through the read queue of the SPI interface.

[0120] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; receiving audio data sent by an external audio device through an I2S interface through a read queue of the SPI interface includes: controlling the DMA controller to trigger a read interrupt thread; executing the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0121] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0122] Power on and start up, configure the SPI interface according to the preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface. The synchronization message carries the preset configuration parameters. The synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters;

[0123] The initial clock signal is divided by a frequency division interface to obtain a divided clock signal;

[0124] Transmit the divided clock signal and the initial clock signal to the I2S interface;

[0125] Receive audio data sent by external audio devices through the I2S interface.

[0126] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode.

[0127] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the SPI interface includes a MOSI interface; generating an initial clock signal through the SPI interface includes: generating an initial clock signal through the MOSI interface; after generating the initial clock signal through the SPI interface, it also includes: transmitting the initial clock signal to the frequency division interface.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: generating the initial clock signal through the MOSI interface includes: writing the initial clock signal to the MOSI interface through the write queue of the SPI interface.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving audio data sent by the external audio device through the I2S interface includes: receiving the audio data sent by the external audio device through the I2S interface through the read queue of the SPI interface.

[0130] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the processor is provided with a DMA controller and an audio buffer, and the DMA controller is connected to the audio buffer and the SPI interface; receiving audio data sent by an external audio device through an I2S interface through a read queue of the SPI interface includes: controlling the DMA controller to trigger a read interrupt thread; executing the read interrupt thread to read the audio data sent by the external audio device and write the audio data into the audio buffer.

[0131] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0133] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for obtaining audio data, It is characterized in that Applied to a processor, the processor is provided with a frequency division interface and an SPI interface, the MOSI pin of the SPI interface is externally connected to the frequency division interface, the output of the frequency division interface is connected to the LRCK of the I2S interface of an external audio device; the MOSI pin of the SPI interface is also connected to the BCLK of the I2S interface; The MISO pin of the SPI interface is connected to the ASDOUT pin of the I2S interface; The method for obtaining audio data comprises: Power on and start up, configure the SPI interface according to preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface, the synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters; the preset configuration parameters are configuration parameters in left-aligned mode, the working mode of the processor is Master mode, and the working mode of the external audio device is Slave mode; Divide the frequency of the initial clock signal through the frequency division interface to obtain a frequency-divided clock signal; Transmitting the divided clock signal and the initial clock signal to the I2S interface; Receive audio data sent by the external audio device through the I2S interface.

2. The method according to claim 1, It is characterized in that The frequency division coefficient of the frequency division interface is consistent with the sampling accuracy of the configuration parameters.

3. The method according to claim 1, It is characterized in that The SPI interface includes a MOSI interface; Generating an initial clock signal through the SPI interface includes: Generate the initial clock signal through the MOSI interface; After the initial clock signal is generated through the SPI interface, the method further comprises: The initial clock signal is transmitted to the frequency division interface.

4. The method according to claim 3, It is characterized in that Generating an initial clock signal through a MOSI interface includes: The initial clock signal is written to the MOSI interface through the write queue of the SPI interface.

5. The method according to claim 1, It is characterized in that The receiving audio data sent by the external audio device through the I2S interface includes: The audio data sent by the external audio device through the I2S interface is received through the read queue of the SPI interface.

6. The method according to claim 5, It is characterized in that The processor is provided with a DMA controller and an audio buffer area, and the DMA controller is connected to the audio buffer area and the SPI interface; The receiving, through the read queue of the SPI interface, the audio data sent by the external audio device through the I2S interface comprises: Control the DMA controller to trigger a read interrupt thread; The read interrupt thread is executed to read the audio data sent by the external audio device and write the audio data into the audio buffer area.

7. A device for acquiring audio data, It is characterized in that The device is applied to a processor, wherein the processor is provided with a frequency division interface and an SPI interface, wherein a MOSI pin of the SPI interface is externally connected to the frequency division interface, and an output of the frequency division interface is connected to an LRCK of an I2S interface of an external audio device; the MOSI pin of the SPI interface is also connected to a BCLK of the I2S interface; the MISO pin of the SPI interface is connected to an ASDOUT pin of the I2S interface; and the device comprises: A configuration module, configured to start upon power-on, configure the SPI interface according to preset configuration parameters, generate an initial clock signal through the SPI interface, and send a synchronization message to the I2S interface, wherein the synchronization message carries the preset configuration parameters, and the synchronization message is used to control the I2S interface to perform clock synchronization according to the preset configuration parameters; the preset configuration parameters are configuration parameters in the left-aligned mode, the working mode of the processor is the Master mode, and the working mode of the external audio device is the Slave mode; A frequency division module, used for dividing the frequency of the initial clock signal through the frequency division interface to obtain a frequency-divided clock signal; A transmission module, used for transmitting the divided clock signal and the initial clock signal to the I2S interface; The receiving module is used to receive the audio data sent by the external audio device through the I2S interface.

8. A processor comprising a memory, wherein the memory stores a computer program, It is characterized in that When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, It is characterized in that The processor is provided with a frequency division interface and an SPI interface, and the SPI interface is connected to the I2S interface of an external audio device; when the computer program is executed by the processor, the steps of the method described in any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, It is characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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