Sensing systems and distance measurement systems

Abstract

A system for capturing image data that measures the distance to an object without adding a distance measurement sensor. The sensing system includes a light-emitting unit, a predetermined number of pixels, and a counting unit. In this solid-state imaging element, the light-emitting unit emits illumination light in synchronization with a light-emission control signal having a higher frequency than a predetermined vertical synchronization signal. Furthermore, each of the predetermined number of pixels generates a pulse signal through photoelectric conversion. Furthermore, the counting unit counts the number of pulse signals in synchronization with each of the light-emission control signal and the vertical synchronization signal.

Description

Technical Field

[0001] The present technology relates to a sensing system, and more particularly to a sensing system that counts the number of pulses and a distance measurement system. Background Art

[0002] In recent years, devices called single-photon avalanche diodes (SPADs) have been developed and studied, which capture relatively weak light signals and enable optical communication, distance measurement, photon counting, and the like. SPADs are avalanche photodiodes with such high sensitivity that they can detect a single photon. For example, a solid-state imaging element has been proposed in which a pixel that generates a pulse signal using a SPAD and a counter that counts the number of pulse signals within an exposure period are arranged (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: WO 2019 / 150785 A. Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] In the conventional technology described above, high-sensitivity SPADs are used to detect weak light, resulting in improved image quality when performing imaging in dark environments. However, these solid-state imaging elements cannot measure the distance to objects in the captured image. Adding a distance measurement sensor using infrared or lasers to perform distance measurement increases system power consumption and costs, which is not preferred.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to measure the distance to an object in a system that captures image data without adding a distance measurement sensor.

[0009] Solution to the problem

[0010] The present technology has been developed to address the above-mentioned issues, and its first aspect is a sensing system comprising: a light-emitting section that emits illumination light in synchronization with a light-emission control signal having a higher frequency than a predetermined vertical synchronization signal; a predetermined number of pixels, each of which generates a pulse signal through photoelectric conversion; and a counting section that counts the number of pulse signals in synchronization with each of the light-emission control signal and the vertical synchronization signal. This results in the ability to capture image data and measure distance.

[0011] Furthermore, in the first aspect, the counting section may include: a first counter that counts the pulse signal in synchronization with the light emission control signal; and a second counter that counts the pulse signal in synchronization with the vertical synchronization signal. Therefore, this brings about an effect of performing distance measurement based on the count value of the counter.

[0012] Furthermore, in the first aspect, the counting section may include: a first counter that sequentially performs the following processing: counting the pulse signal in synchronization with the light emission control signal and counting the pulse signal in synchronization with the vertical synchronization signal; and a second counter that counts the pulse signal in synchronization with the vertical synchronization signal. This results in an effect of reducing the number of counters.

[0013] In addition, in the first aspect, the pixel array section in which a predetermined number of pixels are arranged may be divided into a plurality of pixel blocks, the counting section may be provided in each pixel block, and the first counter may count the logical sum of the pulse signals from the respective pixels in the pixel block. This results in an effect of measuring the distance for each pixel block.

[0014] Furthermore, in the first aspect, four first counters and five second counters may be arranged in each pixel block, thereby achieving the effect of measuring the distance based on four count values.

[0015] Furthermore, in the first aspect, eight first counters and one second counter can be arranged in each pixel block, thereby widening the measurable distance range.

[0016] Furthermore, in the first aspect, the pixel array section in which a predetermined number of pixels are arranged may be divided into a plurality of pixel blocks, each of the plurality of pixel blocks may be divided into a plurality of regions, a counting section may be provided corresponding to each of the plurality of regions, and the first counter may count the logical sum of pulse signals from the pixels in the corresponding region. This results in the following effect: distance is measured from the count value of each region.

[0017] Furthermore, in the first aspect, nine pixels can be arranged in each of the plurality of regions. Therefore, this brings about an effect of counting the logical sum of the pulse signals of the nine pixels.

[0018] In the first aspect, four pixels may be arranged in each of the plurality of regions, thereby achieving an effect of counting the logical sum of the pulse signals of the four pixels.

[0019] Furthermore, in the first aspect, four regions can be arranged in the pixel block. Therefore, this brings about the effect of measuring the distance from the count value of each of the two regions.

[0020] Furthermore, in the first aspect, two regions can be arranged in a pixel block. Therefore, this brings about the effect of measuring the distance based on the count value of each of the four regions.

[0021] Furthermore, in the first aspect, the first counter may count the logical sum of the corresponding pulse signals of a set number of pixels in the pixel block.

[0022] Furthermore, in the first aspect, the counting section may include a predetermined number of counters that sequentially perform the following processing: counting the pulse signal in synchronization with the light emission control signal and counting the pulse signal in synchronization with the vertical synchronization signal.

[0023] Furthermore, in the first aspect, the counting section may include nine counters. Therefore, this brings about an effect of measuring the distance from nine count values.

[0024] Furthermore, in the first aspect, the counting section may include four counters. Therefore, this brings about an effect of measuring the distance from four count values.

[0025] Furthermore, in the first aspect, the sensing system further includes a pixel driver that provides an enable signal, wherein each of the plurality of set values ​​is sequentially set to a phase difference with the light emission control signal. A counter can provide a pulse signal in synchronization with the enable signal. This improves ranging accuracy.

[0026] Furthermore, a second aspect of the present technology is a distance measurement system comprising: a light emitting unit that emits illumination light in synchronization with a light emission control signal having a higher frequency than a predetermined vertical synchronization signal; a predetermined number of pixels, each of which generates a pulse signal through photoelectric conversion; a counting unit that counts the number of pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; and a distance measurement unit that measures the distance to an object based on the count value of the counting unit. This results in the following effects: image data is captured based on the count value, and distance measurement is performed.

[0027] In addition, a third aspect of the present technology is a sensing system comprising: a light-emitting unit that emits illumination light based on a light-emitting control signal; a plurality of pixels that each generate a pulse signal through photoelectric conversion; and a counting unit that counts the number of pulse signals from the plurality of pixels. The counting unit includes a plurality of counters and an output destination control circuit, the output destination control circuit being connected between the plurality of pixels and the plurality of counters, receiving a plurality of pulse signals output from the plurality of pixels, and distributing the plurality of pulse signals to a plurality of arbitrary counters, the plurality of pixels being provided in a first chip, and the output control circuit and the counting unit being provided in a second chip. This results in the effect of performing image data capture and distance measurement in a sensing system having a stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram depicting a configuration example of a distance measurement system according to the first embodiment of the present technology.

[0029] Figure 2 : is a diagram depicting an example of a stacked structure of a solid-state imaging element according to the first embodiment of the present technology.

[0030] Figure 3 is a block diagram depicting a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0031] Figure 4 is a block diagram depicting a configuration example of a pixel block according to the first embodiment of the present technology.

[0032] Figure 5 is a circuit diagram depicting a configuration example of a pixel according to the first embodiment of the present technology.

[0033] Figure 6 is a cross-sectional diagram depicting a configuration example of a pixel according to the first embodiment of the present technology.

[0034] Figure 7 is a circuit diagram depicting a configuration example of an output destination control circuit according to the first embodiment of the present technology.

[0035] Figure 8 : is a diagram depicting an example of a correspondence relationship between a circuit provided in a pixel chip and a circuit provided in a circuit chip according to the first embodiment of the present technology.

[0036] Figure 9 It is a diagram for explaining the operation of the counter according to the first embodiment of the present technology.

[0037] Figure 10 is a timing chart showing an example of the operation of the solid-state imaging element in the distance measurement mode according to the first embodiment of the present technology.

[0038] Figure 11 is a timing chart illustrating an example of the operation of the solid-state imaging element in the imaging mode according to the first embodiment of the present technology.

[0039] Figure 12 is an example of an overall diagram of the distance measurement system according to the first embodiment of the present technology.

[0040] Figure 13 is a flowchart illustrating an example of the operation of the distance measurement system according to the first embodiment of the present technology.

[0041] Figure 14 is a block diagram depicting a configuration example of a pixel block according to the second embodiment of the present technology.

[0042] Figure 15 is a circuit diagram depicting a configuration example of an output destination control circuit according to a second embodiment of the present technology.

[0043] Figure 16 is a diagram depicting an example of a correspondence relationship between a circuit provided in a pixel chip and a circuit provided in a circuit chip according to the second embodiment of the present technology.

[0044] Figure 17 2 is a diagram for explaining the operation of the counter according to the second embodiment of the present technology.

[0045] Figure 18 is a circuit diagram depicting a configuration example of an output destination control circuit according to a third embodiment of the present technology.

[0046] Figure 19 : is a diagram depicting an example of a correspondence relationship between a circuit provided in a pixel chip and a circuit provided in a circuit chip according to a third embodiment of the present technology.

[0047] Figure 20 3 is a diagram for explaining the operation of the counter according to the third embodiment of the present technology.

[0048] Figure 21 is a circuit diagram depicting a configuration example of an output destination control circuit according to a fourth embodiment of the present technology.

[0049] Figure 22 4 is a diagram depicting an example of a correspondence relationship between a circuit provided in a pixel chip and a circuit provided in a circuit chip according to a fourth embodiment of the present technology.

[0050] Figure 23 4 is a diagram for explaining the operation of the counter according to the fourth embodiment of the present technology.

[0051] Figure 24 is a diagram depicting an example of a circuit provided in a pixel block according to a fifth embodiment of the present technology.

[0052] Figure 25 : is a diagram depicting an example of a circuit provided in a pixel block according to a sixth embodiment of the present technology.

[0053] Figure 26 It is a block diagram depicting a configuration example of a 0-degree area in a sixth embodiment of the present technology.

[0054] Figure 27 is a circuit diagram depicting a configuration example of an output destination control circuit according to a sixth embodiment of the present technology.

[0055] Figure 28 is a diagram depicting an example of a circuit provided in a pixel block according to a seventh embodiment of the present technology.

[0056] Figure 29 is a timing chart illustrating an example of the operation of the solid-state imaging element in the distance measurement mode according to the seventh embodiment of the present technology.

[0057] Figure 30 is a diagram depicting an example of a circuit provided in a pixel block according to an eighth embodiment of the present technology.

[0058] Figure 31 is a circuit diagram depicting a configuration example of an output destination control circuit according to an eighth embodiment of the present technology.

[0059] Figure 32 is a timing chart illustrating an example of the operation of the solid-state imaging element in the distance measurement mode according to the eighth embodiment of the present technology.

[0060] Figure 33 : is a diagram illustrating an example of a circuit provided in a pixel block according to a ninth embodiment of the present technology.

[0061] Figure 34 : is a diagram depicting an example of a circuit provided in a pixel block according to a tenth embodiment of the present technology.

[0062] Figure 35 is a circuit diagram depicting a configuration example of an output destination control circuit according to a tenth embodiment of the present technology.

[0063] Figure 36 10 is a diagram for explaining the operation of the pixel driver according to the tenth embodiment of the present technology.

[0064] Figure 37 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0065] Figure 38 It is an explanatory diagram depicting an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0066] Hereinafter, a mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described. The description will be given in the following order.

[0067] 1. First Embodiment (Example of Counting in Synchronization with Light Emission Control Signal and Vertical Synchronization Signal)

[0068] 2. Second Embodiment (Example in which one counter performs counting in synchronization with a light emission control signal and a vertical synchronization signal)

[0069] 3. Third Embodiment (Example in which all counters perform counting in synchronization with the light emission control signal and the vertical synchronization signal)

[0070] 4. Fourth Embodiment (Example in which Eight Counters Perform Counting in Synchronization with Light Emission Control Signals and Vertical Synchronization Signals)

[0071] 5. Fifth Embodiment (Example of Division into Multiple Areas and Counting in Synchronization with Light Emission Control Signal and Vertical Synchronization Signal)

[0072] 6. Sixth Embodiment (Example of Reducing the Number of Pixels in an Area and Counting in Synchronization with a Light Emission Control Signal and a Vertical Synchronization Signal)

[0073] 7. Seventh Embodiment (Example of Reducing the Number of Regions and Counting in Synchronization with Light Emission Control Signal and Vertical Synchronization Signal)

[0074] 8. Eighth Embodiment (Example of Switching Phase Difference and Counting in Synchronization with Light Emission Control Signal and Vertical Synchronization Signal)

[0075] 9. Ninth Embodiment (Example of Fixing Phase Difference and Counting Synchronously with Light Emission Control Signal and Vertical Synchronization Signal)

[0076] 10. Tenth Embodiment (Example of Switching the Number of Pixels to be Counted and Counting in Synchronization with Light Emission Control Signal and Vertical Synchronization Signal)

[0077] 11. Application examples of mobile objects

[0078] <1. First embodiment>

[0079] [Configuration example of distance measurement system]

[0080] Figure 1This is a block diagram illustrating an example configuration of a distance measurement system 100 according to a first embodiment of the present technology. Distance measurement system 100 is configured to capture image data and perform distance measurement. Distance measurement system 100 includes a light emitting unit 110, a driver 120, a controller 130, a solid-state imaging element 200, a processor 140, and an application processor 150.

[0081] The elements of the distance measurement system 100 may be arranged in one electronic device or may be distributed and arranged in multiple devices. For example, when distributed and arranged in multiple devices, the light emitting unit 110, the driver 120, the controller 130, the solid-state imaging element 200, and the processor 140 are arranged in the imaging device, and the application processor 150 is arranged in the image processing device.

[0082] The light emitting unit 110 emits light in accordance with a light emission control signal LCLK from the driver 120 and emits irradiation light. For example, near infrared light or the like is used as the irradiation light.

[0083] The driver 120 generates a predetermined period signal as a light emitting control signal LCLK under the control of the controller 130 , and provides the signal to the light emitting portion 110 .

[0084] Controller 130 operates driver 120 and processor 140 in synchronization with each other. The distance measurement system includes multiple modes, including a distance measurement mode for measuring the distance to an object and an imaging mode for capturing image data. In distance measurement mode, controller 130 causes driver 120 to generate light control signal LCLK and causes processor 140 to generate a signal identical to light control signal LCLK as light control signal LCLK′. In imaging mode, controller 130 deactivates driver 120 and causes processor 140 to generate vertical synchronization signal VSYNC.

[0085] Here, the frequency of the vertical synchronization signal VSYNC is, for example, 30 Hz or 60 Hz. On the other hand, the frequency of the light emitting control signal LCLK is higher than that of the vertical synchronization signal VSYNC and is, for example, 10 to 20 MHz.

[0086] The processor 140 controls the solid-state imaging element 200 and the application processor 150. In the distance measurement mode, the processor 140 generates a light emission control signal LCLK′, supplies the signal to the solid-state imaging element 200, and receives a depth map from the solid-state imaging element 200. On the other hand, in the imaging mode, the processor 140 generates a vertical synchronization signal VSYNC, supplies the signal to the solid-state imaging element 200, and receives image data from the solid-state imaging element 200. The processor 140 then supplies the depth map and image data to the application processor 150.

[0087] The application processor 150 performs predetermined processing, such as image recognition processing, based on the image data and the depth map.

[0088] The solid-state imaging element 200 generates image data or a depth map through photoelectric conversion. In distance measurement mode, the solid-state imaging element 200 photoelectrically converts reflected light relative to the irradiated light in synchronization with the light emission control signal LCLK' to generate a depth map. In imaging mode, on the other hand, the solid-state imaging element 200 photoelectrically converts incident light in synchronization with the vertical synchronization signal VSYNC to generate image data. The solid-state imaging element 200 provides the image data and depth map to the processor 140. It should be noted that the system including the solid-state imaging element 200 is an example of a sensing system.

[0089] Note that the solid-state imaging element 200 may have some or all of the functions of the processor 140 and the application processor 150 .

[0090] [Configuration Example of Solid-State Imaging Element]

[0091] Figure 2 A diagram illustrating an example of a stacked structure of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection portion such as a through-hole. Note that in addition to through-holes, connection can also be made by Cu-Cu bonding or bumps. Connection can also be made by these other methods (such as magnetic coupling). In addition, although two chips are stacked, more than three layers can be stacked.

[0092] Figure 3 1 is a block diagram illustrating a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a pixel driver 210, a vertical scanning circuit 220, a pixel array section 230, a column buffer 240, a signal processing circuit 250, and an output section 260. In the pixel array section 230, a plurality of pixels are arranged in a two-dimensional grid pattern. In addition, the pixel array section 230 is divided into a plurality of pixel blocks 300.

[0093] The pixel driver 210 drives the pixel blocks in the pixel array section 230 in synchronization with the light emitting control signal LCLK′ to count the number of pulses.

[0094] The vertical scanning circuit 220 sequentially selects pixel rows in synchronization with a vertical synchronization signal VSYNC and outputs count values ​​to the column buffer 240 .

[0095] The column buffer 240 holds a count value for each pixel.

[0096] The signal processing circuit 250 performs predetermined signal processing on the data in which the count values ​​are arranged. For example, in distance measurement mode, the signal processing circuit 250 obtains the distance based on the count values ​​of each pixel block 300 and generates a depth map in which the distance data is arranged. In addition, in imaging mode, the signal processing circuit 250 generates image data in which the count values ​​of each pixel are configured as pixel data and performs various types of image processing on the image data. The signal processing circuit 250 then provides the depth map and image data to the processor 140.

[0097] [Pixel block configuration example]

[0098] Figure 4 3 is a block diagram illustrating a configuration example of a pixel block 300 according to the first embodiment of the present technology. The pixel block 300 includes a pixel 310 , pixels 321 to 328 , an output destination control circuit 370 , counters 331 to 343 , and switches 351 to 363 .

[0099] Pixel 310 generates a pulse signal by using a SPAD. Pixel 310 provides the pulse signal P1 to the output destination control circuit 370 and the counter 335. The configuration of pixels 321 to 328 is similar to that of pixel 310. These nine pixels are arranged in, for example, 3 rows × 3 columns. In addition, in the pixel array section 230, a vertical signal line 309 is wired for each column. The vertical signal line of the nth (n is an integer) column is defined as 309-n.

[0100] Pixel 321 generates a pulse signal P2 and supplies it to the output destination control circuit 370 and the counter 336. Pixel 322 generates a pulse signal P3 and supplies it to the output destination control circuit 370 and the counter 337. Pixel 323 generates a pulse signal P4 and supplies it to the output destination control circuit 370 and the counter 338. Pixel 324 generates a pulse signal P5 and supplies it to the output destination control circuit 370 and the counter 339.

[0101] Furthermore, pixel 325 generates a pulse signal P6 and supplies the pulse signal to output destination control circuit 370 and counter 340. Pixel 326 generates a pulse signal P7 and supplies the pulse signal to output destination control circuit 370 and counter 341. Pixel 327 generates a pulse signal P8 and supplies the pulse signal to output destination control circuit 370 and counter 342. Pixel 328 generates a pulse signal P9 and supplies the pulse signal to output destination control circuit 370 and counter 343.

[0102] The output destination control circuit 370 controls the output destinations of the pulse signals P1 to P9. In distance measurement mode, the output destination control circuit 370 generates a signal that is the logical sum of the pulse signals P1 to P9 in synchronization with the enable signals EN1 to EN4 from the pixel driver 210, and inputs this signal to the counters 331 to 334. The signal to the counter 331 is the input signal CIN1, and the signal to the counter 332 is the input signal CIN2. Furthermore, the signal to the counter 333 is the input signal CIN3, and the signal to the counter 334 is the input signal CIN4. On the other hand, in imaging mode, no signal is output from the output destination control circuit 370 to the counters.

[0103] The counter 331 counts the number of input signals CIN1. Since the input signal CIN1 is the logical sum of the pulse signals of the respective pixels in the pixel block 300, its count value indicates the number of photons incident on the pixel block 300. The counter 331 outputs the count value as CNT1 to the switch 351.

[0104] The configurations of the counters 332 to 334 are similar to that of the counter 331. The counters 332 to 334 output count values ​​of the input signals CIN2 to CIN4 to the switches 352 to 354 as CNT2 to CNT4.

[0105] The counter 335 counts the number of pulse signals P1. The counter 335 outputs the count value as CNT5 to the switch 355. The configurations of the counters 336 to 343 are similar to that of the counter 335. The counters 336 to 343 output the count values ​​of the pulse signals P2 to P9 as CNT6 to CNT13 to the switches 356 to 363.

[0106] Furthermore, reset signals RST1 to RST13 from the vertical scanning circuit 220 are input to the counters 331 to 343. The count values ​​of the counters are initialized by the reset signals. Note that the pixel driver 210 may provide the reset signals instead of the vertical scanning circuit 220.

[0107] The switch 351 outputs the count value CNT1 to the column buffer 240 via the vertical signal line 309-n according to the selection signal SELn from the vertical scanning circuit 220. The configuration of the switches 352 to 363 is similar to that of the switch 351. For example, the switches 353, 355, 358, and 361 output the count value to the column buffer 240 via the vertical signal line 309-n according to the selection signal SELn. For example, the switches 352, 356, 359, and 362 output the count value to the column buffer 240 via the vertical signal line 309-(n+1) according to the selection signal SEL(n+1). For example, the switches 354, 357, 360, and 363 output the count value to the column buffer 240 via the vertical signal line 309-(n+2) according to the selection signal SEL(n+2).

[0108] It should be noted that although nine pixels are provided in the pixel block 300, the number of pixels in the pixel block 300 is not limited to nine pixels and may be four pixels, etc., as described later. In addition, although a counter is provided for each pixel, a counter may be arranged for each column. In this case, the vertical scanning circuit 220 sequentially selects rows, and the counter group counts the pulse signals from the selected rows.

[0109] [Pixel configuration example]

[0110] Figure 5 3 is a circuit diagram showing a configuration example of a pixel 310 according to the first embodiment of the present technology. The pixel 310 includes a SPAD 311 , a resistor 312 , and an inverter 313 .

[0111] The SPAD 311 generates a photocurrent by photoelectric conversion and performs avalanche amplification. The resistor 312 and the SPAD 311 are connected in series between a power supply terminal and a ground terminal.

[0112] The inverter 313 inverts the potential at the connection point between the resistor 312 and the SPAD 311 and outputs the inverted potential as a pulse signal P1 to the output destination control circuit 370 .

[0113] Furthermore, for example, the SPAD 311 is provided on the pixel chip 201, and the resistor 312, inverter 313, and subsequent circuits (output destination control circuit 370, etc.) are provided on the circuit chip 202. Note that the entire pixel 310 may also be provided in the pixel chip 201.

[0114] Figure 6This is a cross-sectional diagram illustrating an example configuration of a pixel 310 according to the first embodiment of the present technology. As illustrated in the figure, light collected by the microlens 105 is input to each layer of the pixel 310. The configuration of the region other than the microlens 105 is similar to that described, for example, in paragraphs 0024-0053 of Japanese Patent Application Publication No. 2018-88488.

[0115] [Configuration Example of Output Destination Control Circuit]

[0116] Figure 7 1 is a circuit diagram showing a configuration example of the output destination control circuit 370 according to the first embodiment of the present technology. The output destination control circuit 370 includes OR (logical sum) gates 371 to 374 and AND (logical product) gates 381 to 384.

[0117] OR gate 371 outputs the logical sum of pulse signals P1 to P9 to AND gate 381. OR gate 372 outputs the logical sum of pulse signals P1 to P9 to AND gate 382. OR gate 373 outputs the logical sum of pulse signals P1 to P9 to AND gate 383. OR gate 374 outputs the logical sum of pulse signals P1 to P9 to AND gate 384. Note that when the pulse signals P1-P9 are output almost simultaneously, the number of signals after the logical sum of OR gate 371 becomes 1, and a missing count occurs. Therefore, the number of inputs to OR gate 371 can be reduced to only even numbers (P2, P4, etc.), only odd numbers (P1, P3, etc.), one-third of a pixel, etc. by wiring. The same applies to the OR gate, for example, OR gate 372.

[0118] AND gate 381 outputs the logical product of the signal from OR gate 371 and enable signal EN1 from pixel driver 210 as input signal CIN1 to counter 331. AND gate 382 outputs the logical product of the signal from OR gate 372 and enable signal EN2 from pixel driver 210 as input signal CIN2 to counter 332. AND gate 383 outputs the logical product of the signal from OR gate 373 and enable signal EN3 from pixel driver 210 as input signal CIN3 to counter 333. AND gate 384 outputs the logical product of the signal from OR gate 374 and enable signal EN4 from pixel driver 210 as input signal CIN4 to counter 334.

[0119] Here, the enable signal EN1 is the same signal as the light-emission control signal LCLK. The enable signal EN2 is a signal obtained by shifting the phase of the light-emission control signal LCLK by 90 degrees. The enable signal EN3 is a signal obtained by shifting the phase of the light-emission control signal LCLK by 180 degrees. The enable signal EN4 is a signal obtained by shifting the phase of the light-emission control signal LCLK by 270 degrees. In other words, the enable signals EN1 to EN4 are signals having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees with the light-emission control signal LCLK.

[0120] With the configuration shown in the drawings, the counter 331 can count the number of pulses (in other words, the number of photons) in the pixel block 300 in synchronization with the enable signal EN1 having a phase difference of 0 degrees. Furthermore, the counter 332 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN2 having a phase difference of 90 degrees. The counter 333 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN3 having a phase difference of 180 degrees. The counter 334 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN3 having a phase difference of 270 degrees.

[0121] The signal processing circuit 250 obtains the distance by the following formula based on the count values ​​CNT1 to CNT4 of the counters 331 to 334, for example,

[0122] d=(c / 4πf)×tan -1

[0123] ×{(CNT2-CNT4) / (CNT1-CNT3)}...Formula 1.

[0124] In the above formula, d is the distance, for example, in meters (m). c is the speed of light, for example, in meters per second (m / s). -1 is the inverse function of the tangent function. The value of (CNT2-CNT4) / (CNT1-CNT3) indicates the phase difference between the irradiated light and the reflected light. π represents the circular constant. In addition, f is the frequency of the irradiated light, for example, in megahertz (MHz).

[0125] As described above, a distance measurement method for calculating a distance based on the flight time of light is called a time-of-flight (ToF) method.

[0126] Figure 8This diagram illustrates an example of the correspondence between the circuits provided in the pixel chip 201 and the circuits provided in the circuit chip 202 according to the first embodiment of the present technology. As shown in the figure, for each pixel block 300, SPADs for nine pixels are provided in the pixel chip 201. In addition, for each pixel block 300, thirteen counters are provided in the circuit chip 202. Note that in the figure, circuits other than the counters (such as the output destination control circuit 370) in the circuit chip 202 are omitted.

[0127] Four of the thirteen counters count the number of pulses in pixel block 300 in synchronization with enable signals having phase differences of 0, 90, 180, and 270 degrees. In the figure, the values ​​in parentheses at the bottom of the counters represent the phase differences of the corresponding enable signals. The remaining nine counters count the number of pulses in a corresponding pixel in synchronization with the vertical synchronization signal VSYNC.

[0128] Figure 9 1 is a diagram for explaining the operation of the counter according to the first embodiment of the present technology. Counters #1 to #4 in the figure respectively represent counters 331 to 334. Counters #5 to #13 represent counters 335 to 343.

[0129] In the distance measurement mode, counters #1 to #4 count the number of pulses in the pixel block 300 in synchronization with enable signals EN1 to EN4 having phase differences of 0, 90, 180, and 270 degrees. On the other hand, counters #5 to #13 stop counting.

[0130] In the imaging mode, counters #5 to #13 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC. On the other hand, counters #1 to #4 stop counting.

[0131] [Operation Example of Solid-State Imaging Element]

[0132] Figure 10 This is a timing diagram illustrating an example of the operation of the solid-state imaging element 200 in distance measurement mode according to the first embodiment of the present technology. Assume that distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0133] Furthermore, at timing T1, the driver 120 begins supplying the light emission control signal LCLK, and the light emitting unit 110 emits light in synchronization with this signal. Furthermore, at time T1, the pixel driver 210 begins supplying the enable signal EN1, which has a 0-degree phase difference from the light emission control signal LCLK. Then, at timing T2, the pixel driver 210 begins supplying the enable signal EN2, which has a 90-degree phase difference. At time T3, the pixel driver 210 begins supplying the enable signal EN3, which has a 180-degree phase difference. At time T4, the pixel driver 210 begins supplying the enable signal EN4, which has a 270-degree phase difference.

[0134] Then, when a certain period of time has passed, the vertical scanning circuit 220 outputs count values ​​through the selection signal Based on these count values, the signal processing circuit 250 uses Formula 1 to obtain the distance of each pixel block 300.

[0135] Figure 11 1 is a timing chart showing an example of the operation of the solid-state imaging element 200 in the imaging mode according to the first embodiment of the present technology. Assume that the imaging mode is set at timing T10. The processor 140 starts supplying the vertical synchronization signal VSYNC at and after time T11.

[0136] In addition, the driver 120 stops providing the light emission control signal LCLK, and the pixel driver 210 stops providing the enable signals EN1 to EN4. The vertical scanning circuit 220 provides the reset signal RST to the counters 335 to 343 to initialize the count value. Then, during the exposure period from timing T12 to T13, which is synchronized with the vertical synchronization signal VSYNC, the vertical scanning circuit 220 stops providing the reset signal RST. During this period, the counters 335 to 343 count the number of pulses, and the vertical scanning circuit 220 outputs the count value via the selection signal. The signal processing circuit 250 generates image data in which these count values ​​are arranged.

[0137] Figure 12 3 is an example of an overall diagram of the distance measurement system 100 according to the first embodiment of the present technology. In the pixel block 300 , circuits other than the pixel 310 and the pixels 321 to 328 are arranged in a counting section 330 .

[0138] The light emitting section 110 emits irradiation light in synchronization with a light emitting control signal LCLK having a higher frequency than the vertical synchronization signal VSYNC. In addition, each pixel (such as the pixel 310) generates a pulse signal through photoelectric conversion.

[0139] In distance measurement mode, the output destination control circuit 370 supplies the logical sum of the pulse signals in the pixel block 300 to the counters 331 to 334 in synchronization with the enable signals EN1 to EN4. The counters 331 to 334 count the logical sum signals. As described above, since the enable signal is a signal having a phase difference of a predetermined value (0 degrees or 90 degrees) with the light emission control signal LCLK, the count values ​​of the counters 331 to 334 are obtained by counting the number of pulses in synchronization with the light emission control signal LCLK. Note that the counters 331 to 334 are examples of first counters.

[0140] On the other hand, in the imaging mode, the counters 335 to 343 count the number of pulse signals of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC. Note that the counters 335 to 343 are examples of second counters.

[0141] As shown, the counting section 330 includes counters 335 to 343 that count in synchronization with the vertical synchronization signal VSYNC, and counters 331 to 334 that count in synchronization with the light emission control signal LCLK. Therefore, in addition to capturing image data, the solid-state imaging element 200 can also perform distance measurement using the ToF method. Furthermore, because the solid-state imaging element 200 itself can perform distance measurement, there is no need to add a distance measurement sensor using infrared rays or lasers. Consequently, compared to adding a separate distance measurement sensor, the power consumption and cost of the distance measurement system 100 can be reduced.

[0142] Figure 13 1 is a flowchart showing an example of the operation of the distance measurement system 100 according to the first embodiment of the present technology. For example, when an application for performing distance measurement and imaging is executed, the operation is started.

[0143] The distance measurement system 100 switches to the distance measurement mode, and the light emitting unit 110 emits illumination light in synchronization with the light emission control signal LCLK (step S901). Furthermore, the counters 331 to 334 count the number of pulses in synchronization with the light emission control signal LCLK (step S902). The signal processing circuit 250 then performs distance measurement based on the count value and generates a depth map (step S903).

[0144] Subsequently, the distance measurement system 100 switches to the imaging mode, and the solid-state imaging element 200 switches to the counters 335 to 343 and counts the number of pulses within the exposure period synchronized with the vertical synchronization signal (step S904). The signal processing circuit 250 performs image processing such as facial recognition based on the image data of the count value (step S905). After step S905, the distance measurement system 100 ends the operation.

[0145] Note that the solid-state imaging element 200 performs imaging (step S904 ) after distance measurement (step S903 ), but distance measurement may be performed after imaging. Furthermore, distance measurement and imaging may be performed simultaneously.

[0146] As described above, according to the first embodiment of the present technology, the counting section 330 counts the number of pulses in synchronization with each of the light emission control signal and the vertical synchronization signal, and thus can perform distance measurement in synchronization with the vertical synchronization signal in the pixel when capturing image data.

[0147] <2. Second embodiment>

[0148] In the first embodiment described above, the counters 331 to 334 for distance measurement and the counters 335 to 343 for imaging are provided for every nine pixels. However, as the number of pixels increases, the number of required counters increases, and the circuit scale increases. The solid-state imaging element 200 of the second embodiment differs from the solid-state imaging element of the first embodiment in that a portion of the counters for imaging are also used for distance measurement, thereby reducing the number of counters.

[0149] Figure 14 3 is a block diagram showing a configuration example of a pixel block 300 according to a second embodiment of the present technology. The pixel block 300 of the second embodiment is different from that of the first embodiment in that the counters 340 to 343 and the switches 360 to 363 are not provided.

[0150] Furthermore, the output destination control circuit 370 of the second embodiment supplies input signals CIN1 to CIN9 to the counters 331 to 339. Furthermore, switches 351, 354, and 357 output count values ​​via vertical signal line 309-n. Switches 352, 355, and 358 output count values ​​via vertical signal line 309-(n+1). Switches 353, 356, and 359 output count values ​​via vertical signal line 309-(n+2).

[0151] Figure 15 39 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a second embodiment of the present technology. The output destination control circuit 370 of the second embodiment differs from the output destination control circuit 370 of the first embodiment in further including selectors 391 to 394.

[0152] Furthermore, the AND gate 381 of the second embodiment supplies the logical product to the selector 391, and the AND gate 382 supplies the logical product to the selector 392. The AND gate 383 supplies the logical product to the selector 393, and the AND gate 384 supplies the logical product to the selector 394.

[0153] The selector 391 selects one of the pulse signal P1 and the signal from the AND gate 381 according to the control signal CTRL1 and provides the selected signal as the input signal CIN1 to the counter 331 .

[0154] Furthermore, the pulse signal P2 is directly input to the counter 332 as the input signal CIN2 .

[0155] The selector 392 selects one of the pulse signal P3 and the signal from the AND gate 382 according to the control signal CTRL2 and provides the selected signal as the input signal CIN3 to the counter 333 .

[0156] Furthermore, the pulse signal P4 is directly input as the input signal CIN4 to the counter 334. The pulse signals P5 and P6 are directly input as the input signals CIN5 and CIN6 to the counters 335 and 336.

[0157] The selector 393 selects one of the pulse signal P7 and the signal from the AND gate 383 according to the control signal CTRL3 , and supplies the selected signal as the input signal CIN7 to the counter 337 .

[0158] In addition, the pulse signal P8 is directly input to the counter 338 as the input signal CIN8.

[0159] The selector 394 selects one of the pulse signal P9 and the signal from the AND gate 384 according to the control signal CTRL4 and provides the selected signal as the input signal CIN9 to the counter 339 .

[0160] For example, the control signals CTRL1 to CTRL4 described above are provided from the pixel driver 210. In the distance measurement mode, the pixel driver 210 controls the selectors 391 to 394 through the control signals CTRL1 to CTRL4 to select the signals from the AND gates 381 to 384. Therefore, the counters 331, 333, 337, and 339 can count the number of pulses in synchronization with the enable signals EN1 to EN4 having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. The signal processing circuit 250 then performs distance measurement based on these count values.

[0161] On the other hand, in the imaging mode, the pixel driver 210 controls the selectors 391 to 394 to select the pulse signals P1, P3, P7, and P9 through the control signals CTRL1 to CTRL4. Therefore, the counters 331, 333, 337, and 339, together with the remaining counters, count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal.

[0162] Figure 16This diagram illustrates an example of the correspondence between circuits provided in the pixel chip 201 and circuits provided in the circuit chip 202 according to the second embodiment of the present technology. As shown in the diagram, for each pixel block 300, SPADs for nine pixels are provided in the pixel chip 201. In addition, for each pixel block 300, nine counters are provided in the circuit chip 202.

[0163] In ranging mode, the nine counters (the upper left counter, upper right counter, lower left counter, and lower right counter) count pulses in synchronization with enable signals EN1 to EN4, which have phase differences of 0, 90, 180, and 270 degrees. In imaging mode, each of the nine counters counts pulses for the corresponding pixel in synchronization with the vertical synchronization signal.

[0164] Note that although the four counters also used for distance measurement are arranged at the upper left, upper right, lower left, and lower right, the arrangement is not limited to this.

[0165] Figure 17 1 is a diagram for explaining the operation of the counter according to the second embodiment of the present technology. Counters #1 to #9 in the figure represent counters 331 to 339, respectively.

[0166] In the distance measurement mode, counters #1, #3, #7, and #9 count the number of pulses in the pixel block 300 in synchronization with enable signals EN1 to EN4 (in other words, the light emission control signal LCLK) having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. On the other hand, the remaining counters stop counting.

[0167] In the imaging mode, counters # 1 to # 9 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC.

[0168] As shown in the figure, counters #1, #3, #7, and #9 sequentially perform the following processing: they count the number of pulses in pixel block 300 in synchronization with the light-emission control signal LCLK, and they also count the number of pulses in synchronization with the vertical synchronization signal VSYNC. The remaining counters #2, #4, #5, #6, and #8 count the number of pulses in synchronization with the vertical synchronization signal VSYNC. In other words, four of the nine counters used for imaging are also used for distance measurement. Therefore, compared to the first embodiment, which separately provides nine counters for imaging and four counters for distance measurement, the number of counters can be reduced.

[0169] It should be noted that counters #1, #3, #7, and #9 are examples of first counters, and counters #2, #4, #5, #6, and #8 are examples of second counters.

[0170] As described above, in the second embodiment of the present technology, four counters sequentially count the number of pulses in synchronization with the light emission control signal and the number of pulses in synchronization with the vertical synchronization signal. Therefore, there is no need to provide separate counters for imaging and distance measurement, which reduces the number of counters.

[0171] <3. Third embodiment>

[0172] In the second embodiment described above, four counters count the number of pulses in synchronization with enable signals having a phase difference of 0 to 270 degrees. However, in this configuration, the measurable distance range may be insufficient. The solid-state imaging element 200 of the third embodiment differs from the solid-state imaging element 200 of the second embodiment in that the measurable distance range is expanded by expanding the range of the phase difference.

[0173] Figure 18 3 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a third embodiment of the present technology. The output destination control circuit 370 of the third embodiment differs from the output destination control circuit 370 of the second embodiment in that it further includes OR gates 375 to 379, AND gates 385 to 389, and selectors 395 to 399.

[0174] The connection configuration of the OR gates 375 to 379 , the AND gates 385 to 389 , and the selectors 395 to 399 is similar to the connection configuration of the OR gate 371 , the AND gate 381 , and the selector 391 .

[0175] Enable signals EN5 to EN9 are input to AND gates 385 to 389. Control signals CTRL5 to CTRL9 are input to selectors 395 to 399. Selectors 391 to 399 select one of the pulse signals P1 to P9 and the signals from AND gates 381 to 389, and supply the selected signal as input signals CIN1 to CIN9 to counters 331 to 339.

[0176] The phase differences of the enable signals EN1 to EN9 are set to, for example, 0 degrees, 360 degrees, 90 degrees, 450 degrees, 720 degrees, 630 degrees, 270 degrees, 540 degrees, and 180 degrees, respectively. By setting the phase difference of the enable signals from 0 degrees to 720 degrees, the range of distances that can be measured by the signal processing circuit 250 can be expanded compared to the case of 0 degrees to 270 degrees.

[0177] In the distance measurement mode, the signal processing circuit 250 obtains a rough distance using a phase difference of, for example, 0 to 720 degrees, and then obtains an accurate distance using a phase difference of 0 to 540 degrees, etc. By gradually narrowing the range of the phase difference in this manner, the accuracy of the distance can be gradually improved.

[0178] Figure 19 This diagram illustrates an example of the correspondence between circuits provided in the pixel chip 201 and circuits provided in the circuit chip 202 according to the third embodiment of the present technology. As shown in the diagram, for each pixel block 300, SPADs for nine pixels are provided in the pixel chip 201. Furthermore, for each pixel block 300, nine counters are provided in the circuit chip 202.

[0179] In distance measurement mode, the upper left, upper right, lower left, and lower right counters of the nine counters count pulses in synchronization with enable signals having phase differences of 0, 90, 180, and 270 degrees. Furthermore, the center counter counts pulses in synchronization with an enable signal having a phase difference of 720 degrees. The center-up, center-down, center-left, and center-right counters count pulses in synchronization with enable signals having phase differences of 360, 540, 450, and 630 degrees.

[0180] Figure 20 This is a diagram illustrating the operation of a counter according to a third embodiment of the present technology. In distance measurement mode, counters #1 to #9 count the number of pulses in pixel block 300 in synchronization with enable signals having phase differences of 0, 360, 90, 450, 720, 630, 270, 540, and 180 degrees.

[0181] In the imaging mode, counters # 1 to # 9 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC.

[0182] As described above, according to the third embodiment of the present technology, nine counters count the number of pulses in synchronization with nine enable signals having different phase differences, and therefore the measurable distance range can be expanded compared to the case of counting in synchronization with four enable signals.

[0183] <4. Fourth embodiment>

[0184] In the third embodiment described above, nine counters count the number of pulses in synchronization with the enable signal, but in this configuration, there is a possibility that the number of pieces of data used for distance measurement increases, and the amount of processing by the signal processing circuit 250 increases. The solid-state imaging element 200 according to the fourth embodiment differs from the solid-state imaging element 200 of the third embodiment in that the number of counters used for distance measurement is reduced.

[0185] Figure 211 is a circuit diagram showing an example configuration of an output destination control circuit 370 according to a fourth embodiment of the present technology. The output destination control circuit 370 of the fourth embodiment differs from the output destination control circuit 370 of the third embodiment in that the OR gate 375, AND gate 385, and selector 395 are removed. Furthermore, the pulse signal P5 is directly supplied to the counter 335 as the input signal CIN5.

[0186] Figure 22 This diagram illustrates an example of a correspondence relationship between circuits provided in the pixel chip 201 and circuits provided in the circuit chip 202 according to a fourth embodiment of the present technology. The pixel block 300 of the fourth embodiment differs from the pixel block 300 of the third embodiment in that the central counter does not count in the distance measurement mode.

[0187] Figure 23 This is a diagram illustrating the operation of the counters according to the fourth embodiment of the present technology. In distance measurement mode, the eight counters other than counter #5 count pulses in synchronization with the enable signal. In other words, the number of counters used for distance measurement is reduced from nine to eight. Consequently, the number of pieces of data used for distance measurement is reduced, and the processing load of the signal processing circuit 250 is reduced. Note that the counters other than counter #5 are examples of first counters, and counter #5 is an example of second counters.

[0188] As described above, according to the fourth embodiment of the present technology, eight counters count the number of pulses in synchronization with the enable signal, compared to the case where nine counters are synchronized with the enable signal, and thereby the number of pieces of data for distance measurement can be reduced.

[0189] <5. Fifth embodiment>

[0190] In the first embodiment described above, only one counter synchronized with an enable signal having a phase difference of 0 degrees is arranged for each pixel block. However, with this configuration, there is a possibility that the quality of the signal from the counter will be insufficient. The solid-state imaging element 200 of the fifth embodiment differs from the solid-state imaging element of the first embodiment in that signal quality is improved by providing two or more counters synchronized with the same enable signal.

[0191] Figure 24is a diagram depicting an example of a circuit provided in a pixel block 300 according to a fifth embodiment of the present technology. The pixel block 300 is divided into a plurality of regions. For example, the pixel block 300 is divided into a 0-degree region 410, a 90-degree region 420, a 180-degree region 430, and a 270-degree region 440. In the 0-degree region 410, nine counters such as the counter 411 are arranged into 3 rows × 3 columns. In the 90-degree region 420, nine counters such as the counter 421 are arranged into 3 rows × 3 columns. In the 180-degree region 430, nine counters such as the counter 431 are arranged into 3 rows × 3 columns. In the 270-degree region 440, nine counters such as the counter 441 are arranged into 3 rows × 3 columns. Note that the number of pixels in each region is the same as the number of counters (i.e., nine).

[0192] In the 0-degree region 410, the upper left counter, the upper right counter, the lower left counter, and the lower right counter count the number of pulses in the 0-degree region 410 in synchronization with an enable signal having a phase difference of 0 degrees. In the 90-degree region 420, the upper left counter, the upper right counter, the lower left counter, and the lower right counter count the number of pulses in the 90-degree region 420 in synchronization with an enable signal having a phase difference of 90 degrees. In the 180-degree region 430, the upper left counter, the upper right counter, the lower left counter, and the lower right counter count the number of pulses in the 180-degree region 430 in synchronization with an enable signal having a phase difference of 180 degrees. In the 270-degree region 440, the upper left counter, the upper right counter, the lower left counter, and the lower right counter count the number of pulses in the 270-degree region 440 in synchronization with an enable signal having a phase difference of 270 degrees.

[0193] Furthermore, the output destination control circuit 370 is arranged in each of the 0 degree area 410, the 90 degree area 420, the 180 degree area 430, and the 270 degree area 440. In the figure, the output destination control circuit 370 is omitted. Furthermore, the configuration of the output destination control circuit 370 of the fifth embodiment is the same as that of the Figure 15 The configuration of the second embodiment shown in is similar. However, the same enable signal is input to the four counters.

[0194] As shown in the figure, four count values ​​are generated for each pixel block 300, which are counted synchronously with the enable signal having the same phase difference. Signal processing circuit 250 calculates the total value or average value of these four count values ​​and performs distance measurement by using the calculation result. By calculating the sum or average value of the four count values, signal noise can be reduced and signal quality can be improved.

[0195] It should be noted that the counters in the upper left, upper right, lower left, and lower right of each region are examples of first counters, and the other counters are examples of second counters. In addition, the number of regions of each pixel block 300 is not limited to four, and the number of pixels in each region is not limited to nine pixels.

[0196] As described above, according to the fifth embodiment of the present technology, four counters for counting in synchronization with enable signals having the same phase difference are arranged for each pixel block 300, and thus signal noise can be reduced by calculating the sum or average of the count values ​​of the counters.

[0197] <6. Sixth embodiment>

[0198] In the fifth embodiment described above, nine pixels are arranged for each region. However, in this configuration, there is a possibility that the number of pixels in the pixel block 300 is 36 pixels and the resolution of the depth map is insufficient. The solid-state imaging element 200 of the sixth embodiment differs from the solid-state imaging element of the fifth embodiment in that the number of pixels per region is reduced and the resolution of the depth map is improved.

[0199] Figure 25 This diagram illustrates an example of a circuit configured in a pixel block 300 according to a sixth embodiment of the present technology. The pixel block 300 of the sixth embodiment differs from that of the fifth embodiment in that each region has four pixels. The four pixels are arranged in two rows and two columns. Furthermore, a counter is provided in the upper left corner of each region to count pulses in synchronization with an enable signal.

[0200] As shown in the figure, the number of pixels per region is reduced to four pixels, so the resolution of the depth map can be improved compared to the fifth embodiment in which the number of pixels per region is nine pixels.

[0201] Figure 26 This is a block diagram showing an example configuration of a 0-degree area 410 according to a sixth embodiment of the present technology. Pixels 310 and 321 to 323, as well as a counter 330, are arranged in the 0-degree area 410. The counter 330 also includes an output destination control circuit 370, counters 411 to 414, and switches 351 to 354.

[0202] The pixels 310 and 321 to 323 output pulse signals P1 to P4 to the output destination control circuit 370. The output destination control circuit 370 supplies input signals CIN1 to CIN4 to counters 411 to 414. The counters 411 to 414 supply count values ​​CNT1 to CNT4 to switches 351 to 354. The switches 351 and 353 supply the count values ​​to the vertical signal line 309-n, and the switches 352 and 354 supply the count values ​​to the vertical signal line 309-(n+1).

[0203] Note that the configurations of the 90-degree region 420 , the 180-degree region 430 , and the 270-degree region 440 are similar to that of the 0-degree region 410 .

[0204] Figure 27 3 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a sixth embodiment of the present technology. In the output destination control circuit 370, an OR gate 371, an AND gate 381, and a selector 391 are arranged. The connection configuration of the OR gate 371, the AND gate 381, and the selector 391 of the sixth embodiment is similar to that of FIG. Figure 15 The connection configuration of the second embodiment is similar, however, the output destination is the counter 411.

[0205] Furthermore, the pulse signals P2 to P4 are directly supplied to the counters 412 to 414 as the input signals CIN2 to CIN4 .

[0206] Note that the counter 411 is an example of a first counter, and the counters 412 to 414 are examples of a second counter.

[0207] As described above, according to the sixth embodiment of the present technology, the number of pixels per area is reduced to four pixels, and thus the resolution of the depth map can be improved compared to the case where the number of pixels per area is nine pixels.

[0208] <7. Seventh embodiment>

[0209] In the sixth embodiment described above, four regions are arranged for each pixel block, but in this configuration, there is a possibility that the number of pixels in the pixel block 300 is sixteen pixels and the resolution of the depth map is insufficient. The solid-state imaging element 200 of the seventh embodiment differs from the solid-state imaging element of the sixth embodiment in that the number of regions is reduced and the resolution of the depth map is improved.

[0210] Figure 28is a diagram illustrating an example of a circuit provided in a pixel block according to a seventh embodiment of the present technology. The pixel block 300 of the seventh embodiment differs from the pixel block of the sixth embodiment in that the number of regions is two. For example, a 0-degree region 410 and a 180-degree region 430 are provided in the pixel block 300. By reducing the number of regions in the pixel block 300 from four to two, the size of the pixel block 300 can be reduced. Consequently, the resolution of the depth map can be improved.

[0211] Figure 29 This is a timing diagram illustrating an example of the operation of the solid-state imaging element 200 in distance measurement mode according to the seventh embodiment of the present technology. Assume that distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0212] At timing T1, the driver 120 starts supplying the light emission control signal LCLK, and the light emitting unit 110 emits light in synchronization with the signal. At timing T1, the pixel driver 210 starts supplying the enable signal EN1, which has a 0-degree phase difference from the light emission control signal LCLK. Then, at timing T2, the pixel driver 210 starts supplying the enable signal EN2, which has a 180-degree phase difference.

[0213] Then, when a certain period of time has passed, the vertical scanning circuit 220 outputs a count value through a selection signal Based on these count values, the signal processing circuit 250 obtains the distance of each pixel block 300.

[0214] As described above, according to the seventh embodiment of the present technology, the number of regions per pixel block 300 is reduced to two, and thus the resolution of the depth map can be improved compared to the case where the number of regions is four.

[0215] <8. Eighth embodiment>

[0216] In the seventh embodiment described above, the counter counts the number of pulses in synchronization with the enable signals having phase differences of 0 and 180 degrees. However, since the enable signals having phase differences of 90 and 270 degrees are not used, the distance measurement accuracy is reduced and the measurable distance range is narrowed. The solid-state imaging element 200 of the eighth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that the counter counts the number of pulses in synchronization with the enable signals having phase differences of 90 and 270 degrees in addition to the enable signals having phase differences of 0 and 180 degrees.

[0217] Figure 30This figure shows an example of a circuit provided in a pixel block 300 according to an eighth embodiment of the present technology. The pixel block 300 of the eighth embodiment differs from the pixel block of the seventh embodiment in that the counters 411 to 414 are arranged without dividing the pixel block into a plurality of areas. Furthermore, four pixels are arranged in the pixel block 300. Circuits other than the counters (such as the output destination control circuit 370) are omitted in the figure.

[0218] Furthermore, in the distance measurement mode, the counters 411 and 414 count the number of pulses in synchronization with the enable signals having 0 degrees and 180 degrees, and the counters 412 and 413 count the number of pulses in synchronization with the enable signals having 90 degrees and 270 degrees.

[0219] Figure 31 370 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to an eighth embodiment of the present technology. The output destination control circuit 370 of the eighth embodiment is provided with OR gates 371 to 374 , AND gates 381 to 384 , and selectors 391 to 394 .

[0220] The connection configuration of the OR gates 371 to 374 , the AND gates 381 to 384 , and the selectors 391 to 394 is similar to that of the OR gate 371 , the AND gate 381 , and the selector 391 of the second embodiment.

[0221] The enable signals EN1 to EN4 are input to the AND gates 381 to 384. The control signals CTRL1 to CTRL4 are input to the selectors 391 to 394. The selectors 391 to 394 select one of the pulse signals P1 to P4 and the signals from the AND gates 381 to 384, and provide the selected signal as the input signals CIN1 to CIN4 to the counters 411 to 414.

[0222] Figure 32 This is a timing diagram illustrating an example of the operation of the solid-state imaging element 200 in distance measurement mode according to the eighth embodiment of the present technology. Assume that distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0223] At timing T1, driver 120 starts supplying the light emission control signal LCLK, and light emitting section 110 emits light in synchronization with the signal. At timing T1, driver 210 starts supplying enable signals EN1 and EN4 with a 0-degree phase difference from light emission control signal LCLK. Then, at timing T2, driver 210 starts supplying enable signals EN2 and EN3 with a 90-degree phase difference.

[0224] Then, when a certain period of time has passed, the vertical scanning circuit 220 outputs the count values ​​through the selection signal. The signal processing circuit 250 holds these count values.

[0225] Next, at timing T3, the vertical scanning circuit 220 provides a reset signal RST to the counters 331 to 334 to initialize the count value. At timing T4, the driver 210 starts providing the enable signals EN1 and EN4 with a 180-degree phase difference from the light emission control signal LCLK. Then, at timing T5, the driver 210 starts providing the enable signals EN2 and EN3 with a 270-degree phase difference.

[0226] Then, when a certain period of time has passed, the vertical scanning circuit 220 outputs the count value through the selection signal. Based on the stored count value and the output count value, the signal processing circuit 250 obtains the distance of each pixel block 300.

[0227] As shown in the figure, driver 210 provides an enable signal in which a phase difference is sequentially set for each of a plurality of set values ​​(90 degrees, 270 degrees, etc.). By switching the phase difference in this manner, the counter can count the number of pulses in synchronization with the enable signal having a phase difference of 90 degrees and 270 degrees in addition to the enable signal having a phase difference of 0 degrees and 180 degrees. Due to the increased number of phase differences, ranging accuracy can be improved, and the measurable distance range can be expanded.

[0228] Note that although all four counters perform counting in the distance measurement mode, only two counters (such as counters 411 and 412) can perform counting in the distance measurement mode. Power consumption can be reduced by reducing the number of counters operating in the distance measurement mode.

[0229] As described above, according to the eighth embodiment of the present technology, the pixel driver 210 sequentially sets each of a plurality of set values ​​as a phase difference, thereby increasing the number of phase differences. Therefore, the distance measurement accuracy can be improved, and the measurable distance range can be expanded.

[0230] <9. Ninth embodiment>

[0231] In the eighth embodiment described above, the pixel driver 210 switches the phase difference. However, in this configuration, the distance measurement interval becomes longer than when the phase difference is fixed, and the frame rate of the depth map decreases. The solid-state imaging element 200 of the ninth embodiment differs from the solid-state imaging element of the eighth embodiment in that the phase difference is fixed and the frame rate of the depth map is increased.

[0232] Figure 331 is a diagram showing an example of a circuit provided in a pixel block 300 according to a ninth embodiment of the present technology. In the pixel block 300 of the ninth embodiment, counters 411 to 414 are arranged similarly to those in the eighth embodiment.

[0233] However, in distance measurement mode, the phase difference between enable signals EN1 to EN4 is fixed. For example, counter 411 counts pulses in synchronization with enable signal EN1 at 0 degrees, while counter 412 counts pulses in synchronization with enable signal EN2 at 90 degrees. Counter 413 counts pulses in synchronization with enable signal EN3 at 180 degrees, and counter 414 counts pulses in synchronization with enable signal EN4 at 270 degrees. Because the phase difference is fixed, the depth map frame rate is increased compared to the eighth embodiment.

[0234] As described above, according to the ninth embodiment of the present technology, the pixel driver 210 fixes the phase difference of the enable signal, and thus the frame rate of the depth map can be improved compared to the case of switching the phase difference.

[0235] <10. Tenth embodiment>

[0236] In the ninth embodiment described above, in the distance measurement mode, the counter counts the number of pulses in units of four pixels. However, as the number of pixels to be counted increases, the maximum value of the count value increases, and the data size of the count value increases. The solid-state imaging element 200 of the tenth embodiment differs from the solid-state imaging element of the ninth embodiment in that the number of pixels to be counted is switched between four pixels and two pixels, and the data size is made variable.

[0237] Figure 34 This diagram illustrates an example of a circuit provided in a pixel block according to the tenth embodiment of the present technology. In the pixel block 300 of the tenth embodiment, for example, a 0-degree region 410 and a 180-degree region 430 are provided. Furthermore, four pixels and an output destination control circuit 370 are provided for each region. In distance measurement mode, one of the four counters in the region counts the number of pulses in synchronization with an enable signal. In imaging mode, each of the four counters counts the number of pulses in synchronization with a vertical synchronization signal.

[0238] Figure 35 370 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a tenth embodiment of the present technology. The output destination control circuit 370 of the tenth embodiment is provided with OR gates 371 , 372 , and 380 , AND gates 381 and 382 , and a selector 391 .

[0239] The OR gate 371 provides the logical sum of the pulse signals P1 and P2 to the AND gate 381. The OR gate 372 provides the logical sum of the pulse signals P3 and P4 to the AND gate 382.

[0240] AND gate 381 provides a logical product of the signal from OR gate 371 and enable signal EN1a to OR gate 380. AND gate 382 provides a logical product of the signal from OR gate 372 and enable signal EN1b to OR gate 380.

[0241] The OR gate 380 outputs the logical sum of the signals from the AND gates 381 and 382 to the selector 391 .

[0242] The selector 391 selects one of the pulse signal P1 and the signal from the OR gate 380 according to the control signal CTRL, and provides the selected signal as the input signal CIN1 to the counter 411 .

[0243] Furthermore, the pulse signals P2 to P4 are directly supplied to the counters 412 to 414 as the input signals CIN2 to CIN4 .

[0244] Note that the counter 411 is an example of a first counter, and the counters 412 to 414 are examples of a second counter.

[0245] Figure 36 This is a diagram for explaining the operation of the pixel driver 210 according to the tenth embodiment of the present technology. The control in the diagram corresponds to the 0-degree area 410. In the tenth embodiment, the four-pixel addition mode or the two-pixel addition mode is set as the distance measurement mode. The four-pixel addition mode is a mode in which the number of pixels to be counted in the pulse signal is four pixels, and the two-pixel addition mode is a mode in which the number of pixels to be counted in the pulse signal is two pixels.

[0246] In the four-pixel addition mode, the pixel driver 210 provides a signal with a phase difference of 0 degrees as the enable signals EN1a and EN1b. In the two-pixel addition mode, the pixel driver 210 provides a signal with a phase difference of 0 degrees as one of the enable signals EN1a and EN1b. The other of the enable signals EN1a and EN1b is not provided. In the imaging mode, no enable signal is provided. It should be noted that the control of the 180-degree area 430 is similar to the control of the 0-degree area 410 shown in the figure, except that the phase difference is set to 180 degrees.

[0247] Furthermore, the pixel driver 210 sets the control signal CTRL to "0" and causes the selector 391 to select the signal from the OR gate 380 in the distance measurement mode. On the other hand, in the imaging mode, the pixel driver 210 sets the control signal CTRL to "1" and causes the selector 391 to select the pulse signal P1.

[0248] use Figure 35 and Figure 36 In the configuration shown, the output destination control circuit 370 outputs the logical sum of the corresponding pulse signals of a set number of pixels (four pixels or two pixels) among the four pixels in the pixel block 300, and the counter 411 counts the logical sum. Therefore, the number of pixels to be counted can be switched between four pixels and two pixels, and the data size of the count value can be changed.

[0249] Note that the pixel driver 210 switches the number of pixels to be counted between four pixels and two pixels, but is not limited to this configuration, and for example, may switch to one pixel, three pixels, or the like.

[0250] As described above, according to the tenth embodiment of the present technology, the counter 411 counts the logical sum of pulse signals of a set number of pixels among four pixels in the pixel block 300 , thereby making it possible to change the data size of the count value.

[0251] <11. Application Examples of Mobile Objects>

[0252] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot).

[0253] Figure 37 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0254] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 37 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of integrated control unit 12050 includes, for example, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0255] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the vehicle's drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, a braking device for generating the vehicle's braking force, and the like.

[0256] Body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device as a substitute for key buttons or signals from various switches may be input to body system control unit 12020. Body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0257] The vehicle exterior information detection unit 12030 detects information outside the vehicle, including information about the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the vehicle exterior and receives the captured images. Furthermore, the vehicle exterior information detection unit 12030 can also detect objects such as people, vehicles, obstacles, signs, and text on the road, or measure their distance based on the received images.

[0258] The imaging portion 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging portion 12031 can output the electrical signal as an image or as information regarding the measured distance. The light received by the imaging portion 12031 can be visible light or invisible light such as infrared light.

[0259] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver is dozing off.

[0260] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from a lane, and the like.

[0261] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to drive autonomously without relying on the driver's operation, etc.

[0262] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0263] The audio / video output unit 12052 sends an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the occupants of the vehicle or the outside of the vehicle of information. Figure 37 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0264] Figure 38 12031 is a diagram showing an example of the installation position of the imaging portion 12031.

[0265] exist Figure 38 , the imaging portion 12031 includes imaging portions 12101 , 12102 , 12103 , 12104 and 12105 .

[0266] Imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, on the front nose, side mirrors, rear bumper, and rear doors of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Imaging section 12101 provided on the front nose inside the vehicle and imaging section 12105 provided on the upper portion of the windshield primarily capture images of the front of vehicle 12100. Imaging sections 12102 and 12103 provided on the side mirrors primarily capture images of the sides of vehicle 12100. Imaging section 12104 provided on the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Imaging section 12105 provided on the upper portion of the windshield inside the vehicle is primarily used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0267] Please note that Figure 38 The following describes examples of the imaging ranges of imaging sections 12101 through 12104. Imaging range 12111 represents the imaging range of imaging section 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging sections 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging section 12104 located on the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 viewed from above can be obtained by superimposing image data captured by imaging sections 12101 through 12104.

[0268] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0269] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104. Thus, it can extract the nearest three-dimensional object, located on the travel path of vehicle 12100 and traveling at a predetermined speed (e.g., 0 km / h or greater) in the same direction as vehicle 12100, as the leading vehicle. Furthermore, microcomputer 12051 can set a following distance in advance to maintain a position ahead of the leading vehicle and execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, it is possible to execute cooperative control for autonomous driving, which allows the vehicle to travel autonomously without relying on driver operations or the like.

[0270] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as utility poles), extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and executes forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thus assist driving to avoid collisions.

[0271] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. Microcomputer 12051 can, for example, identify pedestrians by determining whether a pedestrian exists in images captured by imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from images captured by imaging units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When microcomputer 12051 determines that a pedestrian exists in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, audio / video output unit 12052 controls display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. Audio / video output unit 12052 can also control display unit 12062 to display an icon representing the pedestrian at a desired location.

[0272] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the imaging portion 12031 in the above configuration. Specifically, Figure 3 The solid-state imaging element 200 in can be applied to the imaging portion 12031. By applying the technology according to the present disclosure to the imaging portion 12031, distance measurement can be performed without adding a sensor, so that the power consumption and cost of the vehicle control system can be reduced.

[0273] It should be noted that the above-described embodiments describe examples for embodying the present technology, and that the matters in the embodiments correspond to the inventions specified in the claims. Similarly, the inventions specified in the claims correspond to the matters denoted by the same names as the inventions specified in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be embodied by making various modifications to the embodiments without departing from the gist of the present technology.

[0274] In addition, the processing procedures described in the above embodiments may be regarded as methods including these series of processes, and may be regarded as a program for causing a computer to execute these series of processes or a recording medium storing the program. As the recording medium, for example, a compact disc (CD), a mini disc (MD), a digital versatile disc (DVD), a memory card, a Blu-ray (registered trademark) disc, etc. may be used.

[0275] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may be provided.

[0276] It should be noted that the present technology can also have the following configurations.

[0277] (1) A sensing system comprising:

[0278] a light emitting portion that emits irradiation light in synchronization with a light emission control signal having a higher frequency than a predetermined vertical synchronization signal;

[0279] a predetermined number of pixels, each pixel generating a pulse signal through photoelectric conversion; and

[0280] The counting section counts the number of pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal.

[0281] (2) The sensing system according to (1), wherein the counting unit includes:

[0282] a first counter for counting the pulse signal in synchronization with the light emission control signal; and

[0283] The second counter counts the pulse signal in synchronization with the vertical synchronization signal.

[0284] (3) The sensing system according to (1), wherein

[0285] The counting unit includes:

[0286] a first counter that sequentially performs the following processing: counting the pulse signal in synchronization with the light emission control signal, and counting the pulse signal in synchronization with the vertical synchronization signal; and

[0287] The second counter counts the pulse signal in synchronization with the vertical synchronization signal.

[0288] (4) The sensing system according to (3), wherein

[0289] wherein a pixel array section in which a predetermined number of pixels are arranged is divided into a plurality of pixel blocks;

[0290] A counting section is arranged in each pixel block; and

[0291] The first counter counts a logical sum of pulse signals from corresponding pixels in the pixel block.

[0292] (5) The sensing system according to (4), wherein four of the first counters and five of the second counters are arranged in each pixel block.

[0293] (6) The sensing system according to (4), wherein eight first counters and one second counter are arranged in each pixel block.

[0294] (7) The sensing system according to (3), wherein

[0295] wherein a pixel array section in which a predetermined number of pixels are arranged is divided into a plurality of pixel blocks;

[0296] Each pixel block in the plurality of pixel blocks is divided into a plurality of regions;

[0297] The counting section is provided to correspond to each of the plurality of areas; and

[0298] The first counter counts a logical sum of pulse signals from respective pixels in a corresponding area.

[0299] (8) The sensing system according to (7), wherein

[0300] Nine pixels are arranged in each of the plurality of areas.

[0301] (9) The sensing system according to (7), wherein

[0302] Four pixels are arranged in each of the plurality of areas.

[0303] (10) The sensing system according to any one of (7) to (9), wherein

[0304] The four areas are arranged in a pixel block.

[0305] (11) The induction system according to any one of (7) to (9), wherein

[0306] The two areas are arranged in a pixel block.

[0307] (12) The induction system according to any one of (7) to (9), wherein

[0308] The first counter counts a logical sum of corresponding pulse signals of a set number of pixels among the pixels in the pixel block.

[0309] (13) The sensing system according to (1), wherein

[0310] The counting section includes a predetermined number of counters that sequentially perform processing of counting the pulse signal in synchronization with the light emission control signal and counting the pulse signal in synchronization with the vertical synchronization signal.

[0311] (14) The sensing system according to (13), wherein

[0312] The counting section includes nine of the counters.

[0313] (15) The sensing system according to (13), wherein

[0314] The counting section includes four counters.

[0315] (16) The sensing system according to any one of (13) to (15), further comprising:

[0316] The pixel driver provides an enable signal, in which each of the plurality of set values ​​is sequentially set to a phase difference with the light emitting control signal; wherein,

[0317] The counter provides a pulse signal in synchronization with the enable signal.

[0318] (17) A distance measurement system comprising:

[0319] a light emitting portion that emits irradiation light in synchronization with a light emission control signal having a higher frequency than a predetermined vertical synchronization signal;

[0320] A predetermined number of pixels, each pixel generating a pulse signal through photoelectric conversion;

[0321] a counting section that counts the number of pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; and

[0322] The distance measuring unit measures the distance to the object based on the count value of the counting unit.

[0323] (18) A sensing system comprising:

[0324] a light emitting unit that emits irradiation light based on a light emission control signal;

[0325] a plurality of pixels, each pixel generating a pulse signal through photoelectric conversion; and

[0326] The counting unit counts the number of pulse signals of the plurality of pixels; wherein,

[0327] The counting unit includes a plurality of counters and an output destination control circuit. The output destination control circuit is connected between the plurality of pixels and the plurality of counters, receives a plurality of pulse signals outputted by the plurality of pixels, and distributes the plurality of pulse signals to a plurality of arbitrary counters.

[0328] A plurality of pixels are provided in the first chip; and

[0329] The output control circuit and the counting section are provided in the second chip.

[0330] Reference Signs List

[0331] 100 Distance Measurement System

[0332] 105 Microlens

[0333] 110 light-emitting part

[0334] 120 Driver

[0335] 130 controller

[0336] 140 processors

[0337] 150 Application Processor

[0338] 200 solid-state imaging element

[0339] 201 pixel chip

[0340] 202 circuit chip

[0341] 210 pixel driver

[0342] 220 vertical scanning circuit

[0343] 230 pixel array unit

[0344] 240 column buffer

[0345] 250 signal processing circuit

[0346] 260 Output

[0347] 300 pixel blocks

[0348] 310, 321 to 328 pixels

[0349] 311 SPAD

[0350] 312 resistor

[0351] 313: Inverter

[0352] 330 Counting Department

[0353] 331 to 343, 411 to 414, 421, 431, 441 counters

[0354] Switches 351 to 363

[0355] 370 Output destination control circuit

[0356] 371 to 380 OR (Logical AND) Gates

[0357] 381 to 389 AND (logical product) gates

[0358] 391 to 399 selector

[0359] 410 0 degree area

[0360] 420 90 degree area

[0361] 430 180 degree area

[0362] 440 270 degree area

[0363] 12031 Imaging section.

Claims

1. A ranging system, comprising: a light emitting portion that emits irradiation light in synchronization with a light emission control signal having a higher frequency than a predetermined vertical synchronization signal; A predetermined number of pixels, each pixel generating a pulse signal through photoelectric conversion; as well as a counting section that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; a signal processing circuit for measuring a distance to an object based on a count value of the counting unit; a driver, generating the light-emitting control signal and providing the signal to the light-emitting portion; a controller that stops the driver when set to imaging mode and causes the driver to generate the light emission control signal when set to ranging distance; The counting unit includes: a first counter sequentially performing the following processing: counting the pulse signal in synchronization with the light emission control signal, and counting the pulse signal in synchronization with the vertical synchronization signal; as well as a second counter, configured to count the pulse signal in synchronization with the vertical synchronization signal; a pixel array section in which the predetermined number of pixels are arranged, and is divided into a plurality of pixel blocks; Each pixel block of the plurality of pixel blocks is divided into a plurality of regions; The counting section is provided to correspond to each of the plurality of areas; and The first counter counts a logical sum of the pulse signals from corresponding pixels in a corresponding area, The plurality of regions include a first region and a second region, In the first region, two or more first counters are provided for counting the logical sum in synchronization with a first enable signal having a phase difference of a specific value with the light emission control signal. In the second region, two or more first counters are provided for counting the logical sum in synchronization with a second enable signal having a phase difference different from the specific value. The signal processing circuit calculates a statistic of each count value of the first counter according to each phase difference, and measures the distance based on the statistic.

2. The ranging system according to claim 1, wherein: Nine pixels are arranged in each of the plurality of areas.

3. The ranging system according to claim 1, wherein: Four pixels are arranged in each of the plurality of areas.

4. The ranging system according to claim 1, wherein: Four areas are arranged in the pixel block.

5. The ranging system according to claim 1, wherein: Two areas are arranged in the pixel block.

6. A sensing system comprising: a light emitting section that emits irradiation light based on a light emission control signal having a higher frequency than a predetermined vertical synchronization signal; Multiple pixels, each pixel generates a pulse signal through photoelectric conversion; as well as A counting unit counts the number of the pulse signals of the plurality of pixels; wherein, a signal processing circuit for measuring a distance to an object based on a count value of the counting unit; a driver, generating the light-emitting control signal and providing the signal to the light-emitting portion; a controller, which stops the driver when set to an imaging mode, and causes the driver to generate the light-emitting control signal when set to a distance-measuring mode; The counting unit includes a plurality of counters and an output destination control circuit, wherein the output destination control circuit is connected between the plurality of pixels and the plurality of counters, receives a plurality of pulse signals output from the plurality of pixels, and distributes the plurality of pulse signals to a plurality of arbitrary counters; The plurality of pixels are provided in a first chip; and The output destination control circuit, the signal processing circuit, and the counting unit are provided in a second chip, The counting unit includes: a first counter that sequentially performs the following processing: counting the pulse signal in synchronization with the light emission control signal, and counting the pulse signal in synchronization with the vertical synchronization signal; and a second counter, configured to count the pulse signal in synchronization with the vertical synchronization signal; a pixel array section in which the plurality of pixels are arranged, and is divided into a plurality of pixel blocks; Each pixel block of the plurality of pixel blocks is divided into a plurality of regions; The counting section is provided to correspond to each of the plurality of areas; and The first counter counts a logical sum of the pulse signals from corresponding pixels in a corresponding area, The plurality of regions include a first region and a second region, In the first region, two or more first counters are provided for counting the logical sum in synchronization with a first enable signal having a phase difference of a specific value with the light emission control signal. In the second region, two or more first counters are provided for counting the logical sum in synchronization with a second enable signal having a phase difference different from the specific value. The signal processing circuit calculates a statistic of each count value of the first counter according to each phase difference, and measures the distance based on the statistic.

Images