Systems and methods for tuning capacitance of a quantum bit

Abstract

An analog computing system has a qubit provided with inductors positioned proximate to a Josephson junction of the qubit and inductors positioned distal to the Josephson junction of the qubit. As respective inductances of these inductors increase, these proximal inductors exhibit a capacitance decreasing behavior and these distal inductors exhibit a capacitance increasing behavior. The proximal and distal inductors can be tuned based on a predicted capacitance and a target capacitance of the qubit to homogenize the capacitance of the qubit across a range of programmable states. The inductors can be tuned to homogenize both capacitance and inductance.

Description

Technical Field

[0001] This disclosure generally relates to simulation calculations, and more specifically to the design and operation of devices for tuning the physical properties of quantum devices. Background Technology

[0002] Quantum devices

[0003] A quantum device is a structure in which quantum mechanical effects are observable. A quantum device includes a circuit in which current transport is dominated by quantum mechanical effects. Such a device includes a spintronic device in which electron spin is used as a resource, and a superconducting circuit. A superconducting circuit is a circuit that includes a superconducting device. A superconducting device is a device that includes a superconducting material. A superconducting material is a material that has no resistance below critical levels of current, magnetic field, and temperature. Both spin and superconductivity are quantum mechanical phenomena. Superconductivity is a physical phenomenon well known in the art at the time of filing this application. Quantum devices can be used in measuring instruments, computing machines, etc.

[0004] Quantum computing

[0005] Quantum computing and quantum information processing are active research areas and have defined many commercially viable products. A quantum computer is a system that directly uses at least one quantum mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The building blocks of a quantum computer are quantum binary numbers called qubits. Quantum computers promise to provide exponential speedups for certain classes of computational problems, such as those simulating quantum physics. Speedups useful for other classes of problems may also exist.

[0006] One model of quantum computing is adiabatic quantum computing. For example, adiabatic quantum computing can be well-suited for solving difficult optimization problems. Further details regarding adiabatic quantum computing systems, methods, and apparatus are described, for example, in U.S. Patents 7,135,701 and 7,418,283.

[0007] Quantum annealing

[0008] Quantum annealing is a computational method used to find the low-energy state of a system, preferably its ground state. Conceptually similar to classical simulated annealing, it relies on the fundamental principle that natural systems tend to lower energy states because these states are more stable. While classical annealing uses classical thermal fluctuations to guide the system to a lower energy state, quantum annealing can use quantum effects, such as quantum tunneling, as delocalization sources to reach the energy minimum more accurately and / or faster than classical annealing. Thermal effects and other noise may exist in quantum annealing. The final low-energy state may not be the global energy minimum.

[0009] Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally begins and maintains its ground state throughout the adiabatic evolution. Therefore, those skilled in the art will understand that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this application, any reference to quantum annealing is intended to include adiabatic quantum computing unless the context requires otherwise.

[0010] Superconducting qubits

[0011] A quantum processor can be a superconducting quantum processor that includes superconducting qubits. Wendin G. and Shumeiko V.S., “SUPERCONDUCTING QUANTUM CIRCUITS, QUBITS AND COMPUTING” (arXiv:cond-mat / 0508729v1, 2005), introduces the physics and operating principles of quantized superconducting circuits for quantum information processing.

[0012] coupling

[0013] Couplers can provide communication coupling between quantum devices in a quantum processor. For example, coupling can be between adjacent and / or non-adjacent qubits. Unless otherwise expressly indicated, as used herein and in the claims, the terms couple, couples, coupling, and variations of such terms mean direct or indirect communication coupling or communication between two or more components.

[0014] Characteristics of tuned qubits

[0015] Quantum devices, such as qubits and couplers, can handle various properties, such as flux, continuous current, inductance, and capacitance. These properties can affect the results of quantum computations performed by such qubits, and therefore it may be desirable to tune one or more of these properties to match the parameters of a given computation. U.S. Patent Nos. 8,536,566 and 9,152,923 and PCT application No. US2018 / 066613 provide example systems and methods for tuning qubit properties, including example qubits and couplers.

[0016] It is advantageous for qubits in analog computing systems (such as quantum processors) to possess the same (or approximately the same) properties, such as inductance and capacitance. This facilitates accurate mapping from the problem (e.g., represented as a Hamiltonian operator) to the physical analog processor. For this purpose, some analog processors include devices called L-tuners (e.g., as described in U.S. Patent No. 8,536,566) for tuning the inductance of the qubit. Adding a “C-tuner” for tuning the capacitance has proven challenging due to various factors, such as structural complexity, resulting bandwidth limitations, interference with the eigenstates of the flux qubit, operational flexibility, and / or other factors. Therefore, systems and methods for tuning the capacitance of qubits remain desirable.

[0017] The examples and limitations of the related technologies described above are intended to be illustrative and not exclusive. Further limitations in the related art will become apparent to those skilled in the art upon reading this specification and the accompanying drawings. Summary of the Invention

[0018] This disclosure provides an analog computing system including qubits. The qubit includes a qubit loop formed by a first superconducting current path and at least one Josephson junction interrupting the qubit loop. The at least one Josephson junction has a critical distance such that adding a lumped inductance along the qubit loop closer to the at least one Josephson junction than the critical distance reduces the qubit capacitance at the at least one Josephson junction, and adding the lumped inductance along the qubit loop farther from the at least one Josephson junction than the critical distance increases the qubit capacitance. The qubit further includes a plurality of inductors disposed along the qubit loop. Each of the plurality of inductors is tunable to provide tunable inductance. The plurality of inductors includes: one or more proximity inductors, each proximity inductor disposed along the qubit loop at a location less than the critical distance from the at least one Josephson junction; and one or more distance inductors, each distance distance along the qubit loop at a location greater than the critical distance from the at least one Josephson junction.

[0019] In some implementations, the analog computing system includes one or more couplers tunably coupled to the qubit loop. Each of the one or more couplers is tunable to provide a corresponding coupling strength with the qubit.

[0020] In some embodiments, the tunable inductance of each of the plurality of inductors is tunable within a corresponding inductance range and each of the one or more couplers has a corresponding coupler-sensed inductance range, each coupler-sensed inductance range including the difference between the states of the corresponding couplers of the at least one Josephson junction qubit inductance and the states of the corresponding couplers of the one or more couplers, and the sum of the tunable inductance ranges of the plurality of inductors is greater than each of the corresponding coupler-sensed inductance ranges.

[0021] In some embodiments, one of the plurality of inductors includes one or more inductor Josephson junctions that interrupt the qubit loop and are tunable to provide a corresponding tunable inductance range for that one of the plurality of inductors. In some embodiments, that one of the plurality of inductors includes one or more DC-SQUIDs that include the one or more inductor Josephson junctions. In some embodiments, that one of the plurality of inductors includes a plurality of DC-SQUIDs connected in series along the qubit loop.

[0022] In some embodiments, the sum of the tunable inductance ranges of the plurality of inductors is greater than the total coupler-sensed inductance range, which includes the difference between the inductance sensed by the first coupler and the inductance sensed by the second coupler. The first coupler-sensed inductance includes the qubit inductance in a first state, in which each of the one or more couplers is ferromagnetically coupled to the qubit, and the second coupler-sensed inductance includes the qubit inductance in a second state, in which each of the one or more couplers is antiferromagnetically coupled to the qubit.

[0023] In some implementations, the one or more near inductors are tunable together to reduce the capacitance of the qubit induced by the first coupler to within a first threshold of the target capacitance; and the one or more far inductors are tunable together to increase the capacitance of the qubit induced by the second coupler to within a second threshold of the target capacitance.

[0024] In some embodiments, the capacitance sensed by the first coupler includes the qubit capacitance in a third state, in which each of the one or more couplers that is closer to the at least one Josephson junction along the qubit loop than the critical distance, if present, is antiferromagnetically coupled to the qubit loop, and each of the one or more couplers that is farther away from the at least one Josephson junction along the qubit loop than the critical distance, if present, is ferromagnetically coupled to the qubit loop; and the capacitance sensed by the second coupler includes the qubit capacitance in a fourth state, in which each of the one or more couplers that is closer to the at least one Josephson junction along the qubit loop than the critical distance, if present, is ferromagnetically coupled to the qubit loop, and each of the one or more couplers that is farther away from the at least one Josephson junction along the qubit loop than the critical distance, if present, is antiferromagnetically coupled to the qubit loop.

[0025] In some implementations, for a predetermined target qubit inductance and a set of predetermined coupling strengths for the one or more couplers, the plurality of inductors can be tuned to provide a total tunable inductance for each of the first, second, third, and fourth states, thereby increasing the qubit inductance to within a third threshold of the predetermined target qubit inductance and at least one of the following occurs: increasing and decreasing the qubit capacitance to within a fourth threshold of the target capacitance.

[0026] In some embodiments, the qubit includes: a second qubit loop interrupted by the at least one Josephson junction; and at least one secondary inductor disposed along the second qubit loop. In some embodiments, the qubit loop and the second qubit loop partially overlap along a shared portion, and a shared inductor of the plurality of inductors is disposed along the shared portion. In some embodiments, the shared inductor includes one of the one or more proximity inductors.

[0027] In some embodiments, the at least one secondary inductor includes: one or more secondary near-field inductors, each secondary near-field inductor disposed along the second qubit loop at a location less than a second critical distance from the at least one Josephson junction; and one or more secondary far-field inductors, each secondary far-field inductor disposed along the second qubit loop at a location greater than the second critical distance from the at least one Josephson junction. In some embodiments, the plurality of inductors and the at least one secondary inductor collectively provide a common tunable inductance range at least twice the total inductance range induced by the coupler.

[0028] Various aspects of the present invention provide systems and methods for tuning the effective capacitance of a qubit in an analog computing system. The method is performed by a processor communicating with the analog computing system (e.g., by executing at least one of processor-executable instructions or data stored in at least one non-transitory processor-readable storage medium) and includes determining a predicted capacitance of the qubit, determining a target capacitance of the qubit, determining a total capacitance change ΔC based on the target capacitance and the predicted capacitance, and tuning a plurality of inductors. Each inductor is positioned along the qubit loop at a corresponding distance from one or more Josephson junctions of the qubit and is tuned to change the effective capacitance of the qubit based on the corresponding distance from the one or more Josephson junctions and the total capacitance change.

[0029] In some embodiments, the one or more Josephson junctions have a critical distance such that adding a lumped inductance along the qubit loop closer to the one or more Josephson junctions than the critical distance reduces the qubit capacitance at the one or more Josephson junctions, and adding the lumped inductance further away from the one or more Josephson junctions than the critical distance increases the qubit capacitance. In some embodiments, tuning a plurality of inductors includes: tuning a first inductor along the qubit loop closer to the one or more Josephson junctions than the critical distance to reduce the qubit capacitance; and tuning a second inductor along the qubit loop further away from the one or more Josephson junctions than the critical distance to increase the qubit capacitance.

[0030] In some implementations, tuning the plurality of inductors based on corresponding distances from the one or more Josephson junctions includes tuning the first inductor and the second inductor based on corresponding distances from the first inductor and the second inductor to points located along the qubit loop at the critical distance from the one or more Josephson junctions.

[0031] In some embodiments, the method includes: determining a predicted inductance of the qubit; determining a target inductance of the qubit; and determining a total inductance change ΔL based on the target inductance and the predicted inductance. In some embodiments, tuning the plurality of inductors to change the effective capacitance of the qubit includes tuning the plurality of inductors such that the sum of the corresponding plurality of tunable inductances of the plurality of inductors is within a threshold of the total inductance change ΔL, and tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC.

[0032] In some embodiments, tuning the plurality of inductors such that the sum of the plurality of tunable inductors is distributed among the plurality of inductors based on the total capacitance change ΔC includes: tuning the tunable inductance of the first inductor among the plurality of inductors to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning the tunable inductance of the second inductor among the plurality of inductors to increase the effective qubit capacitance and increase the effective qubit inductance.

[0033] In some implementations, tuning the plurality of inductors such that the sum of the plurality of tunable inductors is distributed among the plurality of inductors based on the total capacitance change ΔC includes: selecting a selected distribution from a plurality of candidate distributions of inductor tuning values ​​based on the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of tunable inductors based on the inductor tuning values ​​of the selected distribution.

[0034] In some implementations, each candidate distribution corresponds to a candidate capacitance change, and selecting the selected distribution includes selecting the selected distribution based on the difference between the candidate capacitance change and the total capacitance change ΔC.

[0035] In some implementations, tuning the plurality of tunable inductors based on the selected distribution includes interpolating interpolated inductor tuning values ​​for each of the plurality of inductors based on inductor tuning values ​​of the selected distribution and inductor tuning values ​​of another candidate distribution among the plurality of candidate distributions; and tuning the plurality of tunable inductors based on these interpolated inductor tuning values.

[0036] In some implementations, identifying the plurality of candidate distributions includes identifying the plurality of candidate distributions in a lookup table based on at least one of the total capacitance change ΔC and the total inductance change ΔL; and wherein another candidate distribution among the plurality of candidate distributions is close to the selected distribution in the lookup table.

[0037] In some implementations, identifying the plurality of candidate distributions of inductor tuning values ​​includes searching for a first set of inductor tuning values ​​for one of the first inductors and the second inductor along a first axis of a lookup table, and identifying a corresponding inductor tuning value for the other inductor of the first inductor and the second inductor for each of the first set of inductor tuning values ​​along a second axis of the lookup table, such that the sum of the first inductor tuning value and the second inductor tuning value is within a threshold of the total inductance change ΔL, and each inductor tuning value from the first set paired with the corresponding inductor tuning value of the other inductor of the first inductor and the second inductor includes a candidate distribution and corresponds to a predicted capacitance change.

[0038] In some implementations, selecting a chosen distribution from the plurality of candidate distributions includes selecting the candidate distribution among the plurality of candidate distributions that has the corresponding predicted capacitance change that is closest to the total capacitance change ΔC.

[0039] In some embodiments, tuning the plurality of inductors such that the sum of the plurality of tunable inductors is distributed among the plurality of inductors based on the total capacitance change ΔC includes: searching for the total capacitance change ΔC along a first axis of a lookup table; searching for the total inductance change ΔL along a second axis of the lookup table; identifying a candidate distribution of inductor tuning values ​​in the lookup table corresponding to the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of inductors based on the candidate distribution.

[0040] In some implementations, finding at least one of the total capacitance change ΔC and the total inductance change ΔL includes determining an entry along at least one of the first and second axes of the lookup table that approximates at least one of the total capacitance change ΔC and the total inductance change ΔL.

[0041] In some embodiments, tuning multiple inductors includes tuning a first inductor at a first distance along the qubit loop from the one or more Josephson junctions to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning a second inductor at a second distance along the qubit loop from the one or more Josephson junctions to increase the effective qubit capacitance and increase the effective qubit inductance, the second distance being greater than the first distance.

[0042] In some implementations, determining the predicted capacitance of the qubit includes determining the capacitive load induced by the coupler based on the coupling strength of one or more couplers coupled to the qubit.

[0043] In some implementations, tuning the plurality of inductors based on the total capacitance change to alter the effective capacitance of the qubit includes tuning the plurality of inductors to compensate for capacitive load induced by the coupler.

[0044] Aspects of the present invention provide a computing system comprising: at least one processor communicating with an analog processor having at least one qubit; and at least one non-transitory processor-readable storage medium storing at least one of processor-executable instructions or data, which, when executed by the at least one processor, cause the at least one processor to perform actions including: determining a predicted capacitance of the qubit; determining a target capacitance of the qubit; determining a total capacitance change ΔC based on the target capacitance and the predicted capacitance; and causing the analog processor to tune a plurality of inductors to change the effective capacitance of the qubit based on corresponding distances from one or more Josephson junctions of the qubit and the total capacitance change, each inductor being disposed along the qubit loop at a corresponding distance from the one or more Josephson junctions.

[0045] In some implementations, these actions may further include: determining a predicted inductance of the qubit; determining a target inductance of the qubit; and determining a total inductance change ΔL based on the target inductance and the predicted inductance. Tuning the plurality of inductors to change the effective capacitance of the qubit may include tuning the plurality of inductors such that the sum of the corresponding plurality of tunable inductances of the plurality of inductors is within a threshold value of the total inductance change ΔL, and tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC.

[0046] In some implementations, tuning the plurality of inductors based on corresponding distances from the one or more Josephson junctions may include tuning the first inductor and the second inductor based on corresponding distances from points along the qubit loop located at critical distances from the one or more Josephson junctions. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC may include: tuning the tunable inductance of the first inductor to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning the tunable inductance of the second inductor to increase the effective qubit capacitance and increase the effective qubit inductance.

[0047] In some implementations, tuning the plurality of inductors such that the sum of the plurality of tunable inductors is distributed among the plurality of inductors based on the total capacitance change ΔC includes: selecting a selected distribution from a plurality of candidate distributions of inductor tuning values ​​based on the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of tunable inductors based on the inductor tuning values ​​of the selected distribution. Selecting the selected distribution may include selecting the selected distribution based on the difference between the candidate capacitance change corresponding to the selected distribution and the total capacitance change ΔC.

[0048] In some implementations, tuning the plurality of tunable inductors based on the selected distribution may include interpolating interpolated inductor tuning values ​​for each of the plurality of inductors based on inductor tuning values ​​of the selected distribution and inductor tuning values ​​of another candidate distribution among the plurality of candidate distributions; and tuning the plurality of tunable inductors based on these interpolated inductor tuning values. Identifying the plurality of candidate distributions may include identifying the plurality of candidate distributions in a lookup table based on at least one of the total capacitance change ΔC and the total inductance change ΔL; and wherein another candidate distribution among the plurality of candidate distributions is close to the selected distribution in the lookup table. The plurality of candidate distributions for identifying inductor tuning values ​​may include searching for a first set of inductor tuning values ​​for one of the first inductors and the second inductor along a first axis of a lookup table, and identifying a corresponding inductor tuning value for the other inductor of the first inductor and the second inductor for each of the first set of inductor tuning values ​​along a second axis of the lookup table, such that the sum of the first inductor tuning value and the second inductor tuning value is within a threshold of the total inductance change ΔL, and each inductor tuning value from the first set paired with the corresponding inductor tuning value of the other inductor of the first inductor and the second inductor includes a candidate distribution and corresponds to a predicted capacitance change.

[0049] In some implementations, selecting a chosen distribution from the plurality of candidate distributions may include selecting a candidate distribution among the plurality of candidate distributions that has a corresponding predicted capacitance change that is closest to the total capacitance change ΔC. Tuning the plurality of inductors such that the sum of the plurality of tunable inductors is distributed among the plurality of inductors based on the total capacitance change ΔC may include: searching for the total capacitance change ΔC along a first axis of a lookup table; searching for the total inductance change ΔL along a second axis of the lookup table; identifying candidate distributions in the lookup table for inductor tuning values ​​corresponding to the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of inductors based on the candidate distributions. Searching for at least one of the total capacitance change ΔC and the total inductance change ΔL may include determining an entry along at least one of the first and second axes of the lookup table that approximates at least one of the total capacitance change ΔC and the total inductance change ΔL.

[0050] In some implementations, tuning multiple inductors may include: tuning a first inductor at a first distance along the qubit loop from the one or more Josephson junctions to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning a second inductor at a second distance along the qubit loop from the one or more Josephson junctions to increase the effective qubit capacitance and increase the effective qubit inductance, the second distance being greater than the first distance. Determining the predicted capacitance of the qubit may include determining the capacitive load induced by the couplers based on one or more coupling strengths of one or more couplers coupled to the qubit. Tuning the multiple inductors based on the total capacitance change to change the effective capacitance of the qubit may include tuning the multiple inductors to compensate for the capacitive load induced by the couplers.

[0051] This disclosure provides an analog computing system including qubits, the qubits including a Josephson junction, a first qubit loop formed by a first superconducting current path, and a second qubit loop formed by a second superconducting current path, wherein the first qubit loop and the second qubit loop are electrically connected in parallel across the Josephson junction.

[0052] In some embodiments, the analog computing system may further include a first flux bias line communicating with the first qubit loop and a second flux bias line communicating with the second qubit loop, the first flux bias line receiving signals independently of the second flux bias line. The second qubit loop may include a first portion communicating with the Josephson junction and a second portion spaced apart from the Josephson junction, the first portion and the second portion being separated by a crossover, wherein the current in the second qubit loop travels in a first rotational direction in the first portion and in a second rotational direction opposite to the first rotational direction in the second portion.

[0053] In some embodiments, the Josephson junction may include one of a composite Josephson junction or a composite-composite Josephson junction. The first qubit loop and the second qubit loop may partially overlap along a shared portion. The analog computing system may further include a coupler tunably coupled to one of the first qubit loop and the second qubit loop. The analog computing system may further include a second qubit coupled to the coupler. The first qubit loop and the second qubit loop may be symmetrical about the axis of the Josephson junction, the axis of the Josephson junction passing through a first connection between the first qubit loop and the second qubit loop and the Josephson junction, and a second connection between the first qubit loop and the second qubit loop and the Josephson junction.

[0054] In some embodiments, the analog computing system may further include one or more additional qubit loops electrically connected in parallel across the Josephson junction. The analog computing system may also further include a plurality of inductors disposed along each of the first and second qubit loops, each of the plurality of inductors being tunable to provide a corresponding tunable inductance.

[0055] In other respects, the features described above can be combined in any reasonable combination as those skilled in the art will recognize. Attached Figure Description

[0056] In the accompanying drawings, the same reference numerals identify similar elements or actions. The dimensions and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the readability of the drawings. Furthermore, the specific shapes of the drawn elements are not necessarily intended to convey any information about the actual shape of the particular element and may be chosen simply for ease of identification in the drawings.

[0057] Figure 1A This is a schematic diagram of existing quantum bits.

[0058] Figure 1B This is a schematic diagram of a prior art qubit with an inductive tuner.

[0059] Figure 2 This is a schematic diagram of an example analog computing system including qubits having inductors positioned at different distances relative to one or more Josephson junctions along the qubit loop.

[0060] Figure 3 This is a schematic diagram of an example analog computing system including qubits having series-connected DC-SQUID inductors positioned at different distances relative to one or more Josephson junctions along the qubit loop. It also shows... Figure 2 Various other devices not shown.

[0061] Figure 4A This is a schematic diagram of an example simulated computing system including qubits in two-qubit loops, each loop being essentially similar to... Figure 3 An example of a quantum bit loop.

[0062] Figure 4B Is with Figure 4A The example simulation system is a schematic diagram similar to the example simulation system, except that the two near inductors are replaced with a shared inductor.

[0063] Figure 5 It is used for tuning analog computing systems (e.g.) Figure 2 A flowchart of a method for achieving effective capacitance of an example quantum bit in an analog computing system.

[0064] Figure 6 This is a flowchart of a method for distributing inductance between a near-inductor and a far-inductor, for example, as... Figure 5 It is part of the method.

[0065] Figure 7 This is a schematic diagram of an example hybrid computing system in which the techniques described herein can be implemented.

[0066] Figure 8 This is a schematic diagram of an example qubit with two loops.

[0067] Figure 9A This is a schematic diagram of an example qubit with two asymmetric loops.

[0068] Figure 9B This is a schematic diagram of an example qubit with three loops.

[0069] Figure 10 This is a schematic diagram of an example qubit with two loops and a twisted section.

[0070] Figure 11 This is a schematic diagram of an example qubit with two loops, a twisted section, and other devices. Detailed Implementation

[0071] In the following description, certain specific details are set forth to provide a comprehensive understanding of the various embodiments disclosed. However, those skilled in the art will recognize that these embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communication networks have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0072] Unless the context otherwise requires, throughout this specification and the appended claims, the word “comprising” is synonymous with “including” and is inclusive or open-ended (i.e., does not exclude additional, unlisted elements or methodological actions).

[0073] Throughout this specification, references to "one implementation" or "an implementation" mean that a particular feature, structure, or characteristic described in connection with that implementation is included in at least one implementation. Therefore, the phrases "in one implementation" or "in an implementation" appearing in various places throughout this specification do not necessarily all refer to the same implementation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more implementations in any suitable manner.

[0074] As used in this specification and the appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” include the plural objects referred to. It should also be noted that, unless the context clearly indicates otherwise, the term “or” generally includes “and / or”.

[0075] The subheadings and summaries provided in this disclosure are for convenience only and are not intended to explain the scope or meaning of the embodiments.

[0076] L tuner

[0077] Figure 1A This is a schematic diagram of a superconducting flux qubit 100a. Qubit 100a includes qubit loops 102 (e.g., superconducting material loops) interrupted by one or more Josephson junctions. Figure 1A In an exemplary embodiment, the qubit loop 102 is interrupted by a composite Josephson junction 104 (also referred to as “CJJ”) including current paths 131, 132, each of which is interrupted by a corresponding Josephson junction 111, 112.

[0078] Figure 1B This is a schematic diagram of a superconducting flux qubit 100b. Essentially similar to qubit 100a, qubit 100b includes a qubit loop 102 and a composite Josephson junction 104. Qubit 100b further includes an inductor tuner 140 (or “L-tuner”) that provides tunable inductance to qubit 100b. For example, inductor tuner 140 may include a CJJ connected in series with the composite Josephson junction 104 in qubit loop 102. As described, for example, in U.S. Patent No. 9,152,923, inductor tuner 140 can be tuned using programmable interface 142, for example, by inductively and / or currently coupling a control signal to inductor tuner 140 and thus tuning the Josephson inductance of the composite Josephson junction 140, thereby tuning the Josephson inductance of qubit 100b.

[0079] Quantum bits 100a and 100b can be inductively or otherwise coupled to other devices. For example, in some embodiments, qubits 100a and 100b are inductively coupled to other qubits via an inter-qubit coupler (not shown). Such coupling can affect the electromagnetic properties of qubits 100a and 100b. For example, the capacitance of qubit 100b can be a complex function of both the coupler setting and the L-tuner setting. Although this effect has been negligible in practice in the past, experiments have shown that the effect increases as quantum processors scale up. For example, in some embodiments, both the tuning coupler and the L-tuner can cause a change of approximately 10 fF in the qubit capacitance, potentially leading to calibration errors, coupler-related desynchronization of qubit dynamics, and other difficult-to-solve behaviors.

[0080] Split L-tuner

[0081] For example, the effect of the lumped inductance contributed by the L tuner on the capacitance varies not only with the size of the inductance, but also with the location of the lumped inductance along the qubit loop relative to one or more Josephson junctions that form part of the qubit. For instance, a qubit series-coupled to (and positioned close to) one or more Josephson junctions and possessing an inductance L... 近 An inductor can produce an effective qubit capacitance modeled as follows:

[0082]

[0083] Among them, L Q =L U ×L, C Q =C U ×L, where L is the length of the qubit loop. U It is the inherent inductance per unit length of the quantum bit loop, and C U It is the inherent capacitance per unit length of the qubit loop. It is located further away from one or more Josephson junctions (e.g., at opposite ends of the qubit loop that form part of the qubit) and has an inductance L. 远 An inductor can generate an effective qubit capacitance C measured at one or more Josephson junctions. 有效 The capacitance of this effective qubit can be modeled as follows:

[0084]

[0085] When L 近 =L 远 When C = 0, both models yield C. 有效 =C Q / 3, this is the expected capacitance of the short-circuit loop (the 1 / 3 factor is caused by the input impedance). However, in L 近 When C > 0, the obtained C 有效 It will be less than expected C Q / 3. In other words, increasing the inductance of the near-inductor leads to a reduction in the effective qubit capacitance. Therefore, the near-inductor can be considered as preventing a portion of the inherent capacitance of the superconducting loop from being observed at one or more Josephson junctions. However, the far-inductor may have the opposite effect; C 有效 Tend to follow L 远 Increases as it increases.

[0086] It should be noted that if L 近 If the capacitance reduction behavior of the near-inductor is large enough, other dynamics may dominate, which could potentially lead to an increase in the effective qubit capacitance C. 有效 The increase in capacitance is significant. However, it has been experimentally determined that the capacitance reduction behavior of near-inductors may far exceed the typical programmable range of properly positioned / scaled near-inductors. (In this paper, the “scale” of an inductor refers to these structural features that determine the amount of inductance the inductor can contribute to qubit 201. For example, the scale of example inductor 206 can be determined at least in part by the size of the Josephson junction it constitutes, where a smaller Josephson junction (e.g., with a smaller area) typically corresponds to more inductance and therefore a larger scale. For some inductors, such as helical inductors, a larger area typically corresponds to more inductance and therefore a larger scale.)

[0087] This disclosure provides various aspects of analog computing systems including qubits, which advantageously incorporate multiple tunable inductors, including those exhibiting the characteristics described in the above reference L. 近 The inductors described herein and in the claims are referred to as "near-inductors" and exhibit the capacitance reduction behavior described above. 远 The described capacitance-increasing behavior of inductors (these inductors are referred to herein and in the claims as "far inductors") is described. Near and far inductors can be independently tuned to provide (or at least approximate) homogeneous capacitance across a series of programmable states of quantum bits. In some embodiments, inductors are tuned to provide both (or at least approximate) homogeneous capacitance and homogeneous inductance.

[0088] Figure 2 An example analog computing system 200 is shown, comprising a qubit 201 having a qubit loop 202 and one or more Josephson junctions 204 (in the depicted exemplary embodiment, the one or more Josephson junctions 204 include CJJs). A proximity inductor 206 interrupts the qubit loop 202 and is tunable to provide a corresponding tunable inductance L. 近The remote inductor 208 interrupts the quantum bit loop 202 and is tunable to provide a corresponding tunable inductor L. 远 (In some embodiments, one, some, or all of the inductors 206, 208 are inductively coupled to the quantum bit loop 202.) Figure 2 In the exemplary embodiments depicted, the analog computing system 200 further includes a coupler 222 communicatively coupled to the qubit loop 202. Various devices of the analog computing system 200 can be programmed via one or more programmable interfaces; in the exemplary embodiments depicted, one or more Josephson junctions 204, near-field inductors 206, far-field inductors 208, and couplers 222 can be programmed via programmable interfaces 220a, 220b, 220c, and 220d, respectively. Although Figure 2 The exemplary implementation shows a near inductor 206 and a far inductor 208, but it should be understood in light of the disclosure presented herein that multiple near and far inductors may be provided without departing from the scope of this disclosure.

[0089] Inductors 206 and 208 may include any tunable inductor. In some embodiments, at least one of inductors 206 and 208 includes an L-tuner, such as that described in U.S. Patent No. 8,536,566, and may include, for example, one or more Josephson junctions arranged as one or more DC-SQUIDs. In the exemplary embodiments depicted, each inductor 206 and 208 includes a DC-SQUID having two Josephson junctions connected in parallel and tunable via corresponding programming interfaces 220b and 220c. Alternatively or additionally, inductors 206 and 208 may include other lumped inductance sources, such as quantum flux parameterizers or mutual inductors inductively coupled to a qubit loop. Inductors 206 and 208 may have the same or different structures; for example, inductor 206 may include a single DC-SQUID and inductor 208 may include two DC-SQUIDs connected in series. Figure 3 Inductor 308 is an example of the latter.

[0090] Inductors 206 and 208 are tunable (e.g., via corresponding programmable interfaces 220b and 220c) to provide a corresponding inductance L within the tunable inductance range. 近 and L 远 For example, if inductor 206 is tunable to provide L from as low as 0fF to as high as 10fF. 近Therefore, the tunable inductance range of inductor 206 is referred to as 10fF. These figures do not include any non-tunable parasitic / baseline inductance; for example, continuing the previous example, if inductor 206 also provides a parasitic inductance of 2fF, and thus provides an inductance between 2fF and 12fF depending on its tuning, the tunable inductance range of inductor 206 is still referred to as 10fF. Inductors 206 and 208 may have the same or different tunable inductance ranges.

[0091] The near-field inductor 206 and the far-field inductor 208 are distinguished by their positions relative to one or more Josephson junctions 204 of the qubit 201. As the near-field inductor 206 is positioned closer to one or more Josephson junctions 204 along the qubit loop 202, the near-field inductor 206 will tend to reduce capacitance to a greater extent (for L). 近 As the far inductor 208 is positioned further away from one or more Josephson junctions 204 along the qubit loop 202, the far inductor 208 will tend to increase capacitance to a greater extent (for L). 远 (Given increase). Inductors closer to one or more Josephson junctions than the critical distance 212 will generally behave as near inductors 206 (i.e., reduced capacitance), and inductors farther from one or more Josephson junctions than the critical distance 212 will generally behave as far inductors 208.

[0092] Therefore, it can be deduced that a critical point 210 is located along the qubit loop 202 at a critical distance 212 from one or more Josephson junctions 204. Critical point 210 distinguishes between near-inductor and far-inductor types, such that inductors between the one or more Josephson junctions 204 and the critical point behave as near-inductors, and inductors along the qubit loop 202 that do not contain the one or more Josephson junctions 204 (e.g., those opposite to the one or more Josephson junctions) between the critical point 210 behave as far-inductors. The effect of an inductor closer to the critical point on the qubit capacitance will tend to be less pronounced than that of an inductor farther from the critical point (for a given change in inductance). This scaling of capacitance increase or decrease behavior is not necessarily symmetrical between near-inductors and far-inductors (e.g., a near-inductor may tend to reduce the qubit capacitance by a smaller amount than a far-inductor, even if both near-inductors and far-inductors have the same inductance and distance from the critical point 210). Although it is not necessary to clearly identify the location of the critical point 210 in at least some embodiments, in some embodiments the inductors 206, 208 (and / or other devices of the system 200) are positioned relative to the critical point 210 to determine the relationship between their inductance and their effect on the capacitance of the qubit.

[0093] Inductors 206 and 208 can be tuned to compensate for capacitance and / or inductance (so-called capacitive and / or inductive loads) contributed to qubit 201 by various devices. For example, coupler 222 can sense capacitive and inductive loads in qubit 201, and inductors 206 and 208 can be tuned to compensate for one or both such loads. In some embodiments, inductors 206 and 208 are positioned and operable to provide a tunable inductance range such that inductors 206 and 208 can homogenize qubit capacitance and / or inductance across multiple states of qubit 201.

[0094] For example, the analog computing system 200 may be operable to place the qubit 201 in a maximum inductance state by setting all couplers 222 to be ferromagnetically coupled to the qubit loop 202. For example, if all couplers 222 are programmable to provide a range of coupling strengths expressed in the range [-1, 1], where negative values ​​are ferromagnetic and positive values ​​are antiferromagnetic, then the maximum inductance state may include a state in which all couplers 222 are programmed to provide a coupling strength of -1. Continuing the example above, the analog computing system 200 may be able to place the qubit 201 in a minimum inductance state by setting all couplers 222 to be antiferromagnetically coupled to the qubit loop 202 (e.g., corresponding to a coupling strength of 1).

[0095] In some embodiments, the difference between the qubit inductance in the maximum inductance state and the qubit inductance in the minimum inductance state is no greater than the sum of the tunable inductance ranges of inductors 206 and 208. That is, tunable inductors 206 and 208 are collectively tunable to provide a tunable inductance range sufficient to homogenize the qubit inductance in the minimum and maximum inductance states. For example, consider the following states of an exemplary embodiment of qubit 201:

[0096] state Device setup Quantum bit inductor Minimum Inductance All couplers are set to antiferromagnetic coupling. 100pH Maximum Inductance All couplers are set to ferromagnetic coupling. 200pH

[0097] The difference in qubit inductance between the minimum and maximum inductance states is 100 pH, referred to herein as the target inductance range. In some embodiments, inductors 206 and 208 provide a common tunable inductance range of at least 100 pH. For example, inductor 206 may provide a tunable inductance range of 40 pH, and inductor 208 may provide a tunable inductance range of 60 pH. In some embodiments, inductors 206 and 208 provide a common tunable inductance range greater than the target inductance range (e.g., exceeding 100 pH in the above example), for example, to provide tolerance for manufacturing variations.

[0098] Furthermore, or alternatively, inductors 206, 208 can be tunable to homogenize the capacitance between the maximum and minimum capacitance states of qubit 201. For example, analog computing system 200 can be operable to place qubit 201 in the maximum capacitance state by configuring all couplers 222 within a critical distance 212 of one or more Josephson junctions 204 to be antiferromagnetically coupled to qubit loop 202 (in this case, couplers 222 within the critical distance 212 reduce inductance and increase capacitance because these couplers are in the near-inductor region of qubit loop 202) and configuring all couplers 222 farther from one or more Josephson junctions 204 than the critical distance 212 to be ferromagnetically coupled to qubit loop 202 (in this case, couplers 222 farther from the critical distance 212 increase both inductance and capacitance because these couplers are in the far-inductor region of qubit loop 202). For example, consider the following states of an exemplary embodiment of qubit 201:

[0099]

[0100] In some implementations, inductors 206 and 208 are tunable to homogenize the qubit capacitance between the maximum and minimum capacitance states, for example, by adjusting the qubit capacitance as needed to a target capacitance. For instance, inductors 206 and 208 may be tunable to increase the qubit capacitance of qubit 201 from the minimum capacitance state to within a threshold of the target capacitance and to decrease the qubit capacitance from the maximum capacitance state to within that threshold. (These two thresholds may be the same or different from each other.)

[0101] For example, if the target capacitance of the analog computing system 200 is 150 fF, the near inductor (e.g., inductor 206) can be tunable to reduce the capacitance by at least 50 fF (to address the maximum capacitance case) and the far inductor can be tunable to increase the capacitance by at least 50 fF (to address the minimum capacitance case).

[0102] Although the above discussion pertains to the state sensed by the coupler (which is, in many embodiments, the primary source of varying inductive and capacitive loads), the minimum and maximum inductive and capacitive states can be determined based on the programmable states of any device contributing inductive and / or capacitive loads to the qubit 201. Such devices include, for example, a quantum flux parameterizer and mutual inductance (e.g., a flux biasing device) coupled to the qubit 201.

[0103] In some implementations, inductors 206, 208 are tunable to homogenize both the qubit inductance and qubit capacitance across each of the four limiting states: minimum inductance, maximum inductance, minimum capacitance, and maximum capacitance. The relationship between inductance and capacitance is not always linear, so in most cases, these constraints on both inductance and capacitance can be expected to substantially affect the parameters of inductors 206, 208. However, since the four limiting states define the extrema in the state space of qubit 201, it is anticipated that in at least some implementations, inductors 206, 208 tunable to homogenize all four limiting states across both inductance and capacitance will also be tunable to homogenize all programmable states of system 200 (or more specifically, any programmable state of a device that varies between the four limiting states). For example, consider the following states of an exemplary implementation of qubit 201:

[0104]

[0105] In such an implementation, the near inductor 206 and the far inductor 208 must be positioned and provided with tunable inductance ranges that, once the inductors are properly tuned, allow each of the four extreme states to have (approximately within a threshold) the same inductance and capacitance.

[0106] For example, suppose the analog computing system has a target inductance of 220 pH and a target capacitance of 160 fF. Then, for an exemplary implementation of a qubit 401 with inductors 206, 208 in a given location, the inductance and capacitance may be homogenized across various programmed states (sometimes referred to herein as “scenes”) of the analog system 200, as follows:

[0107] state Quantum bit inductor Quantum bit capacitor <![CDATA[L 近 ]]> <![CDATA[L 远 ]]> Minimum Inductance 220pH 160fF 40pH 80pH Maximum Inductance 220pH 160fF 0pH 20pH Minimum Capacitance 220pH 160fF 80pH 20pH Maximum capacitance 220pH 160fF 40pH 0pH

[0108] Here, the qubit capacitance column does not include the capacitance of one or more Josephson junction 204s, L 近 It is the tuned inductor of near-inductor 206, and L 远 It is the tuned inductor of inductor 208. This example scenario means L 近 and L 远 Each of them requires an 80pH tunable inductance range.

[0109] In some implementations, the near inductor 206 and the far inductor 208 provide a total tunable inductance range substantially the same as the total inductance range of a single L tuner (i.e., the sum of their tunable inductance ranges), for example, as described in U.S. Patent No. 8,536,566. For example, if a single L tuner would require a tunable inductance range of 50 pH, the near inductor 206 and the far inductor 208 may together provide a tunable inductance range of 50 pH. This tunable inductance range may be distributed between inductors 206 and 208 in any suitable manner (e.g., the tunable inductance range of inductor 206 is 20 pH and the tunable inductance range of inductor 208 is 30 pH). The distribution of the tunable inductance range and the selection of the positions of inductors 206 and 208 are intricate. For example, inductors with a smaller tunable inductance range may need to be positioned further away from the critical point 210 to provide sufficient capacitance reduction / increase.

[0110] Various arrangements of inductors 206 and 208 can satisfy these conditions. Different arrangements can be compared (e.g., through simulation), and the choice of a particular arrangement may be influenced by factors such as available space on the processor, proximity to other devices, manufacturing tolerances, and / or other factors. Simulation can be aided by adding a constraint that for each scenario, there exists a fixed total inductance value L. 总 This makes L 总 =L 近 +L 远 (L) 总 It can change between different scenarios. 总 It can be determined based on a single L tuner implementation, as described above; therefore, the scope of the simulation can be reduced to exploring different combinations of the tunable inductance range distribution between inductors 206 and 208 and the placement of inductors 206 and 208.

[0111] In some implementations, system 200 includes more than one proximity inductor 206 and / or more than one distance inductor 208 (e.g., by providing secondary proximity inductors and / or distance inductors). The common proximity inductor 206 can then collectively provide a tunable inductance L. 近 And the corresponding tunable inductance range; various placements of the near inductor 206 will then determine the common effect of the near inductor 206 on the qubit capacitance. Similarly, the common far inductor 208 can then jointly provide the tunable inductance L. 远 And the corresponding tunable inductance range; various placements of the remote inductor 208 will then determine the common effect of the remote inductor 208 on the quantum bit capacitance.

[0112] Figure 2 It was simplified for ease of display.

[0113] Figure 3 A more complex example analog computing system 300 is shown, including a qubit 301 having a qubit loop 302 and one or more Josephson junctions 304. In the depicted exemplary embodiment, the one or more Josephson junctions 304 include a compound-compound Josephson junction or CCJJ, which comprises two compound Josephson junctions. The near-field inductor 306 and the far-field inductor 308 each include two DC-SQUIDs connected in series and each provides a tunable inductance L. 近 and L 远 In at least some embodiments, the combined characteristics of one or more Josephson junctions 304 and inductors 306, 308 can allow relative to Figure 2 A simpler device allows for more precise tuning within a programmable range.

[0114] System 300 also provides multiple couplers that can be coupled to qubit 301, including a far coupler 322 and a near coupler 324. The far coupler 322 is positioned along the qubit loop 302 at a distance greater than a critical distance from one or more Josephson junctions 304 (i.e., on the far side of the critical point 310), and the near coupler 324 is positioned at a distance less than a critical distance from one or more Josephson junctions 304 (i.e., on the near side of the critical point 310). Therefore, couplers 322 and 324 will tend to have different effects on the qubit capacitance as their inductive load on qubit 301 changes.

[0115] In embodiments where inductors 306 and 308 are positioned and appropriately sized to compensate for such inductive and / or capacitive loads, the location and / or size of one or both of inductors 306 and 308 may be influenced by the arrangement of couplers 322 and 324. For example, in some embodiments, in the maximum capacitance scenario where the near coupler 324 is antiferromagnetically coupled to the qubit 301 and the far coupler 322 is ferromagnetically coupled to the qubit 301 (e.g., as described above), inductors 306 and 308 can be positioned and / or scaled to compensate for capacitance, and vice versa for the minimum capacitance scenario.

[0116] One or more Josephson junctions 304, inductors 306, 308, and couplers 322, 324 are programmable via programmable interfaces 320a, 320b, 320c, 320d, 320e, respectively. System 300 further provides exemplary other means, such as a quantum flux parameterizer 330 that interrupts the qubit loop 302 and a programmable flux bias 332 that can be coupled to qubit 301. Such other means can be used to interact with qubit 301 (e.g., to read out the state of the qubit and / or program the qubit with relevant parameters of the problem Hamiltonian operator) and can contribute capacitive and / or inductive loads to qubit 301. In some embodiments, inductors 306, 308 are positioned and / or scaled to compensate for the inductive and / or capacitive loads contributed by such other means (e.g., to compensate for loads contributed by operating such other means to increase or decrease inductive or capacitive loads as appropriate in various scenarios described elsewhere herein).

[0117] The system disclosed in this article is not limited to a single-qubit loop implementation. Figure 4A An example analog computing system 400 is shown, comprising a qubit 401 having multiple qubit loops 402a, 402b interrupted by one or more Josephson junctions 404 shared between qubit loops 402a, 402b. (The qubit loops 402a, 402b may partially overlap along a shared portion 440, e.g., as shown in the diagram.) Figure 4A As shown in the illustration. In at least the exemplary embodiments described, each qubit loop 402a, 402b may be coupled to and / or include a device substantially similar to the qubit loops of systems 200, 300.

[0118] For example, in the depicted embodiment, qubit loop 402a is interrupted by a near inductor 406a and a far inductor 408a (located on opposite sides of the critical point 410a) and is communicatively coupled to a plurality of couplers 422a, 424a, 426a. Qubit loop 402a may be further coupled to and / or include other devices, such as a quantum flux parameterizer 430a and / or a flux biaser 432a. Qubit loop 402b may be coupled to and / or include similar or different devices; in the depicted exemplary embodiment, qubit loop 402b is substantially similar to qubit loop 402a and is interrupted by a near inductor 406b and a far inductor 408b (located on opposite sides of the critical point 410b) and is coupled to a plurality of couplers 422b, 424b, 426b. The qubit loop 402b can be further coupled to and / or include other devices, such as the quantum flux parameter 430b and / or the flux bias 432b.

[0119] In some embodiments, qubit loops 402a, 402b have critical points 410a, 410b located at different critical distances from one or more Josephson junctions 404. For example, qubit loops 402a, 402b may be different (e.g., these qubit loops are made of different materials, have an asymmetric layout, and / or may be asymmetrically coupled to other devices in system 400a). Therefore, critical point 410b may be referred to as being located along qubit loop 402b at a second critical distance from one or more Josephson junctions, which may be the same as or different from the critical distance of critical point 410a.

[0120] In some embodiments, each qubit loop 402a, 402b includes at least one near-field inductor 406a and at least one far-field inductor 408a, thereby allowing independent compensation of inductive and / or capacitive loads in each loop. In some embodiments, qubit loops 402a, 402b share at least one near-field inductor 406a and / or far-field inductor 408a. For example, as in Figure 4B As described in the exemplary system 400b, a shared proximity inductor 406 may be positioned along a shared portion 440. In some embodiments, the shared proximity inductor 406 provides a larger range of tunable inductance than any of the proximity inductors 406a, 406b of other similar systems 400 to compensate for inductance across both qubit loops 402a, 402b. A possible advantage of such an arrangement is space saving; in addition to reducing the minimum number of inductors required (from one inductor on each flank to one inductor per qubit), the shared inductor 406 can also be physically smaller itself (e.g., by providing a DC-SQUID with a smaller Josephson junction, since smaller Josephson junctions typically provide larger inductance than larger Josephson junctions). To maintain Figure 4B The readability of this difference in size is not described.

[0121] In some implementations, the common tunable range of the near-field inductors 406a, 406b and far-field inductors 408a, 408b of the qubits 401 having multiple loops 402a, 402b is larger than the amount indicated by the inductance difference between the maximum and minimum inductance states by a tolerance (e.g., 20 pH). This tolerance can be large enough to allow tuning of the near-field inductors 406a, 406b and far-field inductors 408a, 408b to compensate for variations between the flanks caused by manufacturing defects, design differences, and / or other asymmetries. This tolerance can be further increased to account for differences between the qubits, for example, as described elsewhere herein.

[0122] Tuning split-type L tuner

[0123] Figure 5 This is a flowchart of a method 500 for tuning the effective capacitance of qubits (e.g., qubits 201, 301, or 401 of systems 200, 300, or 400, respectively) in an analog computing system. The method is executed by one or more processors (e.g., classical processors) communicating with the analog computing system.

[0124] At position 502, one or more processors determine the predicted capacitance of the qubit based on a problem to be performed by the analog computing system, denoted as C. 预测 For example, if a given problem is transformed into a Hamiltonian operator to be encoded into an analog computing system (sometimes called the process of "embedding"), then one or more processors can determine the C of the qubit by applying the portion of the Hamiltonian operator relevant to that qubit (e.g., parameters corresponding to the coupling strength of the coupler that can be coupled to the qubit) to a physical model of the qubit. 预测 For example, for each coupler, one or more processors can determine the associated inductive load of the qubit based on the corresponding coupling strength of each coupler, and can further determine the associated inductive load of the qubit based on the corresponding inductive load of each coupler and the corresponding distance of each coupler from one or more Josephson junctions of the qubit along the qubit loop (e.g., based on C as described above). 有效 The associated capacitive load of a qubit is determined using a model. One or more processors can combine these capacitive loads (e.g., by summing the capacitive loads and / or by weighted or nonlinear combination) and determine the predicted capacitance C of the qubit based on the combined capacitive loads and any other suitable factors (such as the capacitive loads of other devices, the baseline capacitance of the qubit, and the programmed state of one or more Josephson junctions). 预测 .

[0125] At position 504, one or more processors determine the target capacitance of the qubit, denoted as C. 目标 The goal of Method 500 is to tune the effective capacitance of the qubit to the target capacitance C. 目标 Within the threshold range. Target capacitance C 目标 It can be predetermined (e.g., target capacitance C). 目标 (This could be a fixed value of the qubits determined at design time). In this case, determining the processor could include retrieving the target capacitance C from the data storage area. 目标 The value of . The predetermined target capacitance C can be determined, for example, by experimental methods, such as using magnetic resonance tunneling, quantum bit spectroscopy, and / or other techniques to identify the quantum bit capacitance. 目标For example, in quantum annealing systems, this could involve observing the behavior of a qubit (and / or larger systems, such as systems 200, 300, 400) at a quantum critical point (that is, at an energy scale where disorder and the problem Hamiltonian operator have equal energies) to ensure that the qubit exceeds a certain baseline noise threshold given a specific capacitance.

[0126] In some implementations, for example, after receiving a given problem to be executed by a quantum processor, the target capacitance C is dynamically determined by the processor. 目标 For example, the target capacitance can be determined by: determining the predicted capacitance C of each of the multiple qubits in the analog computing system for a given problem. 预测 And based on these predicted capacitances C 预测 Determine the target capacitance C 目标 For example, by taking the average value of the target capacitance and / or by determining the C that minimizes the objective function. 目标 The value (e.g., C for each qubit) 预测 With C 目标 The sum of the L1 or L2 norms between them). Such determination may be subject to one or more constraints; for example, C may be constrained. 目标 The choice of [the parameter] allows the analog computing system to operate to [the function] to [the function] the effective capacitance C of each of the multiple qubits. 有效 From the predicted capacitance C of each quantum bit 预测 Increase or decrease (as needed) to the target capacitor C 目标 Within the threshold.

[0127] At position 506, one or more processors are based on the predicted capacitance C. 预测 and target capacitance C 目标 The total capacitance change of the qubit is determined and denoted as ΔC. In at least some embodiments, the total capacitance change ΔC is C0. 目标 With C 预测 The difference between them.

[0128] At 510, one or more processors tune multiple inductors of the analog computing system to change the effective capacitance of the qubit based on the distance of each inductor along the qubit loop from one or more Josephson junctions of the qubit and based on the total capacitance change ΔC. For example, one or more processors can tune multiple inductors to change the effective capacitance C of the qubit. 有效Increase or decrease (as appropriate) the amount within a threshold of ΔC. For example, such tuning may include transmitting a representation of the problem to an analog computing system for execution (and thus causing the analog computing system to execute the representation of the problem), the representation including programming a plurality of inductors to provide parameters of a tunable inductor determined during the execution of method 500. In some implementations, one or more processors tune the inductors to compensate for capacitive loads induced by the coupler (e.g., predicted as described above with reference to action 502).

[0129] In at least some embodiments, the tuning of action 510 includes tuning a near inductor along the qubit loop closer to one or more Josephson junctions than the critical distance to reduce qubit capacitance (at action 512) and tuning a far inductor along the qubit loop further away from one or more Josephson junctions than the critical distance to increase qubit capacitance (at action 514).

[0130] Near-field and far-field inductors can be tuned based on their respective distances from one or more Josephson junctions, for example, by tuning the near-field and far-field inductors based on their distances from a critical point (such as the nearest critical point). As noted elsewhere in this document, the capacitive load per inductor unit typically varies with the inductor's position along the qubit loop. Therefore, for example, determining the effective qubit capacitance C... 有效 The inductance required for a specific change may include: looking up a value from a data storage area (e.g., a lookup table) that stores the capacitance change of an inductor at a certain distance from one or more Josephson junctions for the corresponding inductance change (such values ​​can be predetermined, for example, experimentally); applying a model of the qubit capacitance to the inductor based on the distance between the inductor and one or more Josephson junctions (e.g., by using a model that explicitly includes such a distance as a parameter, and / or by selecting a model based on that distance, such as the C given above). 有效 One of the models); and / or other methods.

[0131] The tuning of action 510 may be as simple as tuning one of the near or far inductors to achieve (or at least approximate) the desired total capacitance change ΔC: for example, increasing the inductance of the far inductor to increase the capacitance by ΔC (or at least to within the threshold of ΔC) or increasing the inductance of the near inductor to decrease the capacitance by ΔC. However, in at least some cases, such tuning may cause the effective inductance of the qubit to become less homogeneous across the different programmed states of the qubit.

[0132] In at least some applications, such inhomogeneity may be undesirable. In at least some embodiments, method 500 further includes determining the expected inductance and target inductance of the qubit, determining the total inductance change Δl based on the expected inductance and target inductance, and tuning a plurality of inductors such that the common inductance of the inductors (i.e., the sum of the inductances of the inductors) increases by an amount within a threshold of ΔL.

[0133] It should be noted that the change in qubit inductance is not necessarily the same as the value of ΔL, because the inductance contributed by the inductor to the effective qubit capacitance may be smaller than the inductance contributed locally by the inductor. For example, Figure 4A In the case of qubit 401, due to the parallel arrangement of qubit loops 402a and 402b, the effective qubit inductance may increase by approximately a quarter unit in some cases for each unit of tunable inductance contributed by inductors 406a, 406b, 408a, and 408b (e.g., where the inductances of qubit loops 402a and 402b are approximately equal). Therefore, in some embodiments, determining the total inductance change ΔL includes determining the total inductance change of the inductors to achieve (or at least approximate) the total inductance change of the qubit, wherein the total inductance change is determinable (e.g., based on the difference between the target inductance and the predicted inductance).

[0134] In at least some implementations, the total inductance change is distributed among the inductors based not only on ΔL but also on ΔC. For example, method 500 can homogenize (within a threshold) both ΔL and ΔC across various programmed states of the analog computing system (such as those described elsewhere herein). A given total inductance change ΔL can be distributed among the inductors in various ways, but in most cases, most such distributions will fail to achieve (or at least approximate) a particular desired change in qubit capacitance.

[0135] Figure 6 This is a flowchart of a method 600 for distributing inductance between a near-inductor and a far-inductor. The method is executed by one or more processors (e.g., classical processors) communicating with an analog computing system and may be executed as part of method 500. At 602, the one or more processors determine the total inductance change ΔL (e.g., based on a target inductance and a predicted inductance, as described above), and at 604, the one or more processors determine the total capacitance change ΔC (e.g., based on a target capacitance and a predicted capacitance, as described above with reference to action 506 of method 500).

[0136] At 606, one or more processors determine the distribution of the total inductance change ΔL among the inductors of the analog computing system based on the total capacitance change ΔC, such that the corresponding tunable inductances of the inductors are collectively within a threshold of the total inductance change ΔL (e.g., such that the sum of these tunable inductances is within a threshold of the total inductance change ΔL). In some embodiments, action 606 includes identifying multiple candidate distributions of inductor tuning values. Each candidate distribution includes the value of the tunable inductance of each inductor and thus corresponds to the capacitance change caused by (and / or predicted by) tuning the inductors to provide these values ​​of tunable inductance. A distribution can then be selected from the multiple candidate distributions, for example, by selecting the candidate distribution with the (predicted) capacitance change closest to the total capacitance change ΔC.

[0137] Multiple candidate distributions can be determined, for example, by looking up a value in a lookup table that associates the value of ΔL with the value of ΔC. In some implementations, the lookup table has ΔL and ΔC values ​​as axes, and each (ΔL, ΔC) coordinate in the table is mapped to a candidate distribution that provides (or predicts to provide) the corresponding ΔL and ΔC values ​​(at least within a threshold) being looked up. For example, in... Figure 2 In the exemplary dual-inductor system 200 shown, if a total inductance change ΔL = 100.1 pH is determined at action 602 and a total capacitance change ΔC = 59.9 fF is determined at action 604, then action 606 may include looking up coordinates (100 pH, 60 fF) in a lookup table and identifying candidate distributions L. 近 =80 pH, L 远 =20pH. (The above example assumes that the coordinates of a more precise approximation of the lookup value are not represented by this table.)

[0138] In some implementations, the lookup table has the value of a tunable inductor as the axis (e.g., L). 近 and L 远 And each coordinate (e.g., (L) 近 L 远 The coordinates are mapped to the coordinate ΔC value. (In some implementations, ΔL is also mapped using this table; in other implementations, ΔL is omitted from the table, in which case it can be mapped by combining coordinate values, for example by calculating ΔL = L.) 近 +L 远 To infer ΔL). Multiple candidate distributions can be identified in this table, for example, by recognizing all coordinates corresponding to the total inductance change ΔL (at least within a threshold). For example, in a table with L... 近 and L 远 In an exemplary dual-axis table as an example of an axis, it can be identified (e.g., for L) 近 Each value is determined by L. 近 =ΔL-L 远 of (L) 近L 远 The coordinates are used to at least approximately define a diagonal, if such a value exists, and the corresponding candidate ΔC value along that diagonal is selected as the closest to the total conductance change ΔC. Such a lookup table can include more than two dimensions (e.g., to explicitly represent more than two inductors along its axis). However, even when providing more than two tunable inductors, the lookup table can provide fewer axes; for example, the lookup table can provide L... 近 and L 远 As an axis, this allows one or more processors to distribute inductance between the near-inductor and the far-inductor. The near-inductor (based on L) can then be determined by referring to other lookup tables, by applying a model, or via other suitable methods. 近 ) and remote inductors (based on L) 远 Sub-distributions between ).

[0139] In some implementations, action 606 includes interpolating the inductor tuning value of the inductor in the analog computing system. For example, the coordinates (e.g., (ΔL, ΔC), (L...) can be interpolated based on a selected distribution and another candidate distribution, such as a candidate distribution that is close to (e.g., adjacent to) the selected distribution in a lookup table. 近 L 远 The inductor tuning value at (100pH, 60fF) and / or some other coordinate is interpolated. As used herein, "close" means a distribution within a small threshold (e.g., an integer value, ±1% of each coordinate value) around the selected distribution. This threshold will define a region around the coordinates of the selected distribution that is referred to as "close". For example, returning to the above example of determining a total inductance change ΔL = 100.1pH at action 602 and a total capacitance change ΔC = 59.9fF at action 604, action 606 may include: selecting a candidate distribution at (100pH, 60fF), for example, as described above; and interpolating the value at (100pH, 59fF) by interpolating the inductor tuning value at (100pH, 60fF) with the inductor tuning value of another candidate distribution having coordinates (101pH, 59fF). Interpolation can include taking a weighted average of the selected distribution and the other candidate distribution, for example, weighted based on the distance of each distribution from the coordinates (100.1pH, 59.9fF) (e.g., Cartesian distance), where closer distributions receive larger weights. In this example, the "closest" distribution is an integer value larger than the selected distribution at each coordinate.

[0140] At 606, one or more processors tune the inductors based on a selected distribution, for example, by tuning each inductor to provide (or at least approximate) the tunable inductance provided for that inductor in the selected distribution. Action 606 may be performed as part of action 510 of method 500.

[0141] Computing System

[0142] The above methods can be performed by hybrid computing systems (e.g., including the above-described simulation computing systems). Figure 7 An example hybrid computing system 700 is shown, comprising a digital computer 702 coupled to an analog computer 704. In some embodiments, the analog computer 704 is a quantum computer and the digital computer 702 is a classical computer.

[0143] The exemplary digital computer 702 includes a digital processor (such as one or more central processing units 706) described in this system and method that can be used to perform classical digital processing tasks. Those skilled in the art will understand that this system and method can be practiced using other digital computer configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (“PCs”), network PCs, microcomputers, mainframe computers, etc., when properly configured or programmed to form a dedicated machine and / or communicatively coupled to control an analog computer (e.g., a quantum computer).

[0144] The digital computer 702 is sometimes referred to in the singular herein, but this is not intended to limit the application to a single digital computer. This system and method can also be practiced in a distributed computing environment, where tasks or sets of instructions are performed or executed by a remote processing device linked via a communication network. In a distributed computing environment, computer-readable instructions and / or processor-readable instructions (sometimes referred to as program modules), application programs, and / or data can be stored in local memory storage devices and / or remote memory storage devices (e.g., non-transitory computer-readable media and / or processor-readable media).

[0145] The digital computer 702 may include at least one or more digital processors (e.g., one or more central processing unit units 706), one or more system memories 708, and one or more system buses 710 that couple various system components, including the system memories 708, to the central processing unit unit 706.

[0146] A digital processor can be any logic processing unit, such as one or more central processing units (“CPU”) with one or more cores, graphics processing units (“GPU”), digital signal processors (“DSP”), application-specific integrated circuits (“ASIC”), field-programmable gate arrays (“FPGA”), programmable logic controllers (“PLC”), etc.

[0147] Digital computer 702 may include a user input / output subsystem 712. In some embodiments, the user input / output subsystem includes one or more user input / output components, such as a display 714, a mouse 716, and / or a keyboard 718. System bus 710 may employ any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 708 may include: non-volatile memory, such as one or more of read-only memory (“ROM”), static random access memory (“SRAM”), and flash NAND; and volatile memory, such as random access memory (“RAM”) (not shown), all of which are examples of non-transitory computer-readable media and / or processor-readable media.

[0148] The Basic Input / Output System (“BIOS”) 720, which can be part of the ROM, contains basic routines that help transfer information between elements within the digital computer 702, such as during startup.

[0149] The digital computer 702 may also include other non-volatile memory 722. The non-volatile memory 722 may take various forms, including: a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to a removable optical disk, and / or a disk drive for reading from and writing to a magnetic disk; all of these elements are examples of non-transitory computer-readable or processor-readable media. The optical disk may be a CD-ROM or DVD, while the magnetic disk may be a floppy disk or a floppy disk. The non-volatile memory 722 may communicate with the digital processor via a system bus 710 and may include a suitable interface or controller 724 coupled to the system bus 710. The non-volatile memory 722 may serve as non-transitory long-term storage space for computer-readable and / or processor-readable instructions, data structures, or other data (also referred to as program modules) of the digital computer 702.

[0150] Although the digital computer 702 has been described as employing hard disks, optical disks, and / or magnetic disks, those skilled in the art will understand that other types of non-volatile computer-readable media can be used, such as magnetic tape cassettes, flash memory cards, flash memory, ROM, smart cards, etc., all of which are further examples of non-transitory computer-readable media or processor-readable media. Those skilled in the art will also understand that some computer architectures combine volatile and non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory or a solid-state drive (SSD) can be used to provide non-volatile memory using integrated circuits. Some computers place data traditionally stored on disks in memory. Furthermore, some media traditionally considered volatile can be in non-volatile form, such as non-volatile dual in-line memory module variants.

[0151] Various computer-readable and / or processor-readable instructions (also referred to as program modules), application programs, and / or datasets may be stored in system memory 708. For example, system memory 708 may store operating system 726, server instructions 728, computing instructions 730, and / or runtime instructions 732.

[0152] Although Figure 7 The data is shown as being stored in system memory 708, but program modules and other data may be stored elsewhere, including in non-volatile memory 722 or in one or more other non-transitory computer-readable and / or processor-readable media.

[0153] The analog computer 704 can be provided in a separate environment (not shown). For example, in the case where the analog computer 704 is a quantum computer, the environment protects the internal components of the quantum computer from heat, magnetic fields, etc. The analog computer 704 includes one or more analog processors, such as quantum processors 734.

[0154] A quantum processor includes programmable elements such as qubits, couplers, and other devices. In one embodiment, the qubit is a superconducting flux qubit. The qubit is read out via a readout system 736. These results can be fed into various computer-readable and / or processor-readable instruction sets of a digital computer 702. An analog computer 704 may include a qubit control system 738 and a coupler control system 740. The coupler control system 740 can provide control over communication coupling between qubits, such as the inductive and capacitive communication coupling described in this application.

[0155] In some embodiments, the hybrid computer 700 is used to implement quantum annealing on the quantum processor 734.

[0156] In some embodiments, the digital computer 702 can operate in a networked environment using a logical connection to at least one client computer system. In some embodiments, the digital computer 702 is coupled to at least one database system via a logical connection. These logical connections can be formed using any digital communication means, such as via a network, like a local area network (“LAN”) or a wide area network (“WAN”) including, for example, the Internet. The networked environment can include wired or wireless enterprise-wide computer networks, intranets, extranets, and / or the Internet. Other embodiments can include other types of communication networks, such as telecommunications networks, cellular networks, paging networks, and other mobile networks. Information sent or received via the logical connection may or may not be encrypted. When used in a LAN networked environment, the digital computer 702 can be connected to the LAN via an adapter or network interface card (“NIC”) (communically linked to the system bus 710). When used in a WAN networked environment, the digital computer 702 can include an interface and a modem (not shown) or a device such as a NIC to establish communication over the WAN. Additionally or alternatively, non-networked communication can be employed.

[0157] According to some embodiments of this system and device, quantum processors (such as...) Figure 7 The quantum processor 734 can be designed to perform quantum annealing and / or adiabatic quantum computation. The evolved Hamiltonian operator, proportional to the sum of the first term of the problem Hamiltonian operator and the second term of the delocalized Hamiltonian operator, is constructed as follows:

[0158] H E ∝A(t)H P +B(t)H D

[0159] Among them, H E It is the evolutionary Hamiltonian operator, H P It is the Hamiltonian operator for the problem, H D It is a delocalized Hamiltonian operator, and A(t) and B(t) are coefficients that can control the evolution rate and are usually in the range [0, 1].

[0160] In some implementations, a time-varying envelope function is applied to the problem Hamiltonian operator. A suitable delocalized Hamiltonian operator is given by:

[0161]

[0162] Where N represents the number of qubits, It is the Pauli x-matrix of the i-th qubit, and Δ i This refers to single-qubit tunneling induced in i qubits. Here, The item is an example of an "off-diagonal" item.

[0163] The Hamiltonian operator, which is frequently discussed, comprises a first component proportional to diagonal single-qubit terms and a second component proportional to diagonal multi-qubit terms, and can be in the following form:

[0164]

[0165] Where N represents the number of qubits, h is the Pauli z-matrix of the i-th qubit. i and J ij These are the dimensionless local field of the qubit and the coupling between the qubits, respectively, and ε is H. P The characteristic energy scale. Here, and The term is an example of a "diagonal" term. The former is a single-qubit term, and the latter is a two-qubit term.

[0166] Programmable states across individual qubits and / or homogenization of inductors and / or capacitors across qubits and quantum processors can help homogenize their physical behavior. Where appropriate, such homogenization of fundamental physics can enable quantum processors to more accurately instantiate the aforementioned computational models, thereby more generally improving the performance of quantum processors and thus the performance of the hybrid computing system 700.

[0167] Butterfly qubit

[0168] As discussed above, superconducting flux qubits (e.g., superconducting flux qubit 100a) may include superconducting material loops (e.g., qubit loop 102) interrupted by a Josephson junction (e.g., CJJ 104). The qubits are connected by couplers (e.g., coupler 222) within a quantum processor, and the type and complexity of problems that the processor can solve may be affected by the connectivity between the qubits. In some embodiments, increasing the connectivity between single-loop flux qubits (e.g., flux qubits 100a, 201) is achieved at least in part by increasing the length of the qubits to accommodate additional couplers. Increasing the qubit length may result in increased inductance and capacitance and a corresponding decrease in energy scale. In some embodiments, as described above... Figure 4A and Figure 4B Multi-loop flux qubits (e.g., qubit 401) described in more detail below may be beneficial. Multi-loop flux qubits can allow for increased connectivity without a corresponding decrease in energy scale.

[0169] exist Figure 8In an example implementation, the analog computing system 800 has a qubit 802 having a Josephson junction 804, a first qubit loop 806 formed by a first superconducting current path, and a second qubit loop 808 formed by a second superconducting current path. The first qubit loop 806 and the second qubit loop 808 are electrically connected in parallel across the Josephson junction 804. A qubit with two loops can also be referred to as a double-winged qubit or a butterfly qubit, with each loop constituting one of the wings. Figure 8 In an example implementation, the first qubit loop 806 and the second qubit loop 808 are symmetrical about axis 816 of the Josephson junction 804, which runs through a first connection 818 between the first qubit loop 806 and the second qubit loop 808 and the Josephson junction 804, and a second connection 820 between the first qubit loop 806 and the second qubit loop 808 and the Josephson junction 804. From the perspective of the Josephson junction, the behavior of the two-wing qubits will be similar to that of RF SQUID flux qubits (e.g., Figure 1A and Figure 1B These qubits (in the junction) behave in the same way. At the applied zero flux, the magnitude of the current flowing in each flank will be half the magnitude of the current flowing through the Josephson junction. The continuous current flowing through the junction is split as it flows into the parallel flanks, such that the total continuous current through the junction is the combination of the continuous currents flowing in each flank. The total effective volume inductance will be equal to the parallel combination of the inductances of the two flanks. Figure 8 In this implementation, the rotation direction of the current is opposite between the two flanks. Figure 8 In the example implementation, the Josephson junction is a compound Josephson junction. In other implementations, it can be a compound-compound Josephson junction, which refers to a compound Josephson junction in which at least one junction is also a compound Josephson junction.

[0170] Independent control of each flank of qubit 802 can be provided by a flux bias source (e.g., a flux bias line that applies bias current to the qubit loop from the outside). The first qubit loop 806 can communicate with the first flux bias line 810, and the second qubit loop 808 can communicate with the second flux bias line 812. The first flux bias line 810 can receive signals independently of the second flux bias line 812, thus allowing independent control of each qubit loop. As discussed above, the first qubit loop 806 and the second qubit loop 808 can partially overlap along a shared portion 814. The two flanks 806 and 808 of qubit 802 allow two distinct current paths: in one path, current flows through the Josephson junction and into the flank, responding to the flux bias difference between the flanks; and in the second path, current flows only around the outer loop formed by the two flanks, responding to the sum of fluxes in the flanks.

[0171] exist Figure 9A In an example implementation, the analog computing system 900a has a qubit 902, which has a Josephson junction 904. It is symmetric with the first qubit loop 806 and the second qubit loop 808. Figure 8 On the contrary, Figure 9A In this circuit, the first qubit loop 906 and the second qubit loop 908 are asymmetric. The first flux bias line 910 and the second flux bias line 912 communicate with the first qubit loop 906 and the second qubit loop 908. Figure 9B In an example implementation, the analog computing system 900b has a qubit 902 having a Josephson junction 904, a first qubit loop 906 and a second qubit loop 908, and a first flux bias line 910 and a second flux bias line 912. Figure 9B In this embodiment, the additional qubit loop 916 is electrically connected in parallel across the Josephson junction 904 and has an independent flux bias line 918. In other embodiments, the qubit may be designed with one or more additional qubit loops, and additional flanks may be added in parallel. Increasing the number of flanks may cause the potential energy of the entire qubit to scale proportionally to the number of flanks.

[0172] exist Figure 10In an example implementation, the analog computing system 1000 has a qubit 1002 having a composite-composite Josephson junction (CCJJ) 1004, a first qubit loop 1006 formed by a first superconducting current path, and a second qubit loop 1008 formed by a second superconducting current path. The first qubit loop 1006 and the second qubit loop 1008 are electrically connected in parallel across the Josephson junction 1004. The second qubit loop 1002 has a first portion 1010 communicating with the Josephson junction 1004, a second portion 1012 spaced apart from the Josephson junction 1004, and a crossover 1014 separating the first portion 1010 and the second portion 1012. Current in the first portion 1010 travels in a first rotational direction (e.g., shown clockwise), and current in the second portion 1012 travels in a second rotational direction opposite to the first rotational direction (e.g., shown counterclockwise). It should be understood that the direction can be reversed. Figure 10 The example embodiment shows an orientation such that the first rotation direction is counterclockwise and the second rotation direction is clockwise. It should be understood that the crossover acts as a "twisted portion" in the second qubit loop and can be formed of superconducting material to cross in multiple layers orthogonally (e.g., vertically) spaced apart in a multilayer circuit. Providing a twisted portion in one wing of the qubit allows the entire qubit to behave like a single, longer loop qubit without the twisted portion. A twisted portion in one wing can homogenize the sensation of continuous current within the circuit. Figure 10 As shown, although the current direction is reversed near CCJJ, the current traveling through the outer part of the qubit is generally counterclockwise.

[0173] The analog computing system 1000 further includes a first flux bias line 1016 and a second flux bias line 1018, and a first coupler 1020 and a second coupler 1022, respectively tunably coupled to a first qubit loop 1006 and a second qubit loop 1008. In other embodiments, the analog computing system may have one or more couplers tunably coupled to one of the first qubit loop and the second qubit loop. The first coupler 1020 and the second coupler 1022 may couple qubit 1002 to another qubit 1024 or to multiple other qubits or other devices. Coupling with adjacent qubits can be performed along the length of the flanks. By reducing the flank length when adding additional flanks, connectivity can be increased to achieve the same energy scale. Conversely, for fixed connectivity, the energy scale can be increased by reducing the flank length and increasing the number of flanks.

[0174] exist Figure 11In an example implementation, the analog computing system 1100 has qubits 1102, CCJJ 1104, a first qubit loop 1106, and a second qubit loop 1108. The second qubit loop 1108 has a first portion 1110, a second portion 1112, and a crossover 1114. Qubit 1102 is similar to qubit 1002, wherein, in addition to flux bias lines 1116 and 1118 and couplers 1120 and 1122, it has additional means for communicating with qubit loops 1106 and 1108. This includes a plurality of inductors 1126 disposed along each of the first qubit loop 1106 and the second qubit loop 1108, each of the plurality of inductors 1126 being tunable to provide a corresponding tunable inductance, as discussed in detail below. Also shown is a continuous current compensator 1128 (referred to herein as a multiplier compensator) that can be coupled to a signal line and provides various waveforms as discussed in U.S. Patent No. 9,015,215. The qubits described herein may include other means such as programming, readout, and calibration devices, and may also include a number of other means shown.

[0175] It should be understood that, Figure 10 and Figure 11 The structure shown is an example implementation of a butterfly qubit. For example, Josephson junction 1004 is shown as a composite-composite Josephson junction, but it could also be a composite Josephson junction with one junction on each side of the loop, or it could have other numbers of junctions. The bias lines shown can provide independent biases, or they can be connected in series and driven by a single source. The biases provided to both sides of the loop can be the same, or they can be different biases. Each of the biases shown (including biases 1016 and 1018) and the bias lines connected to the Josephson junction and the coupler can be provided by more than one bias. For example, in some implementations, each of the bias lines shown can be provided by two independent lines, one of which is provided by an external room temperature source, and the other is driven by an on-chip digital-to-analog converter (DAC). As discussed above, these are example implementations, and the circuit may not include all of the shown devices, and may include other devices such as programming, readout, and calibration devices, and may include other numbers of the shown devices.

[0176] The methods described above (500, 600) can be used with the qubits described above (802, 902, 1002, and 1102).

[0177] Throughout this specification, unless the context otherwise indicates, the terms "problematic Hamiltonian operator" and "final Hamiltonian operator" are used interchangeably. Certain states of a quantum processor are energy-preferred, or simply preferred for the problem Hamiltonian operator. These states include the ground state, but may include excited states.

[0178] The Hamiltonian operator can be physically implemented in various ways (for example, H in the two equations above). D and H P A specific example is achieved by implementing superconducting qubits.

[0179] Examples of superconducting qubits include superconducting flux qubits and superconducting charge qubits. In superconducting flux qubits, the Josephson energy is dominant or equal to the charging energy. In charge qubits, the opposite is true. Examples of usable flux qubits include RF-SQUIDs (including superconducting circuits interrupted by one Josephson junction) and continuous current qubits (including superconducting circuits interrupted by three Josephson junctions). See examples of RF-SQUID qubits in the following literature: Bocko et al., 1997, IEEE Trans. on Appl. Superconducting, 7, 3638; Friedman et al., 2000, Nature, 406, 43; and Harris et al., 2010, Phys. Rev., B 81, 134510, or examples of continuous current qubits in the following literature: Mooij et al., 1999, Science, 285, 1036; and Orlando et al., 1999, Phys. Rev., B60, 15398. Alternatively, mixed-charge phase qubits can be used, where the energies are equal. Further details about superconducting qubits can be found in the following literature: Makhlin et al., 2001, Rev. Mod. Phys. [Review of Modern Physics] 73, 357; Devoret et al., 2004, arXiv:cond-mat / 0411174; Zagoskin and Blais, 2007, Physics in Canada [Canadian Physics] 63, 215; Clarke and Wilhelm, 2008, Nature [Nature] 453, 1031; Martinis, 2009, Quantum Inf. Process. [Quantum Information Processing] 8, 81; and Devoret and Schoelkopf, 2013, Science [Science] 339, 1169. In some embodiments, the qubit and coupler are controlled by an on-chip circuit system. Examples of on-chip control circuitry systems can be found in the following U.S. patents: 7,876,248; 7,843,209; 8,018,244; 8,098,179; 8,169,231; and 8,786,476. Further details and implementations of exemplary quantum processors used in conjunction with this system and apparatus can be described in, for example, the following U.S. patents: 7,533,068; 8,008,942; 8,195,596; 8,190,548; and 8,421,053.

[0180] The methods, processes, or techniques described above may be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods, processes, or techniques described above are performed in part by a dedicated device such as an adiabatic quantum computer or a quantum annealer, or a system (e.g., a computer including at least one digital processor) that programs or otherwise controls the operation of the adiabatic quantum computer or quantum annealer. The methods, processes, or techniques described above may include a variety of actions, but those skilled in the art will understand that certain actions may be omitted in alternative examples, and / or additional actions may be added. Those skilled in the art will also understand that the sequence of actions shown is for illustrative purposes only and may be changed in alternative examples. Some of the exemplary actions or operations of the methods, processes, or techniques described above are performed iteratively. Some of the actions described above from the methods, processes, or techniques can be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0181] The above description of the illustrated embodiments (including those described in the abstract) is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. As those skilled in the art will recognize, although specific embodiments and examples have been described herein for illustrative purposes, various equivalent modifications may be made without departing from the spirit and scope of this disclosure. The teachings of the various embodiments provided herein can be applied to other methods of quantum computing and are not necessarily the exemplary quantum computing methods generally described above.

[0182] The various embodiments described above can be combined to provide further embodiments. The entire contents of all commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference, including but not limited to: U.S. Patent No. 7,135,701; U.S. Patent No. 7,418,283; U.S. Patent No. 8,536,566; U.S. Patent No. 9,015,215; U.S. Patent No. 9,152,923; PCT Application No. US 2018 / 066613; and U.S. Patent Application No. 62 / 951,738.

[0183] In view of the above detailed description, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments, together with the entire scope of the equivalents entitled to be obtained by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An analog computing system comprising qubits and one or more couplers, in, This quantum bit includes: A quantum bit loop, which is formed by the first superconducting current path; At least one Josephson junction interrupts the qubit loop, and the location of the at least one Josephson junction along the qubit loop defines a critical distance that divides the qubit loop into a near-inductor type and a far-inductor type, wherein adding a lumped inductance in the near-inductor type reduces the qubit capacitance at the at least one Josephson junction, and wherein adding the lumped inductance in the far-inductor type increases the qubit capacitance at the at least one Josephson junction; Multiple inductors are arranged along the qubit loop, each of which is tunable to provide tunable inductance, the multiple inductors comprising: One or more proximity inductors, each proximity inductor being disposed in the proximity inductor configuration; and One or more remote inductors, each remote inductor being configured in the remote inductor type; The one or more couplers are tunably coupled to the qubit loop, and each of the one or more couplers is tunable to provide a corresponding coupling strength with the qubit. Wherein, the tunable inductance of each of the plurality of inductors is tunable within a corresponding inductance range, and each of the one or more couplers has a corresponding coupler-sensor inductance range, the coupler-sensor inductance range of each coupler including the difference between the states of the corresponding couplers of the at least one Josephson junction qubit inductance, and the sum of the tunable inductance ranges of the plurality of inductors is greater than each of the corresponding coupler-sensor inductance ranges. The sum of the tunable inductance ranges of the plurality of inductors is greater than the total inductance range induced by the coupler. The total inductance range induced by the coupler includes the difference between the inductance induced by the first coupler and the inductance induced by the second coupler. The inductance induced by the first coupler includes the inductance of the qubit in a first state, in which each of the one or more couplers is ferromagnetically coupled to the qubit. The inductance induced by the second coupler includes the inductance of the qubit in a second state, in which each of the one or more couplers is antiferromagnetically coupled to the qubit.

2. The simulation computing system according to claim 1, wherein, One of the plurality of inductors includes one or more inductor Josephson junctions that interrupt the qubit loop and are tunable to provide a corresponding tunable inductance range for that one of the plurality of inductors.

3. The simulation computing system according to claim 2, wherein, This one of the plurality of inductors includes one or more DC-SQUIDs, and the one or more DC-SQUIDs include the Josephson junction of the one or more inductors.

4. The simulation computing system according to claim 3, wherein, This one of the multiple inductors comprises multiple DC-SQUIDs connected in series along the qubit loop.

5. The simulation computing system according to claim 1, wherein: The one or more proximity inductors are tunable together to reduce the capacitance of the qubit from the capacitance sensed by the first coupler to within a first threshold of the target capacitance; The one or more remote inductors are tunable together to increase the capacitance of the qubit from the capacitance sensed by the second coupler to within a second threshold of the target capacitance; The capacitance sensed by the first coupler includes the qubit capacitance in the third state, in which each of the one or more couplers in the near-inductor type is antiferromagnetically coupled to the qubit loop, and each of the one or more couplers in the far-inductor type is ferromagnetically coupled to the qubit loop; and The capacitance sensed by the second coupler includes the qubit capacitance in the fourth state, in which each of the one or more couplers in the near-inductor type is ferromagnetically coupled to the qubit loop, and each of the one or more couplers in the far-inductor type is antiferromagnetically coupled to the qubit loop.

6. The simulation computing system according to claim 5, wherein, For a predetermined target qubit inductance and a set of predetermined coupling strengths for the one or more couplers, the plurality of inductors are tunable to provide a total tunable inductance for each of the first, second, third, and fourth states, thereby increasing the qubit inductance to within a third threshold of the predetermined target qubit inductance and at least one of the following occurs: increasing the qubit capacitance to within a fourth threshold of the target capacitance, and decreasing the qubit capacitance to within a fourth threshold of the target capacitance.

7. The simulation computing system according to claim 1, wherein, This quantum bit includes: The second qubit loop, wherein at least one Josephson junction interrupts the second qubit loop; and At least one secondary inductor is disposed along the second qubit loop.

8. The simulation computing system according to claim 7, wherein, The qubit loop and the second qubit loop partially overlap along the shared portion, and the shared inductor of the plurality of inductors is arranged along the shared portion.

9. The simulation computing system according to claim 8, wherein, The shared inductor includes one or more of the proximity inductors.

10. The simulation computing system according to claim 7, wherein, The at least one secondary inductor includes: One or more secondary proximity inductors, each secondary proximity inductor being positioned along the second qubit loop at a distance less than a second critical distance from the at least one Josephson junction; and One or more secondary remote inductors, each secondary remote inductor being positioned along the second qubit loop at a distance greater than the second critical distance from the at least one Josephson junction.

11. The simulation computing system according to claim 10, wherein, The plurality of inductors and the at least one secondary inductor together provide a common tunable inductance range that is at least twice the total inductance range induced by the coupler.

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