Optical sensor and method of driving an optical sensor

Abstract

The light sensor of the present application includes: a light receiving section that generates electric charges in response to incident light; a charge transfer gate for transferring the electric charges generated by the light receiving section; and a signal generating section for generating a charge transfer signal applied to the charge transfer gate, the signal generating section generating the charge transfer signal in a manner that the charge transfer gate is set to a charge transfer state in a first time range belonging to a first period of an nth (n is an integer of 1 or more) frame, and the charge transfer gate is set to a charge transfer state in a second time range belonging to a second period of an mth (m is an integer of 1 or more, different from n) frame, a part of the first time range and a part of the second time range overlapping each other when a start time of the first period coincides with a start time of the second period.

Description

Technical Field

[0001] This disclosure relates to optical sensors and methods for driving optical sensors. Background Technology

[0002] Patent Document 1 describes a fluorescence lifetime measuring device. This device includes: a measuring unit that generates fluorescence photons by irradiating a sample with excitation light and detects the generated fluorescence photons; a signal processing unit that measures the number of fluorescence photons at each of a plurality of time gates based on the signals of the fluorescence photons detected by the measuring unit; a computational processing unit that calculates the fluorescence lifetime based on the number of fluorescence photons measured at each of the plurality of time gates; and a control unit that controls the measuring unit, the signal processing unit, and the computational processing unit. The measuring unit includes a detector that converts fluorescence photons emitted from a sample in an excited state into electrical signals and outputs them to the signal processing unit. The signal processing unit amplifies the electrical signals input from the detector and branches them to two switches. The switches control the timing of ON / OFF operations via gating signals from the control unit, outputting electrical signals only during the ON operation.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2005-114528 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] However, according to the inventors' understanding, in order to improve the temporal resolution of the image sensor and achieve improved detection accuracy, it is necessary to control the charge transfer gate in a shorter time, but there are limitations when considering the carrier transport time. In contrast, in the device described in Patent Document 1, as mentioned above, the electrical signal from the detector is branched to two switches after being converted to IV by an amplifier. Furthermore, the ON periods of the two switches partially overlap. Based on this, the temporal resolution can also be considered improved.

[0008] However, while, as in the device of Patent Document 1, the ON periods of multiple switches can be overlapped to obtain a signal if the signal is an IV-converted signal, equal charge distribution is difficult in image sensors utilizing charge transfer gates if the charge transfer periods of the charge transfer gates are overlapped as in the device of Patent Document 1. Furthermore, although it is believed that the structure of the device of Patent Document 1 can be realized if the light-receiving part is a single unit, the circuit size is enormous and impractical when the light-receiving parts are arranged in one or two dimensions.

[0009] Therefore, the purpose of this disclosure is to provide an optical sensor and a driving method for the optical sensor that can improve detection accuracy by controlling the charge transfer gate.

[0010] Methods for solving problems

[0011] The optical sensor disclosed herein includes: a light-receiving section that generates charge based on incident light; a charge transfer gate for transmitting the charge generated by the light-receiving section; and a signal generation section for generating a charge transfer signal applied to the charge transfer gate. The signal generation section generates the charge transfer signal in such a manner that the charge transfer gate is set to a charge transfer state in a first time range during a first period of a first period belonging to a frame n (n is an integer greater than or equal to 1), and the charge transfer gate is set to a charge transfer state in a second time range during a second period of a second period belonging to a frame m (m is an integer greater than or equal to 1, different from n). When the start time of the first period coincides with the start time of the second period, a portion of the first time range overlaps with a portion of the second time range.

[0012] The driving method of the optical sensor disclosed herein is a driving method for an optical sensor having a light-receiving part that generates charge according to incident light and a charge transfer gate for transmitting the charge generated by the light-receiving part. The method generates a charge transfer signal applied to the charge transfer gate in such a way that the charge transfer gate is set to a charge transfer state in a first time range of a first period belonging to the nth (n is an integer greater than or equal to 1) frame, and the charge transfer gate is set to a charge transfer state in a second time range of a second period belonging to the mth (m is an integer greater than or equal to 1 different from n) frame. When the start time of the first period coincides with the start time of the second period, a portion of the first time range overlaps with a portion of the second time range.

[0013] In these optical sensors and their driving methods, a charge transfer signal applied to a charge transfer gate for transmitting charge generated by the light-receiving part is generated such that the charge transfer gate is set to a charge transfer state during a first time range of a first period belonging to the nth frame, and during a second time range of a second period belonging to the mth frame. The first and second time ranges are the ON periods of the charge transfer gate. Furthermore, when the start time of the first period coincides with the start time of the second period, a portion of the first time range overlaps with a portion of the second time range. Thus, if the ON periods of the charge transfer gate overlap between different frames, it is possible to capture phenomena that are repeatedly generated at least corresponding to each frame at a time interval corresponding to the offset of the ON period. That is, temporal resolution and detection accuracy can be improved.

[0014] In the optical sensor disclosed herein, the nth frame and the mth frame may be consecutive. This structure, where the frames partially overlap during the ON period, is effective for slightly varying and recurring phenomena. This is because the variation in this phenomenon between frames becomes relatively small compared to cases where the interval between the partially overlapping frames during the ON period is longer. Furthermore, the nth frame and the mth frame being consecutive corresponds to the case where m is n ± 1.

[0015] In the optical sensor disclosed herein, the signal generation unit may generate a charge transfer signal such that, within one frame, when the start times of multiple periods are made consistent across overlapping time ranges, the charge transfer gate is set to a charge transfer state. In this case, charge accumulation can be performed within one frame.

[0016] In the optical sensor disclosed herein, the charge transfer gate may include a first charge transfer gate and a second charge transfer gate. The signal generation unit generates a charge transfer signal such that one of the first and second charge transfer gates is set to a charge transfer state during a first time period, and the same one is set to a charge transfer state during a second time period. This allows for overlap between the ON periods of at least the same charge transfer gate in the nth and mth frames in an optical sensor equipped with multiple charge transfer gates.

[0017] In the optical sensor disclosed herein, the charge transfer gate may include a first charge transfer gate and a second charge transfer gate. The signal generation unit generates a charge transfer signal such that one of the first and second charge transfer gates is set to a charge transfer state during a first time period, and the other of the first and second charge transfer gates is set to a charge transfer state during a second time period. Thus, in an optical sensor having multiple charge transfer gates, at least the ON periods of mutually different charge transfer gates may overlap between the nth and mth frames.

[0018] In the optical sensor disclosed herein, the charge transfer gate may include a first charge transfer gate and a second charge transfer gate. The signal generation unit generates a charge transfer signal such that the first charge transfer gate is set to a charge transfer state in a first time period, and in a second time period; the second charge transfer gate is set to a charge transfer state in a third time period within the first period, and in a fourth time period within the second period. When the start time of the first period coincides with the start time of the second period, a portion of the third time period overlaps with a portion of the fourth time period. In this way, for an optical sensor having multiple charge transfer gates, by overlapping a portion of the ON period of each charge transfer gate, the temporal resolution can be improved and the frame rate reduced.

[0019] In the optical sensor disclosed herein, the signal generation unit may also generate a signal for the periodic output of light from the light source, wherein the start times of the first and second periods are synchronized with the timing of the light output from the light source. In this case, the temporal resolution and detection accuracy can be improved for phenomena (e.g., fluorescence) that are repeatedly generated based on light from the light source.

[0020] Here, the optical sensor disclosed herein includes: a light-receiving section that generates charge based on incident light; a first charge transfer gate and a second charge transfer gate for transmitting the charge generated by the light-receiving section; an exhaust gate for discharging the charge generated by the light-receiving section; and a signal generation section for generating a charge transfer signal applied to the first charge transfer gate, the second charge transfer gate, and the exhaust gate. The signal generation section generates the charge transfer signal in such a manner that the first charge transfer gate is set to a charge transfer state in a first time range, the second charge transfer gate is set to a charge transfer state in a second time range spaced apart from the first time range, and the exhaust gate is set to a charge discharge state in a third time range between the first and second time ranges.

[0021] Furthermore, the driving method of the optical sensor disclosed herein includes a light-receiving section that generates charge based on incident light, a first charge transfer gate and a second charge transfer gate for transmitting the charge generated by the light-receiving section, and an exhaust gate for discharging the charge generated by the light-receiving section. The method generates a charge transfer signal in such a manner that the first charge transfer gate is set to a charge transfer state in a first time range, the second charge transfer gate is set to a charge transfer state in a second time range spaced apart from the first time range, and the exhaust gate is set to a charge discharge state in a third time range between the first and second time ranges.

[0022] In these optical sensors and their driving methods, a charge transfer signal is applied to the first and second charge transfer gates for transferring the charge generated by the light-receiving section. During a first time period, the first charge transfer gate is set to a charge transfer state; during a second time period spaced apart from the first time period, the second charge transfer gate is set to a charge transfer state; and during a third time period between the first and second time periods, the discharge gate is set to a charge discharge state. The first and second time periods are the ON periods of the charge transfer gates, and the third time period is the charge discharge period. By spacing the ON periods of the charge transfer gates apart and setting the charge discharge period in between, it is possible to discharge any residual readout charge generated by the light-receiving section. As a result, detection accuracy can be improved.

[0023] In the optical sensor disclosed herein, the signal generation unit may generate a charge transfer signal such that each frame includes a first time range, a second time range, and a third time range in multiple frames, and that when the start time of the nth frame (where n is an integer greater than or equal to 1) coincides with that of the mth frame (where m is an integer greater than or equal to 1 different from n), the first time range of the mth frame is located between the first time range of the nth frame and the second time range of the nth frame. This allows for further improvement in detection accuracy by more densely configuring the ON periods of the charge transfer gates across multiple frames.

[0024] In the optical sensor disclosed herein, the signal generation unit may generate a charge transfer signal such that, within one frame, when the start times of multiple periods are made consistent across overlapping time ranges, the first charge transfer gate and the second charge transfer gate are set to charge transfer state. In this case, charge accumulation can be performed within one frame.

[0025] The effects of the invention

[0026] According to this disclosure, a light sensor and a method for driving the light sensor can be provided, which can improve detection accuracy by controlling the charge transfer gate. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating the light detection device involved in the embodiment.

[0028] Figure 2 yes Figure 1 A schematic top view of the pixel section shown.

[0029] Figure 3 yes Figure 2 The image shows a cross-sectional view of the pixel portion.

[0030] Figure 4This is a diagram showing the potential distribution near the second principal surface of a semiconductor substrate used to illustrate the accumulation of signal charge.

[0031] Figure 5 This is a diagram showing the potential distribution near the second principal surface of a semiconductor substrate used to illustrate a charge-free discharge operation.

[0032] Figure 6 It is a graph showing the relationship between excitation light and fluorescence.

[0033] Figure 7 yes Figure 1 The timing diagram shown is for the signals generated and provided by the timing generator.

[0034] Figure 8 yes Figure 1 The timing diagram shown is for the signals generated and provided by the timing generator.

[0035] Figure 9 This is a timing diagram illustrating a variation of the first embodiment.

[0036] Figure 10 This is a top view showing a portion (pixel portion of the light sensor) of the light detection device according to the second embodiment.

[0037] Figure 11 This is a timing diagram of the signals generated by the timing generator according to the second embodiment.

[0038] Figure 12 This is a timing diagram of the signals generated by the timing generator according to the second embodiment.

[0039] Figure 13 This is a diagram used to illustrate a modified example of the light-receiving part.

[0040] Figure 14 This is a diagram used to illustrate another variation of the light-receiving part. Detailed Implementation

[0041] Hereinafter, one embodiment will be described in detail with reference to the accompanying drawings. Furthermore, in the drawings, sometimes the same or equivalent elements are labeled with the same reference numerals, and overlapping descriptions are omitted.

[0042] [First Implementation]

[0043] Figure 1 This is a block diagram illustrating the light detection device involved in the embodiment. Figure 1The light detection device 100 shown is, for example, an image sensor (gate image sensor), a motion sensor, a range sensor, a range image sensor, etc. The light detection device 100 includes a light sensor 50 and a light source 51. The light sensor 50 includes a sensor section 52, a timing generator (signal generation section) 53, and a delay circuit 54. The light source 51 includes, for example, an LED, which outputs pulsed light to an object. The sensor section 52 detects light (reflected light or fluorescence) from the object that corresponds to the pulsed light from the light source 51. The sensor section 52 includes a plurality of pixel sections RS arranged in a two-dimensional manner. The sensor section 52 can be formed as a monolithic chip on a semiconductor substrate (e.g., a silicon substrate) by means of the pixel sections RS and a CMOS readout circuit section.

[0044] Figure 2 yes Figure 1 A schematic top view of the pixel section shown. Figure 3 yes Figure 2 The image shows a cross-sectional view of the pixel portion. Figure 3 (a) is along Figure 2 Cross-sectional view of line IIIa-IIIa, Figure 3 (b) is along Figure 2 A cross-sectional view of line IIIb-IIIb. (See figure.) Figure 2 , 3 As shown, the light sensor 50, in the sensor section 52 (pixel section RS), includes a semiconductor substrate 1 having a first main surface 1a and a second main surface 1b facing each other. The semiconductor substrate 1 comprises a p-type first semiconductor region 3 located on the first main surface 1a side, and a p-type semiconductor region located on the second main surface 1b side with a lower impurity concentration than the first semiconductor region 3. - The second semiconductor region 5 is formed. For example, the semiconductor substrate 1 can be constructed by forming a p-type semiconductor substrate with a lower impurity concentration compared to the p-type semiconductor substrate. - The epitaxial layer is grown to obtain the type. An insulating layer 7 is formed on the second main surface 1b (second semiconductor region 5) of the semiconductor substrate 1.

[0045] A grating electrode PG is disposed on the insulating layer 7. The grating electrode PG is rectangular in top view. In this embodiment, the grating electrode PG is rectangular in shape. The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the grating electrode PG (in...) Figure 3 The region located below the grating electrode PG functions as a light-receiving part 2 that generates charge based on incident light. That is, the light sensor 50 includes a plurality of light-receiving parts 2 arranged in a two-dimensional configuration (the arrangement of the light-receiving parts 2 can also be one-dimensional).

[0046] In the second semiconductor region 5, in each region separated from and positioned from the grating electrode PG, n-type third semiconductor regions 9a and 9b with high impurity concentrations are formed. The third semiconductor region 9a is a first charge accumulation region for accumulating charge generated by the light-receiving section 2, and similarly, the third semiconductor region 9b is a second charge accumulation region for accumulating charge generated by the light-receiving section 2. The third semiconductor regions 9a and 9b are arranged opposite to the grating electrode PG. The third semiconductor regions 9a and 9b are rectangular in top view. In this embodiment, the third semiconductor regions 9a and 9b are square.

[0047] In the second semiconductor region 5, in each region separated from and positioned from the grating electrode PG, n-type third semiconductor regions 9c and 9d with high impurity concentrations are formed respectively. The third semiconductor region 9c is a third charge accumulation section for accumulating the charge generated by the light-receiving section 2, and similarly, the third semiconductor region 9d is a fourth charge accumulation section for accumulating the charge generated by the light-receiving section 2. The third semiconductor regions 9c and 9d are arranged opposite to the grating electrode PG.

[0048] The third semiconductor regions 9a and 9c are arranged opposite to the fourth semiconductor region 11a, which will be described later. The third semiconductor regions 9b and 9d are arranged opposite to the fourth semiconductor region 11b, which will be described later. The third semiconductor regions 9c and 9d are rectangular in shape when viewed from above. In this embodiment, the third semiconductor regions 9c and 9d are square in shape.

[0049] In the second semiconductor region 5, in each region separated from and positioned from each grating electrode PG, there are n-type fourth semiconductor regions 11a and 11b with high impurity concentrations. The fourth semiconductor regions 11a and 11b are charge discharge sections for discharging the charge generated by the light-receiving section 2 to the outside. In this embodiment, three pairs of fourth semiconductor regions 11a and 11b are arranged opposite to the grating electrodes PG. The fourth semiconductor regions 11a and 11b are arranged opposite to each other, sandwiching the grating electrodes PG. The fourth semiconductor regions 11a and 11b are rectangular in top view. In this embodiment, the fourth semiconductor regions 11a and 11b are square.

[0050] In addition, in this embodiment, "high impurity concentration" means, for example, an impurity concentration of 1×10 17 cm -3 The degree is above a certain level, and the conductivity type is indicated with a "+". On the other hand, "low impurity concentration" means, for example, 10 × 10⁻⁶. 15 cm -3 Below a certain level, and the conductivity type is indicated by a "-". The thickness / impurity concentration of each semiconductor region is shown below. Semiconductor Region 3 (First Semiconductor Region): Thickness 10–1000 μm / Impurity Concentration 1 × 10⁻⁶ μm 12~10 19 cm -3 Semiconductor Region 5 (Second Semiconductor): Thickness 1–50 μm / Impurity Concentration 1 × 10⁻⁶ 12 ~10 15 cm -3 Semiconductor regions 9a and 9b (3rd generation) and 11a and 11b (4th generation): thickness 0.1–1 μm / impurity concentration 1 × 10⁻⁶. 18 ~10 20 cm -3 .

[0051] On the semiconductor substrate 1 (first semiconductor region 3 and second semiconductor region 5), a reference potential such as a ground potential is applied via a back gate or a through electrode.

[0052] On the insulating layer 7, transfer electrodes TX1, TX2, TX3, and TX4 are disposed corresponding to the grating electrode PG. Transfer electrode TX1 is located between the grating electrode PG and the third semiconductor region 9a, and is disposed separately from the grating electrode PG. Transfer electrode TX2 is located between the grating electrode PG and the third semiconductor region 9b, and is disposed separately from the grating electrode PG.

[0053] The transfer electrode TX3 is located between the grating electrode PC and the third semiconductor region 9c, and is disposed separately from the grating electrode PG. The transfer electrode TX4 is located between the grating electrode PG and the third semiconductor region 9d, and is disposed at a distance from the grating electrode PG. The transfer electrodes TX1 to TX4 are rectangular in shape when viewed from above. In this embodiment, the transfer electrodes TX1 to TX4 are rectangular in shape.

[0054] The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the transfer electrode TX1 Figure 3 In the region located below the transfer electrode TX1, it functions as a charge transfer gate 4a for transferring the charge generated by the light-receiving part 2 to the third semiconductor region 9a, which serves as the first charge storage part. The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the transfer electrode TX2 ( Figure 3 In the region located below the transmission electrode TX2, it functions as a charge transfer gate 4b for transferring the charge generated by the light-receiving part 2 to the third semiconductor region 9b, which is the second charge storage part.

[0055] The region of semiconductor substrate 1 (second semiconductor region 5) corresponding to the transfer electrode TX3 Figure 3In the region located below the transfer electrode TX3, it functions as a charge transfer gate 4c for transferring the charge generated by the light-receiving part 2 to the third semiconductor region 9c, which is the third charge storage part. The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the transfer electrode TX4 ( Figure 3 In the region located below the transfer electrode TX4, it functions as a charge transfer gate 4d for transferring the charge generated by the light-receiving part 2 to the third semiconductor region 9d, which is the fourth charge storage part.

[0056] On the insulating layer 7, a plurality of (here, six) transfer electrodes TX5 are disposed corresponding to the grating electrode PG. A portion of one side of the grating electrode PG among the plurality of transfer electrodes TX5 is located between the grating electrode PG and the fourth semiconductor region 11a, sandwiching transfer electrodes TX1 and TX3, and is disposed separately from the grating electrode PG. The remaining portion of the other side of the grating electrode PG among the plurality of transfer electrodes TX5 is located between the grating electrode PG and the fourth semiconductor region 11b, sandwiching transfer electrodes TX2 and TX4, and is disposed separately from the grating electrode PG. The transfer electrodes TX5 are rectangular in top view. In this embodiment, the transfer electrodes TX5 are rectangular in shape and have the same shape as the transfer electrodes TX1, etc.

[0057] The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the transfer electrode TX5 on one side ( Figure 3 The region located below the transfer electrode TX5 on one side of the semiconductor substrate 1 (the second semiconductor region 5) functions as a discharge gate 6a for transferring the charge generated by the light-receiving part 2 to the discharge gate 6a of the fourth semiconductor region 11a, which is a charge discharge part. The region of the semiconductor substrate 1 (the second semiconductor region 5) corresponding to the transfer electrode TX5 on the other side... Figure 3 In the region located below the transmission electrode TX5 on the other side, it functions as an exhaust gate 6b for transferring the charge generated by the light-receiving section 2 to the fourth semiconductor region 11b, which serves as a charge exhaust section. Thus, the exhaust gates 6a and 6b are exhaust gates for exhausting the charge generated by the light-receiving section 2.

[0058] Furthermore, the length dimensions of the transmission electrodes TX1 to TX5 in the direction opposite to the grating electrode PG, i.e., the gate width of the transmission electrodes TX1 to TX5, are determined according to the distance that the signal charge and the charge that is not needed can be transmitted, in order to cover the area of ​​the grating electrode PG in which the transmission electrodes TX1 to TX5 can transmit signal charge and charge at high speed.

[0059] In the insulating layer 7, contact holes are provided to expose the surface of the first semiconductor region 3. Within the contact holes, conductors 13 are disposed for connecting the third semiconductor regions 9a, 9b and the fourth semiconductor regions 11a, 11b to the outside. The semiconductor substrate is, for example, made of Si, and the insulating layer 7 is, for example, made of SiO2. The grating electrode PG and the transfer electrodes TX1 to TX5 are, for example, made of polysilicon. Alternatively, other materials may be used.

[0060] As described above, the third semiconductor regions 9a and 9b are regions for accumulating the charge generated by the light-receiving portion 2 based on the incident light. The phases of the charge transmission signals applied to the transmission electrodes TX1 to TX4 are different from each other. Light incident on a pixel portion RS is converted into charge within the semiconductor substrate 1 (second semiconductor region 5), and a portion of the charge generated therefrom, as a signal charge, travels along the direction of the transmission electrodes TX1 to TX4 according to the potential gradient formed by the voltages applied to the grating electrode PG and the transmission electrodes TX1 to TX4.

[0061] When a positive potential is applied to the transfer electrodes TX1 to TX4, the potential under the transfer electrodes TX1 to TX4 is lower for electrons than the potential of the semiconductor substrate 1 (second semiconductor region 5) under the grating electrode PG. Negative charges (electrons) are introduced along the direction of the transfer electrodes TX1 to TX4 and accumulate in the potential well formed by the third semiconductor regions 9a to 9d.

[0062] The n-type semiconductor contains positively ionized donors with a positive potential that attracts electrons. When a potential lower than the aforementioned positive potential (ground potential) is applied to the transfer electrodes TX1 to TX4, a potential barrier is generated by the transfer electrodes TX1 to TX4, and the charge generated on the semiconductor substrate 1 is not introduced into the third semiconductor regions 9a to 9d.

[0063] The fourth semiconductor regions 11a and 11b are regions for collecting unwanted charges generated by the light-receiving section 2 according to the incident light and discharging them to the outside. In the light incident on a pixel section RS, a portion of the charges generated in the semiconductor substrate 1 (second semiconductor region 5) are unwanted charges, which travel along the direction of the transmission electrode TX5 according to the potential gradient formed by the voltage applied to the grating electrode PG and the transmission electrode TX5.

[0064] When a positive potential is applied to the transfer electrode TX5, the potential below the transfer electrode TX5 is lower than the potential of the portion of the semiconductor substrate 1 (second semiconductor region 5) below the grating electrode PG, resulting in a decrease in electron potential. Negative charges (electrons) are introduced along the direction of the transfer electrode TX5 and accumulate in the potential well formed by the fourth semiconductor regions 11a and 11b. When a potential lower than the aforementioned positive potential (ground potential) is applied to the transfer electrode TX5, a potential barrier is generated by the transfer electrode TX5, preventing the charges generated in the semiconductor substrate 1 from being introduced into the fourth semiconductor regions 11a and 11b.

[0065] Figure 4 This is a diagram showing the potential distribution near the second main surface 1b of the semiconductor substrate 1 used to illustrate the accumulation of signal charge. Figure 5 This is a diagram showing the potential distribution near the second main surface 1b of a semiconductor substrate 1 used to illustrate a charge-free discharge operation. Figure 4 and Figure 5 In the middle, downward is the positive direction of electric potential. Figure 4 In the image, (a) and (b) show... Figure 2 The potential distribution along the transverse direction of the cross section is shown in (c). Figure 3 The potential distribution along the transverse direction of the cross section. Figure 5 In the middle, (a) shows Figure 2 (b) shows the potential distribution along the transverse direction of the cross section. Figure 3 The potential distribution along the transverse direction of the cross section.

[0066] exist Figure 4 and Figure 5 The diagram shows the potential φ of the region directly below the transfer electrode TX1 (charge transfer gate 4a). TX1 The potential φ of the region directly below the transfer electrode TX2 (charge transfer gate 4b) TX2 The potential φ of the region directly below the transfer electrode TX5 (exit gates 6a, 6b) TX5 The potential φ of the light-receiving part 2 directly below the grating electrode PG PG The potential φ of the third semiconductor region 9a FD1 The potential φ of the third semiconductor region 9b FD2 The potential φ of the fourth semiconductor region 11a OFD1 The potential φ of the fourth semiconductor region 11b OFD2 .

[0067] The potential φ of the light-receiving part 2 directly below the grating electrode PG PG The potential (φ) of the region directly below the adjacent transmission electrodes TX1, TX2 and TX5 when there is no bias voltage. TX1 φTX2 φ TX5 When the reference potential is φ, it is set to be higher than that reference potential. The potential φ of the light-receiving section 2... PG Becomes more specific to the potential φ TX1 φ TX2 φ TX5 The potential distribution in this region is high, resulting in the downward concave shape shown in the attached figure.

[0068] Reference Figure 4 This describes the accumulation of signal charge. When the phase of the charge transmission signal applied to the transmission electrode TX1 is 0 degrees, a positive potential is applied to the transmission electrode TX1, and an inverse potential, i.e., a potential with a phase of 180 degrees (ground potential), is applied to the transmission electrode TX2. In this case, as... Figure 4 As shown in (a), the negative charge e generated by the light-receiving part 2 passes through the potential φ of the region directly below the transmission electrode TX1. TX1 It descends and flows into the potential well of the third semiconductor region 9a.

[0069] On the other hand, the potential φ in the region directly below the transmission electrode TX2 TX2 The potential does not decrease, and the charge does not flow into the potential well of the third semiconductor region 9b. In the third semiconductor regions 9a and 9b, due to the addition of n-type impurities, the potential dips in the positive direction.

[0070] When the phase of the charge transfer signal applied to the transfer electrode TX2 is 0 degrees, a positive potential is applied to the transfer electrode TX2, and an inverse potential is applied to the transfer electrode TX1, that is, a potential with a phase of 180 degrees (ground potential). In this case, as... Figure 4 As shown in (b), the negative charge e generated by the light-receiving part 2 passes through the potential φ of the region directly below the transmission electrode TX2. TX2 The current flows down into the potential well of the third semiconductor region 9b. On the other hand, the potential φ in the region directly below the transfer electrode TX1... TX1 Without descending, the charge does not flow into the potential well of the third semiconductor region 9a. Therefore, the signal charge is collected and stored in the potential well of the third semiconductor region 9b. Thus, a potential tilt is formed here relative to the light-receiving part 2.

[0071] During the period when charge transfer signals with a 180-degree phase difference are applied to transfer electrodes TX1 and TX2, a ground potential is applied to transfer electrode TX5. Therefore, as Figure 4 As shown in (c), the potential φ in the region directly below the transmission electrode TX5 TX5 The charge does not decrease and does not flow into the potential wells of the fourth semiconductor regions 11a and 11b.

[0072] Thus, signal charge is collected and stored in the potential wells of the third semiconductor regions 9a and 9b. The signal charge stored in the potential wells of the third semiconductor regions 9a and 9b is read out to the outside. In addition, in the above example, the description was given for the group of transmission electrodes TX1 and TX2, and the same applies to the group of transmission electrodes TX3 and TX4.

[0073] Sometimes, a predetermined potential is applied to the transfer electrodes TX1 to TX4 as described above, and the region directly below them, namely the charge transfer gates 4a to 4d, is in a state where charge can be transferred to each of the third semiconductor regions 9a to 9d; this is called the charge transfer state. Alternatively, when the charge transfer gates 4a to 4d are in the charge transfer state, it is sometimes referred to as the transfer gates 4a to 4d being in the ON (connected) state.

[0074] Next, refer to Figure 5 This indicates that no charge discharge operation is required. A ground potential is applied to the transfer electrodes TX1 and TX2 (and further, TX3 and TX4). Therefore, as... Figure 5 As shown in (a), the potential φ in the region directly below the transfer electrodes TX1 and TX2 TX1 φ TX2 The charge does not decrease and does not flow into the potential wells of the third semiconductor regions 9a and 9b.

[0075] On the other hand, a positive potential is applied to the transmission electrode TX5. In this case, as... Figure 5 As shown in (b), the negative charge e generated by the light-receiving part 2 passes through the potential φ of the region directly below the transmission electrode TX5. TX5 The charge descends and flows into the potential wells of the fourth semiconductor regions 11a and 11b. Thus, unwanted charge is collected in the potential wells of the fourth semiconductor regions 11a and 11b. The unwanted charge collected in the potential wells of the fourth semiconductor regions 11a and 11b is discharged to the outside.

[0076] Sometimes, a predetermined potential is applied to the transfer electrodes TX5 as described above, and the regions directly below them, namely the discharge gates 6a and 6b, are in a state where charge can be transferred to the fourth semiconductor regions 11a and 11b, which is called the charge discharge state. Alternatively, the discharge gates 6a and 6b being in the charge discharge state is sometimes referred to as the discharge gates 6a and 6b being in the ON state.

[0077] Additionally, the light sensor 50 includes a reset transistor (not shown) disposed in the sensor section 52 (pixel section RS). A reset process is performed by applying a reset voltage to the reset transistor. The reset voltage is a positive voltage based on the potential of the grating electrode PG. As a result, the charge accumulated in the third semiconductor regions 9a-9d, which serve as charge accumulation sections, is discharged to the outside, and charge accumulation ceases.

[0078] Next, refer to Figure 1 The timing generator 53 generates the charge transfer signal S1 mentioned above and provides the charge transfer signal S1 to the transfer gates TX1 to TX5 respectively. In addition, the timing generator 53 generates a drive signal S2 for the light source 51. The timing generator 53 provides the generated drive signal S2 to the delay circuit 54.

[0079] Here, the charge transfer signal S1 and the drive signal S2 are correlated (synchronized). The delay circuit 54 receives the drive signal S2 from the timing generator 53, applies a certain delay to generate a new drive signal S3, and provides this drive signal S3 to the light source 51. The charge transfer signal S1 is correlated (synchronized) with the drive signal S3 via the drive signal S2. The light source 51 is driven by the drive signal S3 and outputs pulsed light. Alternatively, the timing generator 53 and the delay circuit 54 can also be integrated inside the sensor unit 52.

[0080] The above-described photodetector 100 (photosensor 50) is used, for example, for fluorescence lifetime measurement. Figure 6 As shown, in this case, at time T1, the object is irradiated with an excitation light L1 as a pulse light from the light source 51, and the sensor unit 52 receives the fluorescence L2 from the object excited by the excitation light L1. The fluorescence L2 is incident on the sensor unit 52 at time T2 and decays over a predetermined time.

[0081] In the optical sensor 50, multiple time ranges t are set for a specified period starting from the peak of fluorescence L2. k (k = 1, 2, ..., 16), and for each time interval t k The charge generated by the light-receiving section 2 is distributed and transferred to the charge transfer gates 4a to 4d, and stored in each of the third semiconductor regions 9a to 9d, which serve as charge storage sections. Therefore, the timing generator 53 generates a charge transfer signal S1 applied to the charge transfer gates 4a to 4d via the transfer gates TX1 to TX4.

[0082] As mentioned above, here, due to the setting of 16 time ranges t for fluorescence L2 k Therefore, one charge transfer gate, in each of the four frames, at mutually different time ranges t k Set to charge transfer state (ON state). For example, in frame 1, charge transfer gate 4a is in time range t1, charge transfer gate 4b is in time range t5, charge transfer gate 4c is in time range t9, and charge transfer gate 4d is in time range t... 13 Set to ON state. Furthermore, in frame 2, charge transfer gate 4a is in time range t2, charge transfer gate 4b is in time range t6, and charge transfer gate 4c is in time range t...10 The charge transfer gate 4d in the time range t 14 Set to ON state.

[0083] Furthermore, in the third frame, charge transfer gate 4a is in time range t3, charge transfer gate 4b is in time range t7, and charge transfer gate 4c is in time range t8. 11 , charge transfer gate 4d in time range t 15 Set to the ON state. Furthermore, in frame 4, charge transfer gate 4a is in time range t4, charge transfer gate 4b is in time range t8, and charge transfer gate 4c is in time range t... 12 The charge transfer gate 4d in the time range t 14 Set to ON state. Therefore, for all time ranges t... k With the arbitrary charge transfer gate set to the ON state, charge is accumulated in the third semiconductor region 9a to 9d.

[0084] Additionally, the time range t k It can also be based on at least one pair of time ranges t n t m (n and m are distinct numbers from 1 to 16) The settings are partially overlapping. Alternatively, the time range t... k It can also be based on at least one pair of time ranges t n t m The intervals are set to be spaced apart from each other, and within the time range t n With time range t m There is a way to set the time range for setting the discharge gates 6a and 6b to the ON state.

[0085] Next, the specific driving method of the optical sensor 50 will be explained. Figure 7 and Figure 8 yes Figure 1 The timing diagram shown is for the signals generated by the timing generator. Figure 7 , 8 In this context, Pixel_reset represents the reset signal, indicating the timing for performing the reset process. Lightsource is the drive signal S2 provided to the light source 51 (delay circuit 54), indicating the timing for the emission of the excitation light L1.

[0086] Furthermore, VTX1 represents the charge transfer signal applied to charge transfer gate 4a via the transfer gate TX1, VTX2 represents the charge transfer signal applied to charge transfer gate 4b via the transfer gate TX2, VTX3 represents the charge transfer signal applied to charge transfer gate 4c via the transfer gate TX3, and VTX4 represents the charge transfer signal applied to charge transfer gate 4d via the transfer gate TX4. Moreover, VTX5 = Drain represents the charge transfer signal applied to discharge gates 6a and 6b via the transfer gate TX5.

[0087] also, Figure 7 (a) shows frame A1 of frame 1. Figure 7 (b) shows frame A2 of the second frame. Figure 8 (a) shows frame A3 of the third frame. Figure 8 (b) shows frame A4, which is the fourth frame. Frames A1 through A4 are sequential in time. As an example, each of frames A1 through A4 is defined as the period between a pair of reset processes.

[0088] Furthermore, frame A1 contains multiple periods B1. Period B1 is defined as the interval between the emission of excitation light L1 in frame A1. That is, the start time B1a of period B1 is the emission time of one excitation light L1 in frame A1, and the end time B1b of period B1 is the emission time of the next excitation light L1 in frame A1. Frame A2 contains multiple periods B2. Period B2 is defined as the interval between the emission of excitation light L1 in frame A2. That is, the start time B2a of period B2 is the emission time of one excitation light L1 in frame A2, and the end time B2b of period B2 is the emission time of the next excitation light L1 in frame A2.

[0089] Furthermore, frame A3 contains multiple periods B3. Period B3 is defined as the interval between the emission of excitation light L1 in frame A3. That is, the start time B3a of period B3 is the emission time of one excitation light L1 in frame A3, and the end time B3b of period B3 is the emission time of the next excitation light L1 in frame A3. Similarly, frame A4 contains multiple periods B4. Period B4 is defined as the interval between the emission of excitation light L1 in frame A4. That is, the start time B4a of period B4 is the emission time of one excitation light L1 in frame A4, and the end time B4b of period B4 is the emission time of the next excitation light L1 in frame A4.

[0090] Here, periods B1 to B4 are of the same length, and the time difference between the start times of each of frames A1 to A4 is also the same. Therefore, when periods B1 to B4 make their respective start times B1a to B4a consistent, their respective end times B1b to B4b are also consistent (i.e., they all overlap).

[0091] During period B1, which belongs to frame A1, firstly, with charge transfer gate 4a in the charge transfer state (ON state) during time range C1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Next, during period B1, with charge transfer gate 4b in the ON state during time range C2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. Then, during period B1, with charge transfer gate 4c in the ON state during time range C3, charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer gate TX3.

[0092] Subsequently, during period B1, the charge transfer signal VTX4 is applied to the charge transfer gate 4d via the charge transfer gate TX4, such that the charge transfer gate 4d is in the ON state during time range C4. Frame A1 contains multiple (here, consecutive) such periods B1.

[0093] Next, during period B2 belonging to frame A2, firstly, with charge transfer gate 4a in the ON state during time range D1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Then, during period B2, with charge transfer gate 4b in the ON state during time range D2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. Next, during period B2, with charge transfer gate 4c in the ON state during time range D3, charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer gate TX3.

[0094] Subsequently, during period B2, the charge transfer signal VTX4 is applied to the charge transfer gate 4d via the charge transfer gate TX4, such that the charge transfer gate 4d is in the ON state during time range D4. Frame A2 contains multiple (here, consecutive) such periods B2.

[0095] Next, during period B3 belonging to frame A3, firstly, with charge transfer gate 4a in the ON state during time range E1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Then, during period B3, with charge transfer gate 4b in the ON state during time range E2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. Next, during period B3, with charge transfer gate 4c in the ON state during time range E3, charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer gate TX3.

[0096] Subsequently, during period B3, the charge transfer signal VTX4 is applied to the charge transfer gate 4d via the charge transfer gate TX4, such that the charge transfer gate 4d is in the ON state during time range E4. Frame A3 contains multiple (here, consecutive) such periods B3.

[0097] Furthermore, during period B4, which belongs to frame A4, firstly, with charge transfer gate 4a in the ON state during time range F1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Next, during period B4, with charge transfer gate 4b in the ON state during time range F2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. Then, during period B4, with charge transfer gate 4c in the ON state during time range F3, charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer gate TX3.

[0098] Subsequently, during period B4, the charge transfer signal VTX4 is applied to the charge transfer gate 4d via the charge transfer gate TX4, such that the charge transfer gate 4d is in the ON state during time range F4. Frame A4 contains multiple (here, consecutive) such periods B4. Furthermore, each of the time ranges C1–C4, D1–D4, E1–E4, and F1–F4 is of the same length.

[0099] As described above, the timing generator 53 generates a charge transfer signal in such a way that the charge transfer gate is set to charge transfer state in the first time range of the first period of the nth frame (n is an integer greater than or equal to 1), and the charge transfer gate is set to charge transfer state in the second time range of the second period of the mth frame (m is an integer greater than or equal to 1 that is different from n).

[0100] Here, as an example, n and m are consecutive integers (i.e., m = n ± 1). Therefore, as an example, when n = 1 and m = 2, the timing generator 53 generates the charge transfer signal VTX1 by setting the charge transfer gate 4a to the ON state during the time range (first time range) C1 of the period (first period) B1 belonging to frame A1, and setting the charge transfer gate 4a to the ON state during the time range (second time range) D1 of the period (second period) B2 belonging to frame A2. Other combinations of n and m are the same.

[0101] On the other hand, the timing generator 53 also generates charge transfer signals VTX2 to VTX4 for charge transfer gates 4b to 4c in the same way. As an example, when n=1, m=2, and focusing on charge transfer gate 4b, the timing generator 53 generates charge transfer signal VTX2 in such a way that the charge transfer gate 4b is set to the ON state during the time range (third time range) C2 of the period B1 belonging to frame A1 (first period), and the charge transfer gate 4b is set to the ON state during the time range (fourth time range) D2 of the period B2 belonging to frame A2 (second period). The same applies when the first charge transfer gate and the second charge transfer gate are set to charge transfer gates 4c and 4d.

[0102] Here, the timing generator 53 generates charge transfer signals VTX1 to VTX4 in such a way that a portion of the first time range overlaps with a portion of the second time range when the start time of the first period coincides with the start time of the second period. Furthermore, the timing generator 53 generates charge transfer signals VTX1 to VTX4 in such a way that a portion of the third time range overlaps with a portion of the fourth time range when the start time of the first period coincides with the start time of the second period.

[0103] As an example, when n=1, m=2, the first time range is set as time range C1, and the second time range is set as time range D1, the timing generator 53 generates the charge transfer signal VTX1 in such a way that the start time B1a of the period (first period) B1 belonging to frame A1 coincides with the start time B2a of the period (second period) B2 belonging to frame A2, and the time range (first time range) C1 within period B1 and the time range (second time range) D1 within period B2 only partially overlap. Furthermore, the offset between time range C1 and time range D1, as an example, is half the time of time ranges C1 and D1.

[0104] Furthermore, when n=1, m=2, the third time range is set as time range C2, and the fourth time range is set as time range D2, the timing generator 53 generates the charge transfer signal VTX2 in such a way that the start time B1a of the period (first period) B1 belonging to frame A1 coincides with the start time B2a of the period (second period) B2 belonging to frame A2, and the time range (third time range) C2 within period B1 and the time range (fourth time range) D2 within period B2 only partially overlap. Additionally, the offset between time range C2 and time range D2, as an example, is also half the time of time ranges C2 and D2. The same applies to other combinations of n and m and combinations of time ranges.

[0105] As described above, when charge transfer gate 4a is used as the first charge transfer gate and charge transfer gate 4b is used as the second charge transfer gate among the multiple charge transfer gates 4a to 4d, the above example can be put in other words as follows. That is, the timing generator 53 sets the first charge transfer gate of the first charge transfer gate and the second charge transfer gate to the ON state in the first time range (time range C1), which is one of a pair of overlapping time ranges, and sets the first charge transfer gate of the first charge transfer gate and the second charge transfer gate to the ON state in the second time range (time range D1), which is the other of a pair of overlapping time ranges.

[0106] At this time, the timing generator 53 further generates the charge transfer signal VTX2 by setting the second charge transfer gate to the ON state in the third time range (time range C2), which is one of the overlapping pairs of time ranges, and in the fourth time range (time range D2), which is the other of the overlapping pairs of time ranges. Furthermore, which of the charge transfer gates 4a to 4d is used as the first charge transfer gate and the second charge transfer gate is arbitrary.

[0107] Furthermore, the offsets during the ON period, such as the offset between time range C1 and time range D1 and the offset between time range C2 and time range D2, are not limited to 1 / 2 of each time range C1, C2, D1, D2, etc., but can be arbitrary, such as 1 / 4, 1 / 8, or 3 / 4.

[0108] Furthermore, the timing generator 53 generates a charge transfer signal by setting the charge transfer gate to a charge transfer state within overlapping time ranges when the start times of multiple periods are made consistent across a single frame. For example, the timing generator 53 generates a charge transfer signal VTX1 by setting the charge transfer gate 4a to an ON state within overlapping time ranges C1 when the start times B1a of multiple periods B1 are made consistent across frame A1. This allows charge accumulation in the charge storage section. The same applies to other frames, periods, and charge transfer gates.

[0109] As explained above, in the light sensor 50 and the driving method of the light sensor 50, the charge transfer signal applied to the charge transfer gate for transferring the charge generated by the light receiving unit 2 is generated in such a way that the charge transfer gate (e.g., charge transfer gate 4a) is set to the ON state in the first time range (e.g., time range C1) of the first period (e.g., period B1) belonging to the nth frame (e.g., frame A1), and the charge transfer gate (e.g., charge transfer gate 4a) is set to the ON state in the second time range (e.g., time range D1) of the second period (e.g., period B2) belonging to the mth frame (e.g., frame A2).

[0110] The first and second time ranges are the ON periods of the charge transfer gate. Furthermore, when the start time of the first period (e.g., start time B1a) coincides with the start time of the second period (e.g., B2a), a portion of the first time range overlaps with a portion of the second time range. Thus, if the ON periods of the charge transfer gate overlap between different frames, phenomena that repeatedly occur at least corresponding to each frame (e.g., fluorescence L2 corresponding to the excitation light L1 irradiated in each period) can be captured at a time interval corresponding to the offset of the ON period (e.g., half of time ranges C1 and D1). That is, temporal resolution and detection accuracy can be improved.

[0111] Furthermore, while the device structure described in Patent Document 1, as mentioned above, is also considered feasible if the light-receiving part is a single unit, the circuit size is enormous and impractical when the light-receiving parts are arranged in one or two dimensions. In contrast, the light sensor 50 according to this embodiment achieves high-precision detection through timing control of the charge transfer gates 4a to 4d. Therefore, even when multiple light-receiving parts 2 are arranged in an array, the sensor structure can be kept simple, thus ensuring practicality.

[0112] Furthermore, in the optical sensor 50, the nth frame and the mth frame are consecutive frames. Thus, the partially overlapping structure between consecutive frames during the ON period (e.g., between frame A1 and frame A2) is effective for slightly varying and recurring phenomena. This is because the variation in this phenomenon between frames becomes relatively small compared to cases where the interval between the partially overlapping frames during the ON period is longer.

[0113] Furthermore, in the light sensor 50, the timing generator 53 generates a charge transfer signal (e.g., charge transfer signal VTX1) by setting the first charge transfer gate (e.g., charge transfer gate 4a) to the ON state within an overlapping range (e.g., time range C1) when the start time (e.g., start time B1a) of the period is consistent across multiple periods (e.g., period B1). In this case, charge accumulation is possible within one frame.

[0114] Furthermore, in the light sensor 50, the timing generator 53 generates a charge transfer signal (e.g., charge transfer signal VTX1) by setting one of the first charge transfer gate (e.g., charge transfer gate 4a) and the second charge transfer gate (e.g., charge transfer gate 4b) to the ON state during a first time range (e.g., time range C1), and by setting one of the first charge transfer gate and the second charge transfer gate to the ON state during a second time range (e.g., time range D1). Thus, in the light sensor 50 equipped with multiple charge transfer gates 4a to 4d, the ON periods of at least the same charge transfer gate can overlap between the nth frame and the mth frame.

[0115] Furthermore, in the optical sensor 50, the timing generator 53 further generates a charge transfer signal (e.g., charge transfer gate 4b) applied to the second charge transfer gate in a manner that the second charge transfer gate is set to the ON state in a third time range (e.g., time range C2) of the first period (e.g., period B1) and in a fourth time range (e.g., time range D2) of the second period (e.g., period B2). Moreover, when the start time of the first period (e.g., start time B1a) coincides with the start time of the second period (e.g., start time B2a), a portion of the third time range overlaps with a portion of the fourth time range. In this way, for the optical sensor 50 equipped with multiple charge transfer gates, by overlapping a portion of the ON periods of each charge transfer gate, the temporal resolution can be improved and the frame count can be reduced.

[0116] Furthermore, in the light sensor 50, the timing generator 53 further generates a drive signal S2 for the light source 51 to periodically output excitation light L1. Moreover, the start times (e.g., start times B1a and B2a) of the first period (e.g., period B1) and the second period (e.g., period B2) are synchronized with the timing of the excitation light L1 output by the light source 51. Therefore, it is possible to improve the temporal resolution and detection accuracy for phenomena (e.g., fluorescence L2) that are repeatedly generated corresponding to the excitation light L1 from the light source 51.

[0117] Furthermore, the optical sensor 50 according to the first embodiment, like the optical sensor according to the second embodiment described later, can control the ON period of the discharge gates 6a and 6b. That is, as an example, Figure 7 In (a), the timing generator 53 sets the discharge gates 6a and 6b to the ON state during a time range C1 (the fifth time range) during the ON period of the charge transfer gate 4a and a time range C2 (the sixth time range) that is separated from the time range C1 by an interval from the time range C1 during the ON period of the charge transfer gate 4b. When the fifth time range is set to the first time range described above, and the sixth time range is set to the third time range described above, the seventh time range can be considered as the time range between the first and third time ranges. The same applies to the variations according to the first embodiment described below. Accordingly, the readout residue of the charge generated by the light-receiving section 2 can be discharged, resulting in further improvement in detection accuracy.

[0118] [Modifications according to the first embodiment]

[0119] The first embodiment described above illustrates one aspect of this disclosure. Therefore, this disclosure is not limited to the above-described aspect, but can be modified in any way.

[0120] Figure 9 This is a timing diagram illustrating a variation of the first embodiment. For example... Figure 9 As shown, in this example, when the start time B1a of period B1 coincides with the start time B2a of period B2, the time range C1 and the time range D2 only partially overlap. That is, in this example, when the charge transfer gate 4a is used as the first charge transfer gate and the charge transfer gate 4b is used as the second charge transfer gate, it can be expressed in the following other way.

[0121] That is, in this example, the timing generator 53 generates charge transfer signals VTX1 and VTX2 by setting one of the first charge transfer gate and the second charge transfer gate to the ON state in the first time range (time range C1), which is one of a pair of overlapping time ranges, and setting the other of the first charge transfer gate and the second charge transfer gate to the ON state in the second time range, which is the other of a pair of overlapping time ranges. In this way, in the optical sensor 50 equipped with multiple charge transfer gates 4a to 4d, the ON periods of at least the different charge transfer gates can overlap in the nth frame and the mth frame.

[0122] Furthermore, in the above embodiment, the ON periods (time ranges C3 and D3) of charge transfer gate 4c and the ON periods (time ranges C4 and D4) of charge transfer gate 4d also overlap across multiple frames. However, in Figure 9 In the example, the ON periods of charge transfer gate 4c and the ON periods of charge transfer gate 4d do not overlap. Thus, in the optical sensor 50, at least one pair of ON periods of charge transfer gates 4a to 4d overlaps between at least one pair of frames.

[0123] For example, in the first embodiment described above, the timing generator 53 was described as generating a charge transfer signal in a manner where the ON periods of specific charge transfer gates overlap between consecutive frames (i.e., when m = n ± 1). However, the manner in which the charge transfer signal is generated is not limited to this. The timing generator 53 may also generate a charge transfer signal in a manner where the ON periods of specific charge transfer gates overlap between a pair of frames that are separated by other frames and have intervals between them.

[0124] As an example of this situation, let n = 2, m = 4, set the first time range as time range D3, and set the second time range as time range F3. The timing generator 53 generates the charge transfer signal VTX3 in such a manner that the start time B2a of the period (first period) B2 belonging to frame A2 coincides with the start time B4a of the period (second period) B4 belonging to frame A4, and the time range (first time range) D3 within period B2 and the time range (second time range) F3 within period B4 only partially overlap. In this case, the ON period of the charge transfer gate 4c partially overlaps between frames A2 and A4.

[0125] Thus, in the optical sensor 50, during the ON period of at least one charge transfer gate, there needs to be at least one partial overlap between at least two frames. Alternatively, the ON periods of specific charge transfer gates can partially overlap between three or more frames.

[0126] Furthermore, while the first embodiment described above illustrates the use of the photodetector 100 for fluorescence lifetime measurement, it can also be applied to other phenomena. In cases where irradiation with excitation light L1 is not required, B1 to B4 may not be synchronized with the timing of the excitation light L1 output by the light source 51.

[0127] Furthermore, in the first embodiment described above, the light sensor 50 is described as including four charge transfer gates 4a to 4c for each of the pixel units RS. The light sensor 50 may include at least one charge transfer gate for each of the pixel units RS (for example, it may also include eight charge transfer gates).

[0128] Furthermore, frames A1 to A4 are not limited to the period between a pair of reset processes, but can be set arbitrarily. For example, frames A1 to A4 can also be set based on the readout of the signal from the charge storage section (third semiconductor regions 9a to 9d), and when the light sensor 50 is a motion sensor, one image can be set as one frame. Moreover, the light sensor 50 and the driving method of the light sensor 50 according to the first embodiment can also be used to detect non-repeating phenomena other than repetitive phenomena.

[0129] [Second Implementation]

[0130] Next, the second embodiment will be described. Figure 10 This is a top view showing a portion (pixel section of the light sensor) of the light detection apparatus according to the second embodiment. The overall structure of the light detection apparatus according to the second embodiment is the same as that of the light detection apparatus 100 according to the first embodiment. The light detection apparatus according to the second embodiment differs from the first embodiment in that the light sensor 50 includes two charge transfer gates 4a, 4b in each of the pixel sections RS, in the charge transfer signal generated by the timing generator 53 and the driving method. Figure 10 The diagram shows the charge transfer gates TX1 and TX2 corresponding to the two charge transfer gates 4a and 4b.

[0131] Figure 11 and Figure 12 This is a timing diagram related to the second embodiment. Figure 11 (a) shows frame 1, G1. Figure 11 (b) shows frame 2, G2. Figure 11 (a) shows frame G3, Figure 12 (b) shows frame G4, which is the fourth frame. Frames G1 through G4 are sequential in time. As an example, each of frames G1 through G4 is defined as the period between a pair of reset processes.

[0132] Frame G1 contains multiple periods H1. Period H1 is defined as the interval between the emission of excitation light L1 (in the case of fluorescence lifetime measurement) in frame G1. That is, the start time H1a of period H1 is the emission time of one excitation light L1 in frame G1, and the end time H1b of period H1 is the emission time of the next excitation light L1 in frame G1. Frame G2 contains multiple periods H2. Period H2 is defined as the interval between the emission of excitation light L1 in frame G2. That is, the start time H2a of period H2 is the emission time of one excitation light L1 in frame G2, and the end time H2b of period H2 is the emission time of the next excitation light L1 in frame G2.

[0133] Furthermore, frame G3 contains multiple periods H3. Period H3 is defined as the interval between the emission of excitation light L1 in frame G3. That is, the start time H3a of period H3 is the emission time of one excitation light L1 in frame G3, and the end time H3b of period H3 is the emission time of the next excitation light L1 in frame G3. Similarly, frame G4 contains multiple periods H4. Period H4 is defined as the interval between the emission of excitation light L1 in frame G4. That is, the start time H4a of period H4 is the emission time of one excitation light L1 in frame G4, and the end time H4b of period H4 is the emission time of the next excitation light L1 in frame G4.

[0134] Here, periods H1 to H4 are of the same length, and the time difference between the start times of each of frames G1 to G4 is also the same. Therefore, when the start times H1a to H4a of periods H1 to H4 are consistent, their end times H1b to H4b are also consistent (i.e., they all overlap).

[0135] During period H1, which belongs to frame G1, firstly, the charge transfer signal VTX1 is applied to the charge transfer gate 4a via the transfer gate TX1, such that the charge transfer gate 4a is in the charge transfer state (ON state) during time range J1. Next, during period H1, the charge transfer signal VTX2 is applied to the charge transfer gate 4b via the transfer gate TX2, such that the charge transfer gate 4b is in the ON state during time range J2. On the other hand, during period H1, the charge transfer signal VTX5 = Drain is applied to the discharge gates 6a and 6b via the transfer gate TX5, such that the discharge gates 6a and 6b are in the ON state during time range J3, which is between time range J1 and time range J2. Frame G1 contains multiple (here, consecutive) such periods H1.

[0136] Here, as an example, the end time of time range J1 coincides with the start time of time range J3, and the end time of time range J3 coincides with the start time of time range J2. That is, here, in all time ranges between time range J1 when charge transfer gate 4a is in the ON state and time range J2 when charge transfer gate 4b is in the ON state, discharge gates 6a and 6b are set to the ON state.

[0137] Next, during period H2 belonging to frame G2, firstly, with charge transfer gate 4a in the ON state during time range K1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Then, during period H2, with charge transfer gate 4b in the ON state during time range K2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. On the other hand, during period H2, with discharge gates 6a and 6b in the ON state during time range K3 between time ranges K1 and K2, charge transfer signal VTX5 = Drain is applied to discharge gates 6a and 6b via transfer gate TX5. Frame G2 contains multiple (here, consecutive) such periods H2.

[0138] Here, as an example, the end time of time range K1 coincides with the start time of time range K3, and the end time of time range K3 coincides with the start time of time range K2. That is, here, in all time ranges between time range K1 when charge transfer gate 4a is in the ON state and time range K2 when charge transfer gate 4b is in the ON state, discharge gates 6a and 6b are set to the ON state.

[0139] Next, during period H3 belonging to frame G3, firstly, with charge transfer gate 4a in the ON state during time range M1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Then, during period H3, with charge transfer gate 4b in the ON state during time range M2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. On the other hand, during period H3, with discharge gates 6a and 6b in the ON state during time range M3 between time ranges M1 and M2, charge transfer signal VTX5 = Drain is applied to discharge gates 6a and 6b via transfer gate TX5. Frame G3 contains multiple (here, consecutive) such periods H3.

[0140] Here, as an example, the end time of time range M1 coincides with the start time of time range M3, and the end time of time range M3 coincides with the start time of time range M2. That is, here, in all time ranges between time range M1 when charge transfer gate 4a is in the ON state and time range M2 when charge transfer gate 4b is in the ON state, discharge gates 6a and 6b are set to the ON state.

[0141] Furthermore, during period H4 belonging to frame G4, firstly, with charge transfer gate 4a in the ON state during time range N1, charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer gate TX1. Next, during period H4, with charge transfer gate 4b in the ON state during time range N2, charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer gate TX2. On the other hand, during period H4, with discharge gates 6a and 6b in the ON state during time range N3 (between time range N1 and time range N2), charge transfer signal VTX5 = Drain is applied to discharge gates 6a and 6b via transfer gate TX5. Frame G4 contains multiple (here, consecutive) such periods H4. Additionally, time ranges J1, J2, K1, K2, M1, M2, and N1, N2 are each of the same length.

[0142] Here, as an example, the end time of time range N1 coincides with the start time of time range N3, and the end time of time range N3 coincides with the start time of time range N2. That is, here, in all time ranges between time range N1 when charge transfer gate 4a is in the ON state and time range N2 when charge transfer gate 4b is in the ON state, discharge gates 6a and 6b are set to the ON state.

[0143] As described above, here, the timing generator 53 generates a charge transfer signal in such a manner that the first charge transfer gate is set to charge transfer state in the first time range, the second charge transfer gate is set to charge transfer state in the second time range which is separated from the first time range, and the discharge gate is set to charge discharge state in the third time range between the first time range and the second time range.

[0144] As an example, when focusing on frame G1, the timing generator 53 generates charge transfer signals VTX1, VTX2, and VTX5 = Drain by setting the charge transfer gate 4a (first charge transfer gate) to the ON state in time range J1 (first time range), setting the charge transfer gate 4b (second charge transfer gate) to the ON state in time range J2 (second time range), which is separated from time range J1, and setting the discharge gates 6a and 6b to the ON state in time range J3 (third time range) between time range J1 and time range J2. The same applies to other frames G2 to G4.

[0145] Here, when the time ranges J1, K1, M1, and N1 for the charge transfer gate 4a to be ON are defined as the first time range, the time ranges J2, K2, M2, and N2 for the charge transfer gate 4b to be ON are defined as the second time range, and the time ranges J3, K3, M3, and N3 for the discharge gates 6a and 6b to be ON are defined as the third time range, then all frames G1 to G4 include the first, second, and third time ranges. Furthermore, as an example, when the start time of frame G1 coincides with the start time of frame G2, time range K2 lies between time ranges J1 and J2. The same applies to frames G2 and G3, and frames G3 and G4.

[0146] That is, here, the timing generator 53 generates a charge transfer signal in a manner that includes a first time range, a second time range, and a third time range in each of the multiple frames, and in a manner that, when the start time of the nth (n is an integer greater than or equal to 1) frame is consistent with that of the mth (m is an integer greater than or equal to 1 different from n) frame, the first time range of the mth frame is located between the first time range of the nth frame and the second time range of the nth frame.

[0147] Furthermore, the timing generator 53 generates charge transfer signals by setting the first charge transfer gate and the second charge transfer gate to the charge transfer state within overlapping time ranges when the start times of multiple periods are consistent across a single frame. For example, the timing generator 53 generates charge transfer signals VTX1 and VTX2 by setting the charge transfer gates 4a and 4b to the ON state within overlapping time ranges J1 and J2 when the start times H1a of multiple periods H1 are consistent across frame G1. This allows charge accumulation in the charge accumulation section. The same applies to other frames and periods.

[0148] As explained above, in the optical sensor 50 and its driving method according to the second embodiment, the charge transfer signals VTX1 and VTX2 applied to the charge transfer gates 4a and 4b for transferring the charge generated by the light-receiving section 2 are applied as follows: During a first time range (e.g., time range J1), the charge transfer gate 4a is set to the ON state; during a second time range (e.g., time range J2) spaced apart from the first time range, the charge transfer gate 4b is set to the ON state; and during a third time range (e.g., time range J3) between the first and second time ranges, the discharge gates 6a and 6b are set to the ON state. By spacing the ON periods of the charge transfer gates 4a and 4b and providing a charge discharge period in between, residual readout charge generated by the light-receiving section 2 can be discharged. As a result, detection accuracy can be improved.

[0149] Furthermore, in the optical sensor 50 and timing generator 53 of the second embodiment, charge transfer signals VTX1 and VTX2 are generated in a manner that includes a first time range, a second time range, and a third time range in each of the multiple frames, and in a manner that, when the start time of the nth frame (e.g., frame G1) coincides with that of the mth frame (e.g., frame G2), the first time range (e.g., time range K2) of the mth frame is located between the first time range (e.g., time range J1) and the second time range (e.g., time range J2) of the nth frame. Therefore, by arranging the ON periods of the charge transfer gates 4a and 4b more densely across multiple frames, the detection accuracy can be further improved.

[0150] Furthermore, in the optical sensor 50 according to the second embodiment, the timing generator 53 generates charge transfer signals VTX1 and VTX2 such that, within one frame (e.g., frame G1), when the start times (e.g., start times H1a) of multiple periods (e.g., period H1) are consistent across the overlapping time range, the charge transfer gates 4a and 4b are set to the ONN state. Therefore, charge accumulation can be performed within one frame.

[0151] [Modifications according to the second embodiment]

[0152] The second embodiment described above illustrates one aspect of the present invention. Therefore, this disclosure is not limited to the above-described embodiment, but can be modified in any way.

[0153] For example, in the second embodiment described above, the light sensor 50 is described as including two charge transfer gates 4a and 4b for each pixel unit RS. The light sensor 50 may also include, for example, four charge transfer gates 4a to 4d for each pixel unit RS. In this case, with respect to at least one pair (or all of the four charge transfer gates 4a to 4d) and the discharge gates 6a and 6b, the above-described relationship exists: the timing generator 53 generates a charge transfer signal such that the first charge transfer gate is set to a charge transfer state in a first time range, the second charge transfer gate is set to a charge transfer state in a second time range separated from the first time range, and the discharge gate is set to a charge discharge state in a third time range between the first and second time ranges.

[0154] Furthermore, in the second embodiment described above, an example was given where the discharge gates 6a and 6b were set to the ON state for all time periods between the first time period (e.g., time period J1) when the charge transfer gate 4a was in the ON state and the second time period (e.g., time period J2) when the charge transfer gate 4b was in the ON state. However, the timing generator 53 may also generate charge transfer signals VTX1, VTX2, VTX5 = Drain by setting the discharge gates 6a and 6b to the ON state for a portion of the time period between the first time period (e.g., time period J1) when the first charge transfer gate (e.g., charge transfer gate 4a) was in the ON state and the second time period (e.g., time period J2) when the second charge transfer gate (e.g., charge transfer gate 4b) was in the ON state. In this case, the discharge gates 6a and 6b can be set to the ON state until just before the second charge transfer gate is about to become ON.

[0155] Furthermore, in the second embodiment described above, it was explained that the timing generator 53 generates charge transfer signals VTX1, VTX2, VTX5 = Drain across multiple frames G1 to G4, but it can also be a single frame.

[0156] Furthermore, in the second embodiment described above, when applied to phenomena where irradiation by excitation light L1 is not required, H1 to H4 may not be synchronized with the timing of the excitation light L1 output by the light source 51. In particular, the optical sensor 50 and its driving method described in the second embodiment can also improve detection accuracy for non-recurring phenomena other than recurring phenomena by eliminating readout residue from the light-receiving section 2.

[0157] Furthermore, frames G1 to G4 are not limited to the period between a pair of reset processes, but can be set arbitrarily. For example, frames G1 to G4 can also be set based on the readout of the signal from the charge storage section (third semiconductor regions 9a to 9d), and when the light sensor 50 is a motion sensor, one image can be set as one frame.

[0158] Furthermore, all or a portion of all matters relating to the operation / control of the discharge gates 6a and 6b in the second embodiment and its variations can be arbitrarily selected and applied to the optical sensor 50 in the first embodiment.

[0159] [Common variations of the first and second embodiments]

[0160] In the aforementioned optical sensor 50, the signal can be read from the charge transfer gates 4a to 4d and stored in the charge storage section (third semiconductor region 9a to 9d) within one frame, or it can be read to the subsequent circuitry each time the charge transfer gates 4a to 4d are turned on, regardless of whether there is a charge storage section.

[0161] Furthermore, in the aforementioned light sensor 50, a grating structure is exemplified as the light-receiving part 2. However, the light-receiving part 2 is not limited to a grating structure and may be other structures. As an example, it may also be as follows: Figure 13 As shown in (a), the light-receiving part 2 is an embedded PD structure. In this case, the light-receiving part 2 is composed of a p-type diode disposed on the second main surface 1b side of the second semiconductor region 5. + It consists of a type-n semiconductor region 2B and an n-type semiconductor region 2A disposed directly below the second semiconductor region 5.

[0162] In this case, in order to achieve high-speed charge transfer, a potential tilt can be provided in the light-receiving part 2. As an example of a structure to achieve this purpose, the following can be listed: Figure 13 As shown in (b) and (c), a structure with an electric field gradient is achieved by making the n-type semiconductor region 2A include, for example, a plurality (here, three) of n-type semiconductor regions 21, 22, and 23 arranged in such a manner that the impurity concentration increases as it moves toward the charge transfer gate 4a. Furthermore, Figure 13 (b) is a schematic cross-sectional view. Figure 13 (c) is the top view.

[0163] Furthermore, the inclined structure used to set an electric potential in the light-receiving part 2 can also be, for example, Figure 14 As shown, the n-type semiconductor region 2A includes: a pair of n-type semiconductor regions 25, 26, and semiconductor regions 25, 26 sandwiching and, for example, expanding in width W as they move toward the charge transfer gate 4a. + The semiconductor region 27 has a structure with an electric field gradient. Additionally, Figure 14 This is a top view from the second main plane 1b side.

[0164] Furthermore, the aforementioned light sensor 50 can be used, for example, for motion detection. In this case, the light sensor 50 can detect moving objects by acquiring the difference between the shutter signal of the nth frame and other shutter signals of the same nth frame (or, the shutter signal of the (n+1)th frame) and utilizing the fact that only the RS of the moved pixel changes. In this case, the detection accuracy can also be improved by controlling (driving method) the charge transfer gates 4a-4d and the discharge gates 6a, 6b as described above. Moreover, the light generated by the light source 51 is not limited to pulsed light such as the excitation light L1 described above, and can be set to any waveform such as a sine wave or a sawtooth wave.

[0165] Industrial availability

[0166] Provides optical sensors and driving methods for optical sensors that can improve detection accuracy.

[0167] Explanation of reference numerals in the attached figures

[0168] 2… Light receiving section, 4a~4d… Charge transfer gates (first charge transfer gate, second charge transfer gate), 6a, 6b… Exhaust gates, 50… Photosensitive sensor, 53… Timing generator (signal generation section), A1~A4, G1~G4… Frames, B1~B4… Periods (first period, second period), H1~H4… Periods (first period, second period), C1~C4, D1~D4, E1~E4, F1~F4… Time ranges (first time range, second time range), J1, J2, K1, K2, M1, M2, N1, N2… Time ranges (first time range, second time range), J3, K3, M3, N3… Time ranges (third time range).

Claims

1. An optical sensor, wherein, have: A light-receiving part that generates an electric charge based on incident light from an object excited by excitation light; A charge transfer gate for transmitting the charge generated by the light-receiving part; A signal generation unit for generating a charge transfer signal applied to the charge transfer gate; and An exhaust gate for discharging the charge generated by the light-receiving part. The signal generation unit, The charge transfer signal is generated such that the charge transfer gate is set to the charge transfer state during the first time range of the first period belonging to the nth frame, and during the second time range of the second period belonging to the mth frame, the charge transfer gate is set to the charge transfer state, wherein n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1 that is different from n. When the start time of the first period coincides with the start time of the second period, a portion of the first time range overlaps with a portion of the second time range. When the start time of the first period coincides with the start time of the second period, a portion of the time range during which the discharge gate is in a non-charge discharge state overlaps with the first time range and the second time range. The start time of the first period is the emission time of the excitation light in the nth frame. The start time of the second period is the emission time of the excitation light in the m-th frame. The signal generation unit generates the charge transfer signal by setting the charge transfer gate to a charge transfer state within an overlapping time range when the start times of multiple periods are made consistent across one frame.

2. The optical sensor according to claim 1, wherein, The nth frame and the mth frame are consecutive frames.

3. The optical sensor according to claim 1, wherein, The charge transfer gate includes: a first charge transfer gate and a second charge transfer gate. The signal generation unit generates the charge transfer signal in such a manner that, during the first time range, one of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state, and during the second time range, the same one of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state.

4. The optical sensor according to claim 2, wherein, The charge transfer gate includes: a first charge transfer gate and a second charge transfer gate. The signal generation unit generates the charge transfer signal in such a manner that, during the first time range, one of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state, and during the second time range, the same one of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state.

5. The optical sensor according to claim 1 or 2, wherein, The charge transfer gate includes: a first charge transfer gate and a second charge transfer gate. The signal generation unit generates the charge transfer signal in such a manner that, during the first time range, one of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state, and during the second time range, the other of the first charge transfer gate and the second charge transfer gate is set to a charge transfer state.

6. The optical sensor according to any one of claims 1 to 4, wherein, The charge transfer gate includes: a first charge transfer gate and a second charge transfer gate. The signal generation unit generates the charge transfer signal by setting the first charge transfer gate to a charge transfer state during the first time period, setting the first charge transfer gate to a charge transfer state during the second time period, setting the second charge transfer gate to a charge transfer state during the third time period of the first period, and setting the second charge transfer gate to a charge transfer state during the fourth time period of the second period. When the start time of the first period is made to coincide with the start time of the second period, a portion of the third time range overlaps with a portion of the fourth time range.

7. The optical sensor according to any one of claims 1 to 4, wherein, It includes: a discharge gate for discharging the charge generated by the light-receiving part. The signal generation unit generates the charge transfer signal by setting the charge transfer gate to a charge transfer state in a 5th time range, setting the charge transfer gate to a charge transfer state in a 6th time range spaced apart from the 5th time range, and setting the discharge gate to a charge discharge state in a 7th time range between the 5th and 6th time ranges.

8. The optical sensor according to claim 5, wherein, It includes: a discharge gate for discharging the charge generated by the light-receiving part. The signal generation unit generates the charge transfer signal by setting the charge transfer gate to a charge transfer state in a 5th time range, setting the charge transfer gate to a charge transfer state in a 6th time range spaced apart from the 5th time range, and setting the discharge gate to a charge discharge state in a 7th time range between the 5th and 6th time ranges.

9. The optical sensor according to claim 6, wherein, It includes: a discharge gate for discharging the charge generated by the light-receiving part. The signal generation unit generates the charge transfer signal by setting the charge transfer gate to a charge transfer state in a 5th time range, setting the charge transfer gate to a charge transfer state in a 6th time range spaced apart from the 5th time range, and setting the discharge gate to a charge discharge state in a 7th time range between the 5th and 6th time ranges.

10. The optical sensor according to any one of claims 1 to 4, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

11. The optical sensor according to claim 5, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

12. The optical sensor according to claim 6, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

13. The optical sensor according to claim 7, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

14. The optical sensor according to claim 8, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

15. The optical sensor according to claim 9, wherein, The signal generation unit also generates a signal for the light source to periodically output light. The start times of the first and second periods are synchronized with the timing of the light output by the light source.

16. A driving method for an optical sensor, It is a driving method for an optical sensor having a light-receiving section that generates charge based on incident light from an object excited by excitation light, a charge transfer gate for transferring the charge generated by the light-receiving section, and an discharge gate for discharging the charge generated by the light-receiving section. The driving method of the optical sensor, A charge transfer signal is generated by setting the charge transfer gate to a charge transfer state during a first time range within the first period of the nth frame, and again during a second time range within the second period of the mth frame, wherein... n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1 that is different from n. When the start time of the first period coincides with the start time of the second period, a portion of the first time range overlaps with a portion of the second time range. When the start time of the first period coincides with the start time of the second period, a portion of the time range during which the discharge gate is in a non-charge discharge state overlaps with the first time range and the second time range. The start time of the first period is the emission time of the excitation light in the nth frame. The start time of the second period is the emission time of the excitation light in the m-th frame. The charge transfer signal is generated in such a way that the charge transfer gate is set to charge transfer state within an overlapping time range when the start time of the period is made consistent across multiple periods within one frame.

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