Sensor device and related methods and systems

Abstract

Embodiments of the present disclosure relate to sensor devices and related methods and systems. A sensor includes a detection circuit device and a control circuit device coupled to the detection circuit device. The detection circuit device generates a detection signal indicative of a detected physical quantity. In operation, the control circuit device receives the detection signal and a frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is temporally aligned with the digital output signal.

Description

Technical Field

[0001] The present disclosure relates to sensors, for example, sensors obtained in MEMS (Micro Electro Mechanical Systems) technology. Background Art

[0002] As is well known, electronic devices incorporating a plurality of sensors are widely used, for example in the consumer electronics field as well as in the industrial and automotive fields, each sensor being configured to detect one or more respective physical quantities for operating the respective electronic device.

[0003] For example, the sensor may be an accelerometer, a gyroscope, a temperature sensor, a pressure sensor, a resistance sensor, a mechanical stress sensor, a strain gauge, and the like.

[0004] It is also known to manufacture such sensors using MEMS technology, which makes it possible to obtain sensors with small dimensions, low energy consumption and high detection accuracy.

[0005] The MEMS sensor converts a physical quantity into a corresponding analog electrical signal, the temporal evolution of which is a function of the temporal evolution of the detected physical quantity. Furthermore, each MEMS sensor is configured to convert the corresponding analog signal into a corresponding (digital) discretized signal with a corresponding output sampling rate and provide the corresponding discretized signal to a control unit of the electronic device.

[0006] The control unit of the electronic device is configured to process the discretized signals received from the plurality of sensors.

[0007] It is desirable to ensure that the sensors send corresponding discretized signals to the electronics in a mutually synchronized manner. Different approaches are used for this purpose.

[0008] In one approach, the analog signal generated by the sensor is first stored in a sample-and-hold circuit and then discretized by a single analog-to-digital converter.

[0009] In another approach, the sensors each include a respective analog-to-digital converter whose discretization functions are controlled in parallel by a single trigger signal.

[0010] However, both of these approaches involve incorporating additional components into the electronic device and, therefore, involve high cost and high energy consumption of the electronic device. Additionally, these approaches are not suitable for applications requiring high output data rates from the sensor.

[0011] In another approach, the electronic device's control unit is configured to receive specific configuration information from the sensor. Based on this information, the control unit determines a series of synchronization instructions to be sent to the sensor. However, this approach requires significant computing resources from the electronic device's control unit, resulting in high energy consumption. Furthermore, this approach requires a dedicated communication interface between the sensor and the control unit, reducing the versatility and simplicity of the electronic device's implementation. Summary of the Invention

[0012] In one embodiment, a sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. In operation, the control circuitry receives the detection signal and a frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting samples of the digital output signal based on the trigger signal. The lock signal is temporally aligned with the digital output signal.

[0013] In one embodiment, a system includes: a plurality of sensors, each sensor including: a detection circuit device that generates a detection signal indicative of a detected physical quantity in operation; and a processing circuit device coupled to the detection circuit device, wherein the processing circuit device, in operation: receives the detection signal; receives a frequency indication signal; generates a trigger signal based on the frequency indication signal and a set of local reference signals; generates a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal, and the lock signal is aligned in time with the digital output signal, wherein the plurality of sensors include a reference sensor and a slave sensor coupled to the reference sensor; and the lock signal of the reference sensor is the received frequency indication signal of the slave sensor.

[0014] In one embodiment, a method includes: synchronizing samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronizing including: receiving a first frequency indication signal by the reference sensor; generating a first trigger signal by the reference sensor based on the first frequency indication signal and a first local reference signal set; generating, by the reference sensor, samples of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second local reference signal set; and generating, by the slave sensor, samples of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor.

[0015] In one embodiment, the contents of a non-transitory computer-readable medium configure a processing circuit device to synchronize samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronization comprising: receiving a first frequency indication signal by the reference sensor; generating a first trigger signal by the reference sensor based on the first frequency indication signal and a first local reference signal set; generating, by the reference sensor, samples of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second local reference signal set; and generating, by the slave sensor, samples of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a better understanding of the present disclosure, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0017] Figure 1 A block diagram of an electronic device including a plurality of sensors according to one embodiment is shown;

[0018] Figure 2 Shown Figure 1 A block diagram of an embodiment of a sensor of an electronic device;

[0019] Figure 3 Shown Figure 1 A block diagram of another embodiment of a sensor of an electronic device;

[0020] Figure 4 An embodiment including a decimator is shown. Figure 2 and Figure 3 The structure of the frame;

[0021] Figure 5 According to one embodiment, Figure 4 The structure of the frame extractor;

[0022] Figure 6 According to one embodiment, Figure 3 The structure of the sensor frame;

[0023] Figure 7 Shown Figure 6 The box shows an example trend of the input signal changing over time in use;

[0024] Figure 8 According to one embodiment, Figure 3The structure of another frame of the sensor;

[0025] Figure 9 According to one embodiment, Figure 8 A flowchart of a method performed by the box;

[0026] Figure 10 A block diagram illustrating an electronic device including a plurality of sensors according to one embodiment is shown; and

[0027] Figure 11 According to one embodiment, Figure 10 Block diagram of the sensor of the electronic device.

[0028] In the following, if not stated otherwise, reference to the frequency of a discretized (digital) signal indicates its sampling frequency, the data rate at which samples of the discretized signal are provided at the output from the respective block generating it. DETAILED DESCRIPTION

[0029] Figure 1 is a schematic diagram of an electronic system or device 1, which is, for example, a smart phone, a wearable device, a device for augmented reality or virtual reality, a device for monitoring one or more physical quantities (for example, for monitoring vibrations), a car control system, etc.

[0030] The electronic device 1 comprises a plurality of sensors 5, a control unit or circuit 7 and an interface 10 which operatively couples the plurality of sensors 5 and the control unit 7 to each other.

[0031] The control unit 7 comprises a memory 8 and a processing unit or core and is configured to send instructions, such as configuration instructions, to the sensor 5 and to receive measurement data or samples from the sensor 5 by means of an interface 10, such as a bus of known type for transmitting electrical signals.

[0032] Electronic device 1 further comprises input and output peripherals 12, such as a screen, in particular a touchscreen type screen, one or more keys, etc., and a power supply unit 14, such as a battery. Input and output peripherals 12 and power supply unit 14 are coupled to control unit 7. Power supply unit 14 can also be configured to provide a supply voltage to sensor 5 via interface 10.

[0033] The plurality of sensors 5 here include a first sensor 5A, a second sensor 5B, and a third sensor 5C, each of which is configured to detect one or more respective physical quantities associated with the operation of the electronic device 1. Embodiments may include more or fewer sensors 5.

[0034] For example, the first, second and third sensors 5A, 5B, 5C may each be, for example, an acceleration sensor, a temperature sensor, a pressure sensor, a mechanical stress sensor, a resistance sensor, a gyroscope, or the like.

[0035] Specifically, in this embodiment, the first, second and third sensors 5A, 5B, 5C are MEMS type sensors.

[0036] Furthermore, the first, second and third sensors 5A, 5B, 5C are configured to each provide a respective output signal S of digital type to the control unit 7 via the interface 10. O , output signal S O According to one or more corresponding detected physical quantities and having an output frequency f ou Specifically, the output signal S of the sensor 5 is formed O The samples are provided and stored in the memory 8.

[0037] As described in detail below, the first, second and third sensors 5A, 5B, 5C are configured to transmit the respective output signals S in a mutually synchronized manner. O The samples are supplied to the control unit 7 to have the same output frequency f ou and the same phase (to align in time).

[0038] Specifically, in this embodiment, Figure 2 The first sensor 5A shown in FIG is configured to operate as a reference (or main) sensor, while the second and third sensors 5B, 5C ( Figure 3 ) are configured to operate as slave sensors respectively.

[0039] As described in detail below, the first, second, and third sensors 5A, 5B, 5C herein can have similar general structures to one another, except for the differences discussed below; therefore, common elements are denoted by the same reference numerals. Specifically, the second and third sensors 5B, 5C herein can have similar general structures except for the sensitive portions, each of which is optimized for detecting one or more specific physical quantities. Thus, for example, Figure 3 Any sensor of the second sensor 5B or the third sensor 5C is represented indiscriminately.

[0040] like Figure 2 and Figure 3 As shown, the first, second and third sensors 5A, 5B, 5C each include a detection unit 20 , a signal conditioning stage 25 and a clock 30 .

[0041] The detection unit 20 is the sensitive part of the first, second and third sensors 5A, 5B, 5C; the detection unit or circuit 20 is configured to detect the corresponding physical quantity associated with the operation of the electronic device 1 and generate one or more electrical signals, here analog signals S, according to the physical quantity. A .

[0042] Specifically, in this embodiment, the detection unit 20 includes a sensing element 35 and a mechanical oscillator 37 .

[0043] The detection units 20 of the first, second, and third sensors 5A, 5B, and 5C, in particular, the sensing elements 35 and / or the mechanical oscillators 37, are designed based on the specific physical quantity to be detected and the specific application; therefore, they may be different in each sensor 5. Specifically, except for the differences in the corresponding sensing elements 35 and / or the corresponding mechanical oscillators 37, the second and third sensors 5B and 5C may be identical to each other.

[0044] The mechanical oscillator 37 comprises a oscillator having a resonant frequency f r A structure that is movable and / or deformable, for example in an elastic manner, such as a cantilever beam, a membrane, or a structure having any other shape.

[0045] In use, the mechanical oscillator 37 is actuated, for example according to electrostatic, piezoelectric or electromagnetic actuation principles, so that the corresponding movable and / or deformable structure is actuated at an operating frequency f o Oscillation. Usually, the operating frequency f o is the resonant frequency f r function, for example it is equal to the resonant frequency f r .

[0046] The mechanical oscillator 37 is configured such that the physical quantity to be detected changes the movement of a movable and / or deformable structure of the mechanical oscillator 37 , for example changes its phase, amplitude and / or frequency.

[0047] The sensing element 35 is configured to detect the movement of the movable and / or deformable structure of the mechanical oscillator 37, for example according to electrostatic, piezoresistive, piezoelectric or electromagnetic detection principles, and convert it into an analog signal S A . Analog signal S A The trends over time are therefore indicative of movement changes of the movable and / or deformable structure of the mechanical oscillator 37 , these movement changes being caused by the temporal changes of the physical quantity to be detected.

[0048] The clock 30 is configured to provide a clock frequency f having an order of magnitude of, for example, several MHz. clk A periodic signal, hereinafter referred to as clock signal CLK, such as a square wave signal. For example, the clock 30 can be formed by any type of known electronic oscillator, such as a voltage-controlled oscillator.

[0049] The signal conditioning stage or circuit 25 receives the clock signal CLK and the analog signal S A And generate the output signal S O As discussed below, the output signal S O From the analog signal S A The discretization is obtained.

[0050] In detail, the signal conditioning stage 25 includes an analog conditioning circuit (or analog front end, AFE) 40 , an analog-to-digital converter 43 , a filter 46 and an output data rate (ODR) modification block or circuit 49 , hereinafter also referred to as an ODR modification block 49 .

[0051] The analog conditioning circuit 40 includes, for example, one or more operational amplifiers and is configured to, for example, A Filter, amplify or demodulate to provide a conditioned analog signal S' A .

[0052] The analog-to-digital converter 43 is configured to receive the conditioned analog signal S′ A And provide sampling signal S S . Sampling signal S S By sampling at a frequency f s The conditioned analog signal S' A Obtained by discretization.

[0053] Sampling frequency f s The selection is made during the design phase based on the requirements of the specific application. For example, the sampling frequency f s Satisfies the Nyquist sampling theorem and is greater than the operating frequency f of the mechanical oscillator 37 of the detection unit 20 o twice as much.

[0054] The sampling signal S output from the analog-to-digital converter 43 S So it has a sampling frequency f s The sampling frequency of .

[0055] The filter 46 comprises one or more low-pass or band-pass type filters having one or more corresponding cut-off frequencies and is configured to receive the sampled signal S S And provide digital signal S D Therefore, the digital signal S D By sampling the signal S S The filtering is performed to obtain, for example, in order to remove undesired spectral components thereof introduced by the analog-to-digital converter 43 , the analog conditioning circuit 40 and / or the detection unit 20 .

[0056] According to specific application and design requirements, for example, to meet the die area requirements, the filter 46 can also be configured to reduce the sampling signal SS The frequency of , for example, is reduced by an integer reduction factor, for example comprised between 1 and 1024.

[0057] Therefore, the digital signal S D With an adjusted sampling frequency f' s , which is lower than the sampling frequency f s In other applications, the adjusted sampling frequency f' s Equal to the sampling frequency f s .

[0058] In this embodiment, the signal conditioning stages 25 of the first, second and third sensors 5A, 5B, 5C also receive a respective configuration signal set CONF including a frequency selection signal F_C and an output trigger signal OUT_TRG. Each signal conditioning stage 25 also generates a respective reference signal EXT_REF, INT_REF as described below.

[0059] In detail, the ODR modification block 49 is configured to receive the digital signal S D and configure the signal set CONF and provide the output signal S O And reference signals EXT_REF, INT_REF.

[0060] Output signal S O By modifying the digital signal S D The sampling frequency is obtained.

[0061] Here, the reference signal is indicated as being for the first sensor 5A ( Figure 2 ) and the external reference signal EXT_REF for the second sensor 5B ( Figure 3 ) and an internal reference signal INT_REF for the third sensor 5C. The reference signal may be referred to as a locking signal.

[0062] The external reference signal EXT_REF is a periodic signal, such as a square wave signal. In this embodiment, its frequency is equal to the output signal S of the first sensor 5A. O The output sampling rate f ou .

[0063] However, in general, the frequency of the reference signal EXT_REF may be the frequency of the output signal S of the first sensor 5A. O The output sampling rate f ou The divisor of .

[0064] In detail, the first sensor 5A is coupled to the second and third sensors 5B, 5C and, in use, generates an external reference signal EXT_REF and provides the external reference signal EXT_REF to the second and third sensors 5B, 5C.

[0065] The internal reference signal INT_REF of the second sensor 5B and the internal reference signal INT_REF of the third sensor 5C are both periodic signals, such as square wave signals, whose frequency is equal to the corresponding output signal S O The output sampling rate f ou .

[0066] As described in detail below, the second sensor 5B and the third sensor 5C each receive an external reference signal EXT_REF and generate a respective output signal S in response to a comparison between the external reference signal EXT_REF and a respective internal reference signal INT_REF. O Sample.

[0067] like Figure 4 As shown in detail in FIG, the ODR modification block 49 of the first, second and third sensors 5A, 5B, 5C includes an interpolator 52, a decimator 55 and a reference block or circuit 58.

[0068] The interpolator 52 comprises an interpolation filter 61 configured to receive at input a signal having an adjusted sampling frequency f′. s The digital signal S D , and is configured to provide at the output a signal having a sampling frequency f' adjusted to s Higher interpolation frequency f int The interpolated digital signal S D,int Specifically, here, according to formula f int =f' s I1, interpolation frequency f int By adjusting the sampling frequency f' s Increase the interpolation factor I1 to obtain.

[0069] The interpolator 52, in particular the corresponding interpolation filter 61, can be obtained in a known manner, for example using a linear or nonlinear phase interpolation circuit, in particular of the CIC (Cascaded Integrator Comb) type, spline type, Lagrangian type or Hermitian type.

[0070] The decimator 55 is configured to receive the interpolated digital signal S D,int and configuration signal set CONF and provides an output signal S in response to receiving an output trigger signal OUT_TRG O .

[0071] In detail, such as Figure 5 As shown, decimator 55 includes a filter stage or circuit 65, a downsampler 68, and a gain block or circuit 71 connected in cascade to one another.

[0072] The filter stage 65 is a low-pass filter, for example an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter, such as a CIC circuit, and is configured to receive the frequency selection signal F_C and the interpolated digital signal S D,int And provide a filtered signal F.

[0073] The filter stage 65 has a transfer function with a cutoff frequency f c , cutoff frequency f c Based on the output frequency f ou , in particular, is selected based on the frequency selection signal F_C.

[0074] For example, the cutoff frequency f c is chosen so that the output signal S O The frequency and cut-off frequency f c The ratio between them complies with the Nyquist sampling theorem. In addition, the cutoff frequency f c is selected to suppress the high frequency spectral image introduced by the interpolator 52.

[0075] The transfer function of the filter stage 65, in particular the cut-off frequency f c , can be modified in a known manner during use. For example, in the case where the filter stage 65 is formed by a CIC filter of order N, the corresponding coefficients of its transfer function can be determined in a known manner according to the output signal S O The frequency and interpolation digital signal S D,int In case the filter stage 65 is formed by an IIR filter, the corresponding coefficients determining its transfer function can be selected from a specific look-up table stored in the memory 8, for example.

[0076] The downsampler 68 is configured to receive the filtered signal F and the output trigger signal OUT_TRG and provide a downsampled signal DS.

[0077] In detail, the downsampler 68 is configured to receive a first sample F of the filtered signal F at a first time instant t1. i (t1) to store the first sample F i (t1), and in response to receiving a second sample F of the filtered signal F at a second time t2 after the first time t1 i (t2) and using the second sample F i (t2) Overwrite the first sample F i (t1).

[0078] The downsampler 68 is configured to provide at the output a currently stored sample F of the filtered signal F in response to detecting an event (in particular a switching edge, such as a rising edge or a falling edge) of the output trigger signal OUT_TRG. iFor example, if the downsampler 68 does not detect any event of the output trigger signal OUT_TRG between the first instant t1 and the second instant t2, and detects an event of the output trigger signal OUT_TRG after the second instant t2, the downsampler 68 provides a second sample F of the filtered signal F at the output. i (t2). Sample F provided at the output i The set constitutes the downsampled signal DS.

[0079] In other words, the downsampler 68 is configured such that the sampling frequency of the downsampled signal DS is lower than or at most equal to the sampling frequency of the filtered signal F.

[0080] The gain block 71 is configured to receive the down-sampled signal DS and the frequency selection signal F_C and provide an output signal S O .

[0081] In detail, the gain block 71 is configured to amplify or attenuate the sample F of the down-sampled signal DS corresponding to the dc component (zero frequency component) of the down-sampled signal DS by a gain factor G. i For example, the zero frequency component of the downsampled signal DS is identified by performing a Fourier transform on the downsampled signal DS. The gain factor G is selected according to the frequency selection signal F_C and the type of filter used in the filter stage 65.

[0082] Specifically, if the filtering stage 65 is obtained using an IIR filter, the gain factor G can be selected from a specific table stored in the memory 8. If the filtering stage 43 is obtained using a CIC filter, the gain factor G can be calculated as 1 / D1 N , where N is the order of the CIC filter of the filter stage 65, and D1 is the indicator output signal S O The frequency and interpolation digital signal S D,int The value of the ratio between the frequencies.

[0083] In practice, in use, the respective digital signals S are provided by the ODR modification block 49 of the reference sensor 5A and the slave sensors 5B, 5C. D The samples include the corresponding digital signal S D Up-sampling is performed to generate the interpolation signal S D,int And the interpolation signal S D,int Down-sampling is performed to generate the corresponding output signal S O .

[0084] In addition, the interpolation signal S D，int Downsampling involves: cThe interpolation signal is filtered by a low-pass filter (filtering stage 65) to obtain a filtered signal F; in response to receiving corresponding output trigger signals OUT_TRG from the reference sensor 5A and the slave sensors 5B, 5C, the filtered signal F is down-sampled to obtain a down-sampled signal DS having a dc component; and the dc component of the down-sampled signal DS is modified by amplifying or attenuating the dc component using a gain value G.

[0085] Reference block or circuit 58 ( Figure 4 ) is configured to receive an output trigger signal OUT_TRG and, in response to receiving the corresponding output trigger signal OUT_TRG, provide a corresponding reference signal (an external reference signal EXT_REF in the case of the first sensor 5A and an internal reference signal INT_REF in the case of the second and third sensors 5B, 5C).

[0086] In detail, the reference block 58 is configured to generate a switching edge (e.g., a rising edge or a falling edge) of the corresponding reference signal in response to receiving the corresponding output trigger signal OUT_TRG, in particular, in response to detecting a switching event or switching edge (e.g., a rising edge or a falling edge) of the output trigger signal OUT_TRG. In other words, the switching edge of the external reference signal EXT_REF of the first sensor 5A is correlated with the output signal S of the first sensor 5A provided in response to receiving the corresponding output trigger signal OUT_TRG. O The samples are aligned in time.

[0087] Likewise, the switching edge of the internal reference signal INT_REF of the second sensor 5B is synchronized with the output signal S of the second sensor 5B provided in response to receiving the corresponding output trigger signal OUT_TRG. O Additionally, the switching edge of the internal reference signal INT_REF of the third sensor 5C is aligned with the output signal S of the third sensor 5C provided in response to receiving the corresponding output trigger signal OUT_TRG. O The samples are aligned in time.

[0088] Reference again Figure 2 The first sensor 5A further comprises a configuration block or circuit 80, which is configured to receive the corresponding clock signal CLK and the user signal S U And generate the corresponding configuration signal set CONF.

[0089] like Figure 1 As shown, the user signal S U Sent by the control unit 7 via the interface 10 to the first sensor 5A and indicating the desired output data rate ODR from the plurality of sensors 5 E .

[0090] For example, in use, a user of the electronic device 1 may indicate a desired output data rate ODR via the peripheral unit 12 E .

[0091] In this embodiment, the user signal S U Indicates set value N s , which is equal to the number of cycles of the clock signal CLK of the first sensor 5A, such as the number of rising edges or falling edges. The configuration block 80 ( Figure 2 ) is configured to count the cycles of the corresponding clock signal CLK and count the number of cycles of the corresponding clock signal CLK equal to the set value N s Specifically, the frequency selection signal F_C of the first sensor 5A indicates the set value N s .

[0092] refer to Figure 3 The configuration blocks or circuits of the second and third sensors 5B, 5C, represented by 83, are configured to receive the clock signal CLK from the corresponding clock 30, the internal reference signal INT_REF from the corresponding reference block 58 (see Figure 4 ) and the external reference signal EXT_REF from the first sensor 5A, and generates a corresponding configuration signal set CONF.

[0093] The configuration block 83 of the second sensor 5B and the configuration block 83 of the third sensor 5C each include a corresponding measurement block or circuit 85 and a corresponding correction block or circuit 90 .

[0094] The measurement blocks 85 of the second and third sensors 5B, 5C are configured to receive the respective clock signal CLK, the respective internal reference signal INT_REF and the external reference signal EXT_REF; and to generate a respective set of correction signals CORR comprising the phase correction signal PH_C and the frequency selection signal F_C.

[0095] like Figure 6 As shown in detail in FIG, the measurement block 85 includes a counter 100, a first register 105A, a second register 105B, a third register 105C, a first subtraction device 110A, and a second subtraction device 110B.

[0096] Counter 100 is a free-running counter configured to receive a clock signal CLK, store a count value, and provide a clock count signal N_CLK indicating the count value. Counter 100 increments the count by one unit at each cycle of clock signal CLK (e.g., at each rising or falling edge). In other words, the count value has an increasing monotonic value that is equal to the number of cycles of clock signal CLK counted since counter 100 was last reset (e.g., when electronic device 1 is restarted).

[0097] The first register 105A is configured to receive and store the clock count signal N_CLK, receive the internal reference signal INT_REF, and provide the internal phase signal N_INT in response to detecting a switching edge (e.g., a rising edge or a falling edge) of the internal reference signal INT_REF. When the switching edge of the internal reference signal INT_REF is detected, the internal phase signal N_INT is equal to the value of the clock count signal N_CLK stored in the first register 105A.

[0098] The second register 105B is configured to receive and store the clock count signal N_CLK, receive the external reference signal EXT_REF, and provide the first external count signal N1_EXT in response to detecting a switching edge (e.g., a rising edge or a falling edge) of the external reference signal EXT_REF. When the switching edge of the external reference signal EXT_REF is detected, the first external count signal N1_EXT is equal to the value of the clock count signal N_CLK stored in the second register 105B.

[0099] The first subtraction element 110A is configured to receive the internal phase signal N_INT and the first external count signal N1_EXT and provide a phase correction signal PH_C. The phase correction signal PH_C is given by the difference between the internal phase signal N_INT and the first external count signal N1_EXT and corresponds to the number of phase shift cycles Nd of the clock signal CLK. Figure 7 As shown, the phase correction signal PH_C indicates a phase difference ΔΦ between the internal phase signal N_INT and the first external counting signal N1_EXT.

[0100] In other words, the phase correction signal PH_C generated by the measurement block 85 of the second sensor 5B indicates the time offset (phase shift) between the internal reference signal INT_REF and the external reference signal EXT_REF of the second sensor 5B (specifically, between the rising edge of the internal reference signal INT_REF of the second sensor 5B and the rising edge of the external reference signal EXT_REF), and the time offset (phase shift) is expressed as the number of cycles of the clock signal CLK of the second sensor 5B.

[0101] Similarly, the phase correction signal PH_C generated by the measurement block 85 of the third sensor 5C indicates the phase shift between the internal reference signal INT_REF and the external reference signal EXT_REF of the third sensor 5C (specifically, between the rising edge of the internal reference signal INT_REF of the third sensor 5C and the rising edge of the external reference signal EXT_REF), and the phase shift is expressed as the number of cycles of the clock signal CLK of the third sensor 5C.

[0102] Reference again Figure 6 The third register 105C is configured to receive and store the first external count signal N1_EXT, receive the external reference signal EXT_REF, and provide the second external count signal N2_EXT in response to detecting a switching edge (e.g., a rising edge or a falling edge) of the external reference signal EXT_REF. When the switching edge of the external reference signal EXT_REF is detected, the second external count signal N2_EXT is equal to the value of the first external count signal N1_EXT stored in the third register 105C.

[0103] The second subtraction element 110B is configured to receive the first external count signal N1_EXT and the second external count signal N2_EXT and provide a frequency selection signal F_C. The frequency selection signal F_C is given by the difference between the first external count signal N1_EXT and the second external count signal N2_EXT and corresponds to the number of frequency cycles Nf of the clock signal CLK. Figure 7 As can be seen in FIG, the frequency selection signal F_C indicates the time difference Δt between two consecutive switching edges, in particular, two consecutive rising edges, of the external reference signal EXT_REF.

[0104] In practice, the frequency selection signal F_C generated by the measurement block 85 of the second and third sensors 5B, 5C indicates the external reference signal EXT_REF, the output signal S of the first sensor 5A, and the frequency selection signal F_C generated by the measurement block 85 of the second and third sensors 5B, 5C. O The output frequency f ou , and thus the expected output data rate ODR from the plurality of sensors 5 E The frequencies are expressed as the number of cycles of the clock signal CLK of the second sensor 5B and the third sensor 5C, respectively.

[0105] Figure 8 A possible implementation of the correction block 90 for the second sensor 5B and the third sensor 5C is shown.

[0106] In detail, Figure 8 The correction block 90 includes a decimation counter 120 and a comparator 125 cascaded to the decimation counter 120 .

[0107] The decimation counter 120 is configured to extract the value from the corresponding measurement block 85 ( Figure 3) receives a phase correction signal PH_C; receives a clock signal CLK from a corresponding clock 30; stores a corresponding extraction count k; and provides a corresponding comparison signal C indicating the extraction count k.

[0108] The comparator 125 is configured to receive the comparison signal C and the frequency selection signal F_C, and generate an output trigger signal OUT_TRG when a trigger condition occurs.

[0109] In this embodiment, the comparator 125 is further configured to provide a reset signal RST to the decimation counter 120 when a trigger condition occurs.

[0110] Figure 8 The operation of the correction block 90 is Figure 9 is shown in flowchart 149.

[0111] Specifically, in an initial step 150, for example, upon startup of the electronic device 1, the decimation counter 120 resets the value of the decimation count k to zero. Next, at each cycle of the clock signal CLK, for example, at each rising or falling edge of the clock signal CLK, the counter 120 verifies (step 152) whether the phase correction signal PH_C and the number of phase shift cycles Nd are non-zero. If not (output N from step 152), the decimation counter 120 updates the decimation count k by incrementing it by one unit (step 154). If yes (output Y from step 152), the decimation counter 120 updates the decimation count k by incrementing it by one unit and the value indicated by the phase correction signal PH_C (step 156); k = k + 1 + Nd.

[0112] The comparator 125 then verifies the trigger condition by comparing the value indicated by the comparison signal C (decimation count k) with the value indicated by the frequency selection signal F_C (step 158). Specifically, the trigger condition includes verifying whether the decimation count k is greater than or equal to the number of frequency cycles Nf indicated by the frequency selection signal F_C.

[0113] If not (output N from step 158 ), the correction block 90 repeats step 152 .

[0114] If yes (output Y of step 158 ), the comparator 125 generates an output trigger signal OUT_TRG (step 160 ) and a reset signal RST (step 162 ).

[0115] In response to receiving the reset signal RST, the decimation counter 120 resets the decimation count k. In this embodiment, the decimation counter 120 resets the decimation count k to a value equal to the result of a modulo operation between the decimation count k and the number of frequency cycles Nf: k=mod(k,Nf).

[0116] The correction block 90 then returns to step 152 .

[0117] In fact, in use and reference Figure 1 and Figure 2 , a user signal S sent by the user of the electronic device 1 to the first sensor 5A U Set the desired output data rate ODR from the first sensor 5A E , that is, the corresponding output signal S O The expected output frequency f ou .

[0118] Specifically, the output trigger signal OUT_TRG of the first sensor 5A is generated by the corresponding configuration block 80 to trigger the extractor 55 ( Figure 4 ) with output frequency f ou Provides output signal S O Sample.

[0119] The reference block 58 of the first sensor 5A generates the external reference signal EXT_REF in response to receiving the output trigger signal OUT_TRG so that its rising edge (or falling edge) is generated to have the same value as the output signal S of the first sensor 5A. O The samples have the same phase and frequency.

[0120] As reference Figure 6-Figure 9 As discussed in detail, the external reference signal EXT_REF provided by the first sensor 5A to the second and third sensors 5B, 5C is thus used by the latter to set the corresponding output signals S O The frequency of the samples.

[0121] In addition, in response to receiving the output trigger signal OUT_TRG, the second and third sensors 5B, 5C each generate a corresponding internal reference signal INT_REF through a corresponding reference block 58. The rising (or falling) edge of the internal reference signal INT_REF of the second sensor 5B is aligned with the output signal S of the second sensor 5B. O Similarly, the rising (or falling) edge of the internal reference signal INT_REF of the third sensor 5C is generated at the same phase and frequency as the output signal S of the third sensor 5C. O The samples are generated with the same phase and frequency.

[0122] Therefore, since the second and third sensors 5B, 5C each compare the external reference signal EXT_REF with the corresponding internal reference signal INT_REF, as shown in FIG. Figure 6-Figure 9 As described in detail, they can also convert the corresponding output signal S O The output signal S of the first sensor 5A O aligned in time, thereby compensating for possible phase shifts (e.g. Figure 7 The phase difference ΔΦ).

[0123] Therefore, except for the initial transient period after the electronic device 1 is started, for example, the output signals S of the plurality of sensors 5 O After an initial adjusted number of samples (for example comprised between 1 and 100), the first, second and third sensors 5A, 5B, 5C generate respective output signals S in a mutually synchronized manner. O Specifically, in one embodiment, the output signals S of the plurality of sensors 5 are O The samples of are temporally coherent with each other. They not only have the same output frequency f ou , and they are also aligned in time with each other (they are in phase).

[0124] This helps to achieve many advantages.

[0125] In fact, the sensor 5 will output a corresponding signal S O The fact that the samples of the CMOS image sensors are supplied simultaneously to the memory 8 means that the control unit 7 of the electronic device 1 can be configured to immediately output the CMOS image sensors at a frequency of f. ou Read the data received from all sensors 5 and from the memory 8. Therefore, the control unit 7 can allocate a shorter time for data collection activities. This means that with respect to the output signal S O In the case where the samples are not synchronized, the electronic device 1 has lower energy consumption, wherein the control unit 7 should periodically control the effective arrival of the samples. Alternatively, the time saved by the control unit 7 in data collection can be used for other activities, thereby improving the performance of the electronic device 1 and / or improving the operating efficiency.

[0126] Furthermore, in the electronic device 1, the plurality of sensors 5 can be self-synchronized by enabling the transmission of only one signal (the external reference signal EXT_REF) between the sensors 5. Furthermore, the external reference signal EXT_REF and the corresponding internal reference signal INT_REF used by the second and third sensors 5B, 5C can compensate for possible variations in the behavior of the clock 30, such as offsets and drifts due to variations in usage conditions such as temperature.

[0127] In other words, data synchronization at the output of the sensor 5 of the electronic device 1 can occur without the control unit 7 being configured to execute a complex synchronization protocol, which would involve significant hardware and software resources. Also for this reason, the electronic device 1 has improved efficiency.

[0128] Additionally, the interface 10 may be a universal and known communication interface. This enables a high degree of versatility in the use of a plurality of sensors 5 that can be easily incorporated into the electronic device 1.

[0129] At the same time, the output signal S of the sensor 5O The fact of being temporally coherent (frequency and phase aligned) enables the control unit 7 to appropriately use the data provided by the sensor 5 in subsequent processing operations, such as subsequent combined processing of the data of the sensor 5 to perform advanced functions of the electronic device 1, such as multi-sensor data fusion processing, advanced compensation, and in particular batch processing in a FIFO (first-in / first-out) type buffer.

[0130] Figure 10 A different embodiment of the present electronic device is shown, here indicated at 200 .

[0131] The electronic device 200 has Figure 1 The electronic device 1 has a similar overall structure; therefore, common elements have the same reference numerals and are briefly described.

[0132] In detail, the electronic device 200 comprises a control unit or circuit 7 , a memory 8 , an interface 10 and a plurality of sensors, here indicated by 205 .

[0133] Furthermore, here too, the electronic device 200 includes a power supply unit 14 and input and output peripherals 12 .

[0134] The plurality of sensors 205 also includes a first sensor 205A, a second sensor 205B, and a third sensor 205C. Fewer or additional sensors may be employed in various embodiments.

[0135] The first sensor 205A has Figure 1 The first sensor 5A has the same structure and is therefore not further illustrated. Figure 2 Description.

[0136] In this embodiment, the first sensor 205A generates a reference signal, which is referred to as the first external reference signal REF1 and is intended to be provided only to the second sensor 205B.

[0137] The second sensor 205B, whose block diagram is Figure 11 As shown in FIG, the detection unit 20, the signal conditioning stage 25 with the ODR modification block 49, the clock 30 and the synchronization block 83 with the measurement block 85 and the correction block 90 are also included here.

[0138] The synchronization block 83 , in particular the measurement block 85 , is here configured to receive at input a respective internal reference signal INT_REF and a first external reference signal REF1 generated by the first sensor 205A as an external reference signal.

[0139] In this embodiment, the second sensor 205B is configured to further generate a second external reference signal REF2 and provide it to the third sensor 205C. The second external reference signal REF2 is a periodic signal, such as a square wave signal, whose rising (or falling) edge is aligned with the corresponding output signal S O Alignment of samples.

[0140] In detail, in this embodiment, the second external reference signal REF2 is generated by the reference block 58 of the ODR modification block 49 and is identical to the internal reference signal INT_REF.

[0141] The third sensor 205C has Figure 11 The same structure as the second sensor 205B is shown and is therefore not further illustrated. The third sensor 205C also comprises a detection unit 20, a signal conditioning stage 25 with an ODR modification block 49, a clock 30, and a synchronization block 83 with a measurement block 85 and a correction block 90. ​​However, the synchronization block 83, in particular the measurement block 85, receives at its input a second external reference signal REF2 generated by the second sensor 205B as an external reference signal in addition to the corresponding internal reference signal INT_REF.

[0142] Thus, in this embodiment, the second sensor 205B operates as a slave sensor with respect to the first sensor 205A and as a reference sensor with respect to the third sensor 205C.

[0143] In practice, the plurality of sensors 205 of the device 200 are configured to perform self-synchronization in a manner similar to that described above for the electronic device 1. Therefore, the electronic device 200 shares the above-mentioned potential advantages of the electronic device 1.

[0144] Finally, it is clear that modifications and variations may be made to the present electronic device 1 , 200 and the corresponding synchronization method as described and illustrated herein without departing from the scope of the present disclosure as defined in the accompanying claims.

[0145] For example, the various embodiments described may be combined to provide further solutions.

[0146] For example, in Figure 1 In the electronic device 1, the first sensor 5A can also provide the external reference signal EXT_REF to the control unit 7 via the dedicated connection 210. Figure 1 In this way, the control unit 7 can read the output signal S in response to receiving the external reference signal EXT_REF. O Sample.

[0147] Similarly, in Figure 10In the electronic device 200, the first sensor 5A can send the first external reference signal REF1 to the control unit 7 via a dedicated connection, which is also represented by 210 and is indicated by a dotted arrow. In another embodiment, the second sensor 5B can send the second external reference signal REF2 to the control unit 7 via a corresponding dedicated connection. In this way, the control unit 7 can read the output signal S in response to receiving the first external reference signal REF1 or the second external reference signal REF2. O Sample.

[0148] For example, the control unit 7 may be configured to output a frequency corresponding to the output frequency f ou The output signal S is read at intervals corresponding to the approximate multiple of O of samples, thereby achieving energy saving.

[0149] For example, the sensors 5 and 205 may have the same structure and be configured to operate as a reference sensor and a slave sensor, respectively. In the initial configuration step of the electronic device 1 or 200, the user of the electronic device 1 or 200 may select which sensor to use as the reference sensor by sending a specific configuration instruction via the interface 10. Specifically, the user may select a sensor with a lower operating frequency f o The sensor is used as the reference sensor.

[0150] The sensors 5, 205 may be equal to each other, detecting the same physical quantity under different conditions and / or locations, or the sensors 5, 205 may be different, detecting different physical quantities.

[0151] The sensors 5, 205 may also differ in their respective clocks 30. For example, the sensors 5, 205 may each have a different type of respective clock 30; in particular, they may each have a respective clock frequency f clk .

[0152] The sensors 5, 205 can each be formed in a respective die or in multiple dies of semiconductor material; furthermore, multiple sensors can be formed in only one die. Specifically, for each sensor 5, the detection unit 20 can be formed in a different die than the other circuit components, the signal conditioning stage 25, the clock 30, and the synchronization blocks 80, 83. Alternatively, for each of the multiple sensors 5, analog components, such as the analog conditioning circuit 40, can be formed in a different die than digital components (such as the clock 30, the ODR modification block 49, and the synchronization blocks 80, 83).

[0153] As an alternative to what has been illustrated, for each sensor 5, 205, the die may integrate the respective detection unit 20 and part of the signal conditioning stage 25, in particular the analog conditioning circuit 40, the analog-to-digital converter 43 and possible filters 46, the ODR modification block 49 being provided on a separate die.

[0154] In general, in any case, for each sensor 5, 205, the detection unit 20, the analog conditioning circuit 40 and the analog-to-digital converter 43 can be considered to functionally form a digital detector 48, which is composed of Figure 2 、 Figure 3 and Figure 11 In some applications, the filter 46 may also be considered as belonging to the digital detector 48.

[0155] According to one embodiment, the configuration block 58 of the reference sensors (the first sensor 5A of the electronic device 1 and the first and second sensors 205A, 205B of the electronic device 200) can be configured so that the frequency of the corresponding external reference signals EXT_REF, REF1, REF2 is equal to the output sampling rate f of the reference sensors. ou In other words, the external reference signal is a factor of the SM order of the corresponding output signal S O Therefore, the configuration blocks 83 of the slave sensors (second sensor 5B, 205B and third sensor 5C, 205C) are configured so that the frequency selection signal F_C indicates the order SM of the number of frequency periods Nf measured by the corresponding measurement block 85 divided by the frequency divisor.

[0156] In practice, the digital output signal S O With a first frequency (output sampling rate f o u), and the reference or frequency indication signal EXT_REF, REF1, REF2 has a second frequency, wherein the second frequency is a divisor equal to the first frequency divided by the division order SM, and wherein the first number of periods (number of frequency periods Nf) indicates the number of periods of the clock signal CLK between two consecutive events of the frequency indication signal divided by the division order SM.

[0157] Finally, all or part of the operations performed by the signal conditioning stage 25 and the configuration blocks 80, 83 may be achieved using a hardware solution via dedicated circuitry or using a software solution via a dedicated computer program.

[0158] An integrated sensor (5A-5C; 205A-205C) configured to receive a frequency indication signal (S U , EXT_REF; REF1, REF2 and provide an output digital signal (S O), the integrated sensor can be summarized as comprising: a digital detector (48) configured to detect a physical quantity and generate a discrete detection signal (S) indicating the detected physical quantity D ); Output timing adjustment block (80, 83), which is configured to receive a frequency indication signal (S U , EXT_REF; REF1, REF2) and a local reference signal set (CLK, INT_REF) and generates a trigger signal (OUT_TRG) according to the frequency indication signal and the local reference signal set; and an output stage (49) configured to receive the discrete detection signal and the trigger signal (OUT_TRG) and provide a digital output signal (S O ) and a lock signal (EXT_REF, INT_REF; REF1, REF2), wherein the output stage (49) is configured to provide samples of the discrete detection signal in response to receiving a trigger signal, thereby generating a digital output signal, and to provide a lock signal in response to receiving the trigger signal, the lock signal being aligned in time with the digital output signal.

[0159] The digital detector (48) may include a detection unit (20) configured to detect a physical quantity and generate an analog signal (S) indicative of the detected physical quantity. A ), and an analog-to-digital conversion stage (40, 43, 46) configured to receive an analog signal (S A ) and discretize it to generate a discrete detection signal (S D ).

[0160] The integrated sensor may include: a clock (30) configured to generate a periodic clock signal (CLK) having a period, wherein a local reference signal set may include a lock signal (INT_REF) and the clock signal, and an output timing adjustment block (83) may include at least one counter (100, 120) configured to count the period of the clock signal; a frequency measurement circuit (105B, 105C, 110B) configured to count a first number of periods (Nf) of the clock signal (CLK) between two consecutive events of the frequency indication signal and generate an internal frequency signal (F_C) indicating the first number of periods, the first number of periods measuring a frequency (Δt) of the frequency indication signal (EXT_REF; REF1, REF2) ); a phase measurement circuit (105A, 110A) configured to count a second number (Nd) of cycles of the clock signal (CLK) between an event of the frequency indication signal (EXT_REF; REF1, REF2) and an event of the lock signal (INT_REF) and generate an internal phase signal (PH_C) indicating the second number of cycles, the second number of cycles measuring a time offset (ΔΦ) between the frequency indication signal (EXT_REF; REF1, REF2) and the lock signal (INT_REF); and a comparison circuit (90, 120, 125) configured to generate a trigger signal (OUT_TRG) after a third number of cycles of the clock signal (CLK), the third number of cycles being a function of the first number of cycles and the second number of cycles.

[0161] The comparison circuit (90, 125) may include a corresponding counter (120) configured to store a count value (k) and to increase the count value by an increment at each cycle of the clock signal, the increment being a function of a second number of cycles (Nd), the comparison circuit being configured to generate a trigger signal (OUT_TRG) if the count value is greater than or equal to a first number of cycles (Nf).

[0162] The comparison circuit (90) may be configured to perform a modulo operation between the count value (k) and the first cycle number, generate a modulo value, and reset the count value (k) to the modulo value if the count value is greater than or equal to the first cycle number.

[0163] The output stage (49) may include an interpolator (52) and a decimator (55), wherein the interpolator is configured to D ) is up-sampled to generate an interpolation signal (S D,int ), the extractor is configured to downsample the interpolation signal in response to receiving a trigger signal to generate a digital output signal.

[0164] The decimator (55) may include a filtering stage (65), a downsampling stage (68), and a gain stage (71); the filtering stage (65) includes a low-pass filter having a corresponding cutoff frequency (fc) and configured to receive the interpolated signal (S D ,int) and generates a filtered signal (F); the downsampling stage is configured to downsample the filtered signal in response to receiving a trigger signal (OUT_TRG) and generate a downsampled signal (DS) having a dc component; and the gain stage (71) is configured to amplify or attenuate the dc component of the downsampled signal by a gain value (G).

[0165] The cut-off frequency of the filter stage (65) and the gain value of the gain stage (71) may be a function of the frequency indication signal (EXT_REF, F_C).

[0166] The integrated sensor may be a MEMS sensor.

[0167] The detection unit (20) may include a mechanical oscillator (37) and a sensing element (35) that undergoes oscillation, the mechanical oscillator being configured to operate at an operating frequency (f o ) is actuated and oscillates at an oscillation frequency that is related to the operating frequency and the physical quantity to be detected, and the sensing element is configured to convert the oscillation of the mechanical oscillator into an analog signal (S A ).

[0168] The electronic device can be summarized as including multiple integrated sensors, wherein the multiple integrated sensors can include a reference sensor (5A; 205A, 205B) and slave sensors (5B, 5C; 205B, 205C) coupled to each other, the reference sensor being configured to provide a corresponding locking signal (EXT_REF; REF1, REF2) to the slave sensor, wherein the frequency indication signal of the slave sensor is the locking signal of the reference sensor.

[0169] The device may include a control unit (7) coupled to a plurality of integrated sensors, the integrated sensors being configured to each output a corresponding digital output signal (S O ) is sent to the control unit.

[0170] The reference sensor may be configured to send a corresponding lock signal to the control unit, and the control unit may be configured to read the digital output signals received from the plurality of integrated sensors in response to receiving the lock signal.

[0171] A method for synchronizing digital output signals (S) provided by a plurality of integrated sensors (5; 205) O) sample method, a plurality of integrated sensors include a reference sensor (5A; 205A, 205B) and a slave sensor (5B, 5C; 205B, 205C), each of the integrated sensors in the plurality of integrated sensors includes an output timing adjustment block (80, 83) and an output stage (49), wherein the output stage receives a discrete detection signal (S) related to a physical quantity to be detected D ), the method can be summarized as comprising: receiving a first frequency indication signal (S U ) and a first local reference signal set (CLK); the output adjustment block (83) of the reference sensor provides a first trigger signal (OUT_TRG) according to the first frequency indication signal and the first local reference signal set (CLK); the output stage of the reference sensor responds to receiving the first trigger signal (OUT_TRG) to provide a sample of the corresponding discrete detection signal, thereby generating a corresponding digital output signal; the output stage of the reference sensor responds to receiving the first trigger signal to provide a first lock signal (EXT_REF) aligned in time with the corresponding digital output signal; the output adjustment block (83) of the slave sensor ) receives a first lock signal; the output conditioning block of the slave sensor provides a second trigger signal (OUT_TRG) based on the first lock signal and a second local reference signal set (CLK, INT_REF); the output stage (49) of the slave sensor provides samples of the corresponding discrete detection signal in response to receiving the second trigger signal (OUT_TRG), thereby generating a corresponding digital output signal; and the output stage (49) of the slave sensor provides a second lock signal (INT_REF; REF2) that is time-aligned with the corresponding digital output signal in response to receiving the second trigger signal (OUT_TRG).

[0172] The output timing adjustment block of the slave sensor, the second trigger signal may include: counting cycles of a clock signal (CLK) of the slave sensor; counting a first number (Nf) of cycles of the clock signal (CLK) between two consecutive events of a first lock signal (EXT_REF; REF1, REF2); generating an internal frequency signal (F_C) indicating the first number of cycles, the first number of cycles measuring the frequency (Δt) of the first lock signal (EXT_REF; REF1, REF2); counting a second number (Nd) of cycles of the clock signal (CLK) between events of the first lock signal (EXT_REF; REF1, REF2) and events of the second lock signal (INT_REF); generating an internal phase signal (PH_C) indicating the second number of cycles, the second number of cycles measuring the time offset (ΔΦ) between the first lock signal (EXT_REF; REF1, REF2) and the second lock signal (INT_REF); and generating a second trigger signal (OUT_TRG) after a third number of cycles of the clock signal (CLK), the third number of cycles being a function of the first number of cycles and the second number of cycles.

[0173] The digital output signal of the reference sensor may have a first frequency (fou), and the first locking signal (EXT_REF; REF1, REF2) may have a second frequency, the second frequency being a submultiple of the first frequency equal to a division order (SM), and counting the first number of cycles of the clock signal may include dividing the first number of cycles (Nf) by the division order.

[0174] Generating a second trigger signal (OUT_TRG) after a third number of cycles may include: storing a count value (k) by an output timing adjustment block of the slave sensor; increasing the count value by an increment at each cycle of the clock signal, the increment being a function of a second number of cycles (Nd); verifying whether the count value is greater than or equal to a first number of cycles (Nf); and generating the second trigger signal (OUT_TRG) if the count value is greater than or equal to the first number of cycles.

[0175] The method may include performing a modulo operation between the count value (k) and the first cycle number (Nf), generating a modulo value, and resetting the count value (k) to the modulo value if the count value is greater than or equal to the first cycle number.

[0176] In one embodiment, the sensor includes a detection circuit device and a control circuit device coupled to the detection circuit device. The detection circuit device generates a detection signal indicative of a detected physical quantity. The control circuit device receives the detection signal and a frequency indication signal in operation, and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is aligned in time with the digital output signal. In one embodiment, the detection circuit device includes: a detector, which detects a physical quantity in operation and generates an analog signal indicative of the detected physical quantity; and an analog-to-digital (A / D) converter coupled to the detector, which generates the detection signal based on the analog signal indicative of the detected physical quantity in operation. In one embodiment, a sensor includes: a clock that generates a periodic clock signal during operation, wherein a local reference signal set includes a lock signal and a periodic clock signal; and control circuitry that generates a frequency signal based on the periodic clock signal and a frequency indication signal, the frequency signal indicating a frequency of the frequency indication signal; generates a phase signal indicating a phase shift between the frequency indication signal and the lock signal; and generates a trigger signal based on the generated frequency signal and the generated phase signal. In one embodiment, the control circuitry includes: a counter that generates a count value based on the periodic clock signal and the generated phase signal during operation; and a comparator that compares the count value with the generated frequency signal during operation to generate the trigger signal. In one embodiment, the control circuitry performs a modulo operation between the count value and the generated frequency signal to generate a modulo value, and resets the count value to the modulo value in response to the count value being greater than or equal to the generated frequency signal. In one embodiment, the control circuitry includes an interpolator that upsamples a detection signal to generate an interpolated signal; and a decimator coupled to the interpolator, wherein the decimator downsamples the interpolated signal based on a trigger signal to generate a digital output signal. In one embodiment, the decimator includes a low-pass filter that filters the interpolated signal to generate a filtered signal; a downsampler that downsamples the filtered signal to generate a downsampled signal; and a gain circuit that applies a gain to a DC component of the downsampled signal to generate the digital output signal. In one embodiment, the cutoff frequency and gain of the low-pass filter are based on a frequency indication signal. In one embodiment, the sensor is a MEMS sensor. In one embodiment, the detector includes a mechanical oscillator that oscillates at an oscillation frequency based on a detected physical quantity; and a sensing element coupled to the mechanical oscillator, wherein the sensing element generates an analog signal based on the oscillation frequency of the mechanical oscillator.

[0177] In one embodiment, a system includes a plurality of sensors, each sensor comprising: detection circuitry operable to generate a detection signal indicative of a detected physical quantity; and processing circuitry coupled to the detection circuitry, wherein the processing circuitry is operable to receive the detection signal; receive a frequency indication signal; generate a trigger signal based on the frequency indication signal and a set of local reference signals; and generate a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal comprises outputting a sample of the digital output signal based on the trigger signal and the lock signal is temporally aligned with the digital output signal, wherein the plurality of sensors comprises a reference sensor and slave sensors coupled to the reference sensor; the lock signal of the reference sensor is the received frequency indication signal of the slave sensor. In one embodiment, the system includes: control circuitry coupled to the plurality of sensors, wherein the sensors are operable to provide corresponding digital output signals to the control circuitry. In one embodiment, the control circuitry is operable to: receive the lock signal from the reference sensor; and, in response to receiving the lock signal from the reference sensor, read the digital output signals of the plurality of sensors.

[0178] In one embodiment, a method includes: synchronizing samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronizing including: receiving a first frequency indication signal by the reference sensor; generating a first trigger signal by the reference sensor based on the first frequency indication signal and a first local reference signal set; generating, by the reference sensor, samples of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second local reference signal set; and generating, by the slave sensor, samples of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor. In one embodiment, generating the second trigger signal comprises: counting cycles of a clock signal of the slave sensor; counting a first number of cycles of the clock signal between two consecutive occurrences of a first lock signal; generating an internal frequency signal indicating the first number of cycles, the first number of cycles indicating a frequency of the first lock signal; counting a second number of cycles of the clock signal between an occurrence of the first lock signal and an occurrence of the second lock signal; generating an internal phase signal indicating the second number of cycles, the second number of cycles indicating a time offset between the first lock signal and the second lock signal; and generating the second trigger signal after a third number of cycles of the clock signal, the third number of cycles being a function of the first number of cycles and the second number of cycles. In one embodiment, the digital output signal of the reference sensor has a first frequency and the first lock signal has a second frequency, the second frequency being a submultiple of the first frequency equal to a division order, and wherein counting the first number of cycles of the clock signal comprises dividing the first period by the division order. In one embodiment, generating the second trigger signal after a third number of cycles includes: storing a count value in the slave sensor; increasing the count value by an increment that is a function of a second number of cycles at each cycle of the clock signal; determining whether the count value is greater than or equal to a first number of cycles; and generating the second trigger signal if the count value is greater than or equal to the first number of cycles. In one embodiment, the method includes performing a modulo operation between the count value and the first number of cycles to generate a modulo value if the count value is greater than or equal to the first number of cycles, and resetting the count value to the modulo value.

[0179] In one embodiment, the contents of a non-transitory computer-readable medium configure a processing circuit device to synchronize samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronization comprising: receiving a first frequency indication signal by the reference sensor; generating a first trigger signal by the reference sensor based on the first frequency indication signal and a first set of local reference signals; generating, by the reference sensor, samples of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second set of local reference signals; generating, by the slave sensor, samples of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor. In one embodiment, the contents comprise instructions for execution by the processing circuit device.

[0180] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided, comprising a computer program adapted to perform one or more of the above methods or functions. The medium may be a physical storage medium, such as, for example, a read-only memory (ROM) chip, or a disk, such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, a network, or a portable media product to be read by an appropriate drive or through an appropriate connection (including encoding with one or more bar codes or other related codes stored on one or more such computer readable media and readable by a suitable reader device).

[0181] In addition, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other manners, such as at least partially in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology and various combinations thereof.

[0182] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide still further embodiments.

[0183] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A sensor comprising: a detection circuit arrangement which, in operation, generates a detection signal indicative of a detected physical quantity; as well as A control circuit arrangement is coupled to the detection circuit arrangement, wherein the control circuit arrangement, in operation: receiving the detection signal; receiving a frequency indication signal; generating a trigger signal based on the frequency indication signal and the local reference signal set; A digital output signal and a lock signal are generated based on the trigger signal and the detection signal, wherein generating the digital output signal includes outputting samples of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal.

2. The sensor according to claim 1, wherein the detection circuit device comprises: a detector operable to detect the physical quantity and generate an analog signal indicative of the detected physical quantity; as well as An analog-to-digital (A / D) converter is coupled to the detector and is operable to generate the detection signal based on the analog signal indicative of the detected physical quantity.

3. The sensor according to claim 1, comprising: a clock that, in operation, generates a periodic clock signal, wherein the set of local reference signals includes the lock signal and the periodic clock signal, and the control circuitry, in operation: generating a frequency signal indicating a frequency of the frequency indication signal based on the periodic clock signal and the frequency indication signal; generating a phase signal indicative of a phase shift between the frequency indication signal and the lock signal; and The trigger signal is generated based on the generated frequency signal and the generated phase signal.

4. The sensor of claim 3, wherein the control circuit device comprises: a counter operable to generate a count value based on the periodic clock signal and the generated phase signal; as well as A comparator compares the count value with the generated frequency signal in operation, thereby generating the trigger signal.

5. The sensor of claim 4 , wherein the control circuit arrangement, in operation: performing a modulo operation between the count value and the generated frequency signal to generate a modulo value; and In response to the count value being greater than or equal to the generated frequency signal, the count value is reset to the modulo value.

6. The sensor of claim 2, wherein the control circuitry comprises: an interpolator operable to upsample the detection signal to generate an interpolated signal; as well as A decimator is coupled to the interpolator, wherein the decimator downsamples the interpolated signal based on the trigger signal to generate the digital output signal.

7. The sensor of claim 6, wherein the extractor comprises: a low-pass filter operative to filter the interpolated signal to generate a filtered signal; a downsampler operative to downsample the filtered signal to generate a downsampled signal; as well as A gain circuit is operable to apply a gain to a DC component of the downsampled signal to generate the digital output signal. 8 . The sensor of claim 7 , wherein a cutoff frequency of the low-pass filter and the gain are based on the frequency indication signal.

9. The sensor of claim 1, wherein the sensor is a MEMS sensor.

10. The sensor of claim 2, wherein the detector comprises: a mechanical oscillator which, in operation, oscillates at an oscillation frequency based on the physical quantity being detected; as well as A sensing element is coupled to the mechanical oscillator, wherein the sensing element is operable to generate the analog signal based on the oscillation frequency of the mechanical oscillator.

11. A system comprising: Multiple sensors, each sensor includes: detection circuitry operable to generate a detection signal indicative of a detected physical quantity; and processing circuitry coupled to the detection circuitry, wherein the processing circuitry, in operation: receiving the detection signal; receiving a frequency indication signal; generating a trigger signal based on the frequency indication signal and the local reference signal set; generating a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal comprises outputting samples of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal, wherein The plurality of sensors includes a reference sensor and a slave sensor coupled to the reference sensor; The locking signal of the reference sensor is a received frequency-indicative signal of the slave sensor.

12. The system according to claim 11, comprising: A control circuit arrangement is coupled to the plurality of sensors, wherein the sensors, in operation, provide corresponding digital output signals to the control circuit arrangement.

13. The system of claim 12, wherein the control circuitry, in operation: receiving the lock signal from the reference sensor; and In response to receiving the lock signal of the reference sensor, the digital output signals of the plurality of sensors are read.

14. A method comprising: Synchronizing samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and slave sensors, the synchronizing comprising: receiving a first frequency indication signal by the reference sensor; generating, by the reference sensor, a first trigger signal according to the first frequency indication signal and a first local reference signal set; generating, by the reference sensor based on the first trigger signal, samples of the digital output signal of the reference sensor and a first lock signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second set of local reference signals; and A sample of the digital output signal of the slave sensor and a second lock signal are generated by the slave sensor based on the second trigger signal, the second lock signal being aligned in time with the digital output signal of the slave sensor.

15. The method of claim 14, wherein generating the second trigger signal comprises: counting cycles of a clock signal of the slave sensor; counting a first number of cycles of the clock signal between two consecutive occurrences of the first lock signal; generating an internal frequency signal indicating the first cycle number, the first cycle number indicating a frequency of the first lock signal; counting a second number of cycles of the clock signal between an occurrence of the first lock signal and an occurrence of the second lock signal; generating an internal phase signal indicative of the second cycle number, the second cycle number indicative of a time offset between the first lock signal and the second lock signal; as well as The second trigger signal is generated after a third number of cycles of the clock signal, the third number of cycles being dependent on the first number of cycles and the second number of cycles.

16. The method of claim 15 , wherein the digital output signal of the reference sensor has a first frequency and the first lock signal has a second frequency, the second frequency being a submultiple of the first frequency equal to a division order, and wherein counting a first number of cycles of the clock signal comprises dividing the first number of cycles by the division order.

17. The method of claim 15, wherein generating the second trigger signal after a third number of cycles comprises, by the slave sensor: Store the count value; increasing the count value at each cycle of the clock signal by an increment dependent on the second number of cycles; determining whether the count value is greater than or equal to the first number of cycles; as well as If the count value is greater than or equal to the first number of cycles, the second trigger signal is generated.

18. The method according to claim 17, comprising: If the count value is greater than or equal to the first cycle number, a modulo operation is performed between the count value and the first cycle number, a modulo value is generated, and the count value is reset to the modulo value.

19. A non-transitory computer-readable medium having content for configuring processing circuitry to synchronize samples of digital output signals of a plurality of sensors, the plurality of sensors comprising a reference sensor and slave sensors, the synchronization comprising: receiving a first frequency indication signal by the reference sensor; generating, by the reference sensor, a first trigger signal according to the first frequency indication signal and a first local reference signal set; generating, by the reference sensor based on the first trigger signal, samples of the digital output signal of the reference sensor and a first lock signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving the first lock signal by the slave sensor; generating, by the slave sensor, a second trigger signal based on the first lock signal and a second set of local reference signals; as well as A sample of the digital output signal of the slave sensor and a second lock signal are generated by the slave sensor based on the second trigger signal, the second lock signal being aligned in time with the digital output signal of the slave sensor.

20. The non-transitory computer-readable medium of claim 19, wherein the content comprises instructions executed by the processing circuitry.

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