Zone namespace storage with zone striping

Abstract

The present application relates to zone striping zone namespace memory. A system may determine a memory range associated with data stored in a zone namespace. The system may identify, at one or more memory devices, a plurality of zones in the zone namespace for the memory range, wherein the data is allocated across the plurality of zones. The system may perform a striped memory access operation on the plurality of zones to retrieve the data.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to region namespace memory for region striping in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a system comprising: one or more memory devices; a processing device operably coupled to the one or more memory devices to perform operations comprising: determining a memory range associated with data stored in a zone name space; identifying a plurality of zones in the zone name space for the memory range at the one or more memory devices, wherein data is allocated across the plurality of zones; and performing striped memory access operations on the plurality of zones to retrieve data.

[0004] In another aspect, the present application provides a method comprising: receiving a data stream from an application, wherein the data stream comprises a plurality of data blocks; segmenting the data blocks into a plurality of chunks; and storing the plurality of chunks in a plurality of chunks in a chunk namespace, wherein the plurality of chunks are allocated across the plurality of chunks.

[0005] In another aspect, the present application provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a memory range associated with data stored in a zone namespace; identifying, at the one or more memory devices, a plurality of zones in the zone namespace for the memory range, wherein data is allocated across the plurality of zones; and performing a striped memory access operation on the plurality of zones to retrieve data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2Flowchart of an example method for reading data from one or more memory devices configured with a zone name space (zns) according to some embodiments of the present disclosure.

[0009] Figure 3 Flowchart of an example method for storing data to one or more memory devices configured with a zone name space (zns) according to some embodiments of the present disclosure.

[0010] Figure 4 A block diagram illustrating an application flow mapped to two or more memory devices according to some embodiments of the present disclosure.

[0011] Figure 5 A block diagram illustrating an application flow mapped to two or more memory devices according to some embodiments of the present disclosure.

[0012] Figure 6 A block diagram illustrating an application flow mapped to a memory device according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to a zone name space (zns) memory device with zone striping. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0015] The memory subsystem may include multiple memory devices that can store data from the host system. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The memory subsystem includes a memory subsystem controller that can communicate with the memory device to perform operations such as reading data, writing data, or erasing data at the memory device and other such operations. Figure 1 The memory subsystem controller is described in more detail.

[0016] The memory subsystem may include a high-density non-volatile memory device, where data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states associated with the number of bits stored. The logical state may be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0017] Various applications may have one or more input / output (I / O) streams to access memory devices of the memory subsystem. For example, the stream may include a series of memory access requests and / or commands for accessing the memory device. When the request involves programming data to the memory device, the I / O stream may include a copy of the data to be programmed. Different streams may have different characteristics depending on the source of the I / O stream. For example, the source of the I / O stream may be a database application, such as Apache Cassandra or any other database application, which may generate one or more streams for data logging, retrieval, compression, etc.

[0018] Each stream has unique performance characteristics. For example, logging functionality utilizes high bandwidth and can impact host I / O performance when continuously available. Compression functionality periodically runs in the background to maintain the source (e.g., Cassandra) data tree and requires a lot of bandwidth, which directly impacts acquisition functionality and I / O performance.

[0019] Some memory devices may be configured with a zone namespace. In a zone namespace, the address space of the memory device is divided into zones that allow for more efficient management of data as the capacity of the memory device increases. Using a zone namespace, writes are performed sequentially starting at the beginning of each zone. Data within a zone cannot generally be overwritten arbitrarily. Instead, the zone write pointer is generally reset, effectively deleting the data in the zone and writing of data can be restarted from the beginning of the zone.

[0020] Some applications may experience lower performance when interacting with a memory device configured with a zone namespace. For example, depending on the unique characteristics of the stream, assigning a stream to a zone may limit the performance of the associated application according to conventional methods. If a particular stream requires a bandwidth greater than the bandwidth supplied by the zone to which the stream is assigned in the zone namespace, then performance will be correspondingly impaired. In addition, if an application primarily uses a particular stream, then performance is limited to the bandwidth of one zone assigned to the stream. When a memory device configured with a zone namespace can operate simultaneously with multiple active zones, assigning one stream to one zone unnecessarily limits the performance of an application.

[0021] Aspects of the present disclosure address the above and other deficiencies by providing application access to a memory device configured with a zone namespace, wherein a particular stream can access multiple zones striped across one or more memory devices. In one embodiment, a processing device in a memory subsystem determines a memory range associated with data stored in a zone namespace and identifies multiple zones in the zone namespace for the memory range at one or more memory devices. The processing device further performs a striped memory access operation on the multiple zones to retrieve the data. In another embodiment, the processing device receives a data stream from an application, comprising multiple data blocks. The processing device can segment at least one of the data blocks into multiple blocks and store the blocks spanning multiple zones in the zone namespace.

[0022] Advantages of the methods described herein include, but are not limited to, improved performance in a memory subsystem. Distributing an application stream to multiple zones enhances the throughput of the application stream when multiple zones are accessed simultaneously, compared to distributing the application stream to one zone. Thus, read and program latency is reduced in the memory subsystem, and the quality of service provided to the host system and the source of the data stream is improved.

[0023] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such memory devices.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC) may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic on the die (e.g., the local controller 132) and a controller for media management within the same memory device package (e.g., the memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem 110 includes a zone striping component 113 that can stripe data across multiple zones. In one embodiment, the zone striping component 113 can identify several zones mapped to zones of variable size, where the zones of variable size are used for host application streams. In some embodiments, the memory subsystem controller 115 includes at least a portion of the zone striping component 113. In some embodiments, the zone striping component 113 is part of the host system 120, the application, or the operating system. In other embodiments, the local media controller 135 includes at least a portion of the zone striping component 113 and is configured to perform the functionality described herein. The zone striping component 113 can map one or more zones to zones of variable size and make the one or more zones appear as zones of variable size to the host application. Additional details about the operation of the host striping component 113 are described below.

[0040] Figure 2 Flowchart of an example method 200 for reading data from one or more memory devices configured with a zone name space (zns) according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The process of striping the area of ​​the component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0041] At operation 210, processing logic determines a memory range associated with data stored in a zone namespace. The memory range may be a variable-sized zone allocated to an application stream, wherein the variable-sized zone includes one or more zones in one or more memory devices configured with a zone namespace. For example, the memory range may be associated with a preconfigured zone size based on a type of application associated with the application stream specified by one or more configuration files associated with the zone striping component 113. In another embodiment, the zone size may be configured by a user of the memory device via one or more configuration files. Processing logic may instantiate the memory range and allocate the memory range to the application stream in response to receiving a request from the application stream based on the configuration settings in the one or more configuration files.

[0042] At operation 220, processing logic identifies, at the one or more memory devices, a number of regions in a region name space for a memory range, across which the data is allocated. Identifying the number of regions may be performed using region identifiers for the plurality of regions. For example, if a memory device has regions with identifiers 0 to 4, a first I / O stream may be assigned to region 0, a second I / O stream may be assigned to region 1, and so on. It should be noted that each region identifier may correspond to a contiguous physical address range of memory in the memory device and the region identifiers may be identified using a region mapping table that maps available regions to physical memory addresses of the memory device.

[0043] In one embodiment, identifying the zones in the zone namespace includes identifying a first zone on a first memory device and a second zone on a second memory device. For example, zone 0 of memory device 0 and zone 0 of memory device 1 may be assigned to stream 0. In another embodiment, identifying the zones in the zone namespace includes identifying a first zone on a first memory device and a second zone on a first memory device. For example, zone 0 of memory device 0 and zone 1 of memory device 0 may be assigned to stream 0.

[0044] At operation 230, processing logic performs a striped memory access operation on the zone to retrieve the data. For example, performing a striped memory access operation includes simultaneously accessing multiple blocks storing data associated with an application stream. These multiple blocks are arranged in a striped form across multiple zones in the zone namespace. Therefore, the striped memory access operation can increase the bandwidth of the application stream. For example, processing logic can retrieve multiple blocks within one read access latency, while if the application stream is assigned to one zone, the same read access latency only retrieves one block. Since multiple sequential accesses to the same zone will be performed, the total latency will be much higher. In one embodiment, performing a striped memory access operation on a zone includes accessing multiple blocks from the zone namespace by accessing a first block from a first zone and a second block from a second zone in parallel.

[0045] In one embodiment, the processing logic further programs the data to the memory range (variable size region) at a write pointer of the memory range, wherein the write pointer of the memory range is determined according to the sum of the write pointers of each of the plurality of regions corresponding to the memory range. For example, for a memory range striped with three regions, if the write pointers of the three regions are 0x0004, 0x0004, 0x0004, then the write pointer of the memory range is the sum of the three regions, for example, the write pointer is equal to (0x0004, 0x0004, 0x0004)=0x000C.

[0046] Figure 3Flowchart of an example method 300 for writing data to one or more memory devices configured with a zone name space (zns) according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The process of striping the area of ​​the component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0047] At operation 310, processing logic receives a data stream from an application, wherein the data stream includes a plurality of data blocks. The application may be a database and the data stream may be data being stored to a memory system by the database. The data blocks may have a block size equal to the stripe size multiplied by the block size. Here, the size of the data blocks may be managed by the operating system kernel and is agnostic to the application stream. For example, for a stream striped with three zones, the block size (196 kB) is equal to the stripe size (3) multiplied by the block size (64 kB). Although the block size is shown as 64 kB, the block size may be other multiples of 4 kB.

[0048] At operation 320, processing logic segments the data block into a plurality of blocks. For example, the application block size (196 kB) is segmented into three blocks by the stripe size (3). Each block is written to a zone of the plurality of zones (3 zones) corresponding to the stream in a predetermined order according to the identifier of the zone, for example, in the order of zone 0, zone 1, and zone 2. The zone identifier / index may be assigned by a memory controller of the memory device to map to a physical memory address of the memory device when the memory device is configured with a zone name space.

[0049] At operation 330, processing logic stores the plurality of blocks in a plurality of zones in a zone namespace, wherein the plurality of blocks are allocated across the zones. For example, the blocks are written to the zones across one or more memory devices, the zones are allocated to the streams according to their zone indexes. These allocated zones can be mapped to the streams by the zone striping component 113 according to the zone indexes and the memory device indexes. Because the zones are written sequentially, the blocks are appended to the zones according to the write pointers of the zones.

[0050] In one embodiment, a stream may store data to a first region on a first memory device and a second region on a second memory device. For example, region 0 of memory device 0 and region 0 of memory device 1 may be assigned to stream 0. In one embodiment, a stream may store data to a first region on a first memory device and a second region on a first memory device. For example, region 0 of memory device 0 and region 1 of memory device 0 may be assigned to stream 0.

[0051] In one embodiment, processing logic further programs data to the region (i.e., a variable size region striped across a memory device) at a write pointer corresponding to the stream, wherein the write pointer for the stream is determined based on the sum of the write pointers for each of the regions assigned to the stream.

[0052] Figure 4 A block diagram illustrating application flows mapped to two or more memory devices according to some embodiments of the present disclosure. Application 401 may represent any software executed on host system 120. Application 401 may be a standalone application or a database application such as Apache Cassandra or a file system running on an operating system on host system 120. For example, Cassandra (application 401) may generate input / output (I / O) stream 0, which corresponds to a processing thread of the application that records information about the running status of the application, I / O stream 1 corresponding to a compression thread, and I / O stream 2 corresponding to an acquisition thread.

[0053] Cassandra can output several logs including system logs, debug logs, and garbage collection logs, where the amount of detail in the logs can be configured by the user via the application. The system log is intended for users of the application to manually review and study events related to the health / debugging / garbage collection of the application. Logging events can occur periodically. Cassandra creates immutable files in the file system. The compression process creates new immutable files. Compression can occur automatically periodically in response to some predetermined events or can be manually triggered by user-activated events. Data acquisition is the process of introducing data from other sources (e.g., applications) into Cassandra. The acquired data can be indexed for querying, analysis, modeling, reporting, etc. Data acquisition can have the characteristics of continuous throughput. These Cassandra tasks have different bandwidth and / or throughput characteristics, so they can be better managed by separate I / O streams, such as streams 0 to 2. In one embodiment, the zone striping component 113 is configured to map streams 0 to 2 of the application 401 to zones on the memory device 130. For example, stream 0 may be mapped to region 0 of memory devices 130-1 and 130-2, stream 1 may be mapped to region 1 of memory devices 130-1 and 130-2, stream 2 may be mapped to region 2 of memory devices 130-1 and 130-2, and so on.

[0054] The zone striping component 113 may contain a mapping table that stores name-value pairs of the streams mapped to one or more zones. In one embodiment, the various application streams are identified by unique tag identifiers. When these streams communicate I / O packets to the memory devices 130-1 and 130-2, the zone striping component 113 then assigns the streams to zones that are not assigned to the streams. For example, the zone striping component 113 may assign a stream tag identifier and a corresponding name-value pair, such as stream0: dev0_zone0, dev1_zone0, where the name is a tag identifier identifying stream0, and the value contains: dev0 zone 0 corresponding to device 0 zone 0 and dev1 zone 0 corresponding to device 1 zone 0.

[0055] In one embodiment, the write pointer of stream 0 is calculated using the write pointers assigned to the regions of stream 0. For example, if the write pointer at dev0 region 0 is 0x0004 and the write pointer at dev1 region 0 is 0x0004, then the write pointer of the stream is the sum of the write pointers of their corresponding regions 0x0004+0x0004=0x0008.

[0056] The application stream block size may be the sum of the block sizes among the zones allocated to the application stream. The block size is the smallest unit of data for write or read access. For example, if the block size is 64kB and two zones are allocated to stream0, then the block size of stream0 is 128kB.

[0057] Figure 5 A block diagram illustrating application flows mapped to two or more memory devices according to some embodiments of the present disclosure. Application 401 may represent any software executed on host system 120. For example, application 401 may be a B-tree file system (BTRFS) (Linux's copy-on-write file system format) running on a Linux operating system on host system 120. BTRFS stores host data separately from metadata. BTRFS metadata is data that describes the underlying BTRFS data. In this case, application 401 may have an input / output (I / O) stream 0 corresponding to a BTRFS metadata I / O, an I / O stream 1 corresponding to a BTRFS data I / O, and an I / O stream 2 corresponding to another BTRFS data I / O.

[0058] In one embodiment, the zone striping component 113 is configured to map streams 0 through 2 of the application 401 to multiple zones on the memory devices 130-1 and 130-2. For example, stream 0 may be mapped to zone 0 of the memory devices 130-1 and 130-2, stream 1 may be mapped to zone 5 of the memory devices 130-1 and 130-2, and stream 2 may be mapped to zone 10 of the memory devices 130-1 and 130-2, and so on. The zone striping component 113 may contain a mapping table that stores name-value pairs of the streams mapped to one or more zones.

[0059] Figure 6 A block diagram illustrating an application flow mapped to a memory device according to some embodiments of the present disclosure. Application 401 may represent any software executed on host system 120. For example, application 401 may be Apache Cassandra and / or BTRFS running on a Linux operating system on host system 120.

[0060] In one embodiment, the zone striping component 113 is configured to map streams 0 through 2 of the application 401 to multiple zones on the memory device 130-1. For example, stream 0 may be mapped to zones 0 through 2 of the memory device 130-1, stream 1 may be mapped to zones 5 through 7, and stream 2 may be mapped to zones 10 through 12. The zone striping component 113 may contain a mapping table that stores name-value pairs of the streams mapped to one or more zones.

[0061] Figure 7An example machine of a computer system 600 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0062] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0063] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0064] Processing device 602 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via network 620.

[0065] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0066] In one embodiment, instructions 626 include implementing instructions corresponding to a zone striping component (e.g., Figure 1 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0067] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. In this document, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0068] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0069] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0071] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that is readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0072] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A memory system, comprising: a plurality of memory devices; a processing device operatively coupled to the plurality of memory devices to perform operations comprising: determining a memory range associated with data stored in a region namespace, the region namespace comprising a plurality of regions and requested by a data stream associated with a host system, wherein the region namespace requires sequential writing starting from the beginning of each of the plurality of regions, and wherein the data stored in the region namespace cannot be arbitrarily overwritten; identifying, at the plurality of memory devices for the memory range, the plurality of regions in the region name space, wherein the data is allocated across the plurality of regions, wherein each of the plurality of memory devices includes a region associated with a plurality of different data streams, and wherein each of the plurality of different data streams is associated with a region that spans the plurality of memory devices; as well as Striped memory access operations are performed on the plurality of regions to retrieve the data from the plurality of regions in parallel.

2. The memory system of claim 1, wherein identifying a plurality of regions in the region namespace comprises identifying the plurality of regions in the region namespace based on an index of the plurality of regions.

3. The memory system of claim 1, wherein identifying a plurality of regions in the region namespace comprises identifying a first region on a first memory device and a second region on a second memory device.

4. The memory system of claim 1, wherein identifying a plurality of regions in the region namespace comprises identifying a first region on a first memory device and a second region on the first memory device.

5. The memory system of claim 1, wherein performing striped memory access operations on the plurality of zones comprises accessing a plurality of blocks from the zone namespace by accessing a first block from a first zone and a second block from a second zone in parallel.

6. The memory system of claim 1 , wherein the processing device is to perform operations further comprising: Programming data to the memory range at a write pointer of the memory range, wherein the write pointer of the memory range is determined by: determining a write pointer for each of the plurality of regions corresponding to the memory range; and The write pointer for the memory range is determined as a sum of the write pointers for the plurality of regions.

7. The memory system of claim 1, wherein the region name space is sequentially addressable.

8. A method for a memory system, the method comprising: receiving a data stream from an application, wherein the data stream includes a plurality of data blocks; Segment the data block into multiple blocks; as well as The plurality of blocks are stored in a plurality of zones in a zone namespace, wherein the plurality of blocks are allocated across the plurality of zones on a plurality of memory devices, wherein the zone namespace requires sequential writes starting from the beginning of each of the plurality of zones, wherein data stored in the zone namespace cannot be arbitrarily overwritten, wherein each of the plurality of memory devices includes zones associated with a plurality of different data streams, and wherein each of the plurality of different data streams is associated with zones spanning the plurality of memory devices.

9. The method of claim 8, wherein storing the plurality of chunks in a plurality of zones in a zone namespace comprises storing the plurality of chunks in the plurality of zones based on indexes of the plurality of zones.

10. The method of claim 8, wherein storing the plurality of chunks in a plurality of chunks in a chunk namespace comprises storing a first chunk to a first chunk on a first memory device and storing a second chunk to a second chunk on a second memory device.

11. The method of claim 8, wherein storing the plurality of chunks in a plurality of chunks in a chunk namespace comprises storing a first chunk to a first chunk on a first memory device and storing a second chunk to a second chunk on the first memory device.

12. The method of claim 8, further comprising accessing multiple blocks from the zone namespace by accessing a first block from a first zone and a second block from a second zone in parallel.

13. The method of claim 8, wherein storing the plurality of chunks in a plurality of zones in a zone namespace comprises: determining a write pointer for each of the plurality of zones; and The plurality of blocks are stored in the plurality of zones at each respective write pointer.

14. The method of claim 8, wherein partitioned addressable memory areas are addressed sequentially across the plurality of regions.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a memory range associated with data stored in a region namespace, the region namespace comprising a plurality of regions and requested by a data stream associated with a host system, wherein the region namespace requires sequential writing starting from the beginning of each of the plurality of regions, and wherein the data stored in the region namespace cannot be arbitrarily overwritten; identifying, at a plurality of memory devices, the plurality of regions in the region name space for the memory range, wherein the data is allocated across the plurality of regions, wherein each of the plurality of memory devices includes a region associated with a plurality of different data streams, and wherein each of the plurality of different data streams is associated with a region that spans the plurality of memory devices; and Striped memory access operations are performed on the plurality of regions to retrieve the data from the plurality of regions in parallel.

16. The non-transitory computer-readable storage medium of claim 15, wherein identifying a plurality of zones in the zone namespace comprises identifying the plurality of zones in the zone namespace based on an index of a plurality of zones.

17. The non-transitory computer-readable storage medium of claim 15, wherein identifying a plurality of zones in the zone namespace comprises identifying a first zone on a first memory device and a second zone on a second memory device.

18. The non-transitory computer-readable storage medium of claim 15, wherein identifying a plurality of zones in the zone namespace comprises identifying a first zone on a first memory device and a second zone on the first memory device.

19. The non-transitory computer-readable storage medium of claim 15, wherein performing striped memory access operations on the plurality of zones comprises accessing a plurality of blocks from the zone namespace by accessing a first block from a first zone and a second block from a second zone in parallel.

20. The non-transitory computer-readable storage medium of claim 15, wherein the processing device further performs operations comprising: Programming data to the memory range at a write pointer of the memory range, wherein the write pointer of the memory range is determined by: determining a write pointer for each of the plurality of regions corresponding to the memory range; and The write pointer for the memory range is determined as a sum of the write pointers for the plurality of regions.

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