Integrated circuit order reduction method, device and medium

Abstract

The present invention discloses an integrated circuit order reduction method, device and medium, which are applicable to the field of integrated circuits. According to the spanning function of the orthogonal polynomial, the state variables and input signals of the circuit system model are respectively spanned to obtain a first spanned space and a second spanned space; the first spanned space and the second spanned space are input into the circuit system model to obtain a result function; the expansion coefficient of the result function is obtained for the result function according to the iterative strategy; the expansion coefficient is converted and orthogonalized to obtain a reduced-order matrix of the circuit system model, and the reduced-order system model is determined according to the corresponding relationship between the reduced-order matrix and the circuit system model. This method is based on the model order reduction of orthogonal polynomials, retains the structurality of the original system, realizes the same block structure as the original circuit system, and at the same time reduces the amount of calculation required for the signal completeness analysis of large-scale integrated circuits, saves computing power and time, and improves the reliability of the integrity analysis of the entire circuit system.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit order reduction method, device and medium. Background Art

[0002] With the rapid development of integrated circuits, the device feature size has been reduced to the nanometer level, and the number of transistors integrated on a single chip can reach 10 12 With the increasing complexity and integration of heterogeneous integrated systems, the parasitic effects of interconnect structures have become increasingly complex, and their impact on system performance has become more significant. The number of interconnects within a chip has also increased accordingly. Therefore, fast and effective signal integrity simulation and analysis of large-scale interconnects has posed a new challenge to the field of circuit design automation.

[0003] Existing interconnects need to be processed using the distributed parameter theory of transmission lines. Furthermore, the mathematical model used to describe the circuit system due to the multi-layer stacking of integrated circuits becomes complex, and the number of equations increases, resulting in time-consuming computational power consumption for computing devices. Although model order reduction technology can reduce the amount of computation and shorten signal integrity simulation analysis time, the mathematical model of the circuit system after model order reduction cannot maintain the same block structure as the original circuit system. This undoubtedly increases the time-consuming and complex computational power consumption of computing devices required to distinguish block structures, and reduces the reliability of the integrity analysis of the entire circuit system.

[0004] Therefore, how to improve the reliability of integrity analysis of circuit systems is an urgent problem that those skilled in the art need to solve. Summary of the Invention

[0005] The object of the present invention is to provide an integrated circuit order reduction method, device and medium to improve the reliability of circuit system integrity analysis.

[0006] To solve the above technical problems, the present invention provides a model order reduction method for an integrated circuit, comprising:

[0007] Acquiring characteristic data of the integrated circuit and establishing a circuit system model of the integrated circuit based on the characteristic data;

[0008] According to the spanning function of the orthogonal polynomial, the state variables and input signals of the circuit system model are respectively expanded to obtain a first spanning space and a second spanning space;

[0009] Inputting the first and second integral spaces into the circuit system model to obtain a result function;

[0010] Obtain the expansion coefficient of the result function according to the iterative strategy;

[0011] The expansion coefficients are transformed and orthogonalized to obtain a reduced-order matrix of the circuit system model;

[0012] A reduced-order system model is determined according to the corresponding relationship between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit.

[0013] Preferably, establishing a circuit system model of the integrated circuit based on the characteristic data includes:

[0014] Obtaining input parameters of the integrated circuit and using the current input parameters as inputs of a circuit system model, wherein the output parameters are node voltages and / or branch currents;

[0015] Obtaining a circuit parameter matrix under different process conditions in the integrated circuit as a coefficient matrix, wherein the coefficient matrix includes capacitance values ​​and inductance values ​​of the integrated circuit;

[0016] determining a current position of the integrated circuit according to the current input parameters as an input matrix of the circuit system model;

[0017] determining a first output function based on a relationship between a current output parameter, a resistance matrix of the integrated circuit, an input matrix, and a coefficient matrix, wherein the resistance matrix includes resistance values ​​of the integrated circuit;

[0018] Determine the output position of the integrated circuit according to the current input parameters as the output matrix of the circuit system model;

[0019] determining a second output function according to a relationship between the input parameters and the output matrix;

[0020] The first output function and the second output function are used as a circuit system model.

[0021] Preferably, the expansion coefficients are transformed and orthogonalized to obtain a reduced-order matrix of the circuit system model, including:

[0022] Transform the expansion coefficients to obtain the first matrix;

[0023] Divide the first matrix into blocks to obtain a second matrix;

[0024] Orthogonalize the second matrix using the Schmidt orthogonalization method to obtain the third matrix;

[0025] The third matrix is ​​processed according to the matrix form of the circuit system model to construct a reduced-order matrix.

[0026] Preferably, the order of the expansion coefficient is smaller than the total number of node voltages and branch currents of the integrated circuit.

[0027] Preferably, before converting the expansion coefficients to obtain the first matrix, the method further includes:

[0028] Find the initial eigenvalues ​​of the coefficient matrix;

[0029] Perform eigendecomposition on the initial eigenvalue to extract each eigenvalue;

[0030] Sort the eigenvalues ​​from large to small and get the sum of the eigenvalues;

[0031] Select the current sum of the first N eigenvalues;

[0032] Determine the current proportion value based on the relationship between the current sum value and the total value;

[0033] When the current proportion value exceeds the preset proportion value, N is used as the order of the expansion coefficient and the process proceeds to the step of converting the expansion coefficient to obtain the first matrix.

[0034] Preferably, when the current proportion value does not exceed the preset proportion value, the method further includes:

[0035] Add the N+1th eigenvalue to the current sum to determine the new current sum;

[0036] Determine the new current proportion value based on the relationship between the new current sum value and the total value;

[0037] Determine whether the new current proportion value is greater than the preset proportion value;

[0038] If so, take N+1 as the order of the expansion coefficient;

[0039] If not, the process returns to the step of increasing the N+1th eigenvalue on the basis of the current sum value to determine a new current sum value, until the current sum value exceeds the preset proportion value.

[0040] Preferably, determining the reduced-order system model according to the correspondence between the reduced-order matrix and the circuit system model includes:

[0041] According to the reduced-order matrix, the coefficient matrix, the resistance matrix, the input matrix and the output matrix are orthogonalized respectively to obtain a reduced-order system model of the circuit system model.

[0042] To solve the above technical problems, the present invention further provides a model order reduction device for an integrated circuit, comprising:

[0043] an acquisition module, configured to acquire characteristic data of the integrated circuit and establish a circuit system model of the integrated circuit based on the characteristic data;

[0044] A spanning module is used to span the state variables and input signals of the circuit system model according to the spanning function of the orthogonal polynomial to obtain a first spanning space and a second spanning space;

[0045] An input module, used for inputting the first formed space and the second formed space into the circuit system model to obtain a result function;

[0046] An obtaining module, used for obtaining the expansion coefficient of the result function according to the iteration strategy;

[0047] A processing module, configured to convert and orthogonalize the expansion coefficients to obtain a reduced-order matrix of the circuit system model;

[0048] The determination module is used to determine the reduced-order system model according to the corresponding relationship between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit.

[0049] To solve the above technical problems, the present invention further provides a model order reduction device for an integrated circuit, comprising:

[0050] Memory for storing computer programs;

[0051] A processor is used to implement the steps of the above-mentioned integrated circuit model reduction method when executing a computer program.

[0052] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the model reduction method of the integrated circuit as described above are implemented.

[0053] The present invention provides an integrated circuit order reduction method, comprising: obtaining characteristic data of the integrated circuit and establishing a circuit system model of the integrated circuit based on the characteristic data; performing a spanning expansion of the state variables and input signals of the circuit system model according to a spanning function of an orthogonal polynomial to obtain a first spanning space and a second spanning space; inputting the first spanning space and the second spanning space into the circuit system model to obtain a result function; obtaining expansion coefficients of the result function according to an iterative strategy; converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model; and determining the reduced-order system model based on the corresponding relationship between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit. The method expands the state variables and input signals based on the spanning space of the orthogonal polynomial to obtain a result function, then iteratively obtains the expansion coefficients of the result function, and then orthogonalizes the expansion coefficients to obtain a reduced-order matrix. This method, based on model order reduction based on orthogonal polynomials, retains the structural characteristics of the original system, achieving a block structure identical to the original circuit system, while reducing the computational effort required for large-scale integrated circuit signal integrity analysis, saving computing power and time, and improving the reliability of the integrity analysis of the entire circuit system.

[0054] In addition, the present invention also provides an integrated circuit order reduction device and medium, which have the same beneficial effects as the above-mentioned integrated circuit order reduction method. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 A flowchart of a method for reducing the order of an integrated circuit provided by an embodiment of the present invention;

[0057] Figure 2 A comparison diagram of a reduced-order system and an original system provided by an embodiment of the present invention;

[0058] Figure 3 A structural diagram of an integrated circuit order reduction device provided by an embodiment of the present invention;

[0059] Figure 4 This is a structural diagram of another integrated circuit order reduction device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0061] The core of the present invention is to provide an integrated circuit order reduction method, device and medium to improve the reliability of circuit system integrity analysis.

[0062] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0063] It should be noted that for the mixed-signal and radio frequency circuits in integrated circuits, parasitic effects such as integrated circuit (IC) package pin leakage and substrate coupling have now been widely seen. In addition, parasitic parameter extraction also plays an increasingly important role in signal integrity simulation and optimization. In addition, under heterogeneous process conditions, cross-scale modeling, simulation capabilities and system perception analysis are required for multiple levels (chip-package-board level / system). The scale of interconnects within the chip is also getting larger and larger. Simulating and analyzing the completeness of circuit signals requires establishing an accurate data model for the original circuit. As the operating frequency of integrated circuits becomes higher and higher, interconnects are no longer simple metal wires. For example, multiple RC or RLC circuits are used to approximate high-speed interconnects.

[0064] Model order reduction technology is a very effective means to solve this problem. Since its application in the field of circuit simulation in the 1990s, this technology has made great progress and improvement, providing a fast and effective solution for the simulation analysis of large-scale circuits. The main purpose of model order reduction is to extract redundant information from the original large-scale system and find an approximate smaller reduced-order system that can well approximate the input-output relationship of the original system and retain the main properties of the original system, such as passivity and stability. This can greatly reduce the scale of the original system and reduce the difficulty and complexity of the simulation analysis of the original system. Its main mechanism is that the main information in the high-dimensional space can often be represented by the low-dimensional space. By constructing a suitable low-dimensional space, the original system is approximated in the low-dimensional space. The integrated circuit order reduction method provided by the present invention is based on existing model order reduction technology. While effectively reducing the computational complexity in the signal integrity analysis process of large-scale heterogeneous integrated circuits and accelerating the speed of signal integrity simulation analysis, it also solves the problem of maintaining the same block structure. Since heterogeneous integrated circuits are composed of integrated circuit packages produced by multiple different processes stacked inside the same integrated circuit, the mathematical modeling of integrated circuits produced by different processes requires different modeling accuracy. Therefore, their mathematical models are composed of different block matrix structures and have certain structural characteristics. This requires that the mathematical models after model reduction also have the same block structure so that the physical meaning can be maintained.

[0065] Figure 1 A flowchart of a method for reducing the order of an integrated circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0066] S11: Acquire characteristic data of the integrated circuit, and establish a circuit system model of the integrated circuit based on the characteristic data;

[0067] S12: Expand the state variables and input signals of the circuit system model according to the expansion function of the orthogonal polynomial to obtain a first expansion space and a second expansion space;

[0068] S13: inputting the first formed space and the second formed space into the circuit system model to obtain a result function;

[0069] S14: obtaining an expansion coefficient of the result function according to the iteration strategy;

[0070] S15: converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model;

[0071] S16: Determine a reduced-order system model according to the corresponding relationship between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit.

[0072] Acquire characteristic data of the integrated circuit, which is the input parameters of the integrated circuit, including node voltages and / or branch currents, and the circuit parameter matrix (composed of capacitance and inductance values) under different process conditions within the heterogeneous chip. Establish a circuit system model of the integrated circuit based on the characteristic data, specifically including:

[0073] Acquiring input parameters of the integrated circuit and using the current input parameters as inputs of the circuit system model, wherein the input parameters are node voltages and / or branch currents;

[0074] Obtaining a circuit parameter matrix under different process conditions in the integrated circuit as a coefficient matrix, wherein the coefficient matrix includes capacitance values ​​and inductance values ​​of the integrated circuit;

[0075] determining a current position of the integrated circuit according to the current input parameters as an input matrix of the circuit system model;

[0076] determining a first output function based on a relationship between a current output parameter, a resistance matrix of the integrated circuit, an input matrix, and a coefficient matrix, wherein the resistance matrix includes resistance values ​​of the integrated circuit;

[0077] Determine the output position of the integrated circuit according to the current input parameters as the output matrix of the circuit system model;

[0078] determining a second output function according to a relationship between the input parameters and the output matrix;

[0079] The first output function and the second output function are used as a circuit system model.

[0080] Accordingly, the established circuit system model is as follows:

[0081]

[0082] Where x(t)∈Rn×1 Represents the node voltage and / or branch current in the circuit, that is, the input parameter; B∈R n ×1 represents the output matrix of the circuit system model, n is the number of nodes and the total number of branch circuits in the entire circuit system; u(t) represents the input matrix of the circuit system model, A∈R n×1 Represents the resistance input matrix of the circuit system model, y(t) represents the output matrix of the circuit, C∈R 1×n Represents the output matrix of the circuit system, E is the coefficient matrix, which consists of capacitance and inductance values. The structure of the matrix E is as follows:

[0083]

[0084] Among them, E1, E2, and E3 are circuit parameter matrices under different process conditions inside heterogeneous chips, including capacitance parameters and inductance parameters. For example, E1 is a chip with a 10ns chip, E2 is a chip with a 20ns chip, and E3 is a chip with an external interconnection structure, etc. The number of E in the coefficient matrix here is set according to multiple levels. The present invention is only an example for illustration and is set according to actual conditions.

[0085] It should be noted that the first output function is the first function of the circuit system model, and the second output function is the second function of the circuit system model. When performing signal integrity analysis on a circuit system, directly solving the circuit system model is time-consuming when the circuit scale is relatively large. This is especially inefficient when performing multiple simulation verifications on the circuit. Therefore, researchers have proposed a model reduction method to reduce the order of the circuit system model. The reduced-order mathematical model can not only maintain the inherent structure of the original system, but also approximate the original system with high accuracy.

[0086] According to the spanning function of the orthogonal polynomial, the state variables and input signals of the circuit system model are spanned and expanded to obtain the first spanning space and the second spanning space. Specifically, the state variable is x(t) and the input signal is u(t). This embodiment is based on the time domain model reduction of general orthogonal polynomials, which can greatly reduce the amount of calculation in the signal integrity analysis process and maintain the structure of the original model.

[0087] In general, orthogonal polynomials have the following form:

[0088]

[0089] Among them, when α i , β i , γ i When taking different values, g i (t) can represent different orthogonal polynomials. Table 1 is a table of orthogonal polynomial types, as shown in Table 1:

[0090] Table 1 Orthogonal polynomial type table

[0091]

[0092] As shown in Table 1, different types of orthogonal polynomials are selected, and their coefficients are different. This embodiment will not be described in detail. After the general orthogonal polynomial expansion, the expansion system contains important information. Using the expansion coefficients to construct a reduced-order matrix can retain the main information of the original system. Any function or variable can be expanded in the expansion function of the orthogonal polynomial. The expansion function is as follows:

[0093]

[0094] The state variables and input signals are expanded separately, and the first expansion space is as follows:

[0095]

[0096] Among them, w i is the expansion coefficient;

[0097] The second space is as follows:

[0098]

[0099] Among them, h i is the expansion coefficient;

[0100] Input the first and second space into the circuit system model to obtain the result function, as shown in the following formula:

[0101]

[0102] By general orthogonal polynomials The following formula can be obtained:

[0103]

[0104] because Then we can further get the following formula:

[0105]

[0106] Among them S i =E-β i A;

[0107] The above formula is valid for i=1, 2, ..., m-1, and different result functions are obtained according to different variables, which are:

[0108] When i=1, the resulting function is:

[0109] When i=2,…,m-2, the result function is: S i h i =α i-1 Gh i-1 +γ i+1 Gh i+1 +Bw i

[0110] When i=m-1, the result function is S m-1 h m-1 =α m-2 Gh m-2 +Bw m-1 ;

[0111] The expansion system of each result function is obtained according to the iterative strategy, and its initial value is:

[0112]

[0113] Arrange the result functions to get here The M matrix is ​​sorted as follows:

[0114]

[0115] The F matrix is ​​sorted as follows:

[0116]

[0117] The final result is MH (k+1) =FH (k) +J;

[0118] set up but It can be expressed by the following formula:

[0119]

[0120]

[0121] …

[0122]

[0123] So far, the expansion coefficients of the state variable x(t) are h0, h1, ..., h m-1 Since the selection strategy of m is determined according to the coefficient matrix E of the actual circuit system model, h0, h1, ..., h m-1 After that, it is transformed and orthogonalized to obtain a reduced-order matrix of the circuit system model. As a preferred embodiment, it specifically includes:

[0124] Transform the expansion coefficients to obtain the first matrix;

[0125] Divide the first matrix into blocks to obtain a second matrix;

[0126] Orthogonalize the second matrix using the Schmidt orthogonalization method to obtain the third matrix;

[0127] The third matrix is ​​processed according to the matrix form of the circuit system model to construct a reduced-order matrix.

[0128] Specifically, the expansion coefficients are converted into a matrix form to obtain the first matrix, which is shown in the following matrix:

[0129] Q=[h0 h1…h m-1 ]

[0130] In order to maintain the structure of the original circuit system, that is, to maintain the structure of E, its first matrix (Q matrix) is divided into blocks to obtain the second matrix, which is expressed as follows:

[0131]

[0132] The second matrix is ​​orthogonalized by the Schmidt orthogonalization method to obtain the third matrix V1, V2, V3. The third matrix is ​​further processed according to the matrix form of the circuit system model to obtain the reduced-order matrix V, which is expressed as follows:

[0133]

[0134] The reduced-order system model is determined according to the corresponding relationship between the reduced-order matrix V and the circuit system model to perform performance analysis on the integrated circuit.

[0135] The present invention provides an integrated circuit order reduction method, comprising: obtaining characteristic data of the integrated circuit and establishing a circuit system model of the integrated circuit based on the characteristic data; performing a spanning expansion of the state variables and input signals of the circuit system model according to a spanning function of an orthogonal polynomial to obtain a first spanning space and a second spanning space; inputting the first spanning space and the second spanning space into the circuit system model to obtain a result function; obtaining expansion coefficients of the result function according to an iterative strategy; converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model; and determining the reduced-order system model based on the correspondence between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit. The method expands the state variables and input signals based on the spanning space of the orthogonal polynomial to obtain a result function, then iteratively obtains the expansion coefficients of the result function, and then orthogonalizes the expansion coefficients to obtain a reduced-order matrix. This method, based on model order reduction based on orthogonal polynomials, preserves the structure of the original system, achieving a block structure identical to the original circuit system, while reducing the computational effort required for signal integrity analysis of large-scale integrated circuits, saving computing power and time, and improving the reliability of integrity analysis of the entire circuit system.

[0136] Based on the above embodiment, the order of the expansion coefficient is smaller than the total number of node voltages and branch currents of the integrated circuit.

[0137] Specifically, the order of the expansion coefficient is smaller than the total number of node voltages and branch currents of the integrated circuit in order to achieve the purpose of order reduction. The present invention does not impose any specific restrictions on the specific order setting, and it can be set based on empirical values ​​or to a certain set threshold.

[0138] As a preferred embodiment, before converting the expansion coefficients to obtain the first matrix, the method further includes:

[0139] Find the initial eigenvalues ​​of the coefficient matrix;

[0140] Perform eigendecomposition on the initial eigenvalue to extract each eigenvalue;

[0141] Sort the eigenvalues ​​from large to small and get the sum of the eigenvalues;

[0142] Select the current sum of the first N eigenvalues;

[0143] Determine the current proportion value based on the relationship between the current sum value and the total value;

[0144] When the current proportion value exceeds the preset proportion value, N is used as the order of the expansion coefficient and the process proceeds to the step of converting the expansion coefficient to obtain the first matrix.

[0145] Specifically, the strategy for selecting the order of the expansion coefficients is determined according to the coefficient matrix E of the circuit system model. Since the coefficient matrix is ​​a sparse matrix, it is necessary to perform eigenvalue decomposition on the coefficient matrix to extract each eigenvalue, sort the eigenvalues ​​by size, obtain the sum of the eigenvalues, and further select the current sum of the first N eigenvalues. The current proportion value is determined based on the relationship between the current sum value and the total value. If the current proportion value exceeds the preset proportion value, N is used as the order.

[0146] If the current proportion value does not exceed the preset proportion value, then continue to select N+1 eigenvalues, that is, add the N+1th eigenvalue on the basis of the current sum value to determine the new current sum value;

[0147] Determine the new current proportion value based on the relationship between the new current sum value and the total value;

[0148] Determine whether the new current proportion value is greater than the preset proportion value;

[0149] If so, take N+1 as the order of the expansion coefficient;

[0150] If not, the process returns to the step of increasing the N+1th eigenvalue on the basis of the current sum value to determine a new current sum value, until the current sum value exceeds the preset proportion value.

[0151] For example, the order is determined by selecting the order whose eigenvalue accounts for more than 90% of the total eigenvalues, where 90% is the preset proportion value. It can also be adjusted according to the required accuracy. If a larger preset proportion value is desired, the larger the order, the greater the computing power will be, but the accuracy will be improved.

[0152] The order of the expansion coefficients provided by the embodiment of the present invention is less than the total number of node voltages and branch currents of the integrated circuit. Before converting the expansion coefficients to obtain the first matrix, the order of the expansion coefficients is determined to ensure the purpose of order reduction.

[0153] On the basis of the above embodiment, determining the reduced-order system model according to the correspondence between the reduced-order matrix and the circuit system model includes:

[0154] According to the reduced-order matrix, the coefficient matrix, the resistance matrix, the input matrix and the output matrix are orthogonalized respectively to obtain a reduced-order system model of the circuit system model.

[0155] Specifically, the order of each matrix in the circuit system model is reduced using the reduced-order matrix V. The resulting reduced-order system model is expressed as follows:

[0156]

[0157] in,

[0158] The structure of the coefficient matrix E is maintained, and the physical meaning of its circuit system model is also maintained. The physical meaning of its various matrices is expressed as follows:

[0159]

[0160]

[0161]

[0162] For example, if n is 2004, the coefficient matrix E1 and E2 correspond to the coefficient matrices in the two circuit modules respectively, and the final reduced-order coefficient matrix is

[0163] The order is reduced from 2004 in the original system to 60, Figure 2 A comparison diagram of a reduced-order system and an original system provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the dotted line represents the output of the original system, and the safety line represents the output of the reduced-order system. The structure of the original matrix E is retained. Under the same input as the original system, the reduced-order system can well approximate the original system.

[0164] The embodiment of the present invention provides a reduced-order system model for obtaining a circuit system model by orthogonalizing the coefficient matrix, the resistance matrix, the input matrix, and the output matrix according to the reduced-order matrix, thereby facilitating performance analysis of the integrated circuit.

[0165] The above detailed descriptions of various embodiments corresponding to the integrated circuit order reduction method are based on which the present invention further discloses an integrated circuit order reduction device corresponding to the above method. Figure 3 This is a structural diagram of an integrated circuit order reduction device provided by an embodiment of the present invention. Figure 3 As shown, the order reduction device of the integrated circuit includes:

[0166] an acquisition module 11, configured to acquire characteristic data of the integrated circuit and establish a circuit system model of the integrated circuit based on the characteristic data;

[0167] A spanning module 12 is configured to span the state variables and input signals of the circuit system model according to a spanning function of an orthogonal polynomial to obtain a first spanning space and a second spanning space;

[0168] An input module 13 is used to input the first formed space and the second formed space into the circuit system model to obtain a result function;

[0169] An obtaining module 14 is used to obtain the expansion coefficient of the result function according to the iteration strategy;

[0170] A processing module 15 is used to convert and orthogonalize the expansion coefficients to obtain a reduced-order matrix of the circuit system model;

[0171] The determination module 16 is configured to determine a reduced-order system model according to the corresponding relationship between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit.

[0172] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part please refer to the description of the embodiments of the method part, and will not be repeated here.

[0173] The present invention provides an integrated circuit order reduction device, comprising: obtaining characteristic data of the integrated circuit and establishing a circuit system model of the integrated circuit based on the characteristic data; performing a spanning expansion of the state variables and input signals of the circuit system model based on an orthogonal polynomial spanning function to obtain a first spanning space and a second spanning space; inputting the first spanning space and the second spanning space into the circuit system model to obtain a result function; obtaining expansion coefficients of the result function based on an iterative strategy; converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model; and determining the reduced-order system model based on the correspondence between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit. The device expands the state variables and input signals based on the spanning space of the orthogonal polynomial to obtain a result function, then iteratively obtains the expansion coefficients of the result function, and then orthogonalizes the expansion coefficients to obtain a reduced-order matrix. The device, based on the orthogonal polynomial model order reduction, retains the structural properties of the original system, achieving a block structure identical to the original circuit system, while reducing the computational effort required for signal integrity analysis of large-scale integrated circuits, saving computing power and time, and improving the reliability of integrity analysis of the entire circuit system.

[0174] Figure 4 A structural diagram of another integrated circuit order reduction device provided by an embodiment of the present invention, such as Figure 4 As shown, the device includes:

[0175] Memory 21, for storing computer programs;

[0176] The processor 22 is configured to implement the steps of the integrated circuit order reduction method when executing a computer program.

[0177] The integrated circuit order reduction device provided in this embodiment may include but is not limited to a tablet computer, a notebook computer, or a desktop computer.

[0178] Among them, the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 can be implemented in at least one hardware form of a digital signal processor (DSP), a field programmable gate array (FPGA), and a programmable logic array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0179] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, it can implement the relevant steps of the integrated circuit reduction method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include but is not limited to data involved in the integrated circuit reduction method, etc.

[0180] In some embodiments, the integrated circuit reduction device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0181] Those skilled in the art will understand that Figure 4 The structure shown in the figure does not constitute a limitation on the reduced-order device of the integrated circuit, and may include more or fewer components than shown in the figure.

[0182] The processor 22 implements the integrated circuit order reduction method provided by any of the above embodiments by calling the instructions stored in the memory 21 .

[0183] The present invention provides an integrated circuit order reduction device, comprising: obtaining characteristic data of the integrated circuit and establishing a circuit system model of the integrated circuit based on the characteristic data; performing a spanning expansion of the state variables and input signals of the circuit system model based on an orthogonal polynomial spanning function to obtain a first spanning space and a second spanning space; inputting the first spanning space and the second spanning space into the circuit system model to obtain a result function; obtaining expansion coefficients of the result function based on an iterative strategy; converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model; and determining the reduced-order system model based on the correspondence between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit. The device expands the state variables and input signals based on the spanning space of the orthogonal polynomial to obtain a result function, then iteratively obtains the expansion coefficients of the result function, and then orthogonalizes the expansion coefficients to obtain a reduced-order matrix. The device, based on the orthogonal polynomial model order reduction, retains the structural properties of the original system, achieving a block structure identical to the original circuit system, while reducing the computational effort required for signal integrity analysis of large-scale integrated circuits, saving computing power and time, and improving the reliability of integrity analysis of the entire circuit system.

[0184] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by the processor 22, the steps of the integrated circuit order reduction method described above are implemented.

[0185] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0186] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. The method has the same beneficial effects as the above integrated circuit order reduction method.

[0187] The above is a detailed introduction to the integrated circuit reduction method, integrated circuit reduction device and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0188] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A method for reducing the order of an integrated circuit, characterized in that: include: Acquiring characteristic data of an integrated circuit, and establishing a circuit system model of the integrated circuit based on the characteristic data; Expand the state variables and input signals of the circuit system model according to the expansion function of the orthogonal polynomial to obtain a first expansion space and a second expansion space; Inputting the first formed space and the second formed space into the circuit system model to obtain a result function; Obtaining an expansion coefficient of the result function according to an iterative strategy; Converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model; Determining a reduced-order system model according to a correspondence between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit; Correspondingly, establishing a circuit system model of the integrated circuit according to the characteristic data includes: Acquiring input parameters of the integrated circuit and using the current input parameters as inputs of the circuit system model, wherein the output parameters are node voltages and / or branch currents; Obtaining a circuit parameter matrix under different process conditions in the integrated circuit as a coefficient matrix, wherein the coefficient matrix includes capacitance values ​​and inductance values ​​of the integrated circuit; determining a current position of the integrated circuit according to the current input parameters as an input matrix of the circuit system model; determining a first output function according to a relationship between a current output parameter, a resistance matrix of the integrated circuit, the input matrix, and the coefficient matrix, wherein the resistance matrix includes resistance values ​​of the integrated circuit; determining the output position of the integrated circuit according to the current input parameters as the output matrix of the circuit system model; Determine a second output function according to the relationship between the input parameters and the output matrix; The first output function and the second output function are used as the circuit system model.

2. The integrated circuit order reduction method according to claim 1, wherein: The step of converting and orthogonalizing the expansion coefficients to obtain a reduced-order matrix of the circuit system model includes: Converting the expansion coefficients to obtain a first matrix; Performing block processing on the first matrix to obtain a second matrix; Orthogonalizing the second matrix using a Schmidt orthogonalization method to obtain a third matrix; The third matrix is ​​processed according to the matrix form of the circuit system model to construct the reduced-order matrix.

3. The integrated circuit order reduction method according to claim 2, wherein: The order of the expansion coefficient is smaller than the total number of the node voltages and the branch currents of the integrated circuit.

4. The integrated circuit order reduction method according to claim 3, wherein: Before converting the expansion coefficients to obtain the first matrix, the method further includes: Obtaining initial eigenvalues ​​of the coefficient matrix; Performing eigendecomposition on the initial eigenvalue to extract each eigenvalue; Sort the eigenvalues ​​from largest to smallest and obtain the sum of the eigenvalues; Select the current sum of the first N eigenvalues; Determine a current proportion value according to a relationship between the current sum value and the total value; When the current proportion value exceeds the preset proportion value, N is used as the order of the expansion coefficient and the process proceeds to the step of converting the expansion coefficient to obtain a first matrix.

5. The integrated circuit order reduction method according to claim 4, wherein: When the current proportion value does not exceed the preset proportion value, the method further includes: Adding the N+1th characteristic value to the current sum value to determine a new current sum value; Determine a new current proportion value according to the relationship between the new current sum value and the total value; Determine whether the new current proportion value is greater than the preset proportion value; If yes, then N+1 is used as the order of the expansion coefficient; If not, the process returns to the step of adding the N+1th characteristic value to the current sum value to determine a new current sum value, until the current sum value exceeds the preset proportion value.

6. The integrated circuit order reduction method according to any one of claims 1 to 5, characterized in that: Determining the reduced-order system model according to the correspondence between the reduced-order matrix and the circuit system model includes: The coefficient matrix, the resistance matrix, the input matrix and the output matrix are orthogonalized according to the reduced-order matrix to obtain the reduced-order system model of the circuit system model.

7. An integrated circuit order reduction device, characterized in that: include: an acquisition module, configured to acquire characteristic data of an integrated circuit and establish a circuit system model of the integrated circuit according to the characteristic data; A spanning module, configured to span the state variables and input signals of the circuit system model according to a spanning function of an orthogonal polynomial to obtain a first spanning space and a second spanning space; An input module, configured to input the first formed space and the second formed space into the circuit system model to obtain a result function; An obtaining module, configured to obtain an expansion coefficient of the result function based on an iterative strategy; a processing module, configured to convert and orthogonalize the expansion coefficients to obtain a reduced-order matrix of the circuit system model; a determination module, configured to determine a reduced-order system model based on a correspondence between the reduced-order matrix and the circuit system model to perform performance analysis on the integrated circuit; Correspondingly, establishing a circuit system model of the integrated circuit according to the characteristic data includes: Acquiring input parameters of the integrated circuit and using the current input parameters as inputs of the circuit system model, wherein the output parameters are node voltages and / or branch currents; Obtaining a circuit parameter matrix under different process conditions in the integrated circuit as a coefficient matrix, wherein the coefficient matrix includes capacitance values ​​and inductance values ​​of the integrated circuit; determining a current position of the integrated circuit according to the current input parameters as an input matrix of the circuit system model; determining a first output function according to a relationship between a current output parameter, a resistance matrix of the integrated circuit, the input matrix, and the coefficient matrix, wherein the resistance matrix includes resistance values ​​of the integrated circuit; determining the output position of the integrated circuit according to the current input parameters as the output matrix of the circuit system model; Determine a second output function according to the relationship between the input parameters and the output matrix; The first output function and the second output function are used as the circuit system model.

8. An integrated circuit order reduction device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the integrated circuit order reduction method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the integrated circuit order reduction method according to any one of claims 1 to 6 are implemented.

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