A method for predicting path delay after routing of digital integrated circuits

Abstract

The present invention discloses a method for predicting the path delay after wiring of a digital integrated circuit. First, the circuit is physically designed and statically analyzed by commercial physical design tools and static timing analysis tools, and the timing and physical information of the path before the circuit wiring are extracted as the input features of the prediction model. Then, the transformer network is used to capture the timing and physical correlation of each level of units in the path, and the residual prediction structure is used to calibrate the predicted value of the path delay after wiring, and finally the predicted value of the path delay after wiring is output. Compared with the traditional static timing analysis process, the present invention can accurately and efficiently predict the path delay after wiring before wiring, thereby effectively guiding the design and optimization of the circuit before wiring, which is of great significance for accelerating the design process of digital integrated circuits.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation and relates to a method for predicting path delay after wiring of a digital integrated circuit. Background Art

[0002] As chip design and manufacturing become more and more complex, static timing analysis has become a necessary step in verifying the correctness of chip timing and evaluating whether the chip can work properly at the expected frequency in each design stage of digital integrated circuits. Each stage in the physical design of digital integrated circuits requires frequent interaction with static timing analysis, and the design process is guided by the results of timing analysis. With the continuous advancement of process nodes, the problem of inconsistent timing between design stages is becoming more and more serious. For the downstream design stage, inaccurate timing estimation will cause timing non-convergence, leading to design iterations, affecting the design progress, and consuming huge computing resources, resulting in a waste of design costs, which brings great challenges to the design process.

[0003] Timing analysis and optimization run through all stages of the digital integrated circuit design process, and their accuracy and execution speed are particularly critical for timing closure. Especially in the later stage of physical design, the parasitic capacitance introduced by wiring and the necessary timing optimization measures lead to timing inconsistencies before and after wiring, which pose a challenge to accurate and efficient timing analysis in the early stage of physical design. The pessimistic timing estimation strategy commonly used in engineering will cause over-optimization, waste circuit area, power consumption and design time. The traditional fast pre-wiring timing estimation method based on mathematical models mainly focuses on line length or line delay, ignoring the impact of wiring on unit delay and path delay. In recent years, the pre-wiring timing prediction method based on machine learning has only stayed at the delay prediction of single-level units and networks after wiring, ignoring the timing and physical correlation between units at all levels in the path, and when accumulating the predicted value of path delay, there are the disadvantages of error accumulation and increased computational complexity. Summary of the invention

[0004] Technical problem: The purpose of the present invention is to propose a method for predicting the path delay after wiring of a digital integrated circuit, which can accurately predict the path delay after wiring in the layout stage before wiring, thereby effectively guiding the design and optimization of the circuit before wiring.

[0005] Technical solution: A method for predicting the path delay after wiring of a digital integrated circuit, wherein the prediction of the path delay after wiring refers to the prediction of the path delay after wiring in the layout stage of the back-end design process of the digital integrated circuit; the path includes at least two levels of combinational logic units and does not include sequential logic units; the method includes the following steps:

[0006] S1: Physical design is performed on the circuit netlist after logic synthesis through physical design tools. The design steps include layout planning, layout, clock tree synthesis, routing, etc.

[0007] S2: Extract sample data, perform static timing analysis on the circuits after layout and routing in step S1 respectively through a static timing analysis tool, extract the timing and physical information of each level of cells in the path from the static timing report and layout information of the circuit after layout, form a characteristic sequence of the path, and extract the delay value of the corresponding path from the static timing analysis report of the circuit after routing as a label;

[0008] S3: preprocessing the sample data extracted in step S2, discretizing each continuous feature value in the continuous feature sequence, mapping each discrete feature value in the discrete feature sequence from discrete text to category variables, and padding the feature sequence to ensure that all feature sequences have the same length;

[0009] S4: Build a post-wiring path delay prediction model, input the sample data pre-processed in step S3 into the encoder network, merge the pre-wiring path delay value with the output data of the encoder network, and obtain the residual prediction value of the path delay before and after wiring after dimensionality reduction. Add the pre-wiring path delay value to the residual prediction value of the path delay before and after wiring to finally obtain the post-wiring path delay prediction value;

[0010] S5: Train and verify the model built in step S4, randomly divide the sample data preprocessed in step S3 into training set data and test set data, use the training set data to train the model, and use the test set data to verify the model prediction accuracy and efficiency.

[0011] In the step S2, static timing analysis is performed on the circuit after layout in step S1, and the timing and physical information of each level of the unit in the path are extracted from the static timing analysis report and the layout information to form a characteristic sequence of the path. The timing information of the unit includes the input conversion time of the unit at this level, the output conversion time of the unit at this level, the unit delay of the unit at this level, the input signal polarity of the unit at this level, and the output signal polarity of the unit at this level; the physical information of the unit includes the input pin capacitance of the unit at this level, the total output load capacitance of the unit at this level, the fan-out number of the unit at this level, the type of the unit at this level, the distance between the output pin of the unit at this level and the input pin of the unit at the next level, and the distance between the input pin of the unit at this level and the input pin of the unit at the next level.

[0012] The step S3 specifically comprises the following steps:

[0013] S31: Discretize each continuous eigenvalue in the continuous feature sequence by binning. The continuous feature sequence includes the input conversion time sequence of each level unit in the path, the output conversion time sequence of each level unit, the delay sequence of each level unit, the input pin capacitance sequence of each level unit, the total output load capacitance sequence of each level unit, the distance sequence between the output pin of each level unit and the input pin of the next level unit, and the distance sequence between the input pin of each level unit and the input pin of the next level unit. The binning method determines the accuracy of the eigenvalue that needs to be retained by observing the median, maximum value, minimum value and physical meaning of the eigenvalue. If a continuous eigenvalue in the continuous feature sequence is x, the continuous eigenvalue after binning is x', m is the multiple that the continuous eigenvalue needs to be enlarged, and the round() function returns the integer closest to the input value. The calculation formula of the binning method is formula (1):

[0014] x′=round(m·x) (1)

[0015] S32: Map each discrete feature value in the discrete feature sequence from discrete text to categorical variables through the word segmentation method. The discrete feature sequence includes the input signal polarity sequence of each level unit in the path, the output signal polarity sequence of each level unit, the fan-out number sequence of each level unit, and the type sequence of each level unit. The word segmentation method first trains the mapping dictionary, and then obtains the mapped categorical variable sequence according to the dictionary.

[0016] S33: Fill the feature sequence to make the feature sequence length the same. Set the maximum length of the feature sequence of the training set data to max_len, and fill "0" at the end of the feature sequence whose length is less than max_len, so that the feature sequence length is max_len. For the feature sequence in the test set data with a length greater than max_len, truncate the sequence part with a length greater than max_len, so that the feature sequence length is max_len.

[0017] In step S4, the encoder network is a transformer network, which includes input embedding and position encoding, multi-head self-attention mechanism, fully connected feedforward network, addition and normalization. Step S4 specifically includes the following steps:

[0018] S41: During the input embedding process, there is a dedicated trainable embedding layer for each input sequence feature, which transforms each element in the input sequence into a dim k That is, the input feature sequence with dimension (samples, max_len) is converted to a vector with dimension (samples, max_len, dim k), where samples is the number of samples, max_len is the maximum number of paths, dim k is the word vector dimension specified by the kth feature sequence in the embedding layer, k = 1, 2, ..., n, n is the number of input feature sequences. In the position encoding process, the trigonometric functions shown in formulas (2) and (3) are used to help the network understand the position relationship of the features of each level of the path in the sequence. Where pos represents the position of a feature value in the sequence, pos = 1, 2, ..., max_len, m is the dimension index of the position encoding sequence of the feature value, m = 0, 1, ..., dim k / 2-1, where the even dimension (2m) is coded with the sine function (sin), and the odd dimension (2m+1) is coded with the cosine function (cos). The dimension of the output tensor after position coding is also (samples, max_len, dim k ). That is, the position coding sequence of the feature value at the feature sequence pos has a coding value of PE at 2m. (pos,2m) , the encoding value at 2m+1 is PE (pos,2m+1) For each feature sequence, the positional encoding output tensor is added to the input embedded output tensor to obtain n dimensions (samples, max_len, dim k )

[0019]

[0020]

[0021] S42: Merge the n new tensors in step S41 to obtain a tensor with a dimension of (samples, max_len, dim) as the input X of the multi-head self-attention mechanism, where dim = dim1 + dim2 + ... + dim n , n is the number of input feature sequences. The j-th row vector of X is the comprehensive feature expression of the j-th level unit in the path in terms of timing and physical information, j = 1, 2, ..., max_len. Through three trainable matrices W i Q , W i K , W i V , i = 1, 2, ..., h, perform h linear transformations on X respectively, and obtain h groups of word vectors with dimensions of d k = dim / h matrix Q i , K i 、V i, h is the number of heads of the self-attention mechanism, Q, K, and V represent query, key, and value respectively. i , K i 、V i The attention function is executed in parallel. The calculation formula of the attention mechanism based on the dot product is formula (4). First, calculate Q i With K i Transpose the dot product and divide by the coefficient d k 1 / 2 , then the weight matrix C is obtained by the softmax operation, and finally the weight matrix C is multiplied by V i Get the dimension d k The matrix Z i , which is the calculation result of the attention mechanism Attention(Q i ,K i ,V i ). The elements in the ath row and bth column of the weight matrix C can be considered as the timing and physical correlation between the ath level unit and the bth level unit in the path, a=1,2,…,max_len; b=1,2,…,max_len, and the matrix Z i The number of row vectors is the same as the input X, so Z i The row vector has similar unit timing and physical meaning as X.

[0022]

[0023] Merge the calculation results of the h head attention mechanism head i , i = 1, 2, ..., h, and through a trainable matrix W O Perform a linear transformation to obtain the output MultiHead(X) of the multi-head self-attention mechanism. The calculation formula of the multi-head self-attention mechanism is formula (5), where X is the input of the multi-head self-attention mechanism, W i Q , W i K , W i V , W O is a trainable matrix, i=1,2,…,h.

[0024]

[0025] S43: Add the input X and output MultiHead(X) of the multi-head self-attention mechanism in step S42 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the multi-head self-attention mechanism can be expressed as (6), where LayerNorm() is the output function of the normalization layer.

[0026] LayerNorm(X+MultiHead(X)) (6)

[0027] S44: Connect the standardized output of the multi-head self-attention mechanism in step S43 to a fully connected feedforward neural network, where the neurons in two adjacent layers are fully connected. First, the input is linearly transformed, then passed through the linear rectification activation function max(0,s), where s is the input of the linear rectification activation function, and finally passed through a linear transformation. t is the input of the fully connected feedforward neural network, W1, b1 and W2, b2 are the parameters of the two linear transformations respectively, and the output calculation formula of the fully connected feedforward neural network is formula (7):

[0028] FFN(t)=max(0,tW1+b1)W2+b2 (7)

[0029] S45: Add the input t and output FFN(t) of the fully connected feedforward neural network in step S44 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the connected feedforward neural network can be expressed as (8), where LayerNorm() is the output function of the normalization layer.

[0030] LayerNorm(t+FNN(t)) (8)

[0031] S46: Connect the output of the fully connected feedforward neural network normalization layer in step S45 to the pooling layer, flatten the three-dimensional data into two-dimensional data, and connect it to the fully connected (dense) layer for nonlinear transformation, and randomly discard part of the information through the dropout function to prevent overfitting. Then merge the data with the pre-wiring path delay value features after nonlinear transformation and random information discarding, and transform the merged data nonlinearly to one dimension to obtain the residual prediction value of the path delay before and after wiring. Finally, add the pre-wiring path delay value to the pre-wiring path delay residual prediction value to obtain the final post-wiring path delay prediction value.

[0032] Beneficial effects: The present invention discloses a method for predicting the path delay after wiring of a digital integrated circuit. The self-attention mechanism of the transformer network is used to capture the timing and physical correlation of each level of units in the path, so as to directly predict the path delay. The residual prediction structure is used to calibrate the predicted value of the path delay after wiring, thereby improving the prediction accuracy. Compared with the traditional static timing analysis process, the present invention can accurately and efficiently predict the path delay after wiring before wiring, thereby effectively guiding the design and optimization of the circuit before wiring, which is of great significance for accelerating the design process of digital integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A schematic diagram of a path delay prediction framework after wiring of a digital integrated circuit according to the present invention;

[0034] Figure 2 A schematic diagram of a path delay residual prediction structure after wiring of a digital integrated circuit according to the present invention;

[0035] Figure 3 This is a schematic diagram of the transformer network structure;

[0036] Figure 4 Schematic diagram of the calculation process of the multi-head self-attention mechanism. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is further introduced below in conjunction with specific implementation methods.

[0038] A method for predicting a path delay after wiring of a digital integrated circuit, wherein the prediction of the path delay after wiring refers to the prediction of the path delay after wiring in the layout stage of the back-end design process of the digital integrated circuit; the path includes at least two levels of combinational logic units and does not include sequential logic units; the method includes the following steps:

[0039] S1: Physical design of the circuit netlist after logic synthesis is performed using physical design tools. The design steps include layout planning, layout, clock tree synthesis, routing, etc. For example, physical design of 9 ISCAS and OpenCores benchmark circuits after logic synthesis is performed using IC Complier at SMIC 40nm process, TT process corner, 1.1V voltage, and 25℃ temperature;

[0040] S2: Extract sample data, perform static timing analysis on the circuits after layout and routing in step S1 respectively through static timing analysis tools, extract the timing and physical information of each level of cells in the path from the static timing report and layout information of the circuit after layout, form the characteristic sequence of the path, and extract the delay value of the corresponding path from the static timing analysis report of the circuit after routing as a label. For example, under SMIC 40nm process, TT process corner, 1.1V voltage, 25℃ temperature, set the clock cycle to 5ns, and use PrimeTime to perform static timing analysis on 9 ISCAS and OpenCores benchmark circuits after layout and routing;

[0041] S3: Preprocess the sample data extracted in step S2, discretize each continuous feature value in the continuous feature sequence by binning, map each discrete feature value in the discrete feature sequence from discrete text to category variables by tokenizer, and fill the feature sequence to ensure that all feature sequences have the same length. For example, the binning method, tokenizer method and sequence filling can be completed by using the open source artificial neural network library Keras written in Python;

[0042] S4: Build a post-wiring path delay prediction model, input the pre-processed sample data in step S3 into the transformer network, merge the pre-wiring path delay value with the output data of the transformer network, and obtain the residual prediction value of the path delay before and after wiring after dimensionality reduction. Add the pre-wiring path delay value to the residual prediction value of the path delay before and after wiring to finally obtain the post-wiring path delay prediction value. For example, the post-wiring path delay prediction model can be built using the open source artificial neural network library Keras written in Python and the machine learning library Scikit-learn;

[0043] S5: Train and verify the model built in step S4, randomly divide the sample data preprocessed in step S3 into training set data and test set data, use the training set data for model training, and use the test set data to verify the model prediction accuracy and efficiency. For example, randomly select 80% of all paths extracted from 6 of the 9 ISCAS and OpenCores benchmark circuits as training set data for model training, and the remaining 20% ​​of the paths are used to verify the prediction performance of the model on known circuits, and all paths extracted from the remaining 3 circuits are used to verify the prediction performance of the model on unknown circuits. During training, set the optimizer to Adam, the learning rate to 0.001, the number of training batches to 1080, and the loss function to the root mean square error (RMSE).

[0044] In the step S2, static timing analysis is performed on the circuit after layout in step S1, and the timing and physical information of each level of the unit in the path are extracted from the static timing analysis report and the layout information to form a characteristic sequence of the path. The timing information of the unit includes the input conversion time of the unit at this level, the output conversion time of the unit at this level, the unit delay of the unit at this level, the input signal polarity of the unit at this level, and the output signal polarity of the unit at this level; the physical information of the unit includes the input pin capacitance of the unit at this level, the total output load capacitance of the unit at this level, the fan-out number of the unit at this level, the type of the unit at this level, the distance between the output pin of the unit at this level and the input pin of the unit at the next level, and the distance between the input pin of the unit at this level and the input pin of the unit at the next level.

[0045] The step S3 specifically comprises the following steps:

[0046] S31: Discretize each continuous eigenvalue in the continuous feature sequence by binning. The continuous feature sequence includes the input conversion time sequence of each level unit in the path, the output conversion time sequence of each level unit, the delay sequence of each level unit, the input pin capacitance sequence of each level unit, the total output load capacitance sequence of each level unit, the distance sequence between the output pin of each level unit and the input pin of the next level unit, and the distance sequence between the input pin of each level unit and the input pin of the next level unit. The binning method determines the accuracy of the eigenvalue that needs to be retained by observing the median, maximum value, minimum value and physical meaning of the eigenvalue. If a continuous eigenvalue in the continuous feature sequence is x, the continuous eigenvalue after binning is x', m is the multiple that the continuous eigenvalue needs to be enlarged, and the round() function returns the integer closest to the input value. The calculation formula of the binning method is formula (1):

[0047] x′=round(m·x) (1)

[0048] S32: Map each discrete feature value in the discrete feature sequence from discrete text to categorical variables through the tokenizer method. The discrete feature sequence includes the input signal polarity sequence of each level unit in the path, the output signal polarity sequence of each level unit, the fan-out number sequence of each level unit, and the type sequence of each level unit. The tokenizer method first trains the mapping dictionary, and then obtains the mapped categorical variable sequence based on the dictionary. For example, the tokenizer method is completed through the Tokenizer of Keras, an open source artificial neural network library written in Python. First, fit_on_texts is used to train the mapping dictionary, and then texts_to_sequences is used to obtain the mapped sequence features.

[0049] S33: Pad the feature sequence to make the feature sequence length the same. Set the maximum length of the feature sequence of the training set data to max_len, and fill "0" at the end of the feature sequence whose length is less than max_len, so that the feature sequence length is max_len. For the feature sequence in the test set data with a length greater than max_len, truncate the sequence part whose length is greater than max_len, so that the feature sequence length is max_len. For example, feature sequence padding is completed by pad_sequences of Keras, an open source artificial neural network library written in Python.

[0050] In step S4, a transformer network is used, which includes input embedding and position encoding, multi-head self-attention mechanism, fully connected feedforward network, addition and normalization. Step S4 specifically includes the following steps:

[0051] S41: During the input embedding process, there is a dedicated trainable embedding layer for each input sequence feature, which transforms each element in the input sequence into a dim k That is, the input feature sequence with dimension (samples, max_len) is converted to a vector with dimension (samples, max_len, dim k ), where samples is the number of samples, max_len is the maximum number of paths, dim k is the word vector dimension specified by the kth feature sequence in the embedding layer, k = 1, 2, ..., n, n is the number of input feature sequences. In the position encoding process, the trigonometric functions shown in formulas (2) and (3) are used to help the network understand the position relationship of the features of each level of the path in the sequence. Where pos represents the position of a feature value in the sequence, pos = 1, 2, ..., max_len, m is the dimension index of the position encoding sequence of the feature value, m = 0, 1, ..., dim k / 2-1, where the even dimension (2m) is coded with the sine function (sin), and the odd dimension (2m+1) is coded with the cosine function (cos). The dimension of the output tensor after position coding is also (samples, max_len, dim k ). That is, the position coding sequence of the feature value at the feature sequence pos has a coding value of PE at 2m. (pos,2m) , the encoding value at 2m+1 is PE (pos,2m+1) For each feature sequence, the positional encoding output tensor is added to the input embedded output tensor to obtain n dimensions (samples, max_len, dim k ). For example, the maximum number of paths max_len = 21, and the word vector dimension dim specified in the embedding layer is set to 16.

[0052]

[0053]

[0054] S42: Merge the n new tensors in step S41 to obtain a tensor with a dimension of (samples, max_len, dim) as the input X of the multi-head self-attention mechanism, where dim = dim1 + dim2 + ... + dim n , n is the number of input feature sequences. The j-th row vector of X is the comprehensive feature expression of the j-th level unit in the path in terms of timing and physical information, j = 1, 2, ..., max_len. Through three trainable matrices W i Q , W iK , W i V , i = 1, 2, ..., h, perform h linear transformations on X respectively, and obtain h groups of word vectors with dimensions of d k = dim / h matrix Q i , K i 、V i , h is the number of heads of the self-attention mechanism, Q, K, and V represent query, key, and value respectively. i , K i 、V i The attention function is executed in parallel. The calculation formula of the attention mechanism based on the dot product is formula (4). First, calculate Q i With K i Transpose the dot product and divide by the coefficient d k 1 / 2 , then the weight matrix C is obtained by the softmax operation, and finally the weight matrix C is multiplied by V i Get the dimension d k The matrix Z i , which is the calculation result of the attention mechanism Attention(Q i ,K i ,V i ). The elements in the ath row and bth column of the weight matrix C can be considered as the timing and physical correlation between the ath level unit and the bth level unit in the path, a=1,2,…,max_len; b=1,2,…,max_len, and the matrix Z i The number of row vectors is the same as the input X, so Z i The row vector also has similar unit timing and physical meaning as X. For example, if the number of heads h is set to 2, the dimension d of each word vector after linear transformation is k =8.

[0055]

[0056] Merge the calculation results of the h head attention mechanism head i , i = 1, 2, ..., h, and through a trainable matrix W O Perform a linear transformation to obtain the output MultiHead(X) of the multi-head self-attention mechanism. The calculation formula of the multi-head self-attention mechanism is formula (5), where X is the input of the multi-head self-attention mechanism, W i Q , W i K , W i V , W Ois a trainable matrix, i=1,2,…,h.

[0057]

[0058] S43: Add the input X and output MultiHead(X) of the multi-head self-attention mechanism in step S42 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the multi-head self-attention mechanism can be expressed as (6), where LayerNorm() is the output function of the normalization layer.

[0059] LayerNorm(X+MultiHead(X)) (6)

[0060] S44: Connect the standardized output of the multi-head self-attention mechanism in step S43 to a fully connected feedforward neural network, where the neurons in two adjacent layers are fully connected. First, the input is linearly transformed, then passed through the linear rectification activation function max(0,s), where s is the input of the linear rectification activation function, and finally passed through a linear transformation. t is the input of the fully connected feedforward neural network, W1, b1 and W2, b2 are the parameters of the two linear transformations respectively, and the output calculation formula of the fully connected feedforward neural network is formula (7):

[0061] FFN(t)=max(0,tW1+b1)W2+b2 (7)

[0062] S45: Add the input t and output FFN(t) of the fully connected feedforward neural network in step S44 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the connected feedforward neural network can be expressed as (8), where LayerNorm() is the output function of the normalization layer.

[0063] LayerNorm(t+FNN(t)) (8)

[0064] S46: Connect the output of the fully connected feedforward neural network normalization layer in step S45 to the pooling layer, flatten the three-dimensional data into two-dimensional data, and connect it to the fully connected (dense) layer for nonlinear transformation, and randomly discard part of the information through the dropout function to prevent overfitting. Then merge the data with the pre-wiring path delay value features after nonlinear transformation and random information discarding, and transform the merged data nonlinearly to one dimension to obtain the residual prediction value of the path delay before and after wiring. Finally, add the pre-wiring path delay value to the pre-wiring path delay residual prediction value to obtain the final post-wiring path delay prediction value.

Claims

1. A method for predicting path delay after routing of a digital integrated circuit, characterized in that: The following steps are involved: S1: Physical design of the circuit netlist after logic synthesis. The design steps include layout planning, layout, clock tree synthesis, and routing. S2: Perform static timing analysis on the circuits after layout and routing in step S1, extract the timing and physical information of each level of cells in the path from the static timing report and layout information of the circuit after layout, form a characteristic sequence of the path, and extract the delay value of the corresponding path from the static timing analysis report of the circuit after routing as a label; S3: preprocessing the sample data extracted in step S2, discretizing each continuous feature value in the continuous feature sequence, mapping each discrete feature value in the discrete feature sequence from discrete text to category variables, and padding the feature sequence to ensure that all feature sequences have the same length; S4: Build a post-routing path delay prediction model, input the sample data pre-processed in step S3 into the encoder network, merge the pre-routing path delay value with the output data of the encoder network, and obtain the residual prediction value of the path delay before and after wiring through dimensionality reduction; The path delay value before routing is added to the residual prediction value of the path delay before and after routing, and finally the path delay prediction value after routing is obtained; S5: Train and verify the model built in step S4, divide the sample data preprocessed in step S3 into training set data and test set data, use the training set data to train the model, and use the test set data to verify the model prediction accuracy and efficiency.

2. The method for predicting path delay after routing of a digital integrated circuit according to claim 1, characterized in that: The timing information of the unit includes the input conversion time of the unit at this level, the output conversion time of the unit at this level, the unit delay of the unit at this level, the input signal polarity of the unit at this level, and the output signal polarity of the unit at this level; the physical information of the unit includes the input pin capacitance of the unit at this level, the total output load capacitance of the unit at this level, the fan-out number of the unit at this level, the type of the unit at this level, the distance between the output pin of the unit at this level and the input pin of the next level unit, and the distance between the input pin of the unit at this level and the input pin of the next level unit.

3. The method for predicting path delay after routing of digital integrated circuit according to claim 1, characterized in that: Each continuous eigenvalue in the continuous feature sequence is discretized by the binning method; the continuous feature sequence includes the input conversion time sequence of each level unit in the path, the output conversion time sequence of each level unit, the delay sequence of each level unit, the input pin capacitance sequence of each level unit, the total output load capacitance sequence of each level unit, the distance sequence between the output pin of each level unit and the input pin of the next level unit, and the distance sequence between the input pin of each level unit and the input pin of the next level unit; the binning method determines the accuracy of the eigenvalue that needs to be retained by observing the median, maximum value, minimum value and physical meaning of the eigenvalue; if a continuous eigenvalue in the continuous feature sequence is x, the continuous eigenvalue after the binning method is x', m is the multiple that the continuous eigenvalue needs to be enlarged, and the round() function returns the integer closest to the input value, then the calculation formula of the binning method is formula (1): x′=round(m·x) (1).

4. The method for predicting path delay after routing of a digital integrated circuit according to claim 1, characterized in that: Each discrete feature value in the discrete feature sequence is mapped from discrete text to categorical variables through the word segmentation method; the discrete feature sequence includes the input signal polarity sequence of each level unit in the path, the output signal polarity sequence of each level unit, the fan-out number sequence of each level unit, and the type sequence of each level unit; the word segmentation method first trains the mapping dictionary, and then obtains the mapped categorical variable sequence according to the dictionary.

5. The method for predicting path delay after routing of digital integrated circuit according to claim 1, characterized in that: The specific steps for padding feature sequences to make the feature sequences of the same length are as follows: set the maximum length of the feature sequence of the training set data to max_len, then fill "0" at the end of the feature sequence whose length is less than max_len, so that the length of the feature sequence is max_len; for the feature sequence in the test set data whose length is greater than max_len, truncate the sequence part whose length is greater than max_len, so that the length of the feature sequence is max_len.

6. The method for predicting path delay after routing of a digital integrated circuit according to claim 1, characterized in that: The encoder network is a transformer network.

7. The method for predicting path delay after routing of a digital integrated circuit according to claim 6, characterized in that: The transformer network includes input embedding and position encoding, multi-head self-attention mechanism, fully connected feedforward network, addition and normalization; step S4 specifically includes the following steps: S41: Convert the input feature sequence of dimension (samples, max_len) to dimension (samples, max_len, dim k ), where samples is the number of samples, max_len is the maximum number of paths, dim k is the word vector dimension specified by the kth feature sequence in the embedding layer, k = 1, 2, ..., n, n is the number of input feature sequences; in the position encoding process, the trigonometric functions shown in formulas (2) and (3) are used to help the network understand the position relationship of the features of each level of the path in the sequence, where pos represents the position of a feature value in the sequence, pos = 1, 2, ..., max_len, m is the dimension index of the position encoding sequence of the feature value, m = 0, 1, ..., dim k / 2-1, where the sine function is used for encoding in even dimensions and the cosine function is used for encoding in odd dimensions. The dimension of the output tensor after position encoding is also (samples, max_len, dim k ), that is, the positional encoding sequence of the feature value at the feature sequence pos has a coding value of PE at 2m (pos,2m) , the encoding value at 2m+1 is PE (pos,2m+1) ; For each feature sequence, add the positional encoded output tensor to the input embedded output tensor to obtain n dimensions (samples, max_len, dim k )’s new tensor; S42: Merge the n new tensors in step S41 to obtain a tensor with a dimension of (samples, max_len, dim) as the input X of the multi-head self-attention mechanism, where dim = dim1 + dim2 + ... + dim n ; The j-th row vector of X is the comprehensive feature expression of the j-th level unit in the path in terms of timing and physical information, j = 1, 2, ..., max_len; through three trainable matrices W i Q , W i K , W i V , i = 1, 2, ..., h, perform h linear transformations on X respectively, and obtain h groups of word vectors with dimensions of d k = dim / h matrix Q i , K i 、V i , h is the number of heads of the self-attention mechanism, Q, K, V represent query, address, and value respectively; for h group Q i , K i 、V i The attention function is executed in parallel. The calculation formula of the dot product-based attention mechanism is formula (4); first calculate Q i With K i Transpose the dot product and divide by the coefficient d k 1 / 2 , then the weight matrix C is obtained by the flexible maximum transfer function operation, and finally the weight matrix C is multiplied by V i Get the dimension d k The matrix Z i , which is the calculation result of the attention mechanism Attention(Q i ,K i ,V i ); the elements of the ath row and bth column of the weight matrix C are the timing and physical correlations between the ath level unit and the bth level unit in the path, a=1,2,…,max_len; b=1,2,…,max_len, the matrix Z i The number of row vectors is the same as the input X, so Z i The row vector also has similar unit timing and physical meaning as X; Merge the calculation results of the h head attention mechanism head i , i = 1, 2, ..., h, and through a trainable matrix W O Perform a linear transformation to obtain the output MultiHead(X) of the multi-head self-attention mechanism. The calculation formula of the multi-head self-attention mechanism is formula (5), where X is the input of the multi-head self-attention mechanism, and W i Q , W i K , W i V , W O is a trainable matrix, i=1,2,…,h; S43: Add the input X and output MultiHead(X) of the multi-head self-attention mechanism in step S42 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the multi-head self-attention mechanism can be expressed as (6), where LayerNorm() is the output function of the normalization layer. LayerNorm(X+MultiHead(X)) (6) S44: The output of the multi-head self-attention mechanism after standardization in step S43 is connected to a fully connected feedforward neural network, and the neurons in two adjacent layers are fully connected; first, a linear transformation is performed on the input, and then it passes through the linear rectification activation function max(0,s), where s is the input of the linear rectification activation function, and finally it passes through a linear transformation again; t is the input of the fully connected feedforward neural network, W1, b1 and W2, b2 are the parameters of the two linear transformations respectively, and the output calculation formula of the fully connected feedforward neural network is formula (7): FFN(t)=max(0,tW1+b1)W2+b2 (7) S45: Add the input t and output FFN(t) of the fully connected feedforward neural network in step S44 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the connected feedforward neural network is expressed as (8), where LayerNorm() is the output function of the normalization layer. LayerNorm(t+FNN(t)) (8) S46: Connect the output of the normalization layer of the fully connected feedforward neural network in step S45 to the pooling layer, flatten the three-dimensional data into two-dimensional data, and connect it to the fully connected layer for nonlinear transformation. Randomly discard part of the information through the discard function to prevent overfitting; then merge the data with the pre-wiring path delay value features after nonlinear transformation and random information discarding, and nonlinearly transform the merged data to one dimension to obtain the residual prediction value of the path delay before and after wiring; finally, add the pre-wiring path delay value to the residual prediction value of the path delay before and after wiring to obtain the final post-wiring path delay prediction value.

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