Integrated circuit path delay prediction method based on feature selection and deep learning

Abstract

The present invention discloses a method for predicting integrated circuit path delay based on feature selection and deep learning. First, an integrated feature selection method based on filtering and packaging methods is established to determine the optimal feature subset. Then, the timing information and physical topology information of the circuit are extracted as the input features of the model, and the convolution calculation mechanism of the convolutional neural network is used to capture the local physical and timing expressions of the units in the circuit path. In addition, a residual network is used to calibrate the path delay. Compared with the traditional back-end design process, the present invention has obvious advantages in prediction accuracy and efficiency, and is of great significance for accelerating the integrated circuit design process.

Description

Technical Field

[0001] The present invention relates to a method for predicting an integrated circuit path delay, and in particular to a method for predicting an integrated circuit path delay based on feature selection and deep learning. Background Art

[0002] With the continuous development of integrated circuits and the continuous advancement of process nodes, cost, quality and predictability have become the three major interactive challenges facing integrated circuit design. Cost refers to engineering workload, computing workload and design cycle. Quality refers to traditional evaluation indicators, including power consumption, performance, area, reliability, yield, etc. Predictability refers to the reliability of design progress, such as whether there will be unforeseen layout planning engineering modifications, whether there will be timing convergence cycles that exceed the planned time, etc. With the increasing complexity and integration of chip design and manufacturing, static timing analysis has become a necessary link in all stages of integrated circuit design to verify the correctness of chip timing and evaluate whether the chip can work normally at the expected frequency. Due to the unpredictability of timing convergence and the need to minimize pessimistic design, time-consuming and labor-intensive design iterations have become inevitable. Therefore, in this case, research that can reduce the unpredictability of timing convergence is of great value.

[0003] Each stage of integrated circuit design requires frequent interaction with static timing analysis. With the continuous development of technology and the continuous evolution of process nodes, the problem of inconsistent timing analysis in each stage is becoming more and more serious. Inaccurate timing estimation in the downstream design stage will lead to design iterations, affect the design progress, consume computing resources, and cause cost waste. For example, it is difficult to evaluate the timing inconsistency with subsequent stages at a certain stage in the back-end process. In the actual digital circuit design process, overly pessimistic timing design and multiple iterations are usually used to reduce the impact of inconsistent timing before and after. These solutions either have inaccurate timing estimates or take a long time to calculate, so there is an urgent need for a timing analysis method that can efficiently and accurately predict the timing of a subsequent stage at the current stage. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide an integrated circuit path delay prediction method based on feature selection and deep learning, which can accurately and efficiently predict the circuit path delay of a subsequent stage at a certain stage of circuit back-end design.

[0005] Technical solution: To achieve this purpose, the present invention adopts the following technical solution:

[0006] The integrated circuit path delay prediction method based on feature selection and deep learning of the present invention, wherein the feature selection refers to an integrated feature selection method, and the deep learning refers to a convolutional neural network; the circuit path of the integrated circuit includes at least two levels of combinational logic; the method comprises the following steps:

[0007] S1: Physically implement the synthesized circuit netlist, which includes floorplanning, layout, clock tree synthesis, and routing. Floorplanning is a graphical representation of the main functional modules of the circuit in the experimental layout; layout is the process of placing circuit units and modules on a chip of a specified area for physical design; clock tree synthesis defines the parameters expected to be implemented through the clock tree constraint file, including clock definition, input delay, output delay, etc.; routing configures the interconnection lines of the units and modules arranged at the specified position after layout;

[0008] S2: Extract information from the physical implementation of stage 1 and stage 2 in step S1, and train and predict the circuit path delay of stage 2 based on the information extracted in stage 1. In the physical implementation process, stage 1 is earlier than stage 2. In stage 1, the timing and physical topology information of each level unit in each path is extracted from the static timing report and network report as feature quantities. A total of d features constitute the feature set F = {F1, F2, ..., F d In stage 2, the unit delay and path delay of the static timing report are extracted as the label values ​​of feature selection and convolutional neural network respectively.

[0009] S3: Combine the filtering method and the packaging method to form an integrated feature selection method. The filtering method includes the Pearson correlation coefficient method and the coefficient of variation method, and the packaging method includes backward recursive feature elimination based on the random forest model and backward recursive feature elimination based on linear regression. The full set of features F and the unit delay label obtained in step S2 are input into the integrated feature selection method. According to the principle of minority obeys majority, the results of the above four feature selection methods are voted to determine the best feature subset;

[0010] S4: Build a path delay prediction model. The feature sequence representing the path corresponding to the best feature subset determined in step S3 is used as the input of the one-dimensional convolutional neural network. The path delay of stage 1 passes through the fully connected layer and is merged with the output of the convolutional neural network. After dimensionality reduction, the predicted residual value of the path delay of stage 1 and stage 2 is obtained, which is then added to the path delay of stage 1 to obtain the path delay of stage 2 estimated by the model.

[0011] S5: All data are randomly divided into training set and test set. The integrated feature selection method established in step S3 is used to calculate the feature importance using the training set data and obtain the best feature subset. The model built in step S4 is trained using the training set data, and the model accuracy and efficiency are verified on the trained model using the test set data.

[0012] Preferably, step S2 specifically comprises the following steps:

[0013] S21: Perform static timing analysis on the circuit netlists of phase 1 and phase 2 respectively. Phase 1 is the layout planning phase, or the layout phase, or the clock tree synthesis phase, or the routing phase; Phase 2 is the layout phase, or the clock tree synthesis phase, or the routing phase, or the routing phase. Phase 1 is earlier than Phase 2. The timing and physical topology information of each level unit of each path is extracted from the static timing report and network report of phase 1 as feature quantities, and a total of d feature quantities are combined into a feature set F = {F1, F2, ..., F d}. The feature matrix X composed of the features of all units is a matrix of dimension n×d, where n represents the number of units in the circuit. The rows of the matrix are row vectors composed of all the features of a unit, and the columns of the matrix are feature column vectors composed of the values ​​of all units on a feature. The corresponding unit delay and circuit path delay values ​​are extracted from the static timing analysis report of stage 2 as the label quantities of feature selection and convolutional neural network respectively. The label quantities of all unit delays constitute the label vector Y, and the label quantities of all path delays constitute the label vector Y'. The unit timing features include the input conversion time, output conversion time, input signal polarity, output signal polarity, and delay of the unit. The physical topology features of the unit include the input pin capacitance of the current unit, the input pin capacitance of the next level unit, the total output capacitance of the current unit, the horizontal and vertical coordinates of the input pin of the current unit, the Manhattan distance between the input pin of the current unit and the input pin of the next level unit, the Manhattan distance between the output pin of the current unit and the input pin of the next level unit, the type of the current unit, the type of the next level unit, and the fan-out number of the output pin of the current unit.

[0014] S22: Then, the characteristics of each unit in step S21 are combined into a path feature sequence according to the connection relationship of the units in the circuit path, and the path timing and physical topology feature sequences are used as the input of the convolutional neural network. The path timing feature sequence includes a sequence composed of the input conversion time of each level of units in the path, a sequence composed of the output conversion time of each level of units, a sequence composed of the input signal polarity of each level of units, a sequence composed of the output signal polarity of each level of units, and a sequence composed of the delay of each level of units. The path physical topology feature sequence includes a sequence composed of the input pin capacitance of each level of units in the path, a feature sequence composed of the output pin capacitance of the next level of units of each level, a feature sequence composed of the current total output capacitance of each level of units, a feature sequence composed of the horizontal and vertical coordinates of the input pins of each level of units, a feature sequence composed of the Manhattan distance between the input pins of each level of units and the input pins of the next level of units, a feature sequence composed of the Manhattan distance between the output pins of each level of units and the input pins of the next level of units, a feature sequence composed of the unit types of each level of units, a feature sequence composed of the types of the next level of units of each level, and a feature sequence composed of the fan-out number of the output pins of each level of units. Set the maximum length of the training path to max_len, fill the feature sequence of the path with a length less than max_len, and truncate the feature sequence of the path with a length greater than max_len.

[0015] Preferably: the step S3 specifically comprises the following steps:

[0016] S31: The filtering method mainly uses the distance correlation coefficient method and the coefficient of variation method to calculate the distance correlation coefficient between each feature and the label quantity in step S3 and the normalized coefficient of variation of each unit feature. The distance correlation coefficient method evaluates the importance of features by calculating the distance correlation coefficient. Set the threshold of the distance correlation coefficient to R t , the distance correlation coefficient between the feature and the label quantity exceeds R t The feature composition is the feature subset selected by the distance correlation coefficient method. The distance correlation coefficient is calculated as follows. The n×d feature matrix X and label vector Y obtained by step S21. Formula (1) gives the intermediate variable A kl The calculation method of X is X1, X2, ..., X n , X k ,X l a represents the row vector composed of the features of the kth and lth units, k = 1, 2...n, l = 1, 2...n, n represents the total number of units, d represents the total number of features; a kl Represents X k With X l The Euclidean norm of ; Respectively represent a kl The average value after summing l; Indicates a klrepresents the average value after summing k; for a kl The average value after summing all; A kl is an intermediate variable.

[0017]

[0018] Similarly, formula (2) gives the intermediate variable B kl The calculation method of Y k ,Y l represents the number of delay value labels of the kth and lth units, k = 1, 2...n, l = 1, 2...n, n represents the total number of units; b kl Represents Y k With Y l is the Euclidean norm; Indicates b kl The average value after summing l; Indicates b kl They represent the average values ​​after summing k respectively; for b kl The average value after summing all; B kl is another intermediate variable.

[0019]

[0020] Formula (3) expresses the covariance V between X and Y n 2 (X,Y) and the covariance V of X and Y with themselves n 2 (X), V n 2 (Y) calculation method.

[0021]

[0022] Formula (4) represents the distance correlation coefficient R between the feature matrix X and the label vector Y n 2 The calculation method of (X,Y).

[0023]

[0024] The coefficient of variation rule calculates the normalized coefficient of variation of the feature to evaluate the importance of the feature. Set the threshold of the normalized coefficient of variation to CV t , the normalized coefficient of variation of the feature exceeds CV t The feature composition of is the feature subset selected by the coefficient of variation method. Formula (5) gives the normalized coefficient of variation CV(X i ) is calculated using the formula. iIt represents the i-th feature column vector, i=1,2...column d, d is the total number of features, std() represents the standard deviation, and mean() represents the mean.

[0025]

[0026] S32: The wrapping method depends on the choice of model. We select the backward recursive elimination method based on the random forest and linear regression models, and set the number of features contained in the target feature subset to m (1≤m≤d).

[0027] S321: The feature matrix X of stage 1 obtained in step S2 and the label vector Y composed of the unit delay of stage 2 are used as the input features and labels of the random forest model. In the backward recursive feature elimination process, starting from the full set of features F, the trained random forest model will use an integrated way to calculate the Gini index score of each feature to give the importance of each feature under the model. Then delete the feature F with the least importance. min , get a new feature subset F new .

[0028] S322: Next, the new feature subset F obtained in step S321 is new The model is retrained and new feature importance is obtained to generate a new feature subset. This iteration is continued until the number of features in the new feature subset is m. At this time, the feature subset consisting of the remaining m features is the target feature subset selected by the backward recursive elimination method based on random forest.

[0029] S331: The feature matrix X of stage 1 obtained in step S2 and the label vector Y composed of the unit delay of stage 2 are used as the input features and labels of the random forest model. The linear regression model formula is as shown in (6). f(X) is the output value of the linear regression model, X = (x1, x2, ..., x d ), X is the feature matrix, x l represents the column vector consisting of the values ​​of all units on the lth feature, w l Represents the eigenvector x l The corresponding coefficient in the model, b is the bias, l = 1, 2, ..., d, d represents the total number of features. In the backward recursive feature elimination process, starting from the full set of features F, after the model is trained, it is sorted according to the corresponding coefficient of each feature in the linear regression model, and then the feature with the smallest coefficient, that is, the feature with the lowest importance, is deleted. min ', get a new feature subset F new '.

[0030] f(X)=w1x1+w2x2+…+w d x d +b (6)

[0031] S332: Next, the new feature subset F obtained in step S331 is new 'Retrain the model and obtain the new feature importance to generate a new feature subset. Repeat this process until the number of features in the new feature subset is m. At this time, the feature subset consisting of the remaining m features is the target feature subset selected by the backward recursive elimination method based on linear regression.

[0032] S34: The feature subsets selected by the distance correlation coefficient, the coefficient of variation method, the backward recursive elimination method based on random forests, and the backward recursive elimination method based on linear regression are not exactly the same. The four feature selection methods give the i-th feature F i The selection result is, i=1,2,……d, d is the total number of features. i The feature selection method selects feature F i , m i =0, 1, 2, 3, 4, then the voting result is m i Finally, according to the principle of minority obeys majority, i All features F ≥m0(1≤m0≤4) i The best feature subset F selected by the ensemble feature selection method opt , the number of features contained in it is m opt .

[0033] Preferably: a one-dimensional convolutional neural network is constructed for path delay prediction. The step S4 specifically includes the following steps:

[0034] S41: The best feature subset F selected by the S3 feature selection step opt As input features of a one-dimensional convolutional neural network.

[0035] S42: Each feature is then encoded through input embedding. For each input sequence feature, there is a dedicated trainable embedding layer that converts each element in the input sequence obtained in step S22 into a dim dimension. j The vector of the input feature sequence with dimension (p, max_len) is converted into a vector with dimension (p, max_len, dim j ), where samples is the number of paths in the circuit, max_len is the maximum number of paths, dim j is the word vector dimension specified by the jth feature in the embedding layer, j = 1, 2, ..., m opt , m opt is the number of input features. optThe tensors are merged to obtain a tensor of dimension (p, max_len, dim) as the input tensor T, where dim is m as shown in formula (7). opt The sum of the dimensions of the vectors.

[0036]

[0037] S43: T performs convolution calculations with multiple convolution kernels of different sizes respectively, and the results of the N convolution calculations are respectively subjected to activation functions and maximum pooling to reduce the dimension of the data, and the reduced-dimensional data is spliced ​​with the nonlinearly transformed stage 1 path delay value, and the spliced ​​data is transformed to one dimension through multiple nonlinear transformations, so as to obtain the predicted stage 1 and stage 2 path delay residual values. Finally, the stage 1 path delay value is added to the stage 1 and stage 2 path delay residual prediction values ​​to obtain the final stage 2 path delay prediction value.

[0038] Beneficial effects: The present invention discloses an integrated circuit path delay prediction method based on feature selection and deep learning, which can predict the path delay of a circuit at a certain stage in the back-end design of the circuit at a subsequent stage, and has obvious advantages in accuracy and efficiency compared with the traditional timing analysis process. It is of great significance for guiding circuit design and optimization and accelerating the integrated circuit design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A flowchart of an integrated circuit path delay prediction method based on feature selection and deep learning implemented in the present invention.

[0040] Figure 2 Schematic diagram of the feature selection scheme framework. DETAILED DESCRIPTION

[0041] The technical solution of the present invention is further introduced below in conjunction with specific implementation methods.

[0042] The specific implementation scheme of the present invention discloses a method for predicting the delay of an integrated circuit path based on feature selection and deep learning, wherein the feature selection refers to an integrated feature selection method, and the deep learning refers to a convolutional neural network; the circuit path of the integrated circuit contains at least two levels of combinational logic, for example, when considering circuit data later, the path without combinational logic in the path will be deleted during data preprocessing. This scheme includes the following steps:

[0043] S1: Based on the process node library of SMIC40nm, TT process corner, 1.1V voltage, and 25℃ temperature, this solution uses Synopsys' DesignCompiler tool to synthesize the circuit netlist of 9 benchmark circuits from ISCAS and OpenCores. Then use IC Compiler tool to perform back-end physical implementation of the synthesized circuit netlist, including floorplanning, layout, clock tree synthesis, routing and other processes;

[0044] S2: Use PrimeTime to perform static timing analysis on the physical implementation of stage 1 and stage 2 in step S1 to extract information, and train and predict the circuit path delay of stage 2 based on the information extracted in stage 1. In the physical implementation process, stage 1 is earlier than stage 2. In stage 1, the timing and physical topology information of each level unit in each path is extracted from the static timing report and network report as feature quantities. A total of d features constitute the feature set F = {F1, F2, ..., F d In stage 2, the unit delay and path delay of the static timing report are extracted as the label values ​​of feature selection and convolutional neural network respectively.

[0045] S21: Use Python to write a text processing script to perform static timing analysis on the circuit netlists of phase 1 and phase 2 respectively. Phase 1 is the layout planning phase, or the layout phase, or the clock tree synthesis phase, or the routing phase; Phase 2 is the layout phase, or the clock tree synthesis phase, or the routing phase, or the routing phase. Phase 1 is earlier than Phase 2. The timing and physical topology information of each path and each level unit are extracted from the static timing report and network report of Phase 1 as feature quantities, and a total of d feature quantities are combined into a feature set F = {F1, F2, ..., F d}. The feature matrix X composed of the features of all units is a matrix of dimension n×d, where n represents the number of units in the circuit. The rows of the matrix are row vectors composed of all the features of a unit, and the columns of the matrix are feature column vectors composed of the values ​​of all units on a feature. The corresponding unit delay and circuit path delay values ​​are extracted from the static timing analysis report of stage 2 as the label quantities of feature selection and convolutional neural network respectively. The label quantities of all unit delays constitute the label vector Y, and the label quantities of all path delays constitute the label vector Y'. The unit timing features include the input conversion time, output conversion time, input signal polarity, output signal polarity, and delay of the unit. The physical topology features of the unit include the input pin capacitance of the current unit, the input pin capacitance of the next level unit, the total output capacitance of the current unit, the horizontal and vertical coordinates of the input pin of the current unit, the Manhattan distance between the input pin of the current unit and the input pin of the next level unit, the Manhattan distance between the output pin of the current unit and the input pin of the next level unit, the type of the current unit, the type of the next level unit, and the fan-out number of the output pin of the current unit.

[0046] S22: Then, the characteristics of each unit in step S21 are combined into a path feature sequence according to the connection relationship of the units in the circuit path, and the path timing and physical topology feature sequences are used as the input of the convolutional neural network. The path timing feature sequence includes a sequence composed of the input conversion time of each level of units in the path, a sequence composed of the output conversion time of each level of units, a sequence composed of the input signal polarity of each level of units, a sequence composed of the output signal polarity of each level of units, and a sequence composed of the delay of each level of units. The path physical topology feature sequence includes a sequence composed of the input pin capacitance of each level of units in the path, a feature sequence composed of the output pin capacitance of the next level of units at each level, a feature sequence composed of the current total output capacitance of each level of units, a feature sequence composed of the horizontal and vertical coordinates of the input pins of each level of units, a feature sequence composed of the Manhattan distance between the input pins of each level of units and the input pins of the next level of units, a feature sequence composed of the Manhattan distance between the output pins of each level of units and the input pins of the next level of units, a feature sequence composed of the unit types of each level of units, a feature sequence composed of the types of the next level of units at each level, and a feature sequence composed of the fan-out number of the output pins of each level of units. The maximum length of the training path is set to max_len, and the feature sequences of paths with a length less than max_len are filled based on Kears' pad_sequences, and the feature sequences of paths with a length greater than max_len are truncated.

[0047] S3: Combine the filtering method and the packaging method to form an integrated feature selection method, where the filtering method includes the Pearson correlation coefficient method and the coefficient of variation method, and the packaging method includes backward recursive feature elimination based on the random forest model and backward recursive feature elimination based on linear regression. According to the principle of minority obeys majority, the results of the four feature selection methods are voted to determine the best feature subset. This solution completes the integrated feature selection process composed of the combination of filtering method and packaging method based on the python environment and the machine learning library scikit-learn.

[0048] S31: The filtering method mainly uses the distance correlation coefficient method and the coefficient of variation method to calculate the distance correlation coefficient between each feature and the label quantity in step S3 and the normalized coefficient of variation of each unit feature. The distance correlation coefficient method evaluates the importance of features by calculating the distance correlation coefficient. Set the threshold of the distance correlation coefficient to R t , the distance correlation coefficient between the feature and the label quantity exceeds R t The feature composition is the feature subset selected by the distance correlation coefficient method. The distance correlation coefficient is calculated as follows. The n×d feature matrix X and label vector Y obtained by step S21. Formula (1) gives the intermediate variable A kl The calculation method of X is X1, X2, ..., X n , Xk ,X l a represents the row vector composed of the features of the kth and lth units, k = 1, 2...n, l = 1, 2...n, n represents the total number of units, d represents the total number of features; a kl Represents X k With X l The Euclidean norm of ; Respectively represent a kl The average value after summing l; Indicates a kl represents the average value after summing k; for a kl The average value after summing all; A kl is an intermediate variable.

[0049]

[0050] Similarly, formula (2) gives the intermediate variable B kl The calculation method of Y k ,Y l represents the number of delay value labels of the kth and lth units, k = 1, 2...n, l = 1, 2...n, n represents the total number of units; b kl Represents Y k With Y l is the Euclidean norm; Indicates b kl The average value after summing l; Indicates b kl They represent the average values ​​after summing k respectively; for b kl The average value after summing all; B kl is another intermediate variable.

[0051]

[0052] Formula (3) expresses the covariance V between X and Y n 2 (X,Y) and the covariance V of X and Y with themselves n 2 (X), V n 2 (Y) calculation method.

[0053]

[0054] Formula (4) represents the distance correlation coefficient R between the feature matrix X and the label vector Y n 2 The calculation method of (X,Y).

[0055]

[0056] The coefficient of variation rule calculates the normalized coefficient of variation of the feature to evaluate the importance of the feature. Set the threshold of the normalized coefficient of variation to CV t , the normalized coefficient of variation of the feature exceeds CV t The feature composition of is the feature subset selected by the coefficient of variation method. Formula (5) gives the normalized coefficient of variation CV(X i ) is calculated using the formula. i It represents the i-th feature column vector, i=1,2...column d, d is the total number of features, std() represents the standard deviation, and mean() represents the mean.

[0057]

[0058] S32: The wrapping method depends on the choice of model. We select the backward recursive elimination method based on the random forest and linear regression models, and set the number of features contained in the target feature subset to m (1≤m≤d).

[0059] S321: The feature matrix X of stage 1 obtained in step S2 and the label vector Y composed of the unit delay of stage 2 are used as the input features and labels of the random forest model. In the backward recursive feature elimination process, starting from the full set of features F, the trained random forest model will use an integrated way to calculate the Gini index score of each feature to give the importance of each feature under the model. Then delete the feature F with the least importance. min , get a new feature subset F new .

[0060] S322: Next, the new feature subset F obtained in step S321 is new The model is retrained and new feature importance is obtained to generate a new feature subset. This iteration is continued until the number of features in the new feature subset is m. At this time, the feature subset consisting of the remaining m features is the target feature subset selected by the backward recursive elimination method based on random forest.

[0061] S331: The feature matrix X of stage 1 obtained in step S2 and the label vector Y composed of the unit delay of stage 2 are used as the input features and labels of the random forest model. The linear regression model formula is as shown in (6). f(X) is the output value of the linear regression model, X = (x1, x2, ..., x d ), X is the feature matrix, x l represents the column vector consisting of the values ​​of all units on the lth feature, w l Represents the eigenvector x lThe corresponding coefficient in the model, b is the bias, l = 1, 2, ..., d, d represents the total number of features. In the backward recursive feature elimination process, starting from the full set of features F, after the model is trained, it is sorted according to the corresponding coefficient of each feature in the linear regression model, and then the feature with the smallest coefficient, that is, the feature with the lowest importance, is deleted. min ', get a new feature subset F new '.

[0062] f(X)=w1x1+w2x2+…+w d x d +b (6)

[0063] S332: Next, the new feature subset F obtained in step S331 is new 'Retrain the model and obtain the new feature importance to generate a new feature subset. Repeat this process until the number of features in the new feature subset is m. At this time, the feature subset consisting of the remaining m features is the target feature subset selected by the backward recursive elimination method based on linear regression.

[0064] S34: The feature subsets selected by the distance correlation coefficient, the coefficient of variation method, the backward recursive elimination method based on random forests, and the backward recursive elimination method based on linear regression are not exactly the same. The four feature selection methods give the i-th feature F i The selection result is, i = 1, 2, ... d, d is the total number of features. i The feature selection method selects feature F i , m i =0, 1, 2, 3, 4, then the voting result is m i Finally, according to the principle of minority obeys majority, i All features F ≥m0(1≤m0≤4) i The best feature subset F selected by the ensemble feature selection method opt , the number of features contained is M opt .

[0065] S4: Complete the construction of the path delay prediction model in the Python environment. The feature sequence representing the path corresponding to the best feature subset determined in step S3 is used as the input of the one-dimensional convolutional neural network. The path delay of stage 1 passes through the fully connected layer and is merged with the output of the convolutional neural network. After dimensionality reduction, the predicted residual value of the path delay of stage 1 and stage 2 is obtained, which is then added to the path delay of stage 1 to obtain the path delay of stage 2 estimated by the model.

[0066] S41: The best feature subset F selected by the S3 feature selection step opt As input features of a one-dimensional convolutional neural network.

[0067] S42: Each feature is then encoded through input embedding. For each input sequence feature, there is a dedicated trainable embedding layer that converts each element in the input sequence obtained in step S22 into a dim dimension. j The vector of the input feature sequence with dimension (p, max_len) is converted into a vector with dimension (p, max_len, dim j ), where samples is the number of paths in the circuit, max_len is the maximum number of paths, dim j is the word vector dimension specified by the jth feature in the embedding layer, j = 1, 2, ..., M opt , M opt is the number of input features. opt The tensors are merged to obtain a tensor of dimension (p, max_len, dim) as the input tensor T, where dim is M as shown in formula (7). opt The sum of the dimensions of the vectors.

[0068]

[0069] S43: T performs convolution calculations with multiple convolution kernels of different sizes, and the results of the convolution calculations are respectively subjected to activation functions and maximum pooling to reduce the dimension of the data. The reduced-dimensional data is spliced ​​with the nonlinearly transformed stage one path delay value, and the spliced ​​data is transformed to one dimension through multiple nonlinear transformations to obtain the predicted stage one and stage two path delay residual values. Finally, the stage one path delay value is added to the stage one and stage two path delay residual prediction values ​​to obtain the final stage two path delay prediction value. This solution implements the construction of a one-dimensional convolutional neural network based on the pytorch framework, and sets some parameters of the network, including: the number of convolution kernels is 2, the sizes of the three convolution kernels are 3, 4, and 5, the convolution step size is 1, and the activation function is linear rectification (Relu).

[0070] S5: Divide the training set and the test set, use the training set to train the model, and verify the model accuracy and efficiency on the test set. The training and test circuits are selected from the benchmark circuits of ISCAS and OpenCores, of which systemcaes, aes_core, ecg, s38417, vga_lcd, and wb_commax are known circuits, and ethenet, pci_bridge32, and tv80 are unknown circuits. 80% of the paths of the known circuits are randomly selected as training sets, and 20% are used as test sets to predict the prediction performance of the model on known circuits. All paths of unknown circuits are used as test sets to verify the prediction performance of the model on unknown circuits. At the same time, this scheme also considers the running time of the integrated circuit path delay prediction method based on feature selection and deep learning and compares it with the time of the traditional process to obtain a large amount of time savings.

Claims

1. An integrated circuit path delay prediction method based on feature selection and deep learning, characterized by: The following steps are involved: S1: Physically implement the synthesized circuit netlist, including floorplanning, layout, clock tree synthesis, and routing stages; S2: Perform static timing analysis on the circuit netlist of the physical implementation phase 1 and the phase 2 after phase 1, respectively, and extract the timing and physical topology information of each path and each level unit from phase 1 as feature quantities. Construct a feature set F, extract unit delay and circuit path delay from stage 2 as feature selection and label values ​​of convolutional neural network, train convolutional neural network, and predict circuit path delay of stage 2; S3: Combining the filtering method and the packaging method to form an integrated feature selection method; The full feature set F and the unit delay labels are input into an integrated feature selection method to determine the best feature subset; S4: The feature sequence representing the path composed of the features corresponding to the best feature subset is used as the input of the one-dimensional convolutional neural network. The path delay of stage 1 is merged with the output of the convolutional neural network after passing through the fully connected layer. After dimensionality reduction, the predicted residual value of the path delay of stage 1 and stage 2 is obtained, which is then added to the path delay of stage 1 to obtain the path delay of stage 2 estimated by the model. S5: All data are randomly divided into training set and test set, and the integrated feature selection method uses the training set data to calculate the feature importance and obtain the best feature subset; Use the training set data to train the constructed model, and use the test set data to verify the model accuracy and efficiency on the trained model; The filtering methods include distance correlation coefficient method and coefficient of variation method, and the packaging methods include backward recursive feature elimination based on random forest model and backward recursive feature elimination based on linear regression; The steps to evaluate feature importance using the wrapper method include: S32: Set the number of features included in the target feature subset to m, 1≤m≤d, and d is the total number of features; S321: The feature matrix X of stage 1 obtained in step S2 and the unit delay label vector Y of stage 2 are used to train the random forest model, and then the Gini index score of each feature is calculated to obtain the importance of each feature under the random forest model; the feature with the least importance is selected and deleted from the feature matrix X to obtain an updated feature matrix X with a dimension of n×(d-1); S322: Repeat step 321 by backward recursive feature elimination to update the feature quantity matrix X until its dimension is n×m, and stop iteration; at this time, the feature subset composed of the remaining m features is the target feature subset selected by the backward recursive elimination method based on the random forest model; S331: The feature matrix X of stage 1 obtained in step S2 and the unit delay label vector Y of stage 2 are used to train the linear regression model, and then the output value f(X) of the linear regression model is calculated according to formula (1), x i The eigenvector of the i-th column of the unit feature matrix X corresponds to the i-th feature of all n units, 1≤i≤d, w i represents the eigenvector x of column i i The corresponding coefficient in the linear regression model, b is the bias; select w i The smallest feature quantity is deleted from the feature quantity matrix X to obtain the updated feature quantity matrix X. S332: Repeat step S331 by backward recursive feature elimination to update the feature matrix X until its dimension is n×m, and stop iteration; at this time, the feature subset composed of the remaining m features is the target feature subset selected by the backward recursive elimination method based on the linear regression model; The steps to determine the best feature subset using the ensemble feature selection method include: The threshold selected by the distance correlation coefficient method exceeds R t The feature subset composed of the feature vectors and the threshold selected by the coefficient of variation method exceeds CV t The feature subset composed of the feature vector of , the feature subset composed of m features selected by the backward recursive elimination method based on the random forest model, and the feature subset composed of m features selected by the backward recursive elimination method based on the linear regression model are not exactly the same; the four feature selection methods give the i-th feature F i The selection result is 1≤i≤d, d is the total number of features; if there are m i The feature selection method selects feature F i , 0≤m i ≤4, then the voting result is m i According to the principle of majority rule, i ≥m0, 1≤m0≤4, all features F i The best feature subset F selected by the ensemble feature selection method opt , the number of features contained in it is m opt ; The one-dimensional convolutional neural network for path delay prediction is constructed. Step S4 specifically includes the following steps: S41: The best feature subset F selected according to the S3 feature selection step opt , select the corresponding columns in the feature matrix X of stage 1 obtained in step S2 to form the matrix X opt , with dimensions of n×m opt , as the input feature matrix of the one-dimensional convolutional neural network; S42: Encode each feature through the input embedding layer; for each input sequence feature, there is a dedicated trainable embedding layer that converts each feature in the input sequence obtained in step S22 into a dim dimension. j The vector of the input feature sequence with dimension (p, max_len) is converted into a vector with dimension (p, max_len, dim j ), where p is the number of paths in the circuit, max_len is the maximum length of the path, dim j is the word vector dimension specified by the jth feature in the embedding layer, 1≤j≤m opt ; m opt The tensors are merged to obtain a tensor of dimension (samples, max_len, dim) as the input tensor T, where dim is m as shown in formula (2). opt The sum of the dimensions of the vectors, S43: Perform convolution calculations on the input tensor T obtained in step S42 with multiple convolution kernels of different sizes, respectively, and perform data dimensionality reduction on the convolution calculation results through activation functions and maximum pooling, and concatenate the reduced-dimensional data with the stage 1 path delay value that has undergone nonlinear transformation, and transform the concatenated data to one dimension through multiple nonlinear transformations to obtain predicted stage 1 and stage 2 path delay residual values; finally, add the stage 1 path delay value to the stage 1 and stage 2 path delay residual prediction values ​​to obtain the stage 2 path delay prediction value.

2. The integrated circuit path delay prediction method based on feature selection and deep learning according to claim 1, characterized in that: The unit timing characteristics include the unit's input conversion time, output conversion time, input signal polarity, output signal polarity, and delay; the unit physical topology characteristics include the input pin capacitance of the current unit, the input pin capacitance of the next-level unit, the total output capacitance of the current unit, the horizontal and vertical coordinates of the input pin of the current unit, the Manhattan distance between the input pin of the current unit and the input pin of the next-level unit, the Manhattan distance between the output pin of the current unit and the input pin of the next-level unit, the current unit type, the type of the next-level unit, and the fan-out number of the output pin of the current unit.

3. The integrated circuit path delay prediction method based on feature selection and deep learning according to claim 1, characterized in that: In step S2, the features of each unit, i.e., the full feature set F, are combined into a path feature sequence according to the connection relationship of the units in the circuit path, and the path timing and physical topology feature sequence are used as inputs of the convolutional neural network.

4. The integrated circuit path delay prediction method based on feature selection and deep learning according to claim 1, characterized in that: The distance correlation coefficient method evaluates the importance of features by calculating the distance correlation coefficient; The coefficient of variation method evaluates feature importance by calculating the normalized coefficient of variation of the feature.

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