An electronic synaptic circuit and neural network circuit based on ferroelectric tunneling junction

Abstract

An electronic synaptic circuit and a neural network circuit based on a ferroelectric tunneling junction. The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive a first input signal, a second input signal and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit comprises at least a switch unit, an input unit and a weight calculation unit; the present application also relates to an electronic system and an electronic device comprising the aforementioned neural network circuit.

Description

Technical Field

[0001] The present application relates to the field of neural network circuit design, and in particular to an electronic synapse circuit and a neural network circuit based on a ferroelectric tunneling junction. Background Art

[0002] With the rapid development of information technology industries such as artificial intelligence and big data, people's social production and daily life have higher and higher requirements for computer processing speed and performance. The amount of data that computers need to process is growing exponentially, which has brought unprecedented pressure on data storage and computing. The most commonly used computer architecture at present is the traditional von Neumann architecture, which has the characteristics of storage and computing separation. This means that when computers process massive amounts of data, they have to frequently migrate data between microprocessors and memories, which leads to a significant decrease in computing speed and a significant increase in energy consumption, which is the so-called von Neumann bottleneck.

[0003] In order to solve the problems of the von Neumann architecture, researchers turned their attention to brain-like computing technology. By imitating the connection between neurons and synapses in the brain, neuroscience theoretical modeling is completed to solve complex computing problems that cannot be processed at high speed in traditional architectures. The LIF neuron model is one of the most basic models commonly used in neuromorphic computing architectures. Its essence abstracts neurons into capacitors and converts the way neurons communicate into action potentials and pulses. In the LIF neuron model, the potential of the electrical signal input to the neuron and the stability of the final output pulse are both core factors that can improve the stability and processing speed of the neuron model.

[0004] As an emerging computing paradigm, if the behavior of neurons or synapses is simulated at the physical level through hardware circuits, neuromorphic computing with low power consumption and high computing performance can be achieved. Therefore, choosing a reasonable computing method and designing and building hardware circuits are also important issues in realizing neuromorphic computing. Summary of the invention

[0005] The present application proposes a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive a first input signal, a second input signal and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit at least comprises: a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control the connection state between the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of the control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive a first input signal and a second input signal from the presynaptic neuron circuit under the control of the feedback signal from the postsynaptic neuron circuit; a weight calculation unit, coupled between the switch unit and the ground and coupled to the input unit, the weight calculation unit at least comprising a ferroelectric tunneling junction, the ferroelectric tunneling junction being configured to receive the first input signal and the second input signal from the input unit to update the tunneling resistance of the ferroelectric tunneling junction.

[0006] In particular, the postsynaptic neuron circuit at least includes a comparator, whose negative input terminal is coupled to the switch unit of the electronic synapse circuit, the positive input terminal of the comparator is configured to receive a preset constant signal, and the output terminal of the comparator is coupled to the input unit of the electronic synapse circuit; a resistor, which is coupled between the negative input terminal of the comparator and a power supply; a capacitor, which is coupled between the negative input terminal of the comparator and ground; when the switch unit connects the postsynaptic neuron circuit to the electronic synapse circuit and the ferroelectric tunnel junction is turned on, the voltage at the negative input terminal of the comparator drops, and when the voltage drops below the preset constant signal, the comparator is configured to output the feedback signal.

[0007] Particularly, the switch unit comprises at least a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the negative input terminal of the comparator, and a second electrode of which is coupled to the first end of the ferroelectric tunnel junction.

[0008] In particular, the input unit includes at least a second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the first end of the ferroelectric tunnel junction; a third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction; and a fourth transistor, which is of a type complementary to the third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction.

[0009] Particularly, the post-synaptic neuron circuit further comprises a delay unit, which is coupled between the output terminal of the comparator and the input terminal of the input unit and is configured to generate a time interval between the effective levels of the control signal and the feedback signal.

[0010] In particular, the first end of the ferroelectric tunnel junction is configured to receive the first input signal, and the second end of the ferroelectric tunnel junction is configured to receive the second input signal; the control signal jumps to a valid level after the first input signal jumps to an invalid level and before the second input signal jumps to a valid level, and the first input signal jumps to a valid level when the valid level of the second input signal jumps to an invalid level; the valid level of the second input signal gradually increases during a pulse, and the valid level of the first input signal gradually decreases during a pulse.

[0011] Particularly, the effective level amplitude of the feedback signal is greater than the maximum amplitude of the effective level of the first input signal or the second input signal.

[0012] The present application also discloses an electronic synaptic circuit, configured to receive a first input signal, a second input signal and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit at least includes a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control the connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of the control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive the first input signal and the second input signal from the presynaptic neuron circuit under the control of the feedback signal from the postsynaptic neuron circuit; a weight calculation unit, coupled between the switch unit and the ground, and coupled to the input unit, the weight calculation unit at least includes a ferroelectric tunneling junction, the ferroelectric tunneling junction is configured to receive the first input signal and the second input signal from the input unit to update the tunneling resistance of the ferroelectric tunneling junction.

[0013] Particularly, the switch unit comprises at least a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the negative input terminal of the comparator, and a second electrode of which is coupled to the first end of the ferroelectric tunnel junction.

[0014] In particular, the input unit includes at least a second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the first end of the ferroelectric tunnel junction; a third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction; and a fourth transistor, which is of a type complementary to the third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction.

[0015] In particular, the first end of the ferroelectric tunnel junction is configured to receive the first input signal, and the second end of the ferroelectric tunnel junction is configured to receive the second input signal; the control signal jumps to a valid level after the first input signal jumps to an invalid level and before the second input signal jumps to a valid level, and the first input signal jumps to a valid level when the valid level of the second input signal jumps to an invalid level; the valid level of the second input signal gradually increases during a pulse, and the valid level of the first input signal gradually decreases during a pulse.

[0016] Particularly, the effective level amplitude of the feedback signal is greater than the maximum amplitude of the effective level of the first input signal or the second input signal.

[0017] The present application also discloses an electronic system, comprising the neural network circuit as described above.

[0018] The present application also discloses an electronic device, comprising the neural network circuit as described above.

[0019] The scheme of this application can achieve the advantages of low power consumption and high computing performance by simulating neurons based on the physical structure of the circuit. On the other hand, the signal transmission of the neuromorphic circuit can be optimized by using the STDP mechanism, which can further shorten the time spent on circuit processing. The use of ferroelectric tunneling junctions in circuit design can further reduce the power consumption of the circuit and improve the processing speed through its non-volatile characteristics. The new neural network circuit structure proposed in this scheme also has a positive significance for promoting the development of neuromorphic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0021] Figure 1 Shown is a schematic diagram of a neural network circuit model according to an embodiment of the present application;

[0022] Figure 2 Shown is a schematic diagram of a characteristic curve of the STDP mechanism of an electronic synapse;

[0023] Figure 3A Shown is a schematic diagram of an electronic synaptic circuit and a portion of a postsynaptic neuron circuit according to an embodiment of the present application;

[0024] Figure 3B Shown Figure 3A The working timing diagram of the circuit shown;

[0025] Figure 4 Shown is a curve showing the change of normalized conductance of an electronic synaptic circuit over time according to one embodiment of the present application. DETAILED DESCRIPTION

[0026] In the specific description of the following embodiments, reference will be made to the attached drawings that constitute a part of the present application. The attached drawings show specific embodiments that can implement the present application by way of example. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present application. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present application. Therefore, the following specific description is not restrictive, and the scope of the present application is limited by the attached claims.

[0027] The technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0028] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0029] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor.

[0030] Traditional computer architecture divides the device into computing units and storage units. To complete a calculation, the computing unit needs to be called to calculate the data to be processed, and then the calculation result is stored in the storage unit. When faced with large data and more complex calculation processes, traditional computer architecture needs to split the calculation process into multiple simple calculations and repeat the above steps many times. Before the final calculation result is obtained, multiple intermediate values ​​will be generated and stored in the storage unit, and these intermediate values ​​will be called to complete the calculation of the final result.

[0031] The artificial neural network circuit (hereinafter referred to as the neural network circuit) proposed in this application can effectively simplify complex calculation processes and avoid the problems caused by the separation of storage and calculation.

[0032] Figure 1 Schematic diagram of a neural network circuit model according to an embodiment of the present application. A neural network circuit includes multiple nodes, also known as neurons, and two neurons can be connected through electronic synapses. The synapse transmits electrical signals from the electronic presynaptic neuron to the postsynaptic neuron, and the transmission path depends on the weight of the electronic synapse between the neurons. The higher the weight, the tighter the connection between the two neurons.

[0033] like Figure 1 As shown, according to one embodiment of the present application, a neuron in a neural network circuit can be connected to multiple neurons, and two neurons are connected and transmit signals through electronic synapses. The calculation to be completed can be converted into multiple loop calculations in the neural network circuit, and a single calculation process can be converted into a process of transmitting signals from the initial neuron set by the user in the neural network circuit, passing through multiple neurons and electronic synapses, and finally transmitting to the target neuron set by the user. The neural network circuit automatically adjusts the weights between neurons based on a preset learning mechanism, thereby realizing the calculation process of different problems.

[0034] Each electronic synapse can receive signals from at least one neuron (referred to as a presynaptic neuron with respect to the synapse), and / or can send signals to at least one neuron (referred to as a postsynaptic neuron with respect to the synapse).

[0035] Figure 2 The figure shows a characteristic curve of the STDP learning mechanism of an electronic synapse. The time Δt on the horizontal axis represents the time difference between the moment when the postsynaptic neuron emits a signal and the moment when the presynaptic neuron emits a signal, and the ΔW on the vertical axis represents the rate of change of the weight of the electronic synapse. Figure 2 It can be seen that for this type of electronic synapse, when Δt is positive, the rate of change of the weight of the electronic synapse will decrease as Δt increases.

[0036] In order to prepare an electronic synapse having the above STDP learning mechanism characteristic curve, the present application provides an electronic synapse circuit. In particular, the electronic synapse circuit includes a ferroelectric tunneling junction (FTJ).

[0037] With the development of semiconductor device technology, some new devices with adjustable resistance and non-volatile characteristics have been proposed, including resistive memory, phase change memory, ferroelectric tunneling junction (FTJ), etc. Among them, ferroelectric tunneling junction has the advantages of high density, low power consumption and high operating speed, so it has attracted extensive attention from scientific research and industry.

[0038] FTJ is a new type of tunnel junction based on ferroelectric materials. It is a heterostructure with an ultra-thin ferroelectric layer as a potential barrier in the middle and asymmetric conductive layers on both sides. When voltage is applied to both ends of the FTJ, the height of the potential barrier inside the FTJ as a whole will change, thereby changing the tunnel resistance. It has a variety of structures. The most common one is the MFIS structure, which is composed of four materials stacked in sequence: silicon, insulating layer, ferroelectric layer, and metal. There are also MFS, MFM, and MFIM structures. However, even if the applied voltage is removed, the above-mentioned conduction characteristics will not change, so that the tunnel resistance of the FTJ remains unchanged until the applied voltage changes to set its tunnel resistance again. Therefore, ferroelectric tunnel junctions are often used as linear resistors as memory.

[0039] Memories made of ferroelectric tunnel junctions have the advantages of non-volatility, non-destructive readout, fast read and write speeds, and low power consumption. Compared with traditional ferroelectric memories, they also have the advantages of simple structure, small size, easy integration, and long service life, which can further broaden the application scope of ferroelectric memories.

[0040] Figure 3A Shown is a schematic diagram of an electronic synapse circuit and a portion of a postsynaptic neuron circuit according to an embodiment of the present application. Figure 3B Shown Figure 3A The working timing diagram of the circuit shown.

[0041] like Figure 3A As shown, the electronic synapse circuit 200 is coupled to its postsynaptic neuron circuit 300, and the electronic synapse circuit 200 is also coupled to a presynaptic neuron circuit (not shown). According to one embodiment, the presynaptic neuron circuit may have a circuit structure similar to that of the postsynaptic neuron circuit.

[0042] According to one embodiment, each neuron circuit can transmit at least four signals when transmitting a signal, including STDP WL1, STDP WL2, and LIF WL. These three signals can be provided to the rear neuron circuit as a control signal and an input signal through the rear synapse; and STDP BL, this signal can be provided to the front synapse as a control signal, and the front synapse is connected between the neuron circuit and the front neuron circuit. The so-called "front" or "back" here refers to the signal transmission path of the user input, and the one that is relatively closer to the most initial neuron circuit becomes "front", and the one that is relatively farther away from the most initial neuron circuit becomes "back".

[0043] For a specific electronic synaptic circuit, LIF WL is the control signal provided by the presynaptic neuron circuit, which determines the connection state between the electronic synaptic circuit and the postsynaptic neuron circuit. STDP WL1 and STDP WL2 are the input signals provided by the presynaptic neuron circuit, which determine the updated value of the weight of the electronic synaptic circuit. The feedback signal STDP BL is provided by the postsynaptic neuron circuit, which determines the timing of modifying the current weight of the electronic synaptic circuit to the updated value.

[0044] According to one embodiment, Figure 3A As shown, the electronic synapse circuit 200 may include at least a switch unit 201 , an input unit 202 and a weight calculation unit 203 .

[0045] According to one embodiment, the switch unit 201 may include at least, for example, an NMOS transistor M21, whose gate may be configured to receive a control signal LIF WL from a presynaptic neuron circuit. Figure 3B As shown, LIF WL includes a plurality of short high-level pulses. When LIF WL is at a high level, the electronic synapse circuit 200 is started to operate, and the electrical connection with the post-synaptic neuron circuit 300 is turned on.

[0046] According to one embodiment, the input unit 202 may include at least, for example, NMOS transistors M22 and M23 , and a PMOS transistor M24 .

[0047] According to one embodiment, the drain of M22 may be configured to receive an input signal STDP WL1 from a presynaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive a feedback signal STDP BL from a postsynaptic neuron circuit.

[0048] According to one embodiment, the drain of M23 can be configured to receive an input signal STDP WL2 from a presynaptic neuron circuit, the source can be coupled to the weight calculation unit 203, and the gate can be configured to receive a feedback signal STDP BL from a postsynaptic neuron circuit. The input signals STDP WL1 and STDP WL2 can come from the output of the same presynaptic neuron circuit. Figure 3B As shown, STDP WL1 and STDP WL2 may be pulse signals with the same period but different waveforms.

[0049] According to one embodiment, the source of M24 may be coupled to the source of M23 and the weight calculation unit 203 , the gate may be configured to receive a feedback signal STDP BL from the post-synaptic neuron circuit, and the drain may be grounded.

[0050] According to one embodiment, the weight calculation unit 203 may include at least a ferroelectric tunnel junction FTJ. According to one embodiment, a first end of the FTJ is coupled to the sources of M21 and M22, and the other end of the FTJ is coupled to the source of M24.

[0051] like Figure 3A As shown, a neuron circuit, such as a post-synaptic neuron circuit 300, may include at least a comparator 301, a resistor 302, and a capacitor 303. The negative input terminal of the comparator 301 may be coupled to the electronic synapse circuit 200 (e.g., may be coupled to the drain of the transistor M21), and is also coupled to a power supply through the resistor 302. The positive input terminal of the comparator 301 is configured to receive a preset threshold voltage Vth. Once the negative input terminal voltage Vout of the comparator 301 is lower than the positive input terminal voltage Vth, the neuron will output an output signal Y (including LIF WL', STDP WL1', STDP WL2', and STDP BL).

[0052] According to one embodiment, the neuron circuit may further include a delay unit 304 configured to ensure that there is a certain time difference between the high level pulse of the STDP BL and the high level pulse of the LIF WL output by the presynaptic neuron circuit.

[0053] According to one embodiment of the present application, there are no restrictions on the structure of the FTJ and the corresponding parameters such as the ferroelectric layer material, ferroelectric layer thickness, insulating layer material, insulating layer thickness, metal material, and Si doping type and doping concentration, and they can be adjusted according to actual needs.

[0054] According to an embodiment of the present application, device parameters such as gate length, doping concentration and gate insulation layer thickness of M21, M22, M23 and M24 are not restricted and can be adjusted according to actual needs.

[0055] According to one embodiment, Figure 3B As shown, when Vout is higher than Vth, the postsynaptic neuron circuit does not output signal Y, so STDP BL is also at a low level. In this case, transistors M22 and M23 in the input unit 202 are disconnected, and transistor M24 is turned on. The resistance of FTJ is set when a voltage was applied to both ends last time, so at this time, although the voltage applied to both ends is removed, the tunneling resistance of FTJ remains unchanged.

[0056] When LIF WL reaches a high level, the charge in capacitor 303 is discharged through the path where FTJ is located in the electronic synaptic circuit. If Vout drops below Vth after one discharge, the post-synaptic neuron circuit 300 transmits signal Y, and STDL BL jumps to a high level.

[0057] According to one embodiment, a neuron circuit may have multiple preceding electronic synapse circuits coupled to it. When any of these electronic synapse circuits is able to reduce Vout to a level below Vth, the neuron circuit will emit a signal Y, and all preceding electronic synapse circuits coupled to it will receive a high level of STDP BL.

[0058] However, if Vout cannot be reduced to a level lower than Vth after one discharge, and other preceding electronic synapse circuits have not achieved this goal, the power supply will continue to charge capacitor 303 after the LIF WL high level, and will discharge the charge in capacitor 303 again when the next LIF WL high level comes. After several discharges or integrations, the goal of reducing Vout to a level lower than Vth may be achieved.

[0059] When STDP BL is at a high level, M24 is turned off, M22 and M23 are turned on, and STDP WL1 and STDP WL2 are provided to both ends of FTJ, respectively, thereby changing the tunnel resistance value of FTJ and updating the weight of the electronic synapse circuit. Of course, as described above, the arrival of STDP BL at a high level may be caused by the electronic synapse circuit itself, or may be caused by other electronic synapse circuits coupled to the neuron circuit 300.

[0060] However, no matter which electronic synaptic circuit triggers it, the neuron circuit 300 will emit the STDP BL, so that the weights of all the previous electronic synaptic circuits coupled to it will change. Since different presynaptic neurons provide input signals at different times, when the neuron circuit 300 emits the STDP BL to each previous electronic synapse, the weights written may be different, or the tunneling resistance of the ferroelectric tunneling junction FTJ may be set to different values.

[0061] When the input signal LIF WL is at a high level again, the electronic synapse circuit 200 with updated weights will discharge the charge in the capacitor 303 with the updated tunneling resistance.

[0062] To achieve Figure 2 The electronic synapse properties shown, according to one embodiment, are for Figure 3A The circuit shown, Figure 3B As shown, the input signals STDP WL1 and STDP WL2 have different waveforms but the same period.

[0063] According to one embodiment, LIF WL can transition to active level at the same time or after STDP WL1 transitions from active level to inactive level and at the same time or before STDP WL2 transitions to active level. When STDP WL2 transitions from active level to inactive level, STDP WL1 transitions to active level.

[0064] According to one embodiment, the falling edge of STDP WL2 substantially coincides with the rising edge of STDP WL1. According to one embodiment, there is a certain time interval between the rising edge of STDP WL2 and the falling edge of STDP WL1. According to one embodiment of the present application, the moment when the next high level of LIF WL arrives is in the time interval between the falling edge of STDP WL1 and the rising edge of STDP WL2.

[0065] According to one embodiment, the amplitude of the STDP WL2 high level pulse gradually increases over time. According to one embodiment, the amplitude of the STDP WL1 high level pulse gradually decreases over time. According to one embodiment, the maximum or minimum values ​​of the amplitudes of the STDP WL1 and STDP WL2 high level pulses may be the same or different depending on the material properties of the ferroelectric layer.

[0066] According to one embodiment, in order to satisfy the turn-on rule of M22 and M23 , the amplitude of the high level pulse of STDP BL should be greater than the maximum amplitude of the high level pulses of STDP WL1 and STDP WL2 .

[0067] Figure 4FIG. 4 is a curve showing the change of the normalized conductance of an electronic synaptic circuit over time according to an embodiment of the present application. Figure 4 As shown, the Δt on the horizontal axis is the time difference between the moment when the postsynaptic neuron transmits a signal and the preset moment when the postsynaptic neuron transmits a signal, and the ΔW on the vertical axis represents the conductivity of M22 in the electronic synaptic circuit. To make the curve more intuitive, the conductivity change curve is normalized with respect to Δt.

[0068] According to one embodiment, the time when the postsynaptic neuron transmits a signal is preset in Δt as the time from the high level pulse of STDP BL to the coincidence position of the falling edge of STDP WL2 and the rising edge of STDP WL1 (Δt can also be calculated relative to other moments, but the resulting change curve is different from Figure 4 There will be a difference, it cannot be achieved Figure 2 The mechanism of the characteristic curve shown in the figure). If the high level of STDPBL arrives after the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is positive. In this stage, STDP WL1 is positive and gradually decreases, STDP WL2 is 0, and the conductivity of FTJ and the corresponding weight change rate of the electronic synapse will decrease as Δt increases (the weight change rate of the electronic synapse is positively correlated with the conductivity of FTJ). If the high level of STDP BL arrives before the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is negative. In this stage, STDP WL1 is 0, STDP WL2 is positive and gradually increases, and the conductivity of M22 and the corresponding weight change rate of the electronic synapse will decrease as Δt increases. The magnitude of the change in the conductivity of FTJ is affected by the maximum amplitude of the high level of STDP WL2.

[0069] Of course, different input and control signals can also be used according to different STDP mechanism curves of electronic synapses.

[0070] The scheme of this application utilizes the memory and non-volatile properties of the ferroelectric tunneling junction FTJ and applies it to electronic synapses. By adjusting the voltage value applied to both ends of the FTJ to set the tunneling resistance of the FTJ, the specific weight of the synapse can be set, which can simplify the circuit design to a certain extent while realizing the functions of multiple components. At the same time, due to its advantages of high density, low power consumption and high operating speed, it can further reduce the power consumption of circuits and equipment and improve operating efficiency. By using it in the network design of neuromorphic computing, low-power, high-computing-performance neuromorphic computing can be realized.

[0071] During the calculation and optimization process, the circuit does not need to store the calculated weights and intermediate values ​​of other input signals, nor does it need to call the intermediate values ​​again before the next calculation, which reduces the number of times the circuit is used, improves the calculation speed, and reduces circuit power consumption.

[0072] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A neural network circuit, comprising: a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive a first input signal, a second input signal, and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; Wherein, the electronic synapse circuit at least comprises: a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive a first input signal and a second input signal from the pre-synaptic neuron circuit under the control of a feedback signal from the post-synaptic neuron circuit; A weight calculation unit is coupled between the switch unit and the ground and coupled to the input unit, wherein the weight calculation unit at least includes a ferroelectric tunnel junction, and the ferroelectric tunnel junction is configured to receive the first input signal and the second input signal from the input unit to update the tunnel resistance of the ferroelectric tunnel junction.

2. The neural network circuit of claim 1, wherein The postsynaptic neuron circuit comprises at least: A comparator, whose negative input terminal is coupled to the switch unit of the electronic synapse circuit, whose positive input terminal is configured to receive a preset constant signal, and whose output terminal is coupled to the input unit of the electronic synapse circuit; a resistor coupled between the negative input terminal of the comparator and a power supply; a capacitor coupled between the negative input terminal of the comparator and ground; When the switch unit connects the postsynaptic neuron circuit to the electronic synapse circuit and the ferroelectric tunnel junction is turned on, the voltage at the negative input terminal of the comparator drops. When the voltage drops below the preset constant signal, the comparator is configured to output the feedback signal.

3. A neural network circuit as described in claim 2, wherein the switching unit includes at least a first transistor, whose control electrode is configured to receive the control signal, whose first electrode is coupled to the negative input terminal of the comparator, and whose second electrode is coupled to the first end of the ferroelectric tunneling junction.

4. The neural network circuit according to claim 3, wherein the input unit comprises at least: a second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the first end of the ferroelectric tunneling junction; a third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction; The fourth transistor is of a complementary type to the third transistor, has a control electrode configured to receive the feedback signal, a first electrode grounded, and a second electrode coupled to the second end of the ferroelectric tunnel junction.

5. A neural network circuit as claimed in any one of claims 2 to 4, wherein: The post-synaptic neuron circuit further includes a delay unit coupled between an output terminal of the comparator and an input terminal of the input unit and configured to generate a time interval between effective levels of the control signal and the feedback signal.

6. The neural network circuit according to any one of claims 1 to 4, wherein the first end of the ferroelectric tunneling junction is configured to receive the first input signal, and the second end of the ferroelectric tunneling junction is configured to receive the second input signal; The control signal jumps to a valid level after the first input signal jumps to an invalid level and before the second input signal jumps to a valid level, and the first input signal jumps to a valid level when the valid level of the second input signal jumps to an invalid level; The effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.

7. The neural network circuit as claimed in claim 6, wherein the effective level amplitude of the feedback signal is greater than the maximum amplitude of the effective level of the first input signal or the second input signal.

8. An electronic synaptic circuit configured to receive a first input signal, a second input signal, and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; in, The electronic synapse circuit comprises at least: a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive a first input signal and a second input signal from the pre-synaptic neuron circuit under the control of a feedback signal from the post-synaptic neuron circuit; A weight calculation unit is coupled between the switch unit and the ground and coupled to the input unit, wherein the weight calculation unit at least includes a ferroelectric tunnel junction, and the ferroelectric tunnel junction is configured to receive the first input signal and the second input signal from the input unit to update the tunnel resistance of the ferroelectric tunnel junction.

9. The electronic synapse circuit of claim 8, wherein the switch unit comprises at least a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the post-synaptic neuron circuit, and a second electrode of which is coupled to the first end of the ferroelectric tunneling junction.

10. The electronic synapse circuit of claim 9, wherein the input unit comprises at least, a second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the first end of the ferroelectric tunneling junction; a third transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second end of the ferroelectric tunnel junction; The fourth transistor is of a complementary type to the third transistor, has a control electrode configured to receive the feedback signal, a first electrode grounded, and a second electrode coupled to the second end of the ferroelectric tunnel junction.

11. The electronic synapse circuit according to any one of claims 8 to 10, wherein the first end of the ferroelectric tunneling junction is configured to receive the first input signal, and the second end of the ferroelectric tunneling junction is configured to receive the second input signal; The control signal jumps to a valid level after the first input signal jumps to an invalid level and before the second input signal jumps to a valid level, and the first input signal jumps to a valid level when the valid level of the second input signal jumps to an invalid level; The effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.

12. The electronic synapse circuit of claim 11, wherein the effective level amplitude of the feedback signal is greater than the maximum amplitude of the effective level of the first input signal or the second input signal.

13. An electronic system comprising a neural network circuit as described in any one of claims 1-7.

14. An electronic device comprising a neural network circuit as described in any one of claims 1-7.

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