Automatic labeling and segmentation using machine learning models

Abstract

The present invention relates to automatic labeling and segmentation using machine learning models. In various examples, training methods for generating trained neural networks that are robust to various environmental features are described. In one embodiment, training includes modifying images of a dataset, and generating bounding boxes and / or other segmentation information for the modified images used to train the neural network.

Description

BACKGROUND

[0001] Conventional approaches to automatic labeling and segmentation tools rely on existing data sets, which can not generate robust tools for various applications due to lack of data from different domains. For example, existing training data sets can not include specific environments, object orientations, or other characteristics of the deployment environment for a particular automatic labeling or segmentation tool. Furthermore, obtaining annotations and masks for training data sets is both time consuming and error prone. Moreover, convolutional neural networks (CNNs) for object detection and other tasks typically work best when partitioned into rectangular boxes whose edges are parallel to the boundaries of the images provided to the CNN, which can create a domain gap in various practical applications. Existing automatic labeling and segmentation tools are limited by existing training data sets, which are costly and difficult to generate. Furthermore, these tools require human supervision during training. BRIEF DESCRIPTION OF DRAWINGS

[0002] The present systems and methods for a rotationally robust automatic labeling tool for segmentation are described in detail below with reference to the attached drawing figures, wherein:

[0003] Figure 1 is an illustration of a first training phase for generating a pre-labeling tool to perform image segmentation during a second training phase in accordance with some embodiments of the present disclosure;

[0004] Figure 2 is an illustration of a second training phase for generating a trained neural network to perform image segmentation in accordance with some embodiments of the present disclosure;

[0005] Figure 3 is an illustration of image segmentation generated by a neural network in accordance with some embodiments of the present disclosure;

[0006] Figure 4 is an illustration of image segmentation generated by a neural network in accordance with some embodiments of the present disclosure;

[0007] Figure 5 is an illustration of a two-phase training process for generating a trained neural network to perform image segmentation in accordance with some embodiments of the present disclosure;

[0008] Figure 6 is an illustration of image segmentation generated by a pre-labeling tool and a trained neural network in accordance with some embodiments of the present disclosure;

[0009] Figure 7 is a flowchart illustrating a first training phase for generating a pre-labeling tool to perform image segmentation during a second training phase in accordance with some embodiments of the present disclosure;

[0010] Figure 8This is a flowchart illustrating a second training phase for generating a trained neural network to perform image segmentation according to some embodiments of the present disclosure;

[0011] Figure 9 This is a flowchart illustrating a set of transformations applied to an image of a dataset according to some embodiments of the present disclosure;

[0012] Figure 10A The inference and / or training logic according to at least one embodiment is illustrated;

[0013] Figure 10B The inference and / or training logic according to at least one embodiment is illustrated;

[0014] Figure 11 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0015] Figure 12 An example data center system according to at least one embodiment is shown;

[0016] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0017] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and field of view for autonomous vehicles;

[0018] Figure 13C This is an illustration based on at least one embodiment. Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0019] Figure 13D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 13A A diagram of a system for communication between autonomous vehicles;

[0020] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 15 This is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 16 A computer system according to at least one embodiment is shown;

[0023] Figure 17 A computer system according to at least one embodiment is shown;

[0024] Figure 18A A computer system according to at least one embodiment is shown;

[0025] Figure 18B A computer system according to at least one embodiment is shown;

[0026] Figure 18C A computer system according to at least one embodiment is shown;

[0027] Figure 18D A computer system according to at least one embodiment is shown;

[0028] Figure 18E and Figure 18F A shared programming model according to at least one embodiment is shown;

[0029] Figure 19 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0030] Figure 20A and Figure 20B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0031] Figure 21A and Figure 21B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0032] Figure 22 A computer system according to at least one embodiment is shown;

[0033] Figure 23A A parallel processor according to at least one embodiment is shown;

[0034] Figure 23B A partitioning unit according to at least one embodiment is shown;

[0035] Figure 23C A processing cluster according to at least one embodiment is shown;

[0036] Figure 23D A graphics multiprocessor according to at least one embodiment is shown;

[0037] Figure 24 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0038] Figure 25 A graphics processor according to at least one embodiment is shown;

[0039] Figure 26 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0040] Figure 27A deep learning application processor according to at least one embodiment is shown;

[0041] Figure 28 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0042] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0043] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0044] Figure 31 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 32 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0046] Figure 33 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0047] Figure 34A and Figure 34B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0048] Figure 35 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0049] Figure 36 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0050] Figure 37 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0051] Figure 38 A streaming multiprocessor according to at least one embodiment is illustrated;

[0052] Figure 39 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0053] Figure 40 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0054] Figure 41Example illustrations include an advanced computing pipeline 4010A for processing imaging data according to at least one embodiment;

[0055] Figure 42A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0056] Figure 42B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0057] Figure 43A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0058] Figure 43B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0059] Embodiments of this disclosure relate to rotationally robust automatic labeling tools for segmentation. Systems and methods are disclosed that provide a self-training method to obtain a segmentation mask (e.g., for a pedestrian detection task) from bounding boxes generated by a first model. A second model can then use the obtained segmentation mask to generate tighter (more compact) bounding boxes in the rotated image, which can be used as additional enhancements to generate ground-realistic bounding boxes (e.g., non-axis-aligned bounding boxes) for objects in the image, and / or to generate segmentation labels for objects. Rotation is one example of modification that, in various embodiments, can be applied to a training dataset (e.g., a curated and annotated set of images) to increase the robustness of the trained model and reduce domain gaps. Domain gaps describe the difference between the environment captured in the training dataset and the environment in which the trained model is deployed (e.g., trained using the training dataset). Other examples of modifications to the training dataset used in this disclosure include modifications to brightness, contrast, scale, rotation, orientation, or other modifications to the training dataset to simulate the environment in which the trained model generates inference.

[0060] Compared to traditional systems (as described above), the systems and methods described in this disclosure do not require human interaction (e.g., self-training methods) and can be used with existing training datasets. In other words, the systems and methods described in this disclosure eliminate the costs and errors associated with requiring human intervention and can be implemented using existing training datasets, thereby eliminating the need and cost of generating training datasets. For example, models trained using the systems and methods described in this disclosure (e.g., convolutional neural networks) are robust to rotation, occlusion, truncation, or other forms of obstacles to objects in images or videos.

[0061] In one embodiment, a two-stage self-trained automatic labeling tool is used to obtain segmentation and / or annotation based at least in part on bounding boxes of a set of images. In this embodiment, during the first stage, a model is trained using a training dataset to generate preliminary mask annotations for either the training dataset or another training dataset. In one example, a mask region-based convolutional neural network (Mask R-CNN) is trained using a first dataset (e.g., common objects in a background dataset), and then the Mask R-CNN is used to generate preliminary mask annotations for a second training dataset. Furthermore, in this example, since the training dataset includes bounding boxes of objects in the images, Mask R-CNN is performed without a region proposal network. In various embodiments, the preliminary mask annotations and the second training dataset are subsequently used to train a new model or retrain the aforementioned Mask R-CNN model, thereby producing the pre-labeled tool used in the second stage.

[0062] During the second phase, in one embodiment, a new model (e.g., a new masked R-CNN model) is trained using a second training dataset, which includes bounding boxes and segmentations generated by a pre-labeling tool produced in the first phase. Furthermore, in various embodiments, the second training dataset is modified. In one example, images from the training dataset are rotated (e.g., 5 degrees clockwise), and then coarse bounding boxes are generated around objects in the training dataset images using the pre-labeling tool, while finer bounding boxes are generated around the objects in the images using the new model (e.g., the model trained in the second phase). In this way, additional training data can be generated to expand the training dataset and reduce any domain gaps.

[0063] refer to Figure 1 , Figure 1 This is an example training method according to some embodiments of the present disclosure for training a pre-labeling tool 108 for training a neural network for segmentation rotation robustness. It should be understood that such and other arrangements described herein are merely illustrative examples. Other arrangements and elements (e.g., machines, interfaces, functions, commands, function groups, etc.) may be used to supplement or replace the arrangements and elements shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that can be implemented as discrete or distributed components, or in combination with other components, and can be implemented in any suitable combination and location. The various functions performed by the entities described herein can be performed by hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory.

[0064] Now for reference Figure 1 , 2In sections 100, 200, and 500, each block of methods 100, 200, and 500 described herein includes a computational process that may be performed using any combination of hardware, firmware, and / or software. The various functions and / or operations described in this disclosure can be performed by a processor executing instructions stored in memory. In one example, dataset 102 includes a collection of annotated images stored in a storage device such as a hard disk drive (HDD). In another example, inference neural network 104 includes source code stored in the memory of a computer system, which, when executed by the processor of the computer system, causes the computer system to perform inference operations, as described in more detail below. The methods can also be implemented as computer-usable instructions stored on a computer storage medium. These methods can be provided by standalone applications, services, or managed services (standalone or in combination with another managed service) or plug-ins to another product, to name a few. Furthermore, as an example, for... Figure 12 Methods 100, 200, and 500 are described in the computer systems described herein. However, these methods may be performed additionally or alternatively by any system or any combination of systems, including but not limited to the systems described herein.

[0065] Back Figure 1 , Figure 1 This is a flowchart illustrating a method 100 for generating a pre-labeled tool 108 according to some embodiments of the present disclosure. Method 100 includes a dataset 102, which in various embodiments includes images 110 and bounding boxes 112 depicting various objects and / or object categories (e.g., people, cars, clothing, animals, etc.). In one embodiment, the bounding box 112 includes metadata or other information associated with the images 110 of the dataset 102 that defines a rectangle or other geometry that surrounds (e.g., creates a boundary around) a specific object included in the images of the dataset 102. For example, the bounding box 112 includes a minimum (e.g., minimum area) or perimeter bounding box around an object in the image, wherein all pixels depicting the object lie within the boundary created by the bounding box. In various embodiments, the dimension of the bounding box 112 is N, where N is the total number of dimensions depicted in the images 110 of the dataset 102. For example, the dataset 102 may include a 3D image 110, an image 110 including video, a 2D image 110, or other images suitable for training a neural network or performing inference using a neural network.

[0066] In various embodiments, dataset 102 includes a curated dataset that incorporates segmentation and annotation information (e.g., bounding boxes 112) at least in part based on human-generated segmentation and annotation information. In one example, dataset 102 includes a common object (COCO) dataset in context. In other embodiments, the segmentation and annotation information (e.g., bounding boxes 112) is generated by a model such as a neural network.

[0067] Back Figure 1 Images 110 from dataset 102 are fed to inference neural network 104 to generate preliminary mask annotations 114. In one embodiment, inference neural network 104 is a trained network for detecting objects and / or object categories depicted in image 110. In various embodiments, inference neural network 104 includes any neural network trained to perform image segmentation and annotation. In one example, inference neural network 104 is trained using dataset 102. In another example, inference neural network 104 is trained using a dataset separate from dataset 102.

[0068] In various embodiments, the inference neural network 104 includes a mask-based convolutional neural network (R-CNN) or other convolutional neural network adapted to generate coarse segmentation information for objects in image 110 for training the training neural network 106. In various embodiments, the image 110 provided to the inference neural network 104 does not include segmentation and / or annotation information (e.g., bounding boxes 112). In one embodiment, preliminary mask annotation 114 includes bounding boxes and / or masks for objects and / or a class of objects (e.g., people) depicted in image 110. Figure 3 The preliminary mask is described in more detail below (note 114).

[0069] In various embodiments, the training neural network 106 includes any neural network capable of being trained using segmentation and annotation information. In one example, the training neural network 106 is a masked R-CNN without a region proposal network module. Furthermore, as... Figure 1 As shown in the illustrated embodiments, a training neural network 106 is trained using dataset 102 (including bounding boxes 112) and preliminary mask annotations 114 generated at least partially by an inference neural network 104. In various embodiments, a pre-labeling tool 108 is generated as a result of training the neural network 106 as described above. In one embodiment, the pre-labeling tool 108 is a trained neural network that generates fine-grained segmentations (e.g., masks) and annotations for images of a dataset (e.g., dataset 102) when inference is performed on an input (e.g., an image). In various embodiments, the pre-labeling tool 108 includes software, hardware, or a combination thereof that utilizes a neural network or other model to perform various operations, such as performing inference to generate masks, generate bounding boxes, or other operations described in this disclosure. As described in more detail below, the pre-labeling tool 108 can be used to generate segmentations and annotations for a modified dataset. In one example, images 110 of dataset 102 are rotated or otherwise modified to generate an environment-robust training model.

[0070] Figure 2This is a flowchart illustrating a method 200 for generating a trained neural network 208 according to some embodiments of the present disclosure, the trained neural network 208 being robust to rotation, occlusion, truncation, or other forms of obstruction or blurring of objects in an image or video. In various embodiments, the method 200 for training the trained neural network 208 includes a dataset 202. For example, dataset 202 includes the above-described... Figure 1 The dataset 202 describes a set of images depicting the object (e.g., a curated set of images including bounding boxes and annotations). Furthermore, in various embodiments, the dataset 202 includes modifications and / or alterations to the set of images included in the dataset 202. In such embodiments, the modifications and / or alterations to the set of images augment the dataset 202 by generating at least modified images 210 to reduce the domain gap between the set of images in the dataset 202 and the target domain of the trained neural network 208, enabling the trained neural network 208 to produce better results during inference.

[0071] In one embodiment, dataset 202 is augmented by rotating at least one set of images around the optical axis to generate modified image 210. For example, the set of images is rotated 5 degrees clockwise to generate modified image 210. Furthermore, in various embodiments, modified image 210 is used during the training of neural network 206, which is described in more detail below. In another example, the brightness values ​​associated with image 210 are modified to generate modified image 210.

[0072] Furthermore, in various embodiments, multiple modifications and / or alterations are performed on the set of images to generate a modified image 210 to augment the dataset 202. In one example, the set of images is rotated 5 degrees clockwise and 10 degrees clockwise to generate the modified image 210 (e.g., the modified image 210 comprises images of the set of images rotated 5 and 10 degrees). In one embodiment, multiple types of modifications or alterations are applied to the set of images to generate the modified image 210. For example, the set of images is rotated, and the scale associated with the set of images is modified. These modifications and / or alterations can be performed individually or in combination. Furthermore, the modifications and / or alterations can be applied to the set of images sequentially or in parallel.

[0073] As described above, modifications and / or alterations to a set of images may include a variety of different operations, such as rotation, flipping, cropping, modifying exposure, modifying white balance, modifying color, modifying saturation, sharpening images, applying filters, modifying scale, or otherwise modifying, adjusting, or otherwise altering a set of images to represent the environment in which the trained neural network 208 performs inference.

[0074] Back Figure 2In various embodiments, the modified image 210 is provided to a pre-labeling tool 208, which generates more refined mask annotations 214 for the objects depicted in the modified image 210. In one embodiment, the pre-labeling tool 208 uses the combination of the above... Figure 1 The described method 100 trains a neural network or other model. For example, the pre-labeling tool 208 is a masked R-CNN trained using a dataset (e.g., dataset 102) that includes bounding boxes and annotations. In one embodiment, it is combined with the following... Figure 4 In more detail, the pre-labeling tool 208 generates finer mask annotations 214 for specific categories of objects and / or categories in the modified image 214. In various embodiments, the finer mask annotations 214 include additional data and / or metadata identifying pixels in the modified image 210 that depict specific objects and / or object categories. In one example, the modified image 210 includes a set of images depicting people (e.g., pedestrians) in the background, rotated around an optical axis by a set of values. The pre-labeling tool 208 then generates finer mask annotations 214 that identify pixels in a set of images that include people and markers that identify pixels as associated with people. As described above, in some examples, the rotation of the images around the optical axis results in inaccurate and / or incorrect bounding boxes and other segmentation information associated with dataset 202. In such examples, the pre-labeling tool 208 generates finer mask annotations 214 that provide accurate segmentation information for training the neural network 206.

[0075] In various embodiments, the training neural network 206 includes any neural network capable of being trained using segmentation and annotation information (e.g., more refined mask annotations 214). In one example, the training neural network 206 is a mask R-CNN trained using a dataset 202 that includes modified images 210 and more refined mask annotations 214. Furthermore, as... Figure 2 As illustrated in the depicted embodiments, a trained neural network 208 is obtained when the neural network 206 is trained using dataset 202 (which includes bounding boxes, a modified image 210, and more refined mask annotations 214). In various embodiments, the trained neural network 208 is a trained model that is robust to its environment and capable of recognizing objects or object categories depicted in an image. For example, as a result of rotating images from the dataset to generate the modified image 210, the trained neural network 208 is able to detect objects in the image regardless of the image's optical angle (e.g., camera angle). In another example, the trained neural network 208 is able to detect objects in a low-light image due to the reduction of brightness values ​​associated with images in the dataset.

[0076] Figure 3This is an illustration of an image 300 including a preliminary mask annotation 302 according to at least one embodiment described in this disclosure. In various embodiments, the preliminary mask annotation 302 is generated by a trained model, for example, in conjunction with the above. Figure 1 The inference neural network 104 is described.

[0077] like Figure 3 As shown, image 300 includes preliminary mask annotations 302 for a person depicted in image 300. Although image 300 and preliminary mask annotations 302 include a person, an inference neural network can be trained to generate preliminary mask annotations 302 for any object or object category. Furthermore, in various embodiments, preliminary mask annotations 302 include various types of segmentation information, such as bounding boxes, masks, markers, annotations, or other information suitable for identifying objects in the image. Additionally, although... Figure 3 Image 300 is depicted, but preliminary mask annotation 302 may be generated for three-dimensional representation, four-dimensional representation, video, or other media capable of depicting objects.

[0078] In some examples, the preliminary mask annotation 302 is included within the image 300 as supplementary data. In other examples, the preliminary mask annotation 302 is supplementary data provided along with the image (e.g., as annotations provided to the neural network). Furthermore, as described above, the preliminary mask annotation 302 may include coarse annotations generated by a neural network trained using a selected dataset. In various embodiments, the preliminary mask annotation 302 is used to train the neural network, such as the pre-labeling tool 208 described above.

[0079] Figure 4 This is an illustration of an image 400 including a more refined mask annotation 402, according to at least one embodiment described in this disclosure. The more refined mask annotation 402 is generated by a trained model, such as those described above. Figure 1 The pre-labeling tool 108 is described. (For example...) Figure 3 As shown, image 400 includes more refined mask annotations 402 for the people depicted in image 400. In various embodiments, the more refined mask annotations 402 are generated by a pre-labeling tool for images in a dataset used to train the pre-labeling tool. Furthermore, as described above... Figure 2 The description suggests that images in the dataset may be modified, and more refined mask annotations 402 may be generated, at least in part, based on the modified images. Although image 400 and the more refined mask annotations 402 include people, the inference neural network can be trained to generate more refined mask annotations 402 for any object or object category. Furthermore, in various embodiments, the more refined mask annotations 402 include various types of segmentation information, such as bounding boxes, masks, labels, annotations, or other information suitable for recognizing objects in the image. Additionally, although... Figure 4Image 400 is depicted, but more detailed mask annotations 402 may be generated for 3D images, 4D images, videos, or other media capable of depicting objects.

[0080] In some examples, finer mask annotations 402 are included within image 400 as additional data. In other examples, finer mask annotations 402 are additional data provided along with the image (e.g., as annotations to the image provided to the neural network). In various embodiments, finer mask annotations 402 are used to train neural networks, such as the trained neural network 208 described above.

[0081] Figure 5 This is a flowchart illustrating a method 500 for generating a trained neural network robust to rotation, occlusion, truncation, other forms of obstacles, or other environmental factors in an image or video, according to some embodiments of the present disclosure. In various embodiments, the method 500 for training the neural network includes two training phases: a first training phase 502 and a second training phase 504. Furthermore, in one example, the first training phase 502 includes method 100 as described above, and the second training phase includes method 200 as described above. During the first training phase 502, in block 506, the system performing method 500 performs inference on a dataset using a neural network. As described above, the neural network may include a mask R-CNN trained at least in part on a selected dataset (which may differ from the dataset used to perform the inference). Furthermore, in various embodiments, in block 508, pseudo-mask segmentation is generated as a result of performing inference on the dataset using the neural network. For example, the pseudo-mask segmentation generated by the neural network may include preliminary mask annotations as described above.

[0082] In various embodiments, in the second training phase 504 of box 510, the second neural network is trained at least in part based on pseudomask segmentation and the dataset. As described above, in various embodiments, the dataset is augmented or otherwise expanded by modifying it (e.g., images or videos included in the dataset). For example, images in the dataset are modified, and segmentation data (e.g., masks) is generated for the modified dataset, which is then used to train the neural network. In box 508, the trained neural network is used to generate more refined pseudomask segmentation. In one embodiment, more refined pseudomask segmentation includes the above-described combination of... Figure 4 More refined mask annotations are described. Furthermore, in various embodiments, more refined pseudo-mask segmentation is used to train additional models robust to various environmental factors captured by modifying the dataset by at least the above description.

[0083] Figure 6This is an illustration of a modified image 600 including coarse and fine annotations, according to at least one embodiment described in this disclosure. In the various embodiments described above, images, videos, or other information included in a dataset are modified and used to train an environment-robust model. Figure 6 As shown, the modified image 600 includes an image rotated about an axis. Although Figure 6 The image shown is a rotated modified image, but any number of additional and / or alternative modifications can be applied to the image to generate a modified image as described in more detail above.

[0084] In the various embodiments described above, the first trained neural network generates coarse bounding boxes 602 for objects in the modified image. In one example, the coarse bounding box 602 includes preliminary mask annotations as described above. In another example, the coarse bounding box is generated as a result of not training the neural network in the manner described above to generate a rotation-robust neural network. In such an example, as... Figure 6 As shown, the coarse bounding box 602 includes additional pixels that do not correspond to the person depicted in the modified image 600. In various embodiments, the fine bounding box 604 of the modified image 600 is generated by a pre-labeling tool as described above. Furthermore, in one embodiment, the fine bounding box 604 is used to train a rotation-robust neural network.

[0085] refer to Figure 7 , Figure 7 This is an example flowchart for generating a pre-tagged tool according to some embodiments of this disclosure. It should be understood that this and other arrangements described herein are merely illustrative. Other arrangements and elements (e.g., machines, interfaces, functions, commands, functional groups, etc.) may be used to supplement or replace the arrangements and elements shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that may be implemented as discrete or distributed components, or in combination with other components, and may be implemented in any suitable combination and location. The various functions performed by the entities described herein can be performed by hardware, firmware, and / or software. For example, various functions can be performed by a processor that executes instructions stored in memory.

[0086] Now for reference Figure 7 , 8In sections 700, 800, and 900, each block of methods 700, 800, and 900 described herein includes a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The method can also be implemented as computer-usable instructions stored on a computer storage medium. These methods can be provided by standalone applications, services, or managed services (standalone or in combination with other managed services) or plug-ins to other products, to name a few. Furthermore, methods 700, 800, and 900 are described by way of example relative to the training methods described above. However, these methods may be additionally or alternatively performed by any system or any combination of systems, including but not limited to the systems described herein.

[0087] Figure 7 This is a flowchart illustrating a method 700 for generating a pre-labeled tool according to some embodiments of the present disclosure. At block B702, method 700 includes obtaining a dataset including bounding box information. In various embodiments, the dataset includes images depicting various objects and / or object categories (e.g., people, cars, clothing, animals, etc.), and bounding boxes corresponding to these objects. For example, the dataset includes a Common Objects in Background (COCO) dataset, which includes bounding boxes. In one embodiment, the bounding boxes include metadata or other information defining a rectangle or other geometry associated with an image of the dataset that surrounds a specific object included in the dataset image. For example, the bounding box includes a minimum perimeter bounding box around an object in the image, wherein all pixels depicting the object are within the bounding box. In various embodiments, the bounding box information also includes segmentation information, annotations, or other information suitable for training a model to perform object detection, labeling, or similar tasks. In one embodiment, the bounding box information is generated by a trained model performing inference on images included in the dataset.

[0088] Back Figure 7In box B704, the system executing method 700 performs inference on the dataset to generate preliminary mask annotations. For example, a trained neural network performs inference to detect objects and / or a class of objects depicted in the images. In one embodiment, the neural network is trained on a second dataset different from the dataset described above. In various embodiments, the inference neural network includes any neural network trained to perform image segmentation and annotation. In one example, the inference neural network is trained using the dataset and bounding box information. For example, the inference neural network includes a mask region-based convolutional neural network (R-CNN) or other convolutional neural networks suitable for generating coarse segmentation information for objects in an image. In various embodiments, the images provided to the inference neural network do not include segmentation and / or annotation information (e.g., bounding box information). In one embodiment, the preliminary mask annotation includes bounding boxes and / or masks for objects and / or a class of objects (e.g., people) depicted in the images included in the dataset. In one embodiment, the preliminary mask annotation includes the above-mentioned combination Figure 3 A more detailed description of the initial mask annotations.

[0089] In various embodiments, the system performing method 700 at box B706 trains a model (e.g., a previously untrained neural network) at least in part based on a dataset and preliminary mask annotations. In various embodiments, the trained neural network includes any neural network capable of being trained using segmentation and annotation information. In one example, the trained neural network is a Mask R-CNN without a region proposal network module. Furthermore, at box B704, the neural network is trained using a dataset (including bounding boxes) and preliminary mask annotations at least in part generated by the inference neural network. In various embodiments, the system performing method 700 at box B708 ​​generates a pre-labeling tool as a result of training the neural network. In one embodiment, the pre-labeling tool is a trained neural network that generates fine-grained segmentation (e.g., masks) and annotations for images of a dataset (e.g., a dataset) when inference is performed on an input (e.g., an image). As described in this disclosure, in one embodiment, the pre-labeling tool is used to generate segmentation and annotations for a modified dataset (e.g., a rotated image of the dataset).

[0090] Figure 8This is a flowchart illustrating a method 800 for generating a trained neural network according to some embodiments of the present disclosure. In various embodiments, at block B802, method 800 includes obtaining a training dataset. For example, the training dataset includes a set of images depicting objects with or without additional information (e.g., segmentation information, bounding box information, labeling information, or other information as described above). Furthermore, in various embodiments, at block B804, method 800 includes modifying and / or altering a set of images included in the dataset. In one embodiment, the modification and / or alteration of the set of images augments the dataset by generating at least modified images to reduce the domain gap between the set of images in the dataset and the target domain of the trained neural network, thereby enabling the trained neural network to produce better results during inference. In one example, the images in the training dataset are rotated around an optical axis at different angles (e.g., 5 degrees, -5 degrees, 8 degrees, etc.). In another example, the images are enhanced by at least modifying the scale of the images. In yet another example, in block B804, the brightness values ​​associated with the images are modified.

[0091] In one embodiment, multiple types of modifications or alterations are applied to the set of images to generate modified images. For example, the images are rotated and the scale associated with the images is modified. These modifications and / or alterations can be made individually or in combination. Furthermore, the modifications and / or alterations can be applied to the images sequentially or in parallel.

[0092] As described above, modifications and / or alterations to a set of images may include a variety of different operations, such as rotation, flipping, cropping, modifying exposure, modifying white balance, modifying color, modifying saturation, sharpening images, applying filters, modifying scale, or otherwise modifying, adjusting, or otherwise altering a set of images to represent the environment in which the trained model (e.g., the model obtained as a result of executing method 800) performs inference.

[0093] Back Figure 8 In various embodiments, at box B806, method 800 includes performing inference on the modified dataset by at least providing the modified dataset to a pre-labeling tool. In various embodiments, the pre-labeling tool includes a trained model described in more detail above. For example, pre-labeling tool 208 is a mask R-CNN trained using a dataset (e.g., dataset 102) that includes bounding boxes and annotations. In one embodiment, the pre-labeling tool generates more refined mask annotations for objects depicted in the modified image. For example, as described above... Figure 4In more detail, the pre-labeling tool generates finer mask annotations for specific categories of objects and / or categories within a modified dataset. In various embodiments, the finer mask annotations include additional data and / or metadata identifying pixels (e.g., segmentation information) in the modified images depicting a specific object and / or object category. In one example, the modified images comprise a set of images depicting a person (e.g., a pedestrian) rotated around an optical axis by a set of values. The pre-labeling tool then generates finer mask annotations identifying pixels in the set of images, including people and labels identifying pixels associated with people. As described above, in some examples, the rotation of the images around the optical axis results in inaccurate and / or incorrect bounding boxes and other segmentation information associated with the dataset. In such examples, the pre-labeling tool generates finer mask annotations that provide accurate segmentation information for training neural networks as described in this disclosure.

[0094] In various embodiments, at box B808, method 800 includes training a neural network at least in part based on a modified dataset and more refined mask annotations. In various embodiments, the modified dataset includes a dataset designed to augment the dataset and reduce the domain gaps associated with the environment in which the trained neural network will perform inference as described above. In one embodiment, the neural network includes any neural network capable of being trained using segmentation and / or annotation information (e.g., more refined mask annotations). For example, the neural network is a mask R-CNN trained using a dataset and / or a modified dataset (including modified images and more refined mask annotations generated for the modified dataset). Furthermore, at box B810, method 800 trains the neural network to obtain a trained neural network. In various embodiments, the trained neural network is an environment-robust training model capable of recognizing objects or object categories depicted in an image. For example, as a result of rotating images of a dataset to generate a modified image, the trained neural network is capable of detecting objects in the image regardless of the image's optical angle (e.g., camera angle). In another example, a trained neural network was able to detect objects in low-light images by reducing the brightness values ​​associated with images in the dataset.

[0095] Figure 9 This is a flowchart illustrating a method 900 for modifying a dataset according to some embodiments of the present disclosure. In various embodiments, at block B902, method 900 includes obtaining an image and tags of objects depicted in the image. For example, the image is obtained from a dataset, as described above. Figure 1The dataset 102 is described. In various embodiments, labels are included in the dataset. In other embodiments, the labels are obtained from a neural network or other model. In various embodiments, at box B904, method 900 includes obtaining a segmentation of an image to distinguish the pixels of an object from other pixels in the image. For example, segmentation is performed using data trained on a selected dataset (e.g., as described above). Figure 1 The described pre-labeling tool 108) uses a masked R-CNN to obtain image segmentation. In other embodiments, segmentation is obtained manually or semi-manually. For example, a neural network or other model generates segmentation information for the image, and the user verifies and / or adjusts the output.

[0096] In various embodiments, at block B906, method 900 includes performing a set of transformations on an image to obtain a set of transformed images. For example, as described above, the image is rotated about an axis by different values ​​to generate a set of rotated images. Other examples of transformations include stretching, translating, scaling, color correction, cropping, trimming, otherwise modifying the image, or combinations of transformations performed in parallel or serially.

[0097] In various embodiments, at block B908, method 900 includes using the obtained segmentation to determine a set of bounding boxes of an object depicted in a set of transformed images. For example, a transformation applied to the images to obtain a set of transformed images is applied to the segmentation to determine the location of the object in the transformed images. In various embodiments, calculating the bounding boxes includes calculating boxes with angles having the following angles: (Xmin, Ymax), (Xmin, Ymin), (Xmax, Ymax), (Xmax, Ymin), where Xmin is the x-coordinate of the leftmost pixel of the segmentation, Xmax is the x-coordinate of the rightmost pixel of the segmentation, Ymin is the y-coordinate of the bottommost pixel of the segmentation, and Ymax is the y-coordinate of the topmost pixel of the segmentation. In still other embodiments, the bounding box consists of two sets of coordinates (e.g., (Xmin, Ymax) and (Xmax, Ymin)) and at least one length value (e.g., the length of one side of a square or the length of the bottom and height of a rectangle). Other methods for determining the bounding boxes of objects can be used in conjunction with this disclosure. For example, in embodiments where the object includes long-tailed or similar components that make it difficult to generate a bounding box that only includes the depicted object, histograms or other statistical techniques are used to select a minimum perimeter box that surrounds pixels by a threshold (e.g., 95%) or other value to prevent the bounding box from including at least a portion of the image that does not depict the object's pixels.

[0098] In various embodiments, at box B910, method 900 includes associating tags with bounding boxes of objects in a set of transformed images. For example, a set of transformed images is added to a dataset that includes tags and bounding box information generated as described above. In various embodiments, a set of transformed images is stored in a dataset according to the dataset's format. Furthermore, in various embodiments, the dataset including the set of transformed images is used to train a transformation-robust neural network. For example, because the images are rotated during the transformation, a neural network trained using a dataset including the transformed images and bounding box information is rotation-robust when performing inference. Figure 9 As shown, in various embodiments, method 900 is repeated to augment the dataset. For example, as described above, transformations are applied sequentially to further reduce the domain gaps. In various embodiments, method 900 is performed to generate a set of rotated image and bounding box information for augmenting the dataset, and then repeated to generate a set of stretched image and bounding box information for augmenting the dataset.

[0099] Reasoning and training logic

[0100] Figure 10A Inference and / or training logic 1015 for performing inference and / or training operations associated with one or more embodiments is shown. The following is in conjunction with... Figure 10A and / or Figure 10B Provide details about reasoning and / or training logic 1015.

[0101] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1001 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1001 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 1001 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1001 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0102] In at least one embodiment, any portion of the code and / or data storage 1001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1001 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 1001 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0103] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1005 to store backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 1005 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1005 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0104] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 1005 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1005 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1005 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 1005 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0105] In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be separate storage structures. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be the same storage structure. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 1001 and code and / or data storage 1005 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0106] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1010 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 1020, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1001 and / or code and / or data storage 1005. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 1010 is stored in activation storage 1020, wherein weight values ​​stored in code and / or data storage 1005 and / or code and / or data storage 1001 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 1005 or code and / or data storage 1001 or other on-chip or off-chip storage.

[0107] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 1010, while in another embodiment, one or more ALUs 1010 may be located outside the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 1010 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 1001, code and / or data storage 1005, and activation storage 1020 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 1020 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0108] In at least one embodiment, the active memory 1020 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 1020 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 1020 is internal to or external to the processor may depend on the available on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0109] In at least one embodiment, Figure 10A The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10AThe inference and / or training logic 1015 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0110] Figure 10B An inference and / or training logic 1015 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 1015 includes, but is not limited to, code and / or data storage 1001 and code and / or data storage 1005, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 10B In at least one embodiment shown, each of code and / or data storage 1001 and code and / or data storage 1005 is associated with dedicated computing resources (e.g., computing hardware 1002 and computing hardware 1006), respectively. In at least one embodiment, each of computing hardware 1002 and computing hardware 1006 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 1001 and code and / or data storage 1005, respectively, and the results of the function execution are stored in activation storage 1020.

[0111] In at least one embodiment, each of the code and / or data storage 1001 and 1005 and the corresponding computing hardware 1002 and 1006 corresponds to a different layer of the neural network, such that activations obtained from one “store / computation pair 1001 / 1002” of the code and / or data storage 1001 and computing hardware 1002 provide input as input to the next “store / computation pair 1005 / 1006” of the code and / or data storage 1005 and computing hardware 1006, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 1001 / 1002 and 1005 / 1006 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 1015 following or paralleling the store / computation pairs 1001 / 1002 and 1005 / 1006.

[0112] Neural network training and deployment

[0113] Figure 11 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1106 is trained using a training dataset 1102. In at least one embodiment, the training framework 1104 is the PyTorch framework, while in other embodiments, the training framework 1104 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 and enables it to be trained using the processing resources described herein to generate a trained neural network 1108. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0114] In at least one embodiment, supervised learning is used to train an untrained neural network 1106, wherein the training dataset 1102 includes inputs paired with desired outputs for input, or wherein the training dataset 1102 includes inputs with known outputs and the neural network 1106 is a manually hierarchical output. In at least one embodiment, the untrained neural network 1106 is trained in a supervised manner, and inputs from the training dataset 1102 are processed, and the resulting outputs are compared with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 1106. In at least one embodiment, a training framework 1104 adjusts the weights controlling the untrained neural network 1106. In at least one embodiment, the training framework 1104 includes tools for monitoring the degree to which the untrained neural network 1106 converges to a model (e.g., a trained neural network 1108) adapted to generate the correct answer (e.g., result 1114) based on input data (e.g., a new dataset 1112). In at least one embodiment, the training framework 1104 repeatedly trains the untrained neural network 1106 while adjusting the weights to improve the output of the untrained neural network 1106 using a loss function and tuning algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 until the untrained neural network 1106 reaches the desired accuracy. In at least one embodiment, the trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0115] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1106, wherein the untrained neural network 1106 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1102 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1106 can learn groupings within the training dataset 1102 and can determine how each input relates to the untrained dataset 1102. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 1108, which is capable of performing operations useful for reducing the dimensionality of the new dataset 1112. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1112 that deviate from the normal patterns of the new dataset 1112.

[0116] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1102. In at least one embodiment, the training framework 1104 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1108 to adapt to the new dataset 1112 without forgetting the knowledge injected into the trained neural network 1108 during initial training.

[0117] Data Center

[0118] Figure 12 An example data center 1200 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0119] In at least one embodiment, such as Figure 12 As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, packet computing resources 1214, and node computing resources (“nodes CR”) 1216(1)-1216(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1216(1)-1216(N) may be servers having one or more of the aforementioned computing resources.

[0120] In at least one embodiment, the grouped computing resource 1214 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resource 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0121] In at least one embodiment, resource coordinator 1212 may be configured or otherwise control one or more nodes CR1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may include a software design infrastructure (“SDI”) management entity for data center 1200. In at least one embodiment, resource coordinator 1212 may include hardware, software, or some combination thereof.

[0122] In at least one embodiment, such as Figure 12 As shown, framework layer 1220 includes a job scheduler 1222, a configuration manager 1224, a resource manager 1226, and a distributed file system 1228. In at least one embodiment, framework layer 1220 may include a framework of software 1232 supporting software layer 1230 and / or one or more applications 1242 supporting application layer 1240. In at least one embodiment, software 1232 or application 1242 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1228 for large-scale data processing (e.g., "big data"). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1232 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1200. In at least one embodiment, the configuration manager 1224 may be able to configure different layers, such as software layer 1230 and framework layer 1220 including Spark and a distributed file system 1228 for supporting large-scale data processing. In at least one embodiment, the resource manager 1226 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 1228 and job scheduler 1222. In at least one embodiment, cluster or group computing resources may include group computing resources 1214 on data center infrastructure layer 1210. In at least one embodiment, the resource manager 1226 may coordinate with resource coordinator 1212 to manage these mapped or allocated computing resources.

[0123] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the nodes CR1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0124] In at least one embodiment, one or more applications 1242 included in application layer 1240 may include one or more types of applications used by at least a portion of nodes CR1216(1)-1216(N), grouped computing resources 1214, and / or the distributed file system 1228 of framework layer 1220. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0125] In at least one embodiment, any of the configuration manager 1224, resource manager 1226, and resource coordinator 1212 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1200 and can prevent underutilization and / or poor performance of the data center.

[0126] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1200, by using weight parameters calculated through one or more training techniques described herein.

[0127] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0128] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 12 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0129] In various embodiments, data center 1200 provides computing resources to perform the training methods described above. For example, data center 1200 provides inference and / or training logic 1015 to generate pre-labeled tools as described above.

[0130] Autonomous vehicles

[0131] Figure 13AAn example of an autonomous vehicle 1300 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1300 (which may alternatively be referred to herein as "vehicle 1300") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1300 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1300 may be an aircraft, robotic vehicle, or other type of vehicle.

[0132] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 1300 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1300 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0133] In at least one embodiment, vehicle 1300 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1300 may include, but is not limited to, propulsion system 1350, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1350 may be connected to the drivetrain of vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1300. In at least one embodiment, propulsion system 1350 may be controlled in response to receiving a signal from throttle / accelerator 1352.

[0134] In at least one embodiment, when the propulsion system 1350 is operating (e.g., when the vehicle 1300 is traveling), the steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, the steering system 1354 may receive signals from the steering actuator 1356. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1348 and / or brake sensors.

[0135] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 13A A controller 1336 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 may send signals to operate vehicle braking via brake actuator 1348, to operate steering system 1354 via one or more steering actuators 1356, and to operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, one or more controllers 1336 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0136] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1358 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide-angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360-degree cameras), and remote cameras (…). Figure 13A (not shown in the image), medium-range camera ( Figure 13A (Not shown in the image) One or more speed sensors 1344 (e.g., for measuring the speed of vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of brake sensor system 1346) and / or other sensor types are received.

[0137] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from the dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1334, a voice signaler, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 13A The HMI display 1334 may display information such as (not shown in the image), location data (e.g., the location of vehicle 1300, for example, on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 1336. For example, in at least one embodiment, the HMI display 1334 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has already made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0138] In at least one embodiment, vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, network interface 1324 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1326 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0139] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13A The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0140] In various embodiments, the autonomous vehicle 1300 utilizes inference and / or training logic 1015 to execute a neural network or other model trained using the training methods described above, in order to perform pedestrian and / or object detection using an environment-robust neural network or other model.

[0141] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and fields of view for an autonomous vehicle 1300. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1300.

[0142] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0143] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0144] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1300 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0145] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1300 can be used for surround view and, with the assistance of one or more controllers 1336 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0146] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 13B Only one wide-angle camera 1370 is shown; however, in other embodiments, the vehicle 1300 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1398 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1398 can also be used for object detection and classification, as well as basic object tracking.

[0147] In at least one embodiment, any number of stereo cameras 1368 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1300, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera samples (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1300 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may also be used in addition to those described herein.

[0148] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1300 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1374 (e.g., as...) Figure 13B The four surround cameras shown can be positioned on vehicle 1300. In at least one embodiment, one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1300. In at least one embodiment, vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0149] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1300 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0150] The inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B This document provides details regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can... Figure 13B Used in systems for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0151] Figure 13C The illustration shows an embodiment according to at least one of the embodiments. Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300. In at least one embodiment, Figure 13CEach of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1300 used to help control various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1302 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1302 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0152] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of the buses 1302 may communicate with any component of the vehicle 1300, and two or more buses 1302 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1304 (e.g., SoC 1304(A) and SoC 1304(B)), each of one or more controllers 1336, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0153] In at least one embodiment, vehicle 1300 may include one or more controllers 1336, such as those described herein. Figure 13A As described above. In at least one embodiment, controller 1336 can be used for a variety of functions. In at least one embodiment, controller 1336 can be coupled to any of various other components and systems of vehicle 1300 and can be used to control vehicle 1300, artificial intelligence of vehicle 1300, infotainment and / or other functions of vehicle 1300.

[0154] In at least one embodiment, vehicle 1300 may include any number of SoCs 1304. In at least one embodiment, each of the SoCs 1304 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1306, a graphics processing unit (“one or more GPUs”) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data storage 1316, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1304 may be used to control vehicle 1300 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1304 may be combined with a high-definition (“HD”) map 1322 in a system (e.g., the system of vehicle 1300), the high-definition map 1322 being accessible from one or more servers via a network interface 1324. Figure 13C (Not shown in the image) Get map refresh and / or update.

[0155] In at least one embodiment, one or more CPUs 1306 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1306 can be active at any given time.

[0156] In at least one embodiment, one or more CPUs 1306 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1306 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0157] In at least one embodiment, one or more GPUs 1308 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1308 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1308 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0158] In at least one embodiment, one or more GPU 1308s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1308s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0159] In at least one embodiment, one or more GPUs 1308 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0160] In at least one embodiment, one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1308 to directly access the page tables of one or more CPUs 1306. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1308 experiences a miss, an address translation request may be sent to one or more CPUs 1306. In response, in at least one embodiment, two CPUs of one or more CPUs 1306 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1306 and one or more GPUs 1308, thereby simplifying the programming of one or more GPUs 1308 and the porting of applications to one or more GPUs 1308.

[0161] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0162] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a Level 3 (“L3”) cache available for one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0163] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks from one or more GPUs 1308 (e.g., freeing up more cycles from one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0164] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0165] In at least one embodiment, the DLA can perform any function of one or more GPUs 1308, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1308 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1308 and / or one or more accelerators 1314.

[0166] In at least one embodiment, one or more accelerators 1314 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1338, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0167] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0168] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1306. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0169] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0170] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0171] In at least one embodiment, one or more accelerators 1314 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0172] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0173] In at least one embodiment, one or more SoCs 1304 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0174] In at least one embodiment, one or more accelerators 1314 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1300, PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0175] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0176] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0177] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1366 related to the vehicle 1300 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1364 or one or more RADAR sensors 1360).

[0178] In at least one embodiment, one or more SoCs 1304 may include one or more data storage devices 1316 (e.g., memory). In at least one embodiment, one or more data storage devices 1316 may be on-chip memory of one or more SoCs 1304, which may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data storage devices 1316 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1316 may include L2 or L3 caches.

[0179] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1304s, and / or power state management of one or more SoCs 1304s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1304s may use the ring oscillator to detect the temperature of one or more CPUs 1306s, one or more GPUs 1308s, and / or one or more accelerators 1314s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1304s into a lower power state and / or place the vehicle 1300 into a driver's safe stopping pattern (e.g., bring the vehicle 1300 to a safe stop).

[0180] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0181] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0182] In at least one embodiment, one or more processors 1310 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0183] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1304, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0184] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0185] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0186] In at least one embodiment, one or more SoCs of SoC 1304 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1304 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0187] In at least one embodiment, one or more SoCs of SoC 1304 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1304 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet channels), data from bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1306 from routine data management tasks.

[0188] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data storage devices 1316, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0189] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0190] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0191] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0192] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1300. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0193] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1362, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0194] In at least one embodiment, vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1304 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1318 may include x86 processors. For example, one or more CPUs 1318 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1304, and / or monitoring the status and health of one or more monitoring controllers 1336 and / or on-chip information systems (“information SoCs”) 1330.

[0195] In at least one embodiment, vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1304 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1320 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1300 (e.g., sensor data).

[0196] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1300 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles near vehicle 1300 (e.g., vehicles in front, to the side, and / or behind vehicle 1300). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1300.

[0197] In at least one embodiment, network interface 1324 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, network interface 1324 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0198] In at least one embodiment, vehicle 1300 may further include one or more data storage units 1328, which may include, but are not limited to, off-chip (e.g., one or more SoC 1304) storage. In at least one embodiment, one or more data storage units 1328 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0199] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0200] In at least one embodiment, vehicle 1300 may further include one or more RADAR sensors 1360. In at least one embodiment, one or more RADAR sensors 1360 may be used by vehicle 1300 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0201] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between stationary and moving objects and can be used by the ADAS system 1338 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1300 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1300 entering or leaving the lane.

[0202] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1338 for blind spot detection and / or lane change assistance.

[0203] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned at the front, rear, and / or sides of the vehicle 1300, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1362 may operate at the ASIL B functional safety level.

[0204] In at least one embodiment, vehicle 1300 may include one or more LiDAR sensors 1364. In at least one embodiment, one or more LiDAR sensors 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1364 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1300 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1364 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0205] In at least one embodiment, one or more LiDAR sensors 1364 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1364 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1364 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1300. In at least one embodiment, one or more LiDAR sensors 1364, in such an embodiment, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1364 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0206] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0207] In at least one embodiment, vehicle 1300 may further include one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 may be located at the center of the rear axle of vehicle 1300. In at least one embodiment, one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0208] In at least one embodiment, one or more IMU sensors 1366 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1366 may enable vehicle 1300 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 may be combined in a single integrated unit.

[0209] In at least one embodiment, vehicle 1300 may include one or more microphones 1396 placed inside and / or around vehicle 1300. In at least one embodiment, in addition, one or more microphones 1396 may be used for emergency vehicle detection and identification.

[0210] In at least one embodiment, vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide-angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long-range cameras 1398, one or more mid-range cameras 1376, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1300. In at least one embodiment, the type of camera used depends on vehicle 1300. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 13A and Figure 13B Each camera can be described in more detail.

[0211] In at least one embodiment, the vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, the one or more vibration sensors 1342 may measure vibrations of components of the vehicle 1300 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1342 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0212] In at least one embodiment, vehicle 1300 may include ADAS system 1338. In at least one embodiment, ADAS system 1338 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0213] In at least one embodiment, the ACC system may use one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1300 and automatically adjusts the speed of vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1300 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0214] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1324 and / or one or more wireless antennas 1326 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1300 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1300, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0215] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0216] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0217] In at least one embodiment, when vehicle 1300 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0218] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0219] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1300 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0220] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 1336). For example, in at least one embodiment, ADAS system 1338 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1338 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0221] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0222] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1304s.

[0223] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0224] In at least one embodiment, the output of the ADAS system 1338 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0225] In at least one embodiment, vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1330 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1300. For example, the infotainment SoC 1330 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1334, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1330 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1300, such as information from ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0226] In at least one embodiment, the infotainment SoC 1330 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 may communicate with other devices, systems, and / or components of the vehicle 1300 via bus 1302. In at least one embodiment, the infotainment SoC 1330 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the main computer and / or backup computer of the vehicle 1300). In at least one embodiment, the infotainment SoC 1330 may cause the vehicle 1300 to enter a driver-to-safe-stop mode, as described herein.

[0227] In at least one embodiment, vehicle 1300 may further include instrument panel 1332 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1332 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1330 and instrument panel 1332. In at least one embodiment, instrument panel 1332 may be included as part of infotainment SoC 1330, or vice versa.

[0228] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13C The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0229] Figure 13D It is based on at least one embodiment in a cloud-based server and Figure 13AA diagram of a system 1376 for communication between autonomous vehicles 1300. In at least one embodiment, system 1376 may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. In at least one embodiment, one or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPU 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switch 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPU 1380). GPU 1384, CPU 1380, and PCIe switch 1382 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connection 1386. In at least one embodiment, the GPU 1384 is connected via NVLink and / or NVSwitch SoC, and the GPU 1384 and PCIe switch 1382 are connected via PCIe interconnect. Although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1378 may include, but is not limited to, any combination of any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0230] In at least one embodiment, one or more servers 1378 may receive image data representing images from vehicles via one or more networks 1390, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1378 may transmit updated neural network 1392 and / or map information 1394, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 1390. In at least one embodiment, updates to map information 1394 may include, but are not limited to, updates to HD map 1322, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1392 and / or map information 1394 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1378 and / or other servers).

[0231] In at least one embodiment, one or more servers 1378 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390), and / or the machine learning model may be used by one or more servers 1378 to remotely monitor the vehicle.

[0232] In at least one embodiment, one or more servers 1378 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1378 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 may include a deep learning infrastructure in a data center using CPU power.

[0233] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as image sequences and / or objects located by vehicle 1300 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1300, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1300 is malfunctioning, one or more servers 1378 may signal to vehicle 1300 to instruct the fail-safe computer of vehicle 1300 to take control, notify passengers, and complete a safe stopping operation.

[0234] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 1015 is used to execute one or more embodiments. This document incorporates... Figure 10A and / or Figure 10B Provide details about the hardware architecture 1015.

[0235] Computer System

[0236] Figure 14 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1400 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1400 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0237] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0238] In at least one embodiment, the computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1400 is a single-processor desktop or server system, but in another embodiment, the computer system 1400 may be a multiprocessor system. In at least one embodiment, the processor 1402 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1402 may be coupled to a processor bus 1410, which can transmit data signals between the processor 1402 and other components in the computer system 1400.

[0239] In at least one embodiment, processor 1402 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0240] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1402. In at least one embodiment, processor 1402 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1408 may include logic for processing a packaged instruction set 1409. In at least one embodiment, by including the packaged instruction set 1409 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in processor 1402 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0241] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that can be executed by processor 1402.

[0242] In at least one embodiment, the system logic chip may be coupled to processor bus 1410 and memory 1420. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1416, and processor 1402 may communicate with MCH 1416 via processor bus 1410. In at least one embodiment, MCH 1416 may provide a high-bandwidth memory path 1418 to memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1416 may initiate data signals between processor 1402, memory 1420, and other components in computer system 1400, and bridge data signals between processor bus 1410, memory 1420, and system I / O interface 1422. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1416 may be coupled to memory 1420 via high-bandwidth memory path 1418, and graphics / video card 1412 may be coupled to MCH 1416 via Accelerated Graphics Port (“AGP”) interconnect 1414.

[0243] In at least one embodiment, the computer system 1400 may use the system I / O interface 1422 as a proprietary hub interface bus to couple the MCH 1416 to the I / O controller hub (“ICH”) 1430. In at least one embodiment, the ICH 1430 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub (“Flash BIOS”) 1428, a wireless transceiver 1426, a data storage 1424, a conventional I / O controller 1423 including a user input and keyboard interface 1425, a serial expansion port 1427 (e.g., a Universal Serial Bus (USB) port), and a network controller 1434. In at least one embodiment, the data storage 1424 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0244] In at least one embodiment, Figure 14 One embodiment is shown that includes interconnected hardware devices or "chips," while in other embodiments, Figure 14 An exemplary SoC can be shown. In at least one embodiment, Figure 14The devices shown can be interconnected with dedicated interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1400 are interconnected using a Fast Compute Link (CXL) interconnect.

[0245] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A 10B provides details regarding the inference and / or training logic 1015. In at least one embodiment, the inference and / or training logic 1015 can be used in the system. Figure 14 In this context, it refers to operations used for reasoning or prediction based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage as described herein.

[0246] Figure 15 This is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 according to at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a laptop, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0247] In at least one embodiment, the electronic device 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1510 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 15 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 15 An exemplary SoC can be shown. In at least one embodiment, Figure 15 The devices shown can be interconnected with dedicated interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, a compute fast link (CXL) interconnect is used for interconnection. Figure 15 One or more components.

[0248] In at least one embodiment, Figure 15It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash memory (“BIOS, FW flash”) 1522, a DSP 1560, a drive 1520 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) unit 1555, a camera (“USB 3.0 camera”) 1554 (such as a USB 3.0 camera) and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0249] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described herein. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1562, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as WLAN unit 1550, Bluetooth unit 1552, and WWAN unit 1556 can be implemented in a next-generation form factor (“NGFF”).

[0250] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A 10B provides details regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 may be... Figure 15The system is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage as described herein.

[0251] Figure 16 A computer system 1600 according to at least one embodiment is shown. In at least one embodiment, the computer system 1600 is configured to implement the various processes and methods described throughout this disclosure.

[0252] In at least one embodiment, the computer system 1600 includes, but is not limited to, at least one central processing unit (“CPU”) 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Fast Peripheral Component Interconnect (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in main memory 1604, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1622 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems having the computer system 1600.

[0253] In at least one embodiment, the computer system 1600 includes, but is not limited to, an input device 1608, a parallel processing system 1612, and a display device 1606 that can be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1608, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may reside on a single semiconductor platform to form a processing system.

[0254] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A 10B provides details regarding the inference and / or training logic 1015. In at least one embodiment, the inference and / or training logic 1015 can be used in the system. Figure 16In this context, it refers to operations used for reasoning or prediction based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage as described herein.

[0255] Figure 17 A computer system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1700 includes, but is not limited to, a computer 1710 and a USB stick 1720. In at least one embodiment, the computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0256] In at least one embodiment, the USB stick 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1730 includes an application-specific integrated circuit (“ASIC”) optimized to perform any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1730 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1730 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0257] In at least one embodiment, the USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1750 may include any amount and type of logic that enables the processing unit 1730 to engage with a device (e.g., computer 1710) via the USB connector 1740.

[0258] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 17The operation is used to infer or predict based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architecture, or neural network usage described herein.

[0259] Figure 18A An exemplary architecture is illustrated in which multiple GPUs 1810(1)-1810(N) are communicatively coupled to multiple multi-core processors 1805(1)-1805(M) via high-speed links 1840(1)-1840(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1840(1)-1840(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0260] Furthermore, in at least one embodiment, two or more GPUs 1810 are interconnected via high-speed links 1829(1)-1829(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1840(1)-1840(N). Similarly, two or more multi-core processors 1805 can be connected via high-speed link 1828, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 18A This shows all communication between the various system components.

[0261] In at least one embodiment, each multi-core processor 1805 is communicatively coupled to processor memories 1801(1)-1801(M) via memory interconnects 1826(1)-1826(M), and each GPU 1810(1)-1810(N) is communicatively coupled to GPU memories 1820(1)-1820(N) via GPU memory interconnects 1850(1)-1850(N). In at least one embodiment, memory interconnects 1826 and 1850 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1801(1)-1801(M) and GPU memories 1820 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1801 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0262] As described herein, although various multi-core processors 1805 and GPUs 1810 can be physically coupled to specific memories 1801 and 1820 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1801(1)-1801(M) can each contain 64GB of system memory address space, and GPU memories 1820(1)-1820(N) can each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. N and M may also be other values.

[0263] Figure 18B Additional details are shown regarding the interconnection between a multi-core processor 1807 and a graphics acceleration module 1846 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1846 may include one or more GPU chips integrated on a line card coupled to the processor 1807 via a high-speed link 1840 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1846 may optionally be integrated on a package or chip having the processor 1807.

[0264] In at least one embodiment, the processor 1807 includes a plurality of cores 1860A-1860D, each core having a translation back cover buffer (“TLB”) 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by the respective groups of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1807 and the graphics acceleration module 1846 are connected to a system memory 1814, which may include... Figure 18A The processor memory in the memory is 1801(1)-1801(M).

[0265] In at least one embodiment, consistency of data and instructions stored in the various caches 1862A-1862D, 1856 and system memory 1814 is maintained via inter-core communication through the consistency bus 1864. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1864 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1864 to snoop on cache accesses.

[0266] In at least one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in cache coherence protocols as a peer of cores 1860A-1860D. Specifically, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840, and interface 1837 connects graphics acceleration module 1846 to high-speed link 1840.

[0267] In at least one embodiment, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1831(1)-1831(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having a plurality of graphics processing engines 1831(1)-1831(N), or the graphics processing engines 1831(1)-1831(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0268] In at least one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. In at least one embodiment, the MMU 1839 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1838 may store commands and data for efficient access by the graphics processing engines 1831(1)-1831(N). In at least one embodiment, a fetch unit 1844 may be used to keep data stored in the cache 1838 and graphics memories 1833(1)-1833(M) consistent with the core caches 1862A-1862D, 1856 and system memory 1814. As previously mentioned, this task can be accomplished via proxy circuitry 1825 representing cache 1838 and graphics memory 1833(1)-1833(M) (e.g., sending updates related to the modification / access of cache lines on processor caches 1862A-1862D, 1856 to cache 1838 and receiving updates from cache 1838).

[0269] In at least one embodiment, a set of registers 1845 stores context data of threads executed by graphics processing engines 1831(1)-1831(N), and context management circuitry 1848 manages the thread context. For example, context management circuitry 1848 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1848 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0270] In at least one embodiment, MMU 1839 translates virtual / effective addresses from graphics processing engine 1831 into real / physical addresses in system memory 1814. In at least one embodiment, accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1846 may be dedicated to a single application executing on processor 1807, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1831(1)-1831(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0271] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system of the graphics acceleration module 1846 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1831(1)-1831(N).

[0272] In at least one embodiment, since the hardware resources of the graphics processing engines 1831(1)-1831(N) are explicitly mapped to the real address space seen by the host processor 1807, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1836 is to physically separate the graphics processing engines 1831(1)-1831(N) so that they appear as independent units to the system.

[0273] In at least one embodiment, one or more graphics memories 1833(1)-1833(M) are coupled to each graphics processing engine 1831(1)-1831(N), and N = M. In at least one embodiment, the graphics memories 1833(1)-1833(M) store instructions and data processed by each graphics processing engine 1831(1)-1831(N). In at least one embodiment, the graphics memories 1833(1)-1833(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0274] In at least one embodiment, to reduce data traffic on the high-speed link 1840, a biasing technique is used to ensure that the data stored in the graphics memory 1833(1)-1833(M) is the data most frequently used by the graphics processing engine 1831(1)-1831(N), and preferably data that the cores 1860A-1860D do not use (or at least do not use frequently). Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1831(-1)-1831(N)) in the caches 1862A-1862D, 1856 and system memory 1814.

[0275] Figure 18C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1836 is integrated within the processor 1807. In this embodiment, the graphics processing engines 1831(1)-1831(N) communicate directly with the accelerator integrated circuit 1836 via a high-speed link 1840 through interfaces 1837 and 1835 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1836 can perform operations related to... Figure 18B The described operation is similar to that of the accelerator integrated circuit. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, 1856, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0276] In at least one embodiment, graphics processing engines 1831(1)-1831(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1831(1)-1831(N), thereby providing virtualization within a VM / partition.

[0277] In at least one embodiment, graphics processing engines 1831(1)-1831(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1831(1)-1831(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1831(1)-1831(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1831(1)-1831(N) to provide access to each process or application.

[0278] In at least one embodiment, the graphics acceleration module 1846 or the individual graphics processing engine 1831(1)-1831(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1831(1)-1831(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0279] Figure 18DAn exemplary accelerator integration slice 1890 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1836. In at least one embodiment, the application is an effective address space 1882 in system memory 1814, which stores process element 1883. In at least one embodiment, process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. In at least one embodiment, process element 1883 contains the process state of the corresponding application 1880. In one embodiment, a job descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in the effective address space 1882 of the application.

[0280] In at least one embodiment, the graphics acceleration module 1846 and / or the various graphics processing engines 1831(1)-1831(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1884 to the graphics acceleration module 1846 to begin operations in a virtualized environment.

[0281] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1846 or an individual graphics processing engine 1831. In at least one embodiment, when the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1846 is assigned, the operating system initializes the accelerator integrated circuit 1836 for the owned process.

[0282] In at least one embodiment, during operation, the WD acquisition unit 1891 in the accelerator integration slice 1890 acquires the next WD 1884, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. In at least one embodiment, data from the WD 1884 may be stored in register 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. In at least one embodiment, the interrupt management circuitry 1847 may process an interrupt event 1892 received from the graphics acceleration module 1846. In at least one embodiment, when performing graphics operations, a valid address 1893 generated by the graphics processing engines 1831(1)-1831(N) is translated into a real address by the MMU 1839.

[0283] In at least one embodiment, register 1845 is copied for each graphics processing engine 1831(1)-1831(N) and / or graphics acceleration module 1846, and said register 1845 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1890. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0284]

[0285] Table 2 shows exemplary registers that can be initialized by the operating system.

[0286]

[0287] In at least one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831(1)-1831(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1831(1)-1831(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0288] Figure 18E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1898, in which a list of process elements 1899 is stored. In at least one embodiment, the hypervisor real address space 1898 can be accessed via a hypervisor 1896, which virtualizes the graphics acceleration module engine for operating system 1895.

[0289] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1846. In at least one embodiment, there are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0290] In at least one embodiment, in this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. In at least one embodiment, for the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1846 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1846 must be ensured.

[0291] In at least one embodiment, application 1880 needs to make operating system 1895 system calls using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1846 and can take the form of graphics acceleration module 1846 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1846.

[0292] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1836 (not shown) and the graphics acceleration module 1846 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1896 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1883. In at least one embodiment, CSRP is one of the registers 1845 containing the effective address of a region in the effective address space 1882 of the application for the graphics acceleration module 1846 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0293] Upon receiving a system call, operating system 1895 can verify that application 1880 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, operating system 1895 uses the information shown in Table 3 to invoke hypervisor 1896.

[0294]

[0295]

[0296] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1896 verifies that operating system 1895 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, hypervisor 1896 adds process element 1883 to a linked list of process elements of the corresponding graphics acceleration module 1846 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0297]

[0298] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1890 registers 1845.

[0299] like Figure 18FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1801(1)-1801(N) and GPU memories 1820(1)-1820(N). In this implementation, operations performed on GPUs 1810(1)-1810(N) utilize the same virtual / effective memory address space to access processor memories 1801(1)-1801(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801(1), a second portion to second processor memory 1801(N), a third portion to GPU memory 1820(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1801 and GPU memory 1820, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0300] In at least one embodiment, the bias / coherence management circuitry 1894A-1894E within one or more MMUs 1839A-1839E ensures cache coherence between one or more host processors (e.g., 1805) and the cache of the GPU 1810, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 18F Several instances of bias / coherence management circuits 1894A-1894E are shown, but bias / coherence circuits can be implemented within the MMU of one or more host processors 1805 and / or within the accelerator integrated circuit 1836.

[0301] One embodiment allows GPU memory 1820 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1820 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1805 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1820 without cache coherence overhead may be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1810. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0302] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1810, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1820. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0303] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1820 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1810 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1820. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1805 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1805 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1810. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0304] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1805 bias to the GPU bias, but not for the reverse migration.

[0305] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1805 cannot cache. In at least one embodiment, to access these pages, the processor 1805 may request access from the GPU 1810, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1805 and the GPU 1810, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1805, and vice versa.

[0306] One or more hardware structures 1015 are used to execute one or more embodiments. This document may combine... Figure 10A and / or Figure 10B Provide details about one or more hardware structures 1015.

[0307] Figure 19Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0308] Figure 19 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1900 includes peripheral or bus logic, which includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I... 2 2S / I 2 2C controller 1940. In at least one embodiment, integrated circuit 1900 may include display device 1945 coupled to one or more of High Definition Multimedia Interface (HDMI) controller 1950 and Mobile Industrial Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by flash memory subsystem 1960, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1970.

[0309] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in integrated circuit 1900 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0310] Figure 20A and Figure 20BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0311] Figure 20A-20B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 20B An additional exemplary graphics processor 2040 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 may be... Figure 19 A variant of the 1910 graphics processor.

[0312] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0313] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with… Figure 19 One or more application processors 1905, graphics processors 1915, and / or video processors 1920 are associated with one or more MMUs, enabling each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0314] In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F to 2055N-1 and 2055N), such as Figure 20B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045, which acts as a thread dispatcher to assign execution threads to one or more shader cores 2055A-2055N and tile units 2058 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0315] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be integrated into an integrated circuit. Figure 20A and / or Figure 20B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0316] Figure 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 21A It shows that it can be included in Figure 19 The graphics core 2100 within the graphics processor 1910, and in at least one embodiment, may be as follows: Figure 20B The Unified Shader Cores 2055A-2055N are shown. Figure 21B A highly parallel general-purpose graphics processing unit (“GPGPU”) 2130 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0317] In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and a cache / shared memory 2120, which are common to the execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. In at least one embodiment, slices 2101A-2101N may include supporting logic, including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional functional units (AFU 2112A-2112N), floating-point units (FPU 2114A-2114N), integer arithmetic logic units (ALU 2116A-2116N), address calculation units (ACU 2113A-2113N), double-precision floating-point units (DPFPU 2115A-2115N), and matrix processing units (MPU 2117A-2117N).

[0318] In at least one embodiment, the FPU 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2115A-2115N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2117A-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2112A-2112N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0319] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be used in the graphics core 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0320] Figure 21BA general-purpose processing unit (GPGPU) 2130 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for connection to a host processor. In at least one embodiment, the host interface 2132 is a PCI Express interface. In at least one embodiment, the host interface 2132 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to allocate execution threads associated with those commands to a set of compute clusters 2136A-2136H. In at least one embodiment, compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 can be used as a higher-level cache within the cache memory of computing clusters 2136A-2136H.

[0321] In at least one embodiment, the GPGPU 2130 includes memories 2144A-2144B, which are coupled to computing clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memories 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0322] In at least one embodiment, each of the computing clusters 2136A-2136H includes a set of graphics cores, for example... Figure 21A The graphics core 2100 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0323] In at least one embodiment, multiple instances of GPGPU 2130 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 2136A-2136H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in a separate data processing system and communicate via network devices accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor other than or as a replacement for host interface 2132.

[0324] In at least one embodiment, GPGPU 2130 can be configured to train a neural network. In at least one embodiment, GPGPU 2130 can be used within an inference platform. In at least one embodiment, when GPGPU 2130 is used for inference, GPGPU 2130 may include fewer compute clusters 2136A-2136H compared to when GPGPU 2130 is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2144A-2144B can differ between inference and training configurations, wherein higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0325] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be used in the GPGPU 2130 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0326] Figure 22 A block diagram of a computer system 2200 according to at least one embodiment is shown. In at least one embodiment, the computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204 communicating via an interconnect path that may include a memory hub 2205. In at least one embodiment, the memory hub 2205 may be a separate component within a chipset component or may be integrated within one or more processors 2202. In at least one embodiment, the memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, the I / O subsystem 2211 includes an I / O hub 2207 that enables the computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, the I / O hub 2207 enables a display controller to provide output to one or more display devices 2210A, the display controller being included in one or more processors 2202. In at least one embodiment, one or more display devices 2210A coupled to I / O hub 2207 may include local, internal or embedded display devices.

[0327] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 2212 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one or more display devices 2210A coupled via an I / O hub 2207. In at least one embodiment, the parallel processors 2212 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2210B.

[0328] In at least one embodiment, system storage unit 2214 may be connected to I / O hub 2207 to provide a storage mechanism for computer system 2200. In at least one embodiment, I / O switch 2216 may be used to provide an interface mechanism to enable connectivity between I / O hub 2207 and other components, such as network adapter 2218 and / or wireless network adapter 2219 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2220. In at least one embodiment, network adapter 2218 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2219 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0329] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 22 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0330] In at least one embodiment, one or more parallel processors 2212 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, the parallel processor 2212 includes circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 2212, memory hub 2205, processor 2202, and I / O hub 2207 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2200 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0331] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines...Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can... Figure 22 The system 2200 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0332] processor

[0333] Figure 23A A parallel processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2300 is according to an exemplary embodiment. Figure 22 The variant of the 2212, which includes one or more parallel processors, is shown.

[0334] In at least one embodiment, the parallel processor 2300 includes a parallel processing unit 2302. In at least one embodiment, the parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of the parallel processing unit 2302. In at least one embodiment, the I / O unit 2304 can be directly connected to other devices. In at least one embodiment, the I / O unit 2304 is connected to other devices using a hub or switch interface (e.g., a memory hub 2305). In at least one embodiment, the connection between the memory hub 2305 and the I / O unit 2304 forms a communication link 2313. In at least one embodiment, the I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, wherein the host interface 2306 receives commands for performing processing operations, and the memory crossbar switch 2316 receives commands for performing memory operations.

[0335] In at least one embodiment, when host interface 2306 receives a command buffer via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to assign commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is correctly configured and in an active state before assigning tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 2312 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 2312 by the scheduler 2310 logic within the microcontroller, which includes the scheduler 2310.

[0336] In at least one embodiment, the processing cluster array 2312 may include up to "N" processing clusters (e.g., clusters 2314A, 2314B to 2314N), where "N" represents a positive integer (which may be an integer different from the integer "N" used in other diagrams). In at least one embodiment, each cluster 2314A-2314N of the processing cluster array 2312 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2310 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2314A-2314N of the processing cluster array 2312, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2310, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2312. In at least one embodiment, the different clusters 2314A-2314N of the processing cluster array 2312 may be assigned to process different types of programs or to perform different types of computations.

[0337] In at least one embodiment, the processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2312 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0338] In at least one embodiment, the processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2302 may transfer data from system memory via I / O unit 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) and then written back to system memory.

[0339] In at least one embodiment, when the parallel processing unit 2302 is used to perform graphics processing, the scheduler 2310 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2314A-2314N of the processing cluster array 2312. In at least one embodiment, portions of the processing cluster array 2312 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2314A-2314N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2314A-2314N for further processing.

[0340] In at least one embodiment, the processing cluster array 2312 may receive processing tasks to be executed via a scheduler 2310, which receives commands defining the processing tasks from a front end 2308. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2310 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2308. In at least one embodiment, the front end 2308 may be configured to ensure that the processing cluster array 2312 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0341] In at least one embodiment, each of one or more instances of the parallel processing unit 2302 may be coupled to the parallel processor memory 2322. In at least one embodiment, the parallel processor memory 2322 may be accessed via a memory crossbar switch 2316, which may receive memory requests from the processing cluster array 2312 and the I / O unit 2304. In at least one embodiment, the memory crossbar switch 2316 may access the parallel processor memory 2322 via a memory interface 2318. In at least one embodiment, the memory interface 2318 may include a plurality of partition units (e.g., partition units 2320A, 2320B to 2320N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2322. In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory units, such that the first partition unit 2320A has a corresponding first memory unit 2324A, the second partition unit 2320B has a corresponding memory unit 2324B, and the Nth partition unit 2320N has a corresponding Nth memory unit 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory units.

[0342] In at least one embodiment, memory cells 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2324A-2324N, allowing partitioning cells 2320A-2320N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2322. In at least one embodiment, local instances of the parallel processor memory 2322 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0343] In at least one embodiment, any of the clusters 2314A-2314N of the processing cluster array 2312 can process data to be written to any memory cell 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar switch 2316 can be configured to transfer the output of each cluster 2314A-2314N to any partition cell 2320A-2320N or another cluster 2314A-2314N, and the clusters 2314A-2314N can perform further processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with the memory interface 2318 via the memory crossbar switch 2316 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2316 has a connection to a memory interface 2318 for communication with I / O unit 2304, and a connection to a local instance of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory not local to parallel processing unit 2302. In at least one embodiment, the memory crossbar switch 2316 may use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0344] In at least one embodiment, multiple instances of the parallel processing unit 2302 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2302 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2302 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2302 or the parallel processor 2300 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0345] Figure 23B This is a block diagram of a partitioning unit 2320 according to at least one embodiment. In at least one embodiment, the partitioning unit 2320 is... Figure 23A This is an example of one of the partitioning units 2320A-2320N. In at least one embodiment, the partitioning unit 2320 includes an L2 cache 2321, a frame buffer interface 2325, and a ROP 2326 (raster operation unit). In at least one embodiment, the L2 cache 2321 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2316 and the ROP 2326. In at least one embodiment, the L2 cache 2321 outputs read misses and urgent write-back requests to the frame buffer interface 2325 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2325. In at least one embodiment, the frame buffer interface 2325 communicates with memory cells in the parallel processor memory (such as...). Figure 23A It interacts with one of the memory cells 2324A-2324N (e.g., within the parallel processor memory 2322).

[0346] In at least one embodiment, ROP 2326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2326 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2326 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2326 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0347] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., Figure 23A The clusters 2314A-2314N are used instead of the partition unit 2320. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2316 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as one or more display devices 2110 of FIG. 21), routed by processor 2102 for further processing, or... Figure 23A One of the processing entities within the parallel processor 2300 is routed for further processing.

[0348] Figure 23C This is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 23A An instance of one of the processing clusters 2314A-2314N. In at least one embodiment, the processing cluster 2314 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0349] In at least one embodiment, the operation of the processing cluster 2314 can be controlled by a pipeline manager 2332 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2332... Figure 23AThe scheduler 2310 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2334 and / or texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2314 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2314 may include one or more instances of the graphics multiprocessor 2334. In at least one embodiment, the graphics multiprocessor 2334 can process data, and the data cross switch 2340 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2332 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2340.

[0350] In at least one embodiment, each graphics multiprocessor 2334 within the processing cluster 2314 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0351] In at least one embodiment, instructions sent to the processing cluster 2314 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0352] In at least one embodiment, the graphics multiprocessor 2334 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2334 may forgo the internal cache and use a cache memory within the processing cluster 2314 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 may also access partition units (e.g., Figure 23A The L2 cache is located within partition units 2320A-2320N, which are shared among all processing clusters 2314 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2334 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2302 can be used as global memory. In at least one embodiment, the processing cluster 2314 includes multiple instances of the graphics multiprocessor 2334, which can share common instructions and data that can be stored in the L1 cache 2348.

[0353] In at least one embodiment, each processing cluster 2314 may include a memory management unit (“MMU”) 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23A The memory interface 2318 is located within the MMU 2345. In at least one embodiment, the MMU 2345 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2345 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2334, the L1 cache 2348, or the processing cluster 2314. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0354] In at least one embodiment, the processing cluster 2314 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2334 outputs a processed task to a data crossbar switch 2340 to provide the processed task to another processing cluster 2314 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2316. In at least one embodiment, a preROP 2342 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 23A The PreROP 2342 unit is located together with the partitioning units 2320A-2320N. In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0355] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in a graphics processing cluster 2314 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0356] Figure 23D A graphics multiprocessor 2334 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2334 is coupled to a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline including, but not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general-purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. In at least one embodiment, the GPGPU cores 2362 and the load / store units 2366 are coupled to a cache memory 2372 and a shared memory 2370 via a memory and cache interconnect 2368.

[0357] In at least one embodiment, instruction cache 2352 receives a stream of instructions to be executed from pipeline manager 2332. In at least one embodiment, instructions are cached in instruction cache 2352 and dispatched to instruction unit 2354 for execution. In one embodiment, instruction unit 2354 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2362. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2356 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2366.

[0358] In at least one embodiment, register file 2358 provides a set of registers for functional units of graphics multiprocessor 2334. In at least one embodiment, register file 2358 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2334 (e.g., GPGPU core 2362, load / store unit 2366). In at least one embodiment, register file 2358 is partitioned among each functional unit, such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is partitioned among different thread bundles being executed by graphics multiprocessor 2334.

[0359] In at least one embodiment, each of the GPGPU cores 2362 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2334. In at least one embodiment, the GPGPU cores 2362 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2334 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed-function or special-function logic.

[0360] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0361] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network connecting each functional unit of the graphics multiprocessor 2334 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a cross-switch interconnect that allows the load / store unit 2366 to perform load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfer between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2334. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2372, the thread executing on GPGPU core 2362 can also programmatically store data in shared memory.

[0362] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0363] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A 10B and / or 10B provide details regarding the inference and / or training logic 1015. In at least one embodiment, the inference and / or training logic 1015 may be used in the graphics multiprocessor 2334 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0364] Figure 24A multi-GPU computing system 2400 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2400 may include a processor 2402 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2406A-D via a host interface switch 2404. In at least one embodiment, the host interface switch 2404 is a fast PCI switch device that couples the processor 2402 to a fast PCI bus through which the processor 2402 can communicate with the GPGPUs 2406A-D. In at least one embodiment, the GPGPUs 2406A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2416. In at least one embodiment, the GPU-to-GPU links 2416 are connected to each of the GPGPUs 2406A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2416 enable direct communication between each of the GPGPUs 2406A-D without requiring communication on the host interface bus 2404 to which the processor 2402 is connected. In at least one embodiment, the host interface bus 2404 remains available for system memory access or communication with other instances of the multi-GPU computing system 2400, for example, via one or more network devices, through GPU-to-GPU traffic directed to the P2P GPU link 2416. While in at least one embodiment, the GPGPUs 2406A-D are connected to the processor 2402 via the host interface switch 2404, in at least one embodiment, the processor 2402 includes direct support for the P2P GPU link 2416 and can be directly connected to the GPGPUs 2406A-D.

[0365] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A 10B and / or 10B provide details regarding the inference and / or training logic 1015. In at least one embodiment, the inference and / or training logic 1015 may be used in a multi-GPU computing system 2400 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture or neural network usage described herein.

[0366] Figure 25This is a block diagram of a graphics processor 2500 according to at least one embodiment. In at least one embodiment, the graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In at least one embodiment, the ring interconnect 2502 couples the graphics processor 2500 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2500 is one of many processors integrated within a multi-core processing system.

[0367] In at least one embodiment, the graphics processor 2500 receives multiple batches of commands via a ring interconnect 2502. In at least one embodiment, the incoming commands are interpreted by a command stream converter 2503 in a pipeline front-end 2504. In at least one embodiment, the graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2580A-2580N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2503 provides commands to the geometry pipeline 2536. In at least one embodiment, for at least some media processing commands, the command stream converter 2503 provides commands to a video front-end 2534 coupled to a media engine 2537. In at least one embodiment, the media engine 2537 includes a video quality engine (VQE) 2530 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2533 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2536 and the media engine 2537 each generate execution threads for thread execution resources provided by at least one graphics core 2580.

[0368] In at least one embodiment, the graphics processor 2500 includes scalable thread execution resources characterized by graphics cores 2580A-2580N (which may be modular and are sometimes referred to as core slices), each graphics core having multiple sub-cores 2550A-2550N, 2560A-2560N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2500 may have any number of graphics cores 2580A. In at least one embodiment, the graphics processor 2500 includes graphics cores 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In at least one embodiment, the graphics processor 2500 is a low-power processor having a single sub-core (e.g., 2550A). In at least one embodiment, the graphics processor 2500 includes multiple graphics cores 2580A-2580N, each graphics core including a set of first sub-cores 2550A-2550N and a set of second sub-cores 2560A-2560N. In at least one embodiment, each of the first sub-cores 2550A-2550N includes at least a first set of execution units 2552A-2552N and media / texture samplers 2554A-2554N. In at least one embodiment, each of the second sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In at least one embodiment, each sub-core 2550A-2550N and 2560A-2560N shares a set of shared resources 2570A-2570N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0369] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in graphics processor 2500 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0370] Figure 26This is a block diagram illustrating the microarchitecture of a processor 2600 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2600 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2600 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled microprocessors employing MMX technology. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2600 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0371] In at least one embodiment, processor 2600 includes an ordered front end (“front end”) 2601 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2601 may include several units. In at least one embodiment, instruction prefetcher 2626 fetches instructions from memory and provides the instructions to instruction decoder 2628, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2628 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2628 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2630 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2634 for execution. In at least one embodiment, when the trace cache 2630 encounters complex instructions, the microcode ROM 2632 provides the microinstructions required to complete the operation.

[0372] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2628 may access the microcode ROM 2632 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2628. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2632. In at least one embodiment, the trace cache 2630 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2632 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2632 has completed the micro-operation ordering of the instructions, the machine front end 2601 may resume fetching micro-operations from the trace cache 2630.

[0373] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2603 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2603 includes, but is not limited to, an allocator / register renamer 2640, a memory microinstruction queue 2642, an integer / floating-point microinstruction queue 2644, a memory scheduler 2646, a fast scheduler 2602, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2604, and a simple floating-point scheduler (“simple FP scheduler”) 2606. In at least one embodiment, the fast scheduler 2602, the slow / general-purpose floating-point scheduler 2604, and the simple floating-point scheduler 2606 are also collectively referred to as “microinstruction schedulers 2602, 2604, 2606”. In at least one embodiment, the allocator / register renamer 2640 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2640 renames logical registers as entries in a register file. In at least one embodiment, the allocator / register renamer 2640 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2642 for memory operations and an integer / floating-point microinstruction queue 2644 for non-memory operations, preceding the memory scheduler 2646 and microinstruction schedulers 2602, 2604, and 2606. In at least one embodiment, the microinstruction schedulers 2602, 2604, and 2606 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2602 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2604 and the simple floating-point scheduler 2606 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2602, 2604, and 2606 arbitrate the scheduling port to schedule microinstructions for execution.

[0374] In at least one embodiment, execution block 2611 includes, but is not limited to, integer register file / tribute network 2608, floating-point register file / tribute network (“FP register file / tribute network”) 2610, address generation units (“AGU”) 2612 and 2614, fast arithmetic logic units (“fast ALU”) 2616 and 2618, slow arithmetic logic unit (“slow ALU”) 2620, floating-point ALU (“FP”) 2622, and floating-point move unit (“FP move”) 2624. In at least one embodiment, integer register file / tribute network 2608 and floating-point register file / bypass network 2610 are also referred to herein as “register files 2608, 2610”. In at least one embodiment, AGUs 2612 and 2614, fast ALUs 2616 and 2618, slow ALU 2620, floating-point ALU 2622, and floating-point movement unit 2624 are also referred to herein as "execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624". In at least one embodiment, execution block 2611 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0375] In at least one embodiment, register networks 2608, 2610 may be arranged between microinstruction schedulers 2602, 2604, 2606 and execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624. In at least one embodiment, integer register file / tribute network 2608 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2610 performs floating-point operations. In at least one embodiment, each of register networks 2608, 2610 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to a register file to a new dependent object. In at least one embodiment, register networks 2608, 2610 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2608 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2610 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0376] In at least one embodiment, execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624 can execute instructions. In at least one embodiment, register networks 2608 and 2610 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2600 may include, but is not limited to, any number of execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624, and combinations thereof. In at least one embodiment, floating-point ALU 2622 and floating-point movement unit 2624 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2622 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2616 and 2618. In at least one embodiment, fast ALUs 2616 and 2618 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2620, because slow ALU 2620 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUs 2612 and 2614. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can be implemented to support various data bit sizes, including hexadecimal, 32, 128, 266, etc. In at least one embodiment, the floating-point ALU 2622 and the floating-point moving unit 2624 can be implemented to support a range of operands with various bit widths, for example, they can be combined with SIMD and multimedia instructions to operate on 128-bit wide packaged data operands.

[0377] In at least one embodiment, microinstruction schedulers 2602, 2604, and 2606 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2600, processor 2600 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0378] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0379] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, some or all of the inference and / or training logic 1015 may be incorporated into execution block 2611 along with other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2611. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2611 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0380] Figure 27A deep learning application processor 2700 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2700 uses instructions, which, if executed by the deep learning application processor 2700, cause the deep learning application processor 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2700 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2700 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2700 includes, but is not limited to, a processing cluster 2710(1)-2710(12), an inter-chip link (“ICL”) 2720(1)-2720(12), an inter-chip controller (“ICC”) 2730(1)-2730(2), a second-generation high-bandwidth memory (“HBM2”) 2740(1)-2740(4), a memory controller (“Mem Ctrlr”) 2742(1)-2742(4), a high-bandwidth memory physical layer (“HBM PHY”) 2744(1)-2744(4), a management controller central processing unit (“management controller CPU”) 2750, a serial peripheral interface, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2760, a peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2770, and a sixteen-channel peripheral component interconnect fast port (“PCI Express”). x 16”)2780.

[0381] In at least one embodiment, processing cluster 2710 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2710 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2700 can include any number and type of processing cluster 2700. In at least one embodiment, inter-chip link 2720 is bidirectional. In at least one embodiment, inter-chip link 2720 and inter-chip controller 2730 enable multiple deep learning application processors 2700 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2700 can include any number (including zero) and type of ICL 2720 and ICC 2730.

[0382] In at least one embodiment, the HBM2 2740 provides a total of 32GB of memory. In at least one embodiment, the HBM2 2740(i) is associated with both the memory controller 2742(i) and the HBM PHY 2744(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2740s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2742 and HBM PHY 2744. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO 3360, PCIe controller 2760 and DMA2770 and / or PCIe2780 to implement any number and type of communication standards in any technically feasible manner.

[0383] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2700. In at least one embodiment, the deep learning application processor 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2700. In at least one embodiment, the processor 2700 may be used to perform one or more neural network use cases described herein.

[0384] Figure 28This is a block diagram of a neuromorphic processor 2800 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2800 may receive one or more inputs from a source external to the neuromorphic processor 2800. In at least one embodiment, these inputs may be transmitted to one or more neurons 2802 within the neuromorphic processor 2800. In at least one embodiment, the neurons 2802 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, thousands upon thousands of instances of neurons 2802, but any suitable number of neurons 2802 may be used. In at least one embodiment, each instance of a neuron 2802 may include a neuron input 2804 and a neuron output 2806. In at least one embodiment, a neuron 2802 may generate an output that can be transmitted to the inputs of other instances of the neuron 2802. In at least one embodiment, the neuron input 2804 and the neuron output 2806 may be interconnected via synapses 2808.

[0385] In at least one embodiment, neuron 2802 and synapse 2808 may be interconnected, causing neuromorphic processor 2800 to operate to process or analyze information received by neuromorphic processor 2800. In at least one embodiment, neuron 2802 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2804 exceeds a threshold. In at least one embodiment, neuron 2802 may sum or integrate the signal received at neuron input 2804. For example, in at least one embodiment, neuron 2802 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as “membrane potential”) exceeds a threshold, neuron 2802 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2804 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2804 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2802 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2802 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2806 when the result of applying the transfer function to neuron input 2804 exceeds a threshold. In at least one embodiment, once neuron 2802 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2802 may resume normal operation after a suitable period of time (or recovery period).

[0386] In at least one embodiment, neurons 2802 can be interconnected via synapses 2808. In at least one embodiment, synapses 2808 can be operated to transmit signals from the output of a first neuron 2802 to the input of a second neuron 2802. In at least one embodiment, neurons 2802 can transmit information on more than one instance of synapses 2808. In at least one embodiment, one or more instances of neuron outputs 2806 can be connected via instances of synapses 2808 to instances of neuron inputs 2804 in the same neuron 2802. In at least one embodiment, an instance of neuron 2802 that produces an output to be transmitted on the instance of synapse 2808 can be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2802 that receives input transmitted via an instance of synapse 2808 can be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2808, since an instance of neuron 2802 can receive input from one or more instances of synapse 2808 and can also transmit output through one or more instances of synapse 2808, a single instance of neuron 2802 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0387] In at least one embodiment, neurons 2802 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2802 may have a neuron output 2806, which may fan out to one or more neuron inputs 2804 via one or more synapses 2808. In at least one embodiment, the neuron output 2806 of neuron 2802 in the first layer 2810 may be connected to the neuron input 2804 of neuron 2802 in the second layer 2812. In at least one embodiment, layer 2810 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2802 in an instance of the first layer 2810 may fan out to each instance of neuron 2802 in the second layer 2812. In at least one embodiment, the first layer 2810 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2802 in an instance of the second layer 2812 fan out to fewer than all instances of neuron 2802 in the third layer 2814. In at least one embodiment, the second layer 2812 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2802 in the second layer 2812 may fan out to neurons 2802 in multiple other layers, including neurons 2802 fan out to the second layer 2812. In at least one embodiment, the second layer 2812 may be referred to as a “recurrent layer.” In at least one embodiment, the neuromorphic processor 2800 may be any suitable combination of recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0388] In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2808 to neurons 2802. In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2802 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2808 may be connected to neurons 2802 using interconnect structures (such as on-chip networks) or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0389] Figure 29A processing system according to at least one embodiment is illustrated. In at least one embodiment, system 2900 includes one or more processors 2902 and one or more graphics processors 2908, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2902 or processor cores 2907. In at least one embodiment, system 2900 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0390] In at least one embodiment, system 2900 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2900 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2900 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2900 is a television or set-top box device having one or more processors 2902 and a graphical interface generated by one or more graphics processors 2908.

[0391] In at least one embodiment, each of the one or more processors 2902 includes one or more processor cores 2907 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2907 is configured to process a specific instruction sequence 2909. In at least one embodiment, the instruction sequence 2909 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2907 may process a different instruction sequence 2909, which may include instructions that facilitate emulating other instruction sequences. In at least one embodiment, the processor core 2907 may also include other processing devices, such as a digital signal processor (DSP).

[0392] In at least one embodiment, processor 2902 includes cache memory 2904. In at least one embodiment, processor 2902 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2902. In at least one embodiment, processor 2902 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2907 using known cache coherence techniques. In at least one embodiment, processor 2902 further includes a register file 2906, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2906 may include general-purpose registers or other registers.

[0393] In at least one embodiment, one or more processors 2902 are coupled to one or more interface buses 2910 to transmit communication signals, such as address, data, or control signals, between the processors 2902 and other components in the system 2900. In at least one embodiment, the interface bus 2910 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2910 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2902 includes an integrated memory controller 2916 and a platform controller hub 2930. In at least one embodiment, the memory controller 2916 facilitates communication between memory devices and other components of the processing system 2900, while the platform controller hub (PCH) 2930 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0394] In at least one embodiment, memory device 2920 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2920 may be used as system memory of processing system 2900 to store data 2922 and instructions 2921 for use when one or more processors 2902 execute an application or process. In at least one embodiment, memory controller 2916 is also coupled to an optional external graphics processor 2912, which may communicate with one or more graphics processors 2908 of processor 2902 to perform graphics and media operations. In at least one embodiment, display device 2911 may be connected to processor 2902. In at least one embodiment, display device 2911 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2911 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0395] In at least one embodiment, the platform controller hub 2930 enables peripheral devices to connect to the storage device 2920 and the processor 2902 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2946, a network controller 2934, a firmware interface 2928, a wireless transceiver 2926, a touch sensor 2925, and a data storage device 2924 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2924 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2925 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2926 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2928 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2934 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2910. In at least one embodiment, audio controller 2946 is a multi-channel high-definition audio contro...

Claims

1. A method comprising: An image is obtained, the image including objects depicted in the image, wherein the image has a first bounding box of the objects; The image regions are labeled using a first neural network to distinguish between regions depicting parts of the object and regions depicting parts of the image that are different from the object, wherein the labeling is a segmentation of the image generated by a neural network trained to perform segmentation; A second neural network is trained to generate a pre-labeled tool, based at least in part on the executed labels and the first bounding box. Perform a set of transformations on the image to generate a set of transformed images; The pre-labeling tool performs labeling on the set of transformed images to generate more refined mask annotations of the objects; The third neural network is trained, at least in part, based on the generated, more refined mask annotations; and The object is identified at least in part based on the trained third neural network.

2. The method of claim 1, wherein performing the set of transformations further includes rotating the image by a set of values.

3. The method of claim 1, wherein the more refined mask annotation includes additional data and / or metadata identifying pixels in the set of transformed images that depict a specific object and / or object category.

4. The method of claim 1, wherein the method further comprises training the third neural network at least in part based on the set of transformed images and the more refined mask annotations.

5. The method of claim 4, wherein the third neural network is trained to perform detection of the object.

6. The method according to claim 1, wherein: The set of transformations includes rotating the image to produce a rotated image; as well as The more refined mask annotation corresponds to the second bounding box of the object, which has an edge parallel to the first bounding box of the object and has an area smaller than the minimum perimeter of the box that will completely surround the first bounding box after the rotation is applied to the first bounding box.

7. The method of claim 1, wherein performing the set of transformations further includes modifying the scale value of the image.

8. The method of claim 1, wherein performing the set of transformations further comprises modifying the brightness values ​​of a set of images in the second dataset.

9. The method of claim 1, wherein performing the set of transformations further comprises modifying the contrast values ​​of a set of images in the second dataset.

10. The method of claim 9, wherein at least one of the first neural network, the second neural network, and the third neural network comprises a mask-based convolutional neural network.

11. The method of claim 1, further comprising associating the more refined mask annotation with the labels of the objects in the training dataset.

12. The method of claim 1, wherein the image further comprises frames from a set of frames, the set of frames including video.

13. The method of claim 6, wherein the second bounding box comprises a rectangular region surrounding the object.

14. A system comprising: One or more processors; as well as A memory that stores instructions, as a result of the execution of those instructions by the one or more processors, enables the system to: Obtain an image of the depicted object, the image having a first bounding box of the object; The first model is used to segment the image by segmenting the target pixel and other pixel regions, so as to distinguish the pixels of the object from other pixels; The neural network is trained to generate pre-labeled tools, based at least in part on the segmentation and the first bounding box. The pre-labeling tool performs segmentation to determine a more refined mask annotation of the objects in a set of modified versions of the image; The second model is trained at least in part based on the segmentation performed by the pre-labeling tool; The object is identified at least in part based on the trained second model; as well as The object is associated with a boundary in the training dataset of the first model.

15. The system of claim 14, wherein the first model further comprises a convolutional neural network trained at least in part on a selected dataset.

16. The system of claim 14, wherein the memory further comprises instructions that, as a result of execution of the instructions by the one or more processors, cause the system to use the training dataset to train the second model to perform the detection of the object.

17. The system of claim 16, wherein the second model comprises a convolutional neural network.

18. The system of claim 14, wherein the set of modified images comprises images generated at least in part based on images obtained by rotation.

19. A machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to at least: A pre-labeling tool is generated by training a second neural network, at least in part, based on labels associated with objects in a first set of images from a first dataset and images within a first set of mask annotations based on a convolutional neural network (CNN). One set of bounding boxes is included in the first dataset, and the labels are generated based on the segmentation of the image, which is generated by the CNN trained to perform segmentation; The second set of images is generated by modifying the first set of images; The pre-labeling tool is used to label the second set of images; A second set of mask annotations is generated for the second set of images, at least in part based on the markings performed on the second set of images by the pre-labeling tool; The third neural network is trained at least in part based on the second set of mask annotations; as well as The object is identified at least in part based on the third neural network.

20. The machine-readable medium of claim 19, wherein the first set of mask annotations is generated by a convolutional neural network based at least in part on the first set of images.

21. The machine-readable medium of claim 19, wherein the set of instructions causing the one or more processors to modify the first set of images to generate the second set of images further includes instructions that, if executed by the one or more processors, cause the one or more processors to rotate the images in the first set of images about a rotation axis by a different amount.

22. The machine-readable medium of claim 19, wherein the set of instructions that causes the one or more processors to modify the first set of images to generate the second set of images further includes instructions that, if executed by the one or more processors, cause the one or more processors to modify color values ​​associated with images in the first set of images.

23. The machine-readable medium of claim 19, wherein the set of instructions causing the one or more processors to modify the first set of images to generate the second set of images further includes instructions that, if executed by the one or more processors, cause the one or more processors to modify brightness values ​​associated with images in the first set of images.

24. The machine-readable medium of claim 19, wherein the set of instructions that causes the one or more processors to modify the first set of images to generate the second set of images further includes instructions that, if executed by the one or more processors, cause the one or more processors to modify the scaling values ​​associated with the images in the first set of images.

25. A method comprising: A neural network is used to obtain image segmentation, wherein the image also includes a first boundary of an object; The pre-labeling tool is trained at least in part based on the segmentation and the first boundary; Perform the transformation on the image to obtain the transformed image; The pre-labeling tool performs segmentation on the transformed image to generate more refined mask annotations of the objects depicted in the transformed image; and The second neural network is trained to recognize the object, at least in part, based on the more refined mask annotations.

26. The method of claim 25, wherein the boundary of the object depicted in the transformed image includes a bounding box.

27. The method of claim 25, wherein the method further comprises training the second neural network at least in part based on the more refined mask annotations.

28. The method according to claim 25, wherein, The boundary of the object corresponding to the more refined mask annotation is different from another boundary generated by applying a transformation to the first boundary.

Images