Signal buffer circuit

Abstract

The present disclosure relates to a signal buffer circuit. An apparatus having a signal line in a semiconductor device is described. An example apparatus includes one or more power supply voltage lines in a first conductive layer, a plurality of transistors and a signal line in a second conductive layer. Each transistor of the plurality of transistors includes an active region disposed in a substrate and a gate electrode over the active region. The signal line in the second conductive line is under the first conductive layer and over the active regions of the plurality of transistors. The signal line is coupled to the gate electrodes of the plurality of transistors. The signal line has a resistance higher than a resistance of the power supply voltage lines.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. Background Technology

[0002] Reduced chip size, high data reliability, lower power consumption, and efficient power usage are the characteristics required for semiconductor memories. To reduce chip size while enhancing current drive capability, circuits in conventional semiconductor devices contain multiple transistors coupled in parallel with each other.

[0003] In semiconductor memory devices, control signals can be distributed across multiple circuits. For example, a data transfer circuit between a data input / output (I / O) circuit and a read / write amplifier circuit can receive timing control signals to control the input and output timing of data registers from global control signal lines. These timing control signals are provided to logic circuits and buffers in the data transfer circuit to control the data input / output timing from local control signal lines. Directly providing the received control signals to the logic circuits and buffers in the data transfer circuit can introduce undesirable loads on the global control signal lines. To prevent undesirable loads, buffers can be provided for each block (e.g., each data queue DQx). The buffers receive control signals from the global control signal lines and provide them to the local control signal lines. However, due to parasitic capacitances between local control signal lines in the metal layer, power consumption on the local control signal lines can be very high. Summary of the Invention

[0004] According to one aspect of this disclosure, an apparatus is provided. The apparatus includes: a transistor configured to transmit a signal, the transistor including: an active region comprising a source region and a drain region disposed in a substrate; and a gate electrode in a gate wiring layer above the substrate; a power line and a first signal line in a first conductive layer adjacent to and above the gate wiring layer, the power line coupled to the source region and the first signal line coupled to the drain region; and a second signal line in a second conductive layer adjacent to and above the first conductive layer, the second signal line coupled to the gate electrode, wherein the first signal line and the second signal line together comprise a conductive material.

[0005] According to another aspect of this disclosure, an apparatus is provided. The apparatus includes: a signal buffer circuit configured to receive a signal from a control signal line in a first conductive layer and further configured to provide the signal to an internal control signal line in a second conductive layer with a delay; and a plurality of control circuits coupled to the internal control signal line and configured to receive the signal from the internal control signal line, wherein the second conductive layer is different from the first conductive layer.

[0006] According to another aspect of this disclosure, an apparatus is provided. The apparatus includes: an input signal line extending in a first conductive layer and in a first direction and configured to provide a control signal; an output signal line extending in a second conductive layer and in a second direction perpendicular to the first direction and configured to provide an inverting control signal; and a transistor including: a gate electrode included in a portion extending in the first direction, the portion configured to receive the control signal; a contact plug on a portion of an active region; and a conductive segment extending in the first direction in a third conductive layer, the conductive segment being coupled to the contact plug and the output signal line, wherein the first conductive layer is between the second conductive layer and the third conductive layer, and wherein the distance from the first conductive layer to the second conductive layer is longer than the distance from the first conductive layer to the third conductive layer. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2A This is a schematic diagram of a data transmission circuit according to an embodiment of the present disclosure.

[0009] Figure 2B This is a schematic diagram of a portion of a block transmission circuit according to an embodiment of the present disclosure.

[0010] Figure 2C This is a schematic diagram of a control circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is a circuit diagram of an inverter in a control circuit according to an embodiment of the present disclosure.

[0012] Figure 4A and 4B This is a diagram showing the layout of a portion of an inverter according to an embodiment of the present disclosure.

[0013] Figures 5A to 5C This is a vertical cross-sectional view of the structure of an inverter according to an embodiment of the present disclosure. Detailed Implementation

[0014] The various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The detailed description below relates to the accompanying drawings, which illustrate specific aspects and embodiments in which this disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0015] The following description is based on references. Figures 1 to 5C The embodiments of the semiconductor memory device 100 and the method of forming the same are shown. The dimensions and aspect ratios of each part in each figure may not necessarily be consistent with the dimensions and aspect ratios of the actual semiconductor device.

[0016] Figure 1 This is a schematic block diagram of a chip 101 in a semiconductor memory device 100 according to an embodiment of the present disclosure. For example, the semiconductor memory device 100 is a device that may include multiple chips, including chip 101. For example, chip 101 may include a clock input circuit 105, an internal clock generator 107, a command and address input circuit 110, an address decoder 120, a command decoder 125, multiple row decoders 130, a memory cell array 150 including a sense amplifier 151 and a transmission gate 152, multiple column decoders 140, multiple read / write amplifiers 160, a data transmission circuit 165, an input / output (IO) circuit 170, and a voltage generator circuit 190. The semiconductor memory device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus, clock terminals CK and / or CK, a data terminal DQ, a data strobe terminal DQS, and a data mask terminal DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0017] The memory cell array 150 includes multiple memory banks (e.g., memory banks 0 to 7), each memory bank including multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of the word lines WL for each memory bank is performed by the corresponding row decoder 130, and the selection of the bit lines BL is performed by the corresponding column decoder 140. Multiple sense amplifiers SAMP 151 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line (e.g., LIOT / B), and the corresponding local I / O line is further coupled to a corresponding one of at least two main I / O line pairs (e.g., MIOT / B) via a transmission gate TG 152 acting as a switch.

[0018] Command and address input circuit 110 can receive address signals and memory address signals from the outside via command / address bus (C / A) at the command / address terminal and transmit the address signals and memory address signals to address decoder 120. Address decoder 120 can decode the address signals received from command and address input circuit 110 and provide address signal ADD. Address signal ADD may include row address signals to row decoder 130 and column address signals to column decoder 140. Address decoder 120 can also receive memory address signals and provide the memory address signals to row decoder 130 and column decoder 140.

[0019] Command and address input circuitry 110 may, for example, receive command signals from an external source via a command / address bus at a command / address terminal and provide the command signals to command decoder 125. Command decoder 125 may decode the command signals and generate various internal command signals. For example, internal command signals may include row command signals for selecting word lines and column command signals for selecting bit lines, such as read or write commands.

[0020] Therefore, when an activation command is issued and the row address is supplied with the activation command in a timely manner, and a read command is issued and the column address is supplied with the read command in a timely manner, read data is read from the memory cell in the memory cell array 150, identified by the row address and column address. The read / write amplifier 160 can receive the read data and provide it to the data transmission circuit 165. The data transmission circuit 165 can receive the read data from the read / write amplifier 160 and, in response to a control signal controlling the timing of receiving the read data from the read / write amplifier 160 and further in response to a control signal controlling the timing of providing the read data to the IO circuit, provide the read data to the IO circuit 170. The IO circuit 170 can provide the read data from the data transmission circuit 165, along with the data strobe signal at the data strobe terminal DQ and the data mask signal at the data mask terminal DM, to the outside via the data terminal DQ. Similarly, when an activation command is issued and the row address is supplied with the activation command in a timely manner, and a write command is issued and the column address is supplied with the write command in a timely manner, the I / O circuit 170 can receive write data, a data strobe signal at DQS, and a data mask signal at DM at the data terminals DQ, DQS, and DM, and provide the write data to the data transmission circuit 165. The data transmission circuit 165 can receive the write data from the I / O circuit 170 and, in response to a control signal controlling the timing of receiving the write data from the I / O circuit 170, and further in response to a control signal controlling the timing of providing the write data to the read / write amplifier 160 that can provide the write data to the cell array 150, provides the write data to the read / write amplifier 160. Therefore, the write data can be written to the memory cell identified by the row address and column address.

[0021] Turning to the explanation of the external terminals included in the semiconductor device 100, clock terminals CK and CKB can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controllable internal clock signal LCLK based on the received internal clock signal ICLK. For example, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controllable internal clock signal LCLK to IO circuit 170. IO circuit 170 can use the phase-controllable internal clock signal LCLK as a timing signal for determining the output timing of read data.

[0022] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VKK, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. The internal voltage VKK can be used in the line decoder 130, the internal voltage VARY can be used in the sense amplifier 151 included in the memory cell array 150, and the internal voltage VPERI can be used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. I / O circuit 170 can receive power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ can be the same voltages as the power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 170.

[0023] The structure of the signal buffer circuit in the semiconductor memory device 100 according to an embodiment of the present disclosure will be referred to... Figures 2A to 5C The following description will be provided. Some embodiments of the signal buffer circuitry in the data transmission circuitry 165 will be described in detail below. However, the signal buffer circuitry may be included in any block of the semiconductor memory device 100 that can provide signals to multiple circuits. In some embodiments, the command decoder 125 may include signal buffer circuitry that can provide control signals, such as enable signals or reset signals, to the row decoder 130 and / or the column decoder 140.

[0024] Figure 2AThis is a schematic diagram of a data transmission circuit 165 according to an embodiment of the present disclosure. The data transmission circuit 165 may include block transmission circuitry 20 provided for corresponding blocks Block-0 to Block-N. In some embodiments, each block transmission circuitry 20 may be provided for each data queue (DQ). In some embodiments, each transmission circuitry 20 may include logic and buffer circuitry 24 for transmitting multiple bits between a read / write amplifier 160 and an I / O circuit 170. Each of the logic and buffer circuitry 24 includes logic circuitry and buffer circuitry, and can provide corresponding bits among the multiple bits provided in parallel between the read / write amplifier 160 and the I / O circuit 170.

[0025] Multiple bits can include both even and odd bits. The positions of the bits can be arranged from the least significant bit (LSB) to the most significant bit (MSB). Each transmission circuit 20 can include a signal buffer circuit 22E and a signal buffer circuit 22O. The signal buffer circuit 22E in each transmission circuit 20 can be coupled to an even number of control signal lines 21E. The even number of control signal lines 21E can provide even number of control signals to the signal buffer circuits 22E of the block transmission circuits 20 from Block-0 to Block-N. The signal buffer circuit 22E in each transmission circuit 20 can be coupled to an even number of internal control signal lines 23E. The even number of internal control signal lines 23E are coupled to the even number of logic and buffer circuits 24 that can receive and provide even number of bits. The signal buffer circuit 22E in each transmission circuit 20 can provide the received even number of control signals to the even number of logic and buffer circuits 24 via the even number of internal control signal lines 23E.

[0026] Similarly, the signal buffer circuit 22O in each transmission circuit 20 can be coupled to the odd-numbered control signal line 21O. The odd-numbered control signal line 21O can provide odd-numbered control signals to the signal buffer circuits 22O of the block transmission circuits 20 from Block-0 to Block-N. The signal buffer circuit 22O in each transmission circuit 20 can be coupled to the odd-numbered internal control signal line 23O. The odd-numbered internal control signal line 23O is coupled to the odd-numbered bits in the logic and buffer circuit 24 that can receive and provide odd-numbered bits. The signal buffer circuit 22O can provide the received odd-numbered control signals to the odd-numbered bits in the logic and buffer circuit 24 via the odd-numbered internal control signal line 23O. The even-numbered control signals and odd-numbered control signals can respectively include, for example, read input timing signals, read output timing signals, write input timing signals, write output timing signals, and / or reset signals.

[0027] During a read operation, each of the logic and buffer circuits 24 may, in response to a read input control signal, receive each bit of a plurality of read data from the read / write amplifier 160 in an input timing sequence. The read input control signal indicates the input timing for receiving each bit of the plurality of read data. Each of the logic and buffer circuits 24 may, in response to a read output control signal, provide the corresponding received bit of the plurality of read data to the I / O circuit 170 in an output timing sequence. The read output control signal indicates the output timing for providing each bit of the plurality of read data. During a write operation, each of the logic and buffer circuits 24 may, in response to a write input control signal, receive each bit of a plurality of write data from the I / O circuit 170. The write input control signal indicates the input timing for receiving each bit of the plurality of write data. Each of the logic and buffer circuits 24 may, in response to a write output control signal, provide the corresponding received bit of the plurality of write data to the read / write amplifier 160 in an output timing sequence. The write output control signal indicates the output timing for providing each bit of the plurality of write data.

[0028] Figure 2B This is a schematic diagram of portion 20' of a block transfer circuit according to an embodiment of the present disclosure. In some embodiments, portion 20' may be... Figure 2A A portion of the block transmission circuit 20. Portion 20' may include signal buffer circuitry 22 and control circuitry 241. In some embodiments, portion 20' may include portions of circuitry and lines associated with even-numbered or odd-numbered bits.

[0029] In some embodiments, Figure 2A Each of the signal buffer circuits 22E and 22O may include a signal buffer circuit 22. In some embodiments, the signal buffer circuit 22 may include an inverter. The signal buffer circuit 22 may receive a control signal from a control signal line 21. In some embodiments, the control signal line 21 may be an even number of control signal lines 21E and / or an odd number of control signal lines 21O. The control signal line 21 may contain a conductive material. For example, the conductive material may have low resistance, such as copper (Cu) or aluminum (Al). In some embodiments, the control signal line 21 may be disposed in a second metal layer (metal 2). In response to a control signal from the control signal line 21, the signal buffer circuit 22 may provide a control signal to an internal control signal line 23 with a delay. Figure 2AEach of the even-numbered internal control signal lines 23E and the odd-numbered internal control signal lines 23O may include an internal control signal line 23. The internal control signal line 23 may contain a conductive material. In some embodiments, the conductive material contained in the internal control signal line 23 may have a higher resistance than the conductive material of the control signal line 21. The material contained in the internal control signal line 23 may also have hardness, heat resistance, corrosion resistance, and / or wear resistance. For example, the material may contain at least one of tungsten (W) or titanium nitride (TiN). In some embodiments, the internal control signal line 23 may be disposed on a substrate on which the second metal layer and the block transmission circuit 20 are disposed (e.g., Figure 2C In a local interconnect layer between semiconductor substrates 251. In some embodiments, the local interconnect layer including the internal control signal line 23 may have a thickness (e.g., height) smaller than the thickness of the second metal layer including the control signal line 21.

[0030] Control circuitry 241 may be coupled to internal control signal line 23. Control circuitry 241 may receive control signals from internal control signal line 23. In some embodiments, each of the control circuits 241 may be included in... Figure 2A Each of the logic and buffer circuits 24 in the circuit.

[0031] Control circuit 241 can receive control signals from internal control signal line 23. Control circuit 241 can also receive data signals at input node Data In 244. In response to an inverted control signal, control circuit 241 can provide an inverted data signal to output node Data Out 245. In some embodiments, input node Data In 244 and output node Data Out 245 can be disposed in a conductive layer. The conductive layer containing input node Data In 244 and output node Data Out 245 can contain a conductive material. The conductive material can have relatively low resistance, such as (for example) copper (Cu) or aluminum (Al). In some embodiments, the conductive layer containing input node Data In 244 and output node Data Out 245 can be formed as a first metal layer (metal 1) below a second metal layer (metal 2) containing control signal 21. The second metal layer (metal 2) can have a thickness greater than the thickness of the first metal layer (metal 1). The first metal layer (metal 1) can be disposed between the second metal layer (metal 2) and a local interconnect layer containing the internal control signal line.

[0032] As described above, the signal buffer circuit 22 can receive control signals from the block transfer circuit 20 provided on the control signal line 21 in the conductive layer (e.g., metal layer 2). The signal buffer circuit 22 can further provide the control signals, with a delay, to the control circuit 241 on the internal control signal line 23 in the local interconnect layer between the conductive layer and the substrate of the control signal line 21. The control circuit 241 can receive the control signals on the internal control signal line 23, and in response to the control signals, can receive data signals at the input node Data In 244 and provide data signals at the output node Data Out 245.

[0033] Figure 2C This is a schematic diagram of control circuits 241A and 241B according to embodiments of the present disclosure. In the following description, the upper part indicates when Figure 2C The semiconductor substrate 251 is located above the bottom. Control circuits 241A and 241B are coupled to internal control signal line 23. Control circuits 241A and 241B receive control signals from internal control signal line 23. Control circuit 241A may include inverters 242A and 243A and an internal node Int 246A coupled to inverters 242A and 243A. Inverter 241A receives control signals from internal control signal line 23. In response to the control signal from internal control signal line 23, inverter 242A inverts the control signal and provides the inverted control signal to inverter 243A at internal node Int 246A. Similarly, control circuit 241B may include inverters 242B and 243B and an internal node Int 246B coupled to inverters 242B and 243B. The inverter 242B of the control circuit 241B can receive a control signal from the internal control signal line 23. In response to the control signal from the internal control signal line 23, the inverter 242B can invert the control signal and provide the inverted control signal to the inverter 243B at the internal node Int 246B.

[0034] Inverters 243A and 243B can receive inversion control signals from internal nodes Int 246A and 246B, respectively. Inverter 243A can receive the data A signal at input node Data A In 244A. In response to the inversion control signal, inverter 243A can provide the inverted data A signal to output node Data A Out 245A. Inverter 243B can receive the data B signal at input node Data B In 244B. In response to the inversion control signal, inverter 243B can provide the inverted data B signal to output node Data B Out 245B.

[0035] In some embodiments, input nodes Data A In 244A and Data B In 244B, output nodes Data A Out 245A and Data B Out 245B, and internal nodes Int 246A and 246B may be disposed in a conductive layer that may contain a conductive material. The conductive material may have low resistance, such as (for example) copper (Cu) or aluminum (Al). In some embodiments, the conductive layer containing input nodes Data A In 244A and Data B In 244B, output nodes Data A Out 245A and Data B Out 245B, and internal nodes Int 246A and 246B may be formed as a first metal layer (metal 1) beneath a second metal layer (metal 2) containing control signal lines 21.

[0036] Each of inverters 242A, 243A, 242B, and 243B may include a transistor. For example, inverter 242A may include a transistor comprising active regions 250AP and 250AN. Inverter 242B may include active regions 250BN and 240BP. Active regions 250AP, 250AN, 250BN, and 250BP may be disposed in substrate 251. Active region 250AP may receive a power supply voltage (e.g., VDD) from power supply voltage line 253A via conductive segments and contact plugs. Active regions 250AN and 250BN may receive a power supply voltage (e.g., VSS) from another power supply voltage line 252 via conductive segments and contact plugs. Active region 250BP may receive a power supply voltage (e.g., VDD) from another power supply voltage line 253B via conductive segments and contact plugs. Power supply voltage lines 253A, 253B, and 252 may be disposed in a conductive layer comprising a conductive material. In some embodiments, power supply voltage lines 253A, 253B, and 252 may be disposed in the same conductive layer as input nodes Data A In 244A and Data B In 244B, output nodes Data A Out 245A and Data B Out 245B, and internal nodes Int 246A and 246B. In some embodiments, the conductive layer comprising power supply voltage lines 253A, 253B, and 252 may be formed as a first metal layer (metal 1) beneath a second metal layer (metal 2) comprising control signal line 21.

[0037] Internal control line 23 can be coupled to Figure 2BThe signal buffer circuit 22. Internal control line 23 can receive control signals from the signal buffer circuit 22. Internal control line 23 can provide control signals to inverters 242A and 242B of control circuits 241A and 241B. Internal control signal line 23 can be a local interconnect in a local interconnect layer above substrate 251 and below a conductive layer containing input nodes Data A In 244A and Data B In 244B, output nodes Data A Out 245A and Data B Out 245B, and power supply voltage lines 253A, 253B, and 252. For example, internal control line 23 can intersect with the region between internal node 246A and active region 250AP and the region between internal node 246B and active region 250AN. In some embodiments, the thickness of the local interconnect layer containing the internal control signal line 23 may be smaller than that of the conductive layer containing the input nodes Data A In 244A and Data B In 244B, the output nodes Data A Out 245A and Data B Out 245B, and the power supply voltage lines 253A, 253B, and 252. The resistance of the local interconnect layer containing the internal control signal line 23 may be greater than that of the conductive layer containing the input nodes Data A In 244A and Data B In 244B, the output nodes Data A Out 245A and Data B Out 245B, and the power supply voltage lines 253A, 253B, and 252.

[0038] Figure 3 This is a circuit diagram of an inverter 30 according to an embodiment of the present disclosure. In some embodiments, the inverter 30 may be... Figure 2B inverter 242 or Figure 2CEach of inverters 242A and 242B. Inverter 30 may include a first-type transistor 31P and a second-type transistor 31N having a polarity different from that of transistor 31P. The first-type transistor 31P may be a p-channel field-effect transistor, and the second-type transistor 31N may be an n-channel field-effect transistor. Transistor 31P may include a gate 32BP, and transistor 31N may include a gate 32BN. Transistors 31P and 31N may be coupled to an input node In 38 and an output node Out 39. Terminal 36P (typically the second terminal) of transistor 31P may be coupled to a power supply voltage line (e.g., VDD), and terminal 36N (typically the source terminal) of transistor 31N may be coupled to another power supply voltage line (e.g., VSS). The gates 32BP and 32BN of transistors 31P and 31N may receive an input signal In from input node 38. One of transistors 31P and 31N can provide an output signal to output node Out 39 through terminal 39P (typically the drain terminal) of transistor 31P or terminal 39N (typically the drain terminal) of transistor 31N.

[0039] Figure 4A and 4B These are diagrams illustrating the layout of portions 4A and 4B of the inverter 4 according to an embodiment of the present disclosure. Figures 5A to 5C This is a vertical cross-sectional view illustrating a schematic structure of an inverter 4 according to an embodiment of the present disclosure. In some embodiments, the inverter 4 may be... Figure 2C The inverter 242A. A portion 4A of the inverter 4 may include active regions 40AP and 40AN disposed as portions of a substrate 40. In some embodiments, the active regions 40AP and 40AN and the substrate 40 may be... Figure 2C The active regions 250AP and 250AN and the substrate 251. A portion 4A of the inverter 4 may include an isolation region 45 (e.g., shallow trench isolation (STI)) surrounding the active regions 40AP and 40AN. Figure 4A The cross sections A-A', B-B', and C-C' shown are perpendicular to the surface of the substrate 40. Cross sections A-A', B-B', and C-C' may be parallel to each other, and cross section B-B' may lie between cross sections A-A' and C-C'. In some embodiments, the inverter 4 may have sections respectively along... Figure 5A , 5B And the structures of cross sections A-A', B-B' and C-C' shown in 5C.

[0040] Inverter 4 may include gate electrodes 44GP and 44GN disposed in a gate wiring layer. Gate electrode 44GP may be L-shaped and may include a portion 44GPA disposed above active region 40AP and extending in direction 401, and may further include another portion 44GPB disposed above isolation region 45 and extending in another direction 402 perpendicular to the first direction 401. Gate electrode 44GN may be L-shaped and may include a portion 44GNA disposed above active region 40AN and extending in direction 401, and may further include another portion 44GNB disposed above isolation region 45 and extending in a second direction 402 perpendicular to direction 401. Portions 44GPA and 44GNA of gate electrodes 44GP and 44GN may be disposed along an axis in direction 401. Contact plug 47GP may be disposed on the other portion 44GPB of gate electrode 44GP above isolation region 45. Contact plug 47GN may be disposed on another portion 44GNB of the gate electrode 44GN above the isolation region 45. In some embodiments, contact plugs 47GP and 47GN may respectively comprise or be coupled to an input node In 38. Figure 3 The gates are 32BP and 32BN.

[0041] Each of the active regions 40AP and 40AN may include a diffusion region (e.g., a source region and / or a drain region) and a channel region (not shown) between the diffusion regions located below the gate electrodes 44GP and 44GN, respectively. In some embodiments, the active region 40AP and the gate 44GP may be included in... Figure 3 In transistor 31P. One or more contact plugs 47SP may be disposed on the diffusion region (e.g., source region) of active region 40AP. In some embodiments, contact plugs 47SP may include or be coupled to a power supply voltage line (e.g., VDD). Figure 3 Terminal 36P is located in the active region 40AP. One or more contact plugs 47DP may be disposed on the diffusion region (e.g., the drain region) of the active region 40AP. In some embodiments, the contact plug 47DP may include or be coupled to the output node Out 39. Figure 3 Terminal 39P is included. In some embodiments, contact plugs 47SP, 47DP, and 47SN may have a rectangular shape extending in direction 401. Similarly, the active region 40AN and the gate 44GN may be included in... Figure 3 In transistor 31N. One or more contact plugs 47SN may be disposed on the diffusion region (e.g., source region) of active region 40AN. In some embodiments, contact plugs 47SN may include or be coupled to a voltage line coupled to another power supply voltage line (e.g., VSS). Figure 3Terminal 36N. One or more contact plugs 47DN may be disposed on the diffusion region (e.g., the drain region) of the active region 40AN. In some embodiments, the contact plug 47DN may include or be coupled to the output node Out 39. Figure 3 Terminal 39N. In some embodiments, contact plugs 47SP, 47GP, 47GN and 47SN may be arranged along an axis in direction 401. In some embodiments, contact plugs 47DP and 47DN may be arranged along an axis in direction 401.

[0042] A portion 4A of inverter 4 may include wells 46N and 46P disposed as a portion of substrate 40. Well 46N may be adjacent to active region 40AP in a direction opposite to direction 401 and may be isolated from active region 40AP by isolation region 45. One or more contact plugs 47WN may be disposed on well 46N. One or more contact plugs 47WN may be coupled to a different power supply voltage line than the power supply voltage lines coupled to contact plugs 47SP and 47SN. Well 46P may be adjacent to active region 40AN in direction 401 and may be isolated from active region 40AN by isolation region 45. One or more contact plugs 47WP may be disposed on well 46P. One or more contact plugs 47WP may be coupled to a different power supply voltage line than the power supply voltage lines coupled to contact plugs 47SP, 47SN, and 47WN.

[0043] In some embodiments, Figure 4B Part 4B of the inverter 4 in the middle can be placed in Figure 4A The inverter 4 is located on portion 4A of the inverter 4. The inverter 4 may include conductive segments 41G, 41D, 41SP, and 41SN. In some embodiments, conductive segments 41G, 41D, 41SP, and 41SN may be included in the same conductive layer adjacent to and above the gate wiring layer containing gate electrodes 44GP and 44GN. The same conductive layer may also include conductive segments 41WN and 41WP disposed on conductive plugs 47WN and 47WP. Conductive segments 41G, 41D, 41SP, 41SN, 41WN, and 41WP may include a material that may have a relatively high resistance compared to the material included in conductive lines 43SP, 43D, 48, and 43SN. The material may also have hardness, heat resistance, corrosion resistance, and / or abrasion resistance. For example, conductive segments 41G, 41D, 41SP, 41WN and 41WP may contain at least one of tungsten (W) or titanium nitride (TiN).

[0044] Conductive segment 41G is disposed on contact plugs 47GP and 47GN and extends in direction 401 over other portions 44GPB and 44GNB of the gate electrodes 44GP and 44GN, which are surrounded by isolation region 45 between active regions 40AP and 40AN. Conductive segment 41G may include or be coupled to Figure 3 The input node In 38. Conductive segment 41D may be disposed on contact plugs 47DP and 47DN and extends in direction 401 over active regions 40AP and 40AN. Conductive segment 41D may contain or be coupled to Figure 3 The output node is Out 39.

[0045] The conductive segment 41SP may be L-shaped and may include adjacent portions 41SPA and 41SPB, such as Figure 4B As shown in the diagram. The conductive section 41SP can be a power line that supplies power to the source region of the active region 40AP via the contact plug 47SP. A portion 41SPA is disposed on the contact plug 47SP and in Figure 5A It extends in direction 401. Part 41SPB is in Figure 5B and 5C It is positioned above the isolation zone 45 between the active zone 40AP and the sink 46N. Part of 41SPB is located in... Figure 4B and 5C It can be placed between conductive section 41D and conductive section 41WN, and in relation to... Figure 4B The conductive segment 41SN extends from portion 41SPA in the opposite direction to 402. The conductive segment 41SN may be L-shaped and may include adjacent portions 41SNA and 41SNB, such as... Figure 4B As shown in the diagram. The conductive section 41SN can be a power line that supplies power to the source region of the active region 40AN via the contact plug 47SN. A portion 41SNA is disposed on the contact plug 47SN and in Figure 5A It extends in direction 401. Part of 41SNB is in Figure 5B and 5C It is positioned above the isolation zone 45 between the active region 40AN and the sink 46P. Part of 41SNB is located in... Figure 4B and 5C It can be placed between conductive section 41D and conductive section 41WP, and in relation to... Figure 4B In the opposite direction of direction 402, it extends from part 41SNA.

[0046] In some embodiments, conductive segment 41G may be disposed along an axis contained in cross section A-A' between portions 41SPA and 41SNA of conductive segments 41SP and 41SN. In some embodiments, conductive segment 41D may be disposed along an axis in direction 401 between portions 41SPB and 41SNB of conductive segments 41SP and 41SN.

[0047] A contact plug 412G may be disposed on the conductive segment 41G. In some embodiments, the contact plug 412G may comprise or be coupled to Figure 3 The input node In 38. A contact plug 412D may be disposed on the conductive segment 41D. In some embodiments, the contact plug 412D may comprise or be coupled to... Figure 3 Output node Out 39. Contact plug 412SP can be mounted on a portion 41SPB of conductive section 41SP. Contact plug 412SN can be mounted on a portion 41SNB of conductive section 41SN. Contact plugs 412SP, 412D and 412SN can be mounted along the axis.

[0048] Inverter 4 may include signal lines 42G and conductive segments 42D, 42SP, and 42SN. In some embodiments, signal lines 42G and conductive segments 42D, 42SP, and 42SN may be contained in the same conductive layer adjacent to and above the conductive layer containing 41G, 41D, 41SP, and 41SN. In some embodiments, the conductive layer containing signal lines 42G and conductive segments 42D, 42SP, and 42SN may be formed as a local interconnect layer. The conductive layer containing signal lines 42G and conductive segments 42D, 42SP, and 42SN and the conductive layer containing 41G, 41D, 41SP, and 41SN may jointly contain a conductive material. For example, the conductive material may have a relatively high resistance compared to the material contained in conductive lines 43SP, 43D, 48, and 43SN. The conductive material may have hardness, heat resistance, corrosion resistance, and / or abrasion resistance. For example, the conductive material may contain at least one of tungsten (W) or titanium nitride (TiN).

[0049] Signal line 42G may include or be coupled to Figure 3 The input node In 38 is provided, and an input signal can be provided. In some embodiments, signal line 42G may be included in... Figures 2B to 2CThe signal line 42G can extend along the axis in direction 401 within the internal control line 23. The signal line 42G is positioned above and parallel to portions 41SPA, 41G, and 41SNA of conductive segments 41SP, 41G, and 41SN. The signal line 42G can also be positioned on contact plugs 47GP and 47GN that couple gate electrodes 44GP and 44GN to conductive segment 41G. The signal line 42G can also be on contact plug 412G. Contact plug 412G can couple the signal line 42G to conductive segment 41G. When signal line 42G is above a portion 41SPA of conductive segment 41SP, a portion 44GPA of gate electrode 44GP can be disposed between contact plugs 47SP and 47DP, and coupled to signal line 42G via a portion 44GPB of gate electrode 44GP that intersects below signal line 42G, contact plug 47GP, conductive segment 41G, and contact plug 412G which intersects cross section A-A'. Similarly, when signal line 42G is above a portion 41SNA of conductive segment 41SN, a portion 44GNA of gate electrode 44GP can be disposed between contact plugs 47SN and 47DN, and coupled to signal line 42G via a portion 44GNB of gate electrode 44GP that intersects cross sections A-A' and B-B', contact plug 47GN, conductive segment 41G, and contact plug 412G.

[0050] Conductive segment 42D may be disposed above a portion of conductive segment 41D. Conductive segment 42D may be on contact plug 412D. Contact plug 412D may couple conductive segment 42D to conductive segment 41D. Conductive segment 42D may include or be coupled to Figure 3 The output node is Out 39.

[0051] Conductive segment 42SP may be disposed above conductive segment 41WN and a portion 41SPB of conductive segment 41SP. Conductive segment 42D may be disposed on contact plug 412SP. Contact plug 412SP may couple conductive segment 42SP to conductive segment 41SP. Conductive segment 42SN may be disposed above conductive segment 41WP and a portion 41SNB of conductive segment 41SN. Conductive segment 42SN may be disposed on contact plug 412SN. Contact plug 412SN may couple conductive segment 42SN to conductive segment 41SN. Conductive segments 42SP, 42D and 42SN may extend in direction 401 along an axis contained in cross section C-C' and parallel to signal line 42G. Contact plug 423D may be disposed on conductive segment 42D. Contact plug 423SP may be disposed on conductive segment 42SP above conductive segment 41WN. Contact plug 423SN can be placed on conductive section 42SN above conductive section 41WP.

[0052] The inverter 4 may include conductive lines 43SP, 43SN, 43D, and 48 extending in direction 402 perpendicular to conductive segments 42SP, 42D, and 42SN, and a signal line 42G extending in direction 401. Conductive lines 43D and 48 may be located between conductive lines 43SP and 43SN. In some embodiments, conductive lines 43SP, 43SN, 43D, and 48 may be contained in the same conductive layer above the conductive layer containing the signal line 42G and conductive segments 42D, 42SP, and 42SN. Conductive lines 43SP, 43SN, 43D, and 48 may contain a conductive material having a resistance lower than that of the conductive material of the signal line 42G and conductive segments 42D, 42SP, and 42SN. For example, the conductive material of conductive lines 43SP, 43SN, 43D, and 48 may contain a metal, such as copper (Cu) or aluminum (Al). In some embodiments, the conductive layer comprising conductive lines 43SP, 43SN, 43D and 48 may be formed as a first metal layer (metal 1).

[0053] Conductive wire 43SP may include or be coupled to Figure 2C The power supply voltage line 253A provides the power supply voltage (e.g., VDD). Contact plug 423SP couples conductive line 43SP to conductive segment 42SP. Conductive line 43SN may include or be coupled to... Figure 2C Another power supply voltage line 252 provides another power supply voltage (e.g., VSS). Contact plug 423SN can couple conductive line 43SN to conductive segment 42SN. Contact plug 423D can couple conductive segment 42D to conductive line 43D. Conductive line 43D may include or be coupled to... Figure 3 Output node Out 39 and / or Figure 2C The internal node Int246A. In some embodiments, the conductor 48 may provide the data A signal across the inverter 242A. Figure 2C The input node 244A of inverter 243A. Inverter 4 may not be coupled to conductor 48.

[0054] A local interconnect layer including conductive lines 42G and conductive segments 42D, 42SP, and 42SN can be disposed between a substrate 40 including active regions 40AP and 40AN and a first metal layer including conductive lines 43SP, 43SN, 43D, and 48. Furthermore, a local interconnect layer including signal lines 42G and conductive segments 42D, 42SP, and 42SN can be disposed between a conductive layer including conductive segments 41G, 41D, 41SP, 41SN, 41WN, and 41WP and the first metal layer. Figures 5A to 5CAs shown, a local interconnect layer containing conductive lines 42G and conductive segments 42D, 42SP, and 42SN can be positioned relatively close to or near the interconnect layer containing conductive segments 41G, 41D, 41SP, 41SN, 41WN, and 41WP, and relatively far from the first metal layer. The distance from the local interconnect containing conductive lines 42G to the first metal layer containing conductive lines 43SP, 43SN, 43D, and 48 is longer than the distance from the local interconnect containing conductive lines 42G to the local interconnect layer containing conductive segments 41G, 41D, 41SP, 41SN, 41WN, and 41WP. The thickness of the local interconnect layer containing signal lines 42G and conductive segments 42D, 42SP, and 42SN, having a thickness (e.g., height) D2, is less than the thickness of the first metal layer containing conductive lines 43SP, 43SN, 43D, and 48, having a thickness (e.g., height) D1. For example, the height D1 can be ten times or more greater than the height D2. The signal line 42G in the local interconnect layer occupies a relatively small space, resulting in an increased distance to other wirings that also provide signals to multiple transistors. The signal line 42G or internal control line 23 may have a smaller parasitic capacitance due to interference from the signal to other wirings. The local interconnect layer containing the signal line 42G and conductive segments 42D, 42SP, and 42SN may have a higher resistance than the first metal layer containing conductive lines 43SP, 43SN, 43D, and 48. The signal line 42G or internal control line 23 in the local interconnect layer can reduce power consumption when providing control signals to the inverter.

[0055] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of the invention, as well as their obvious modifications and equivalents. Furthermore, those skilled in the art will readily understand other modifications within the scope of the invention based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments may be made, and these still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form variations of the disclosed invention. Therefore, it is intended that at least some of the scope of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: A transistor configured to transmit a signal, the transistor comprising: An active region, comprising a source region and a drain region, wherein the active region is disposed in a substrate; and Gate electrode, which is located in the gate wiring layer above the substrate; A power line and a first signal line, which are in a first conductive layer adjacent to and above the gate wiring layer, wherein the power line is coupled to the source region and the first signal line is coupled to the drain region; A second signal line, located in a second conductive layer adjacent to and above the first conductive layer, is coupled to the gate electrode. A power supply voltage line, coupled to the power line, wherein the power supply voltage line is in a third conductive layer above the second conductive layer. The first signal line and the second signal line together include a first conductive material, and the power supply voltage line includes a second conductive material that is different from the first conductive material.

2. The semiconductor device of claim 1, wherein the first conductive material comprises at least one of tungsten (W) or titanium nitride (TiN).

3. The semiconductor device of claim 1, wherein the second conductive material comprises at least one of copper (Cu) or aluminum (Al).

4. The semiconductor device of claim 1, wherein the power supply voltage line has a resistance lower than the resistance of the power line.

5. The semiconductor device of claim 1, wherein the power supply voltage line has a height equal to or greater than ten times the height of the second signal line.

6. The semiconductor device of claim 1, wherein the first signal line is further coupled to an output line coupled to the input of another transistor.

7. A semiconductor device comprising: A signal buffer circuit configured to receive a signal from a control signal line in a first conductive layer and further configured to provide the signal to an internal control signal line in a second conductive layer with a delay. Multiple control circuits coupled to the internal control signal line and configured to receive the signal from the internal control signal line; The power supply voltage line is located in the third conductive layer; as well as A conductive section coupled to the power supply voltage line in a fourth conductive layer, wherein the second conductive layer is located between the third and fourth conductive layers, and wherein the distance from the second conductive layer to the third conductive layer is longer than the distance from the second conductive layer to the fourth conductive layer.

8. The semiconductor device of claim 7, wherein the second conductive layer has a thickness less than that of the first conductive layer.

9. The semiconductor device of claim 7, wherein the first conductive layer comprises a first material, and the second conductive layer comprises a second material, and The second material has a higher resistance than the first material.

10. The semiconductor device according to claim 7, further comprising: Memory array; Input / output circuitry; and A data transmission circuit is configured to receive read data from the memory array and provide the read data to the input / output circuit, and is further configured to receive write data from the input / output circuit and provide the write data to the memory array. The data transmission circuit includes the signal buffer circuit, which is configured to receive control signals for at least one of a control data input timing or a data output timing.

11. The semiconductor device of claim 7, wherein the signal buffer circuit is included in the command decoder and the plurality of control circuits are included in at least one of the column decoder or the row decoder.

12. The semiconductor device of claim 7, further comprising a substrate, wherein the second conductive layer is between the substrate and the first conductive layer.

13. The semiconductor device of claim 12, wherein the power supply voltage line is configured to provide a power supply voltage to a plurality of control circuits, and The first conductive layer is located between the second conductive layer and the third conductive layer.

14. The semiconductor device of claim 13, wherein the fourth conductive layer is located above the substrate. The second conductive layer is located between the first conductive layer and the fourth conductive layer.

15. A semiconductor device comprising: An input signal line extends in a first conductive layer and in a first direction and is configured to provide a control signal; An output signal line extends in the second conductive layer and in a second direction perpendicular to the first direction and is configured to provide an inverting control signal; and Transistor, comprising: A gate electrode comprising a portion extending in the first direction, the portion being configured to receive the control signal; Contact plug, on the active region portion; and A conductive segment extending in the first direction within the third conductive layer, the conductive segment being coupled to the contact plug and the output signal line. The first conductive layer is located between the second conductive layer and the third conductive layer, and The distance from the first conductive layer to the second conductive layer is longer than the distance from the first conductive layer to the third conductive layer.

16. The semiconductor device according to claim 15, The first conductive layer and the third conductive layer include at least one of tungsten (W) or titanium nitride (TiN).

17. The semiconductor device of claim 15, wherein the conductive segment is a first conductive segment, and The transistor further includes a second conductive segment in the third conductive layer, and the second conductive segment is configured to receive a power supply voltage and is further configured to provide the power supply voltage to another portion of the active region.

18. The semiconductor device of claim 17, wherein the second conductive segment comprises: The first portion extends along the first direction on the input signal line and is configured to provide the power supply voltage to the other portion of the active region; and The second portion is configured to receive the power supply voltage from the power supply voltage line in the second conductive layer, wherein the second portion extends from the first portion in the second direction between the power supply voltage line and the first conductive segment.

19. The semiconductor device of claim 17, wherein the portion of the gate electrode is a first portion of the gate electrode, wherein the gate electrode further comprises: The second part extends upward from the first part on a third direction perpendicular to the first direction, and the second part intersects the input signal line.

Images