Sensitive amplifier and semiconductor memory

Abstract

The present disclosure provides a sensitive amplifier and a semiconductor memory, comprising: a write module, configured to drive a bit line and a complementary bit line according to write data in a write phase; an amplification module, connected with the bit line and the complementary bit line, configured to amplify a voltage difference between the bit line and the complementary bit line; and a power supply module, connected with a first end of the amplification module, configured to provide a power supply voltage to the amplification module according to temperature data of the amplification module in the write phase, control a ratio of a driving capability of a transistor in the write module to a driving capability of a transistor in the amplification module to be within a preset ratio range, and ensure that the transistor in the write module can drive the voltage of the bit line and the complementary bit line to an inversion point voltage in an early stage of the write phase, accurately write data, effectively shorten a recovery time, and reduce power loss.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a sense amplifier and a semiconductor memory. BACKGROUND

[0002] With the popularity of electronic devices such as mobile phones, tablets, personal computers, etc., semiconductor memory technology has also developed rapidly.

[0003] A sense amplifier (SA) is an important component of a semiconductor memory, and its main function is to amplify the small signal on the bit line, and then perform read or write operations. The sense amplifier includes a write module and an amplification module. In the design stage, the voltage driving capability of the write module and the amplification module needs to be reasonably designed to make the data of the sense amplifier flip, so as to achieve successful data writing.

[0004] However, when the operating temperature of the sense amplifier changes, the data of the sense amplifier may still fail to flip, resulting in failed data writing. SUMMARY

[0005] The present disclosure provides a sense amplifier, comprising:

[0006] a write module, configured to drive a bit line and a complementary bit line according to write data in a write stage;

[0007] an amplification module, connected with the bit line and the complementary bit line, configured to amplify a voltage difference between the bit line and the complementary bit line;

[0008] a power module, connected with a first end of the amplification module, configured to provide a power voltage to the amplification module according to temperature data of the amplification module in the write stage, and control a ratio of a transistor driving capability in the write module to a transistor driving capability in the amplification module to be within a preset ratio range.

[0009] In an embodiment, the power module is configured to:

[0010] when the temperature data of the amplification module is greater than an upper temperature threshold of a preset temperature range, the power module provides a power voltage with a first voltage amplitude;

[0011] when the temperature data of the amplification module is less than a lower temperature threshold of the preset temperature range, the power module provides a power voltage with a third voltage amplitude;

[0012] when the temperature data of the amplification module is within the preset temperature range, the power module provides a power voltage with a second voltage amplitude;

[0013] wherein the first voltage is greater than the second voltage, and the second voltage is greater than the third voltage.

[0014] In an embodiment, the power module is further configured to:

[0015] The amplification module is connected to the first power supply terminal in the non-writing stage, and the power supply voltage provided to the amplification module has a magnitude equal to that of the first power supply terminal.

[0016] In an embodiment, the power module comprises:

[0017] The voltage control unit comprises a first output terminal, configured to generate a first control signal according to temperature data of the amplification module and a column selection signal;

[0018] The voltage control unit comprises a first output terminal, configured to generate a first control signal according to temperature data of the amplification module and a column selection signal;

[0019] In an embodiment, the voltage control unit comprises a plurality of first output terminals, the first control signal comprises a plurality of first control sub-signals, and the voltage control unit comprises:

[0020] A plurality of voltage reduction sub-units, a control terminal of each voltage reduction sub-unit is connected to a corresponding first output terminal of the voltage control unit, and each voltage reduction sub-unit is configured to output a power supply voltage after performing voltage reduction processing on the voltage of the first power supply terminal when a corresponding first control sub-signal is valid;

[0021] Among the plurality of first control sub-signals, only one first control sub-signal is valid.

[0022] In an embodiment, each voltage reduction sub-unit comprises a first N-type transistor;

[0023] The first N-type transistor has a control terminal connected to a corresponding first output terminal of the voltage control unit, a first terminal connected to the first power supply terminal, and a second terminal connected to the first terminal of the amplification module.

[0024] In an embodiment, the power module further comprises a power switch;

[0025] The voltage control unit comprises a second output terminal, which is further configured to generate a second control signal according to the column selection signal;

[0026] The power switch has a control terminal connected to the second output terminal of the voltage control unit, and is configured to control the amplification module to connect to the first power supply terminal in the non-writing stage under the control of the second control signal.

[0027] In an embodiment, the power switch comprises a first P-type transistor;

[0028] The first P-type transistor has a control terminal connected to the second output terminal of the voltage control unit, a first terminal connected to the first power supply terminal, and a second terminal connected to the first terminal of the amplification module.

[0029] In an embodiment, the voltage control unit comprises:

[0030] a temperature sensor for detecting a temperature of the amplification module and encoding the temperature to obtain temperature encoding data;

[0031] a temperature decoder having an input connected to an output of the temperature sensor for decoding the temperature encoding data to obtain a temperature level signal;

[0032] an output unit having a first input for receiving a column selection signal and a second input connected to an output of the temperature decoder, for generating a first control signal based on the column selection signal and the temperature level signal and outputting the first control signal via a first output, and for generating a second control signal based on the column selection signal and outputting the second control signal via a second output.

[0033] In an embodiment, the temperature decoder comprises a plurality of outputs, the temperature level signal comprises a plurality of temperature level sub-signals, and the output unit comprises a plurality of first outputs, the output unit comprising:

[0034] a first buffer having an input for receiving the column selection signal;

[0035] a plurality of AND gates, each having a first input connected to an output of the first buffer and a second input connected to an output of a corresponding temperature decoder for receiving a temperature level sub-signal, each AND gate having an output as a first output of the output unit for outputting a first control sub-signal.

[0036] In an embodiment, the temperature decoder comprises three outputs, the plurality of temperature level sub-signals comprises a first temperature level sub-signal, a second temperature level sub-signal and a third temperature level sub-signal, and the temperature decoder is configured to:

[0037] output the first temperature level sub-signal as a valid value and output the second temperature level sub-signal and the third temperature level sub-signal as invalid values when the temperature data of the amplification module is greater than an upper temperature threshold of the preset temperature range;

[0038] output the third temperature level sub-signal as a valid value and output the first temperature level sub-signal and the second temperature level sub-signal as invalid values when the temperature data of the amplification module is less than a lower temperature threshold of the preset temperature range;

[0039] output the second temperature level sub-signal as a valid value and output the first temperature level sub-signal and the third temperature level sub-signal as invalid values when the temperature data of the amplification module is within the preset temperature range.

[0040] In an embodiment, the output unit further comprises:

[0041] a delay subunit, an input end of which is connected to an output end of the first buffer;

[0042] an OR gate, a first input end of which is connected to an output end of the first buffer, a second input end of which is connected to an output end of the delay subunit, and an output end of which serves as a second output end of the output unit for outputting a second control signal.

[0043] In an embodiment, the delay subunit comprises:

[0044] a plurality of cascaded second buffers, an input end of a second buffer located at a first stage serving as an input end of the delay subunit, and an output end of a second buffer located at a last stage serving as an output end of the delay subunit.

[0045] In an embodiment, the amplification module comprises:

[0046] a second P-type transistor, a source of which serves as a first end of the amplification module, and a gate of which is connected to a drain of a third P-type transistor;

[0047] a third P-type transistor, a source of which is connected to a source of the second P-type transistor, and a gate of which is connected to a drain of the second P-type transistor;

[0048] a second N-type transistor, a source of which is connected to the second power supply end, a drain of which is connected to a drain of the second P-type transistor, and a gate of which is connected to a drain of a third N-type transistor;

[0049] the third N-type transistor, a source of which is connected to the second power supply end, a drain of which is connected to a drain of the third P-type transistor, and a gate of which is connected to a drain of the second N-type transistor.

[0050] In an embodiment, the write module comprises:

[0051] a fourth N-type transistor, a second end of which receives first write data, a first end of which is connected to the complementary bit line, and a gate of which receives a column selection signal;

[0052] a fifth N-type transistor, a second end of which receives first write complementary data, a first end of which is connected to the bit line, and a gate of which receives the column selection signal;

[0053] wherein the write data comprises the first write data and the first write complementary data.

[0054] Another embodiment of the present disclosure provides a semiconductor memory comprising the sense amplifier according to the above-mentioned embodiments.

[0055] The sensitive amplifier and the semiconductor memory provided by the embodiments of the present disclosure include a power supply module, an amplification module and a write module, the power supply module provides a power supply voltage to the amplification module according to temperature data of the amplification module in a write stage, and adjusts a ratio of driving capabilities of transistors in the amplification module and transistors in the write module, so that the ratio is within a preset ratio range, and the transistors in the write module can drive voltages of a bit line and a complementary bit line to an inversion point voltage in an early stage of the write stage, accurate data writing is ensured, and the recovery time can be effectively shortened and the power loss can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0056] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0057] Figure 1 It is a circuit schematic diagram of a sensitive amplifier;

[0058] Figure 2 It is a working timing diagram of the sensitive amplifier provided by an embodiment of the present disclosure;

[0059] Figure 3 It is a data flip principle diagram of the sensitive amplifier provided by an embodiment of the present disclosure;

[0060] Figure 4 It is a circuit principle diagram of a sensitive amplifier provided by the present disclosure;

[0061] Figure 5 It is a circuit principle diagram of a voltage control unit provided by the present disclosure;

[0062] Figure 6A It is a logic operation principle diagram of an output unit provided by the present disclosure;

[0063] Figure 6B It is another logic operation principle diagram of an output unit provided by the present disclosure;

[0064] Figure 6C It is still another logic operation principle diagram of an output unit provided by the present disclosure;

[0065] Figure 7A It is a working timing diagram of the sensitive amplifier provided by an embodiment of the present disclosure;

[0066] Figure 7B It is another working timing diagram of the sensitive amplifier provided by an embodiment of the present disclosure;

[0067] Figure 7C It is still another working timing diagram of the sensitive amplifier provided by an embodiment of the present disclosure.

[0068] REFERENCE NUMERALS:

[0069] 100. Amplification module; 200. Writing module; 300. Power supply module; 310. Power switch;

[0070] 320. Step-down subunit; 330. Voltage control unit; 340. Step-down unit; 331. Temperature sensor;

[0071] 332. Temperature decoder; 333. Output unit; 401. First buffer; 402. OR gate;

[0072] 403, AND gate; 404, second buffer; 405, delay subunit; 500, driver module;

[0073] 501, First inverter; 502, Second inverter; 503, Third inverter; 504, Fourth inverter;

[0074] 601. Second output terminal of the voltage control unit; 602. First output terminal of the voltage control unit;

[0075] 603, the first input terminal of the output unit; 604, the second input terminal of the output unit.

[0076] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0077] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0078] like Figure 1 As shown, a sensitive amplifier includes an amplification module 100, a writing module 200, and a driving module 500. The driving module 500 is connected to the writing module 200, which is connected to bit line BL and complementary bit line BLB. The amplification module 100 is also connected to bit line BL and complementary bit line BLB.

[0079] The driving module 500 is used to enhance the write data, and the write module 200 drives the bit line BL and the complementary bit line BLB according to the enhanced write data under the control of the column selection signal, so as to generate a voltage difference on the bit line BL and the complementary bit line BLB. The amplifying module 100 is used to amplify the voltage difference on the bit line BL and the complementary bit line BLB.

[0080] The amplifying module 100 comprises a second P-type transistor P2, a third P-type transistor P3, a second N-type transistor N2 and a third N-type transistor N3. The drain of the second P-type transistor P2 and the drain of the second N-type transistor N2 are connected and connected with the complementary bit line BLB. The drain of the third P-type transistor P3 and the drain of the third N-type transistor N3 are connected and connected with the bit line BL. The second P-type transistor P2 and the second N-type transistor N2 constitute an inverter, the third P-type transistor P3 and the third N-type transistor N3 constitute an inverter, and the two inverters constitute a pair of inverters.

[0081] The source of the second P-type transistor P2 and the source of the third P-type transistor P3 are connected and serve as a first end ACT of the amplifying module 100. The source of the second N-type transistor N2 and the source of the third N-type transistor N3 are connected and serve as a second end NLAT* of the amplifying module 100. The first end ACT of the amplifying module 100 is connected to the first power supply end, and the second end NLAT* of the amplifying module 100 is connected to the second power supply end.

[0082] The write module 200 comprises a fourth N-type transistor N4 and a fifth N-type transistor N5. The drain of the fourth N-type transistor N4 is connected with the complementary bit line BLB, and the source of the fourth N-type transistor N4 is connected with the complementary input / output line I / O*. The drain of the fifth N-type transistor N5 is connected with the bit line BL, and the source of the fifth N-type transistor N5 is connected with the input / output line I / O.

[0083] As shown in FIG. 1, when data is written into the memory cell, the following three stages are included: Figure 2

[0084] In the charge sharing stage T1, the word line signal on the word line WL is valid, the transistor in the memory cell is turned on, the capacitor in the memory cell shares the charge with the bit line BL or the complementary bit line BLB, and the voltage of the bit line BL or the complementary bit line BLB is raised. For example, the capacitor in the memory cell shares the charge with the complementary bit line BLB, and the voltage of the complementary bit line BLB is raised.

[0085] In the sensing stage T2, the amplifying module 100 further drives the voltage on the bit line BL and the complementary bit line BLB, so as to form a larger voltage difference on the bit line BL and the complementary bit line BLB.

[0086] ​During the write phase T3, the column select signal on the column select line CSEL is active, and the fourth N-type transistor N3 and the fifth N-type transistor N5 in the write module 200 are turned on. The enhanced write data drives the voltage of the bit line BL and the complementary bit line BLB. Since the write data is different from the data in the memory cell, for example, if the data stored in the memory cell connected to the bit line BL is "0" and the write data is "1", the voltage of the bit line BL will rise and the voltage of the complementary bit line BLB will fall, so that the voltage on the bit line BL and the complementary bit line BLB reaches the inversion point voltage (Vtrip) of the dual inverter in the amplifier module 100. The amplifier module 100 further drives the voltage of the bit line BL and the complementary bit line BLB, so that the voltage of the bit line BL reaches the voltage of the first power supply terminal or the voltage of the second power supply terminal, and the voltage of the complementary bit line BLB is the voltage of the second power supply terminal or the voltage of the first power supply terminal.

[0087] During the recovery phase T4, the complementary bit line BLB or bit line BL charges the capacitor in the memory cell, or the capacitor discharges to the complementary bit line BLB or bit line BL, thereby writing data into the memory cell.

[0088] When writing data into the memory cell, in the early stage of the write phase T3, the write module 200 drives the voltages of bit line BL and complementary bit line BLB, causing the voltages on complementary bit line BLB and bit line BL to reach the inversion point voltage. In the later stage of the write phase T3, the voltage difference between complementary bit line BLB and bit line BL is further amplified. For example, in the early stage of the write phase T3, the fourth N transistor N4 and the fifth N transistor N5 drive bit line BL and complementary bit line BLB, causing the voltage of complementary bit line BLB to decrease and the voltage of bit line BL to increase. When the voltages of bit line BL and complementary bit line BLB reach the inversion point voltage, the amplification module 100 further amplifies the voltage difference between bit line BL and complementary bit line BLB.

[0089] like Figure 3 As shown, in the initial stage of write phase T3, the write capability is determined by the ratio of the driving capability of the P-type transistor in the amplification module 100 to the driving capability of the N-type transistor in the write module 200. The driving capability of a transistor refers to its ability to control the voltage of the same node. If the driving capability of the P-type transistor in the amplification module 100 is too strong or the driving force of the N-type transistor in the write module 200 is too weak, the voltage drop of the complementary bit line BLB or bit line BL will be insufficient, failing to reach the inversion point voltage, thus preventing the formation of positive feedback and the data flipping in the amplification module 100, resulting in write failure. For example, in the initial stage of write phase T3, the written data may cause the voltage drop of the complementary bit line BLB to be insufficient, failing to reach the inversion point voltage, preventing the data flipping in the amplification module 100, and resulting in write failure.

[0090] In the design stage of the sense amplifier, the ratio of the driving capability of the P-type transistor in the amplification module 100 and the N-type transistor in the write module 200 is designed according to the inversion point voltage of the dual inverter in the amplification module 100, so as to ensure that the voltage on the complementary bit line BLB and the bit line BL reaches the inversion point voltage in the write stage T3. However, when the temperature of the sense amplifier changes, the ratio of the driving capability of the P-type transistor in the amplification module 100 and the N-type transistor in the write module 200 will also change.

[0091] When the temperature decreases, that is, the sense amplifier works in a low-temperature condition, the driving capability of the N-type transistor in the write module 200 becomes stronger, but the driving capability of the P-type transistor in the amplification module 100 becomes stronger, so that the ratio of the driving capability of the P-type transistor in the amplification module 100 and the N-type transistor in the write module 200 becomes larger. In the early stage of the write stage T3, the N-type transistor in the write module 200 cannot drive the voltage on the bit line BL and the complementary bit line BLB to the inversion point voltage, and cannot make the data in the amplification module 100 flip, resulting in write failure.

[0092] When the temperature increases, that is, the sense amplifier works in a high-temperature condition, the driving capability of the N-type transistor in the write module 200 becomes weaker, but the driving capability of the P-type transistor in the amplification module 100 becomes weaker. In the early stage of the write stage T3, the N-type transistor in the write module 200 can drive the voltage on the bit line BL and the complementary bit line BLB to the inversion point voltage, and the data in the amplification module 100 can flip, but the voltage on the bit line BL or the complementary bit line BLB reaches the voltage of the first power supply end in advance in the write amplification stage, so that the time of the recovery stage T4 becomes longer, resulting in larger power loss.

[0093] As shown in FIG. 1, Figure 4 An embodiment of the present disclosure provides a sense amplifier, which comprises a write module 200, an amplification module 100 and a power supply module 300.

[0094] The write module 200 is connected with the bit line BL and the complementary bit line BLB, and the amplification module 100 is connected with the bit line BL and the complementary bit line BLB. The amplification module 100 comprises a first end ACT, and the power supply module 300 is connected with the first end ACT of the amplification module 100.

[0095] The write module 200 is used for driving the bit line BL and the complementary bit line BLB according to the write data in the write stage T3, so that the voltage on the bit line BL and the complementary bit line BLB reaches the inversion point voltage. The amplification module 100 is used for amplifying the voltage difference between the bit line BL and the complementary bit line BLB.

[0096] The power module 300 is configured to provide a power voltage to the amplification module 100 according to the temperature data of the amplification module 100 in the write phase T3, control the ratio of the driving capability of the transistor in the write module 200 to the driving capability of the transistor in the amplification module 100 to be within a preset ratio range, and make the write module 200 drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage according to the write data in the write phase T3 when the write data is different from the data stored in the storage unit.

[0097] The driving capability of the transistor refers to the voltage control capability of the transistor on the same node, for example, the capability of the transistor to drive the voltage of the same node downward when the voltage of the node is lowered, or the capability of the transistor to drive the voltage of the same node upward when the voltage of the node is raised.

[0098] When the temperature data of the amplification module 100 is within the preset temperature range, the power module 300 provides the power voltage with a magnitude of the second voltage, and the ratio of the driving capability of the transistor in the write module 200 to the driving capability of the transistor in the amplification module 100 is within the preset ratio range.

[0099] When the temperature data of the amplification module 100 is greater than the upper limit temperature threshold of the preset temperature range, that is, the sensitive amplifier works in a high-temperature condition, the driving capability of the N-type transistor in the write module 200 becomes weaker, but the driving capability of the P-type transistor in the amplification module 100 becomes weaker. The power module 300 provides the power voltage with the first voltage to the amplification module 100, and the first voltage is greater than the second voltage, which strengthens the driving capability of the P-type transistor in the amplification module 100, realizes compensation of the ratio of the driving capability of the transistor in the write module 200 to the driving capability of the transistor in the amplification module 100, controls the ratio of the driving capability of the transistor in the write module 200 to the driving capability of the transistor in the amplification module 100 to be within the preset ratio range, avoids the voltages of the bit line and the complementary bit line from reaching the power voltage in advance, effectively shortens the recovery time, and reduces the power loss.

[0100] When the temperature data of the amplification module 100 is less than the lower limit temperature threshold of the preset temperature range, that is, the sensitive amplifier works in a low temperature condition, the driving capability of the N-type transistor in the write-in module 200 becomes stronger, but the driving capability of the P-type transistor in the amplification module 100 becomes stronger. The power supply module 300 provides the amplification module 100 with a power supply voltage being the third voltage, and the third voltage is less than the second voltage, which weakens the driving capability of the P-type transistor in the amplification module 100, realizes compensation of the ratio of the transistor driving capability in the write-in module 200 to the transistor driving capability in the amplification module 100, controls the ratio of the transistor driving capability in the write-in module 200 to the transistor driving capability in the amplification module 100 to be within the preset ratio range, and ensures that the transistor in the write-in module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage in the early stage of the write-in stage T3, so as to accurately write data.

[0101] In the above technical solution, the power supply module 300 provides the amplification module 100 with a power supply voltage according to the temperature data of the amplification module 100 in the write-in stage T3, adjusts the ratio of the driving capability of the transistor in the amplification module 100 to the driving capability of the transistor in the write-in module 200, so that the ratio is within the preset ratio range, ensures that the transistor in the write-in module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage in the early stage of the write-in stage T3, accurately writes data, and can also avoid the voltages of the bit line and the complementary bit line reaching the power supply voltage in advance, effectively shortens the recovery time, and reduces the power loss.

[0102] In some embodiments, the power supply module 300 is further configured to, in a non-write-in stage, connect the amplification module 100 to the first power supply end, and provide the amplification module 100 with a power supply voltage having an amplitude equal to that of the first power supply end, so that the amplification module 100 drives the voltages of the bit line BL and the complementary bit line BLB under the driving of the first power supply end in the non-write-in stage.

[0103] In some embodiments, the power supply module 300 is further configured to, in a non-write-in stage, connect the amplification module 100 to the first power supply end, and provide the amplification module 100 with a power supply voltage having an amplitude equal to that of the first power supply end, so that the amplification module 100 drives the voltages of the bit line BL and the complementary bit line BLB under the driving of the first power supply end in the non-write-in stage.

[0104] The non-write-in stage includes a sensing stage T2 and a recovery stage T4. The amplification module 100 drives the voltages of the bit line BL and the complementary bit line BLB under the driving of the first power supply end in the sensing stage T2 and the recovery stage T4.

[0105] In the technical solution, the amplification module 100 is connected to the first power supply end in the non-writing stage, and the power supply voltage is provided to the amplification module 100 according to the temperature data of the amplification module 100 in the writing stage T3, so that the power supply voltage provided to the amplification module 100 in the writing stage T3 is different from the power supply voltage provided to the amplification module 100 in the non-writing stage, and the N-type transistor in the writing module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage in the initial stage of the writing stage T3, so that the data can be accurately written, and the recovery time can be effectively shortened and the power loss can be reduced.

[0106] In some embodiments, with continued reference to Figure 4 The power supply module 300 includes a voltage control unit 330 and a step-down unit 340. The voltage control unit 330 includes a first output end 602, and the step-down unit 340 includes a control end. The control end of the step-down unit 340 is connected to the first output end 602 of the voltage control unit 330. The voltage control unit 330 is configured to generate a first control signal according to the temperature data of the amplification module 100 and the column selection signal. The step-down unit 340 is configured to output a power supply voltage after performing step-down processing on the voltage of the first power supply end under the control of the first control signal. In this way, the power supply voltage provided to the amplification module 100 in the writing stage T3 can be generated according to the temperature data of the amplification module 100, and the amplitude of the power supply voltage is smaller than the amplitude of the voltage of the first power supply end. In this way, in the initial stage of the writing stage T3, the N-type transistor in the writing module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage, so that the data can be accurately written, and the recovery time can be effectively shortened and the power loss can be reduced.

[0107] In some embodiments, with continued reference to Figure 4 The voltage control unit 330 includes a plurality of first output ends 602, and the first control signal includes a plurality of first control sub-signals. The step-down unit 340 includes a plurality of step-down sub-units 320. The voltage control unit 330 is configured to generate a plurality of first control sub-signals according to the temperature data of the amplification module 100 and the column selection signal. Only one of the plurality of first control sub-signals is a valid value.

[0108] The control end of each step-down sub-unit 320 is connected to the first output end 602 of the corresponding voltage control unit 330. Each step-down sub-unit 320 is configured to output a power supply voltage after performing step-down processing on the voltage of the first power supply end when the corresponding first control sub-signal is a valid value. Since only one of the plurality of first control sub-signals is a valid value, only one step-down sub-unit 320 outputs a power supply voltage after performing step-down processing on the voltage of the first power supply end in the writing stage T3. In this way, the ratio of the transistor driving capability in the writing module 200 to the transistor driving capability in the amplification module 100 in the writing stage T3 can be controlled to be within a preset ratio range.

[0109] In some embodiments, the voltage reduction amount of each voltage reduction subunit 320 varies with temperature change. The relationship between the voltage reduction amount of each voltage reduction subunit 320 and temperature change is the same. When the temperature increases, the voltage reduction amount of each voltage reduction subunit 320 decreases, and when the temperature decreases, the voltage reduction amount of each voltage reduction subunit 320 increases.

[0110] When the temperature data of the amplification module 100 increases, that is, the sensitive amplifier works in a high-temperature condition, the voltage control unit 330 is configured to generate a plurality of first control sub-signals according to the temperature data of the amplification module 100 and the column selection signal, and only one of the first control sub-signals has a valid value, and only one voltage reduction subunit 320 works. When the temperature increases, the voltage reduction amount of the voltage reduction subunit 320 decreases, the power supply voltage output by the voltage reduction subunit 320 becomes larger, the driving capability of the P-type transistor in the amplification module 100 is strengthened, the compensation of the ratio of the driving capability of the transistor in the write-in module 200 to the driving capability of the transistor in the amplification module 100 is realized, and the ratio of the driving capability of the transistor in the write-in module 200 to the driving capability of the transistor in the amplification module 100 is controlled to be within a preset ratio range.

[0111] When the temperature data of the amplification module 100 decreases, that is, the sensitive amplifier works in a low-temperature condition, the voltage control unit 330 is configured to generate a plurality of first control sub-signals according to the temperature data of the amplification module 100 and the column selection signal, and only one of the first control sub-signals has a valid value, and only one voltage reduction subunit 320 works. When the temperature decreases, the voltage reduction amount of the voltage reduction subunit 320 increases, the power supply voltage output by the voltage reduction subunit 320 becomes smaller, the driving capability of the P-type transistor in the amplification module 100 is weakened, the compensation of the ratio of the driving capability of the transistor in the write-in module 200 to the driving capability of the transistor in the amplification module 100 is realized, and the ratio of the driving capability of the transistor in the write-in module 200 to the driving capability of the transistor in the amplification module 100 is controlled to be within a preset ratio range.

[0112] In some embodiments, the voltage reduction amount of each voltage reduction subunit 320 does not change with temperature change, but the voltage reduction amount of each voltage reduction subunit 320 is different. When the temperature data of the amplification module 100 increases, that is, the sensitive amplifier works in a high-temperature condition, the voltage control unit 330 makes the voltage reduction subunit 320 with a small voltage reduction amount work, so that the power supply voltage output by the voltage reduction subunit 320 becomes larger. When the temperature data of the amplification module 100 decreases, that is, the sensitive amplifier works in a low-temperature condition, the voltage control unit 330 makes the voltage reduction subunit 320 with a large voltage reduction amount work, so that the power supply voltage output by the voltage reduction subunit 320 becomes smaller.

[0113] In some embodiments, continuing to refer to Figure 4The power module 300 further comprises a power switch 310, the voltage control unit 330 further comprises a second output end 601, a control end of the power switch 310 is connected to the second output end 601 of the voltage control unit 330, the voltage control unit 330 is further configured to output a second control signal according to a column selection signal, and the power switch 310 is configured to turn on the first power end in the non-writing stage under the control of the second control signal.

[0114] In some embodiments, continuing to refer to Figure 4 Each voltage reduction sub-unit 320 comprises a first N-type transistor, a control end of each first N-type transistor is connected to a first output end 602 of a corresponding voltage control unit 330, a first end of each first N-type transistor is connected to the first power end, and a second end of each first N-type transistor is connected to the first end ACT of the amplification module. Each first N-type transistor is configured to receive a corresponding first control sub-signal, and only one of the first N-type transistors receives a valid first control sub-signal, that is, only one of the first N-type transistors is turned on. When a certain first N-type transistor is turned on, the voltage drop on the first N-type transistor is its threshold voltage, and the voltage of the first end ACT of the amplification module is the difference between the voltage of the first power end and the threshold voltage of the first N-type transistor.

[0115] In some embodiments, the threshold voltage of each first N-type transistor can change with temperature. When the temperature rises, the threshold voltage of each first N-type transistor decreases, and when the temperature decreases, the threshold voltage of each first N-type transistor increases. Under the control of the plurality of first control sub-signals output by the voltage control unit 330, a certain first N-type transistor is turned on. When the temperature rises, the threshold voltage of the first N-type transistor decreases, the power voltage output by the second end of the first N-type transistor becomes larger, and the driving capability of the P-type transistor in the amplification module 100 is strengthened. When the temperature decreases, the threshold voltage of the first N-type transistor increases, the power voltage output by the second end of the first N-type transistor becomes smaller, and the driving capability of the P-type transistor in the amplification module 100 is weakened.

[0116] In some embodiments, the threshold voltages of the first N-type transistors are different. When the temperature rises, under the control of the plurality of first control sub-signals output by the voltage control unit 330, a first N-type transistor with a small threshold voltage is selected from the plurality of first N-type transistors to be turned on, the power voltage of the amplification module 100 becomes larger, and the driving capability of the P-type transistor in the amplification module 100 is strengthened. When the temperature decreases, under the control of the plurality of first control sub-signals output by the voltage control unit 330, a first N-type transistor with a large threshold voltage is selected from the plurality of first N-type transistors to be turned on, the power voltage of the amplification module 100 becomes smaller, and the driving capability of the P-type transistor in the amplification module 100 is weakened.

[0117] By so arranging, the power supply voltage can be provided to the amplification module 100 according to the temperature data of the amplification module 100, the driving capability of the P-type transistor in the amplification module 100 can be strengthened when the driving capability of the N-type transistor in the write module 200 becomes weaker due to the temperature rise and the driving capability of the P-type transistor in the amplification module 100 becomes weaker, the driving capability of the P-type transistor in the amplification module 100 can be weakened when the driving capability of the N-type transistor in the write module 200 becomes stronger due to the temperature drop and the driving capability of the P-type transistor in the amplification module 100 becomes stronger, and the ratio of the transistor driving capability in the write module 200 to the transistor driving capability in the amplification module 100 can be controlled within the preset ratio range. The N-type transistor in the write module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage at the beginning of the write stage T3, the data can be accurately written, the recovery time can be effectively shortened, and the power loss can be reduced.

[0118] In some embodiments, continuing to refer to Figure 4 , the power switch 310 includes a first P-type transistor P1, a control end of the first P-type transistor P1 is connected to a second output end 601 of the voltage control unit 330, a first end of the first P-type transistor P1 is connected to the first power supply end, and a second end of the first P-type transistor P1 is connected to the first end ACT of the amplification module. The first P-type transistor P1 is turned on under the control of the second control signal, so as to realize that the first end ACT of the amplification module 100 is connected to the first power supply end in the non-write stage. Since the voltage drop of the P-type transistor is very small when it is turned on, it is almost zero, so as to realize that the amplification module 100 is connected to the first power supply end in the non-write stage, and the amplitude of the power supply voltage provided to the amplification module 100 is equal to the voltage amplitude of the first power supply end.

[0119] In some embodiments, as shown in Figure 5 , the voltage control unit 330 includes a temperature sensor 331, a temperature decoder 332, and an output unit 333. The temperature sensor 331 is located near the amplification module 100, the temperature sensor 331 is used to detect the temperature of the amplification module 100, and the temperature is encoded to obtain temperature encoding data. The temperature sensor 331 includes an output end, and the temperature decoder 332 includes an input end and an output end. The input end of the temperature decoder 332 is connected to the output end of the temperature sensor 331, and the temperature decoder 332 is used to decode the temperature encoding data to obtain a temperature gear signal.

[0120] The output unit 333 comprises a first input end 603, a second input end 604, a first output end and a second output end, the first output end of the output unit 333 is the first output end 602 of the voltage control unit 330, the second output end of the output unit 333 is the second output end 601 of the voltage control unit 330, the first input end of the output unit 333 receives the column selection signal, the second input end 604 of the output unit 333 is connected with the output end of the temperature decoder 332, the output unit 333 is configured to generate a first control signal according to the column selection signal and the temperature level signal and output the first control signal via the first output end, and the output unit 333 is further configured to generate a second control signal according to the column selection signal and output the second control signal via the second output end.

[0121] In an embodiment, the temperature decoder 332 comprises a plurality of output ends, the temperature level signal comprises a plurality of temperature level sub-signals, and only one of the plurality of temperature level sub-signals is a valid value. Each output end of the temperature decoder 332 is configured to output one temperature level sub-signal. The output unit 333 comprises a plurality of first output ends, one output end of the output unit 333 is one first output end 602 of the voltage control unit 330, and is configured to output one first control sub-signal.

[0122] In an embodiment, the output unit 333 comprises a first buffer 401 and a plurality of AND gates 403, the first buffer 401 comprises an input end and an output end, and the AND gate 403 comprises a first input end, a second input end and an output end. The output end of the first buffer 401 is connected with the first input end of each AND gate 403, and the second input end of each AND gate 403 is connected with the output end of the corresponding temperature decoder 332, and is configured to receive one temperature level sub-signal. The output end of each AND gate 403 is one first output end of the output unit 333, and is configured to output one first control sub-signal.

[0123] The first buffer 401 is configured to receive the column selection signal, the second input end of each AND gate 403 is configured to receive the corresponding temperature sub-level signal, and each AND gate 403 is configured to output one first control sub-signal by performing AND operation on the received temperature level sub-signal and the column selection signal.

[0124] The first control sub-signal is valid at the write stage T3 and can control the buck unit 340 to work. The first control sub-signal is valid at the non-write stage and controls the buck unit 340 to be closed.

[0125] As Figure 6AAs shown, the column selection signal is high during the write phase T3 and low during the non-write phase. When the second input In2 of an AND gate 403 receives an invalid temperature range sub-signal (low level), the first input In1 of the AND gate 403 receives the column selection signal, and the first control sub-signal output by the output Out2 of the AND gate 403 is low during both the write phase T3 and the non-write phase. Figure 6B As shown, when the second input terminal In2 of another AND gate 403 receives a valid temperature range sub-signal (high level), the first input terminal In1 of AND gate 403 receives the column selection signal. The first control sub-signal output by the output terminal Out1 of AND gate 403 is high level during the write phase T3 and low level during the non-write phase. With this configuration, the temperature range sub-signal determines which AND gate 403 outputs a valid first control sub-signal, that is, the temperature range sub-signal controls which first output terminal of output unit 333 outputs a valid first control sub-signal, thereby enabling the selection of the first N-type transistor to be turned on based on the temperature data.

[0126] In one embodiment, reference continues Figure 5 The output unit 333 further includes a delay subunit 405 and an OR gate 402. The OR gate 402 includes a first input terminal, a second input terminal, and an output terminal. The delay subunit 405 includes an input terminal and an output terminal. The input terminal of the delay subunit 405 is connected to the output terminal of the first buffer 401, the output terminal of the delay subunit 405 is connected to the second input terminal of the OR gate 402, and the first input terminal of the OR gate 402 is connected to the output terminal of the first buffer 401.

[0127] The delay subunit 405 is used to delay the column selection signal, and the OR gate 402 is used to perform an OR operation on the column selection signal and the delayed column selection signal to output a second control signal. The delay subunit 405 includes multiple cascaded second buffers 404. The input terminal of the second buffer 404 in the first stage serves as the input terminal of the delay subunit 405, and the output terminal of the second buffer 404 in the last stage serves as the output terminal of the delay subunit 405.

[0128] like Figure 6CThe first input end of the OR gate 402 receives the column selection signal output by the first buffer 401, the second input end of the OR gate 402 receives the delayed column selection signal, and the OR gate 402 performs OR operation on the column selection signal and the delayed column selection signal to output the second control signal. The second control signal is high in the write stage T3, is also high in the early stage of the recovery stage T4, and is low in the late stage of the recovery stage T4 and the sensing stage T2. Through such arrangement, the first P-type transistor P1 is in the off state in the write stage T3 and the early stage of the recovery stage T4, and is in the on state in the non-write stage, so that the amplification module 100 is turned on with the first power supply end in the non-write stage.

[0129] In an embodiment, continuing to refer to Figure 4 , the sense amplifier further comprises a driving module 500 connected with the write module 200. The write data comprises first write data D and first write complementary data D*.

[0130] The driving module 500 comprises a first inverter 501, a second inverter 502, a third inverter 503 and a fourth inverter 504. The input end of the first inverter 501 is used to receive the first write data D, the output end of the first inverter 501 is connected with the input end of the second inverter 502, the output end of the second inverter 502 is used as the first output end of the driving module 500 and is connected with the input / output line I / O.

[0131] The input end of the third inverter 503 is used to receive the first write complementary data D*, the output end of the third inverter 503 is connected with the input end of the fourth inverter 504, and the output end of the fourth inverter 504 is used as the second output end of the driving module 500 and is connected with the complementary input / output line I / O*.

[0132] The write module 200 comprises a fourth N-type transistor N4 and a fifth N-type transistor N5. The drain of the fourth N-type transistor N4 is connected with the complementary input / output line I / O* and receives the first complementary write data D*. The source of the fourth N-type transistor N4 is connected with the complementary bit line BLB, and the gate of the fourth N-type transistor N4 receives the column selection signal. The drain of the fifth N-type transistor N5 is connected with the input / output line I / O and receives the first write data D. The source of the fifth N-type transistor N5 is connected with the bit line BL, and the gate of the fifth N-type transistor N5 receives the column selection signal.

[0133] The amplification module 100 comprises a second P-type transistor P2, a third P-type transistor P3, a second N-type transistor N2 and a third N-type transistor N3. The source of the second P-type transistor P2 is connected with each voltage reduction sub-module 320 as the first end ACT of the amplification module 100. The gate of the second P-type transistor P2 is connected with the drain of the third P-type transistor P3. The source of the third P-type transistor P3 is connected with the source of the second P-type transistor P2, and the gate of the third P-type transistor P3 is connected with the drain of the second P-type transistor P2.

[0134] The source of the second N-type transistor N2 is connected with the second power terminal as the second end NLAT* of the amplification module 100. The drain of the second N-type transistor N2 is connected with the drain of the second P-type transistor P2, the drain of the second N-type transistor N2 is connected with the complementary bit line BLB, and the gate of the second N-type transistor N2 is connected with the drain of the third N-type transistor N3. The source of the third N-type transistor N3 is connected with the source of the second N-type transistor N2, the drain of the third N-type transistor N3 is connected with the drain of the third P-type transistor P3, the drain of the third N-type transistor N3 is connected with the bit line BL, and the gate of the third N-type transistor N3 is connected with the drain of the second N-type transistor N2.

[0135] With reference to Figure 5 , the temperature decoder 332 comprises three outputs, and the plurality of temperature level sub-signals comprises a first temperature level sub-signal, a second temperature level sub-signal and a third temperature level sub-signal. The output unit 333 comprises three AND gates 403, which are marked as a first AND gate &-1, a second AND gate &-2 and a third AND gate &-3. The second input end of the first AND gate &-1 receives the first temperature level signal, the second input end of the second AND gate &-2 receives the second temperature level signal, and the second input end of the third AND gate &-3 receives the third temperature level signal.

[0136] The voltage reduction unit 340 comprises three voltage reduction sub-modules 320, and each voltage reduction sub-module 320 comprises a first N-type transistor. The three first N-type transistors are marked as a first first N-type transistor N1-1, a second first N-type transistor N1-2 and a third first N-type transistor N1-3. The gate of the first first N-type transistor N1-1 is connected with the output end of the first AND gate &-1, the gate of the second first N-type transistor N1-2 is connected with the output end of the second AND gate &-2, and the gate of the third first N-type transistor N1-3 is connected with the output end of the third AND gate &-3.

[0137] As Figures 7A to 7CAs shown, OR gate 402 outputs a second control signal P1_WR. The second control signal P1_WR outputs a high level in the early stage of the write phase T3 and the recovery phase T4, and outputs a low level in the later stage of the recovery phase T4 and the sensing phase T2, controlling the first P-type transistor to conduct in the non-write phase, so that the amplification module 100 is connected to the first power supply terminal in the non-write phase.

[0138] Temperature decoder 332 is used to decode temperature encoded data and output temperature data. Temperature decoder 332 is also used to output a first temperature range sub-signal as a valid value and the second and third temperature range sub-signals as invalid values ​​when the temperature data from amplification module 100 exceeds the upper limit temperature threshold of a preset temperature range. The first control sub-signal output by the first AND gate &-1 is a valid value, while the first control sub-signals output by the second AND gate &-2 and the third AND gate &-3 are invalid values.

[0139] like Figure 7A As shown, the first control sub-signal N1-1_WR received by the first first N-type transistor N1-1 is a valid value, the first control sub-signal N1-2_WR received by the second first N-type transistor N1-2 is an invalid value, and the first control sub-signal N1-3_WR received by the third first N-type transistor N1-3 is an invalid value. The first first N-type transistor N1-1 is turned on during the write phase T3, while the second first N-type transistor N1-2 and the third N-type transistor are turned off during the write phase T3. During the write phase T3, the power supply voltage provided to the amplification module 100 is the difference between the voltage at the first power supply terminal and the threshold voltage Vth-1 of the first N-type transistor.

[0140] When the temperature data from the amplification module 100 is within the preset temperature range, the output second temperature range sub-signal is valid, while the output first and third temperature range sub-signals are invalid. For example... Figure 7B As shown, the first control sub-signal N1-1_WR received by the first first N-type transistor N1-1 is invalid, the first control sub-signal N1-2_WR received by the second first N-type transistor N1-2 is valid, and the first control sub-signal N1-3_WR received by the third first N-type transistor N1-3 is invalid. The second first N-type transistor N1-2 is turned on during the write phase T3, while the first first N-type transistor N1-1 and the third N-type transistor N1-3 are turned off during the write phase T3. During the write phase T3, the power supply voltage provided to the amplification module 100 is the difference between the voltage at the first power supply terminal and the threshold voltage Vth-2 of the second N-type transistor N2.

[0141] When the temperature data of the amplification module 100 is less than the lower limit temperature threshold of the preset temperature range, the output third temperature gear sub-signal is a valid value; the output first temperature gear sub-signal and the output second temperature gear sub-signal are invalid values. The first control sub-signal output by the third AND gate &-3 is a valid value, and the first control sub-signal output by the first AND gate &-1 and the second AND gate &-2 is an invalid value. As shown in FIG. 3, the first control sub-signal N1-1_WR received by the first first N-type transistor N1-1 is an invalid value, the first control sub-signal N1-2_WR received by the second first N-type transistor N1-2 is an invalid value, and the first control sub-signal N1-3_WR received by the third first N-type transistor N1-3 is a valid value. The third first N-type transistor N1-3 is turned on in the write stage T3, and the first first N-type transistor N1-1 and the second first N-type transistor are turned off in the write stage T3. The power supply voltage provided to the amplification module 100 in the write stage T3 is the difference between the voltage of the first power supply end and the threshold voltage Vth-3 of the third N-type transistor N3. Figure 7C

[0142] In an embodiment, the parameters of the first N-type transistor, the second N-type transistor N2 and the third N-type transistor N3 are the same, and the threshold voltages of the first N-type transistor, the second N-type transistor N2 and the third N-type transistor N3 change with temperature and decrease with the increase of temperature. When the temperature of the amplification module 100 increases, that is, the sensitive amplifier works in a high-temperature condition, the first first N-type transistor N1-1 is controlled to work, and the threshold voltage of the first first N-type transistor N1-1 decreases with the increase of temperature, so that the power supply voltage provided to the amplification module 100 increases. When the temperature of the amplification module 100 decreases, that is, the sensitive amplifier works in a low-temperature condition, the third first N-type transistor N1-3 is controlled to work, and the threshold voltage of the third N-type transistor increases with the decrease of temperature, so that the power supply voltage provided to the amplification module 100 decreases. The compensation of the driving capability of the P-type transistor in the amplification transistor at any temperature is realized.

[0143] In an embodiment, the threshold voltages of the first N-type transistor, the second N-type transistor N2 and the third N-type transistor N3 are different, and the threshold voltage of the first N-type transistor is less than the threshold voltage of the second N-type transistor N2, and the threshold voltage of the second N-type transistor N2 is less than the threshold voltage of the third N-type transistor N3. When the temperature data of the amplification module 100 increases, that is, the sensitive amplifier works in a high-temperature condition, the first first N-type transistor N1-1 with a small threshold voltage is controlled to work, and when the temperature data of the amplification module 100 decreases, that is, the sensitive amplifier works in a low-temperature condition, the third first N-type transistor N1-3 with a large threshold voltage is controlled to work. The compensation of the driving capability of the P-type transistor in the amplification transistor at any temperature is realized. ​

[0144] In the technical solution, the ratio of the driving capability of the transistor in the write module 200 to the driving capability of the transistor in the amplification module 100 is controlled within a preset ratio range by compensating the driving capability of the P-type transistor in the amplification transistor at any temperature. In the initial stage of the write phase T3, the N-type transistor in the write module 200 can drive the voltages of the bit line BL and the complementary bit line BLB to the inversion point voltage, accurately write data, effectively shorten the recovery time, and reduce the power loss.

[0145] The present disclosure also provides a semiconductor memory including the sensitive amplifier provided by the above-mentioned embodiments.

[0146] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure following the general principles thereof and including such departures from the present disclosure as come within known use or custom in the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0147] It should be understood that the present disclosure is not limited to the precise structures herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A sensitive amplifier, characterized in that, include: The write module is used to drive the bit lines and complementary bit lines according to the write data during the write phase; An amplification module, connected to the bit line and the complementary bit line, is used to amplify the voltage difference between the bit line and the complementary bit line; A power module, connected to the first terminal of the amplification module, is used to provide a power supply voltage to the amplification module based on the temperature data of the amplification module during the writing phase, and to control the ratio of the transistor driving capability in the writing module to the transistor driving capability in the amplification module within a preset ratio range; and to control the writing module to reach the inversion point voltage based on the voltage of the bit line and complementary bit line driven by the written data during the writing phase when the written data is different from the data stored in the storage unit. The power module includes: A voltage control unit includes a first output terminal for generating a first control signal based on the temperature data and column selection signal of the amplification module; A step-down unit, whose control terminal is connected to the first output terminal of the voltage control unit, is used to step down the voltage of the first power supply terminal under the control of the first control signal and then output the power supply voltage; The voltage control unit includes multiple first output terminals, the first control signal includes multiple first control sub-signals, and the step-down unit includes: Multiple step-down subunits are provided, and the control terminal of each step-down subunit is connected to the first output terminal of the corresponding voltage control unit. Each step-down subunit is used to step down the voltage of the first power supply terminal and output the power supply voltage when the corresponding first control sub-signal is valid. Of the plurality of first control sub-signals, only one first control sub-signal is a valid value; Each step-down subunit includes a first N-type transistor; The first N-type transistor has its control terminal connected to the first output terminal of the corresponding voltage control unit, its first terminal connected to the first power supply terminal, and its second terminal connected to the first terminal of the amplification module; each of the first N-type transistors has a different threshold voltage.

2. The sensitive amplifier according to claim 1, characterized in that, The power module is used for: When the temperature data of the amplification module is greater than the upper limit temperature threshold of the preset temperature range, the amplitude of the power supply voltage provided by the power supply module is the first voltage. When the temperature data of the amplification module is less than the lower limit temperature threshold of the preset temperature range, the amplitude of the power supply voltage provided by the power supply module is the third voltage. When the temperature data of the amplification module is within the preset temperature range, the amplitude of the power supply voltage provided by the power supply module is the second voltage; Wherein, the first voltage is greater than the second voltage, and the second voltage is greater than the third voltage.

3. The sensitive amplifier according to claim 1, characterized in that, The power module is also used for: During the non-writing phase, the amplification module is connected to the first power supply terminal, and the amplitude of the power supply voltage provided to the amplification module is equal to the voltage amplitude of the first power supply terminal.

4. The sensitive amplifier according to claim 1, characterized in that, The power module also includes: a power switch; The voltage control unit includes a second output terminal, which is also used to generate a second control signal based on the column selection signal; The power switch, whose control terminal is connected to the second output terminal of the voltage control unit, is used to enable the amplification module to turn on the first power terminal during the non-writing phase under the control of the second control signal.

5. The sensitive amplifier according to claim 4, characterized in that, The power switch includes a first P-type transistor; The first P-type transistor has its control terminal connected to the second output terminal of the voltage control unit, its first terminal connected to the first power supply terminal, and its second terminal connected to the first terminal of the amplification module.

6. The sensitive amplifier according to claim 1, characterized in that, The voltage control unit includes: A temperature sensor is used to detect the temperature of the amplification module and encode the temperature to obtain temperature-coded data; A temperature decoder, whose input is connected to the output of the temperature sensor, is used to decode the temperature encoded data to obtain the temperature range signal; The output unit includes a first input terminal and a second input terminal. The first input terminal receives a column selection signal, and the second input terminal is connected to the output terminal of the temperature decoder. It is used to generate a first control signal based on the column selection signal and the temperature range signal and output it through the first output terminal. It is also used to generate a second control signal based on the column selection signal and output it through the second output terminal.

7. The sensitive amplifier according to claim 6, characterized in that, The temperature decoder includes multiple output terminals, and the temperature range signal includes multiple temperature range sub-signals; the output unit includes multiple first output terminals, and the output unit includes: A first buffer, the input of which is used to receive the column selection signal; Multiple AND gates are provided, with the first input of each AND gate connected to the output of the first buffer, the second input of each AND gate connected to the output of the corresponding temperature decoder, for receiving a temperature level sub-signal, and the output of each AND gate serving as a first output of the output unit for outputting a first control sub-signal.

8. The sensitive amplifier according to claim 6, characterized in that, The temperature decoder includes three output terminals and multiple temperature range sub-signals, including a first temperature range sub-signal, a second temperature range signal, and a third temperature range signal; the temperature decoder is used for: When the temperature data of the amplification module is greater than the upper temperature threshold of the preset temperature range, the first temperature level sub-signal output is a valid value; the second and third temperature level sub-signals output are both invalid values. When the temperature data of the amplification module is less than the lower limit temperature threshold of the preset temperature range, the output third temperature level sub-signal is a valid value; the output first temperature level sub-signal and second temperature level sub-signal are both invalid values. When the temperature data of the amplification module is within the preset temperature range, the output second temperature level sub-signal is a valid value; the output first temperature level sub-signal and third temperature level sub-signal are both invalid values.

9. The sensitive amplifier according to claim 7, characterized in that, The output unit further includes: The delay subunit has its input connected to the output of the first buffer. The OR gate has its first input connected to the output of the first buffer, its second input connected to the output of the delay sub-unit, and its output serving as the second output of the output unit for outputting the second control signal.

10. The sensitive amplifier according to claim 9, characterized in that, The delay subunit includes: Multiple cascaded second buffers are used, with the input of the second buffer in the first stage serving as the input of the delay sub-unit, and the output of the second buffer in the last stage serving as the output of the delay sub-unit.

11. The sensitive amplifier according to claim 1, characterized in that, The amplification module includes: The source of the second P-type transistor serves as the first terminal of the amplification module, and its gate is connected to the drain of the third P-type transistor. The third P-type transistor has its source connected to the source of the second P-type transistor and its gate connected to the drain of the second P-type transistor. The second N-type transistor has its source connected to the second power supply terminal, its drain connected to the drain of the second P-type transistor, its drain connected to the complementary bit line, and its gate connected to the drain of the third N-type transistor. The third N-type transistor has its source connected to the second power supply terminal, its drain connected to the drain of the third P-type transistor, its drain connected to the bit line, and its gate connected to the drain of the second N-type transistor.

12. The sensitive amplifier according to claim 11, characterized in that, The writing module includes: The fourth N-type transistor has a second terminal that receives the first write data, a first terminal that is connected to the complementary bit line, and a gate that receives the column select signal. The fifth N-type transistor has a second terminal that receives the first write complementary data, a first terminal that is connected to the bit line, and a gate that receives the column select signal. The written data includes first written data and first written complementary data.

13. A semiconductor memory, characterized in that, Includes the sensitive amplifier as described in any one of claims 1 to 12.

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