Sensitive amplifier and semiconductor memory

Abstract

The present disclosure provides a sensitive amplifier and a semiconductor memory, comprising: a control module provided with an input end and an output end, used for obtaining temperature data of a write-in module, and pulse width adjusting a first column selection signal received by the input end according to the temperature data, and outputting a second column selection signal; the write-in module is provided with a control end, the control end of the write-in module is connected with the output end of the control module, the write-in module is connected with a bit line and a complementary bit line, and the write-in module is used for driving voltages of the bit line and the complementary bit line according to write-in data under the control of the second column selection signal in a write-in stage; the amplification module is connected with the bit line and the complementary bit line, and is used for amplifying the voltages of the bit line and the complementary bit line. Through such setting, the situation that the voltage driving capability of the write-in module changes with temperature is compensated, so that the write-in module drives the bit line and the complementary bit line to reach the inversion point voltage at the expected time, ensures successful write-in data, and improves the performance parameter of the write-in time.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a sense amplifier and a semiconductor memory. BACKGROUND

[0002] With the popularity of electronic devices such as mobile phones, tablets, personal computers, etc., semiconductor memory technology has also developed rapidly.

[0003] A sense amplifier (SA) is an important component of a semiconductor memory, and its main function is to amplify a small signal on a bit line, and then perform a read or write operation. The sense amplifier includes a write module and an amplification module. In the design stage, the time for driving the bit line and the complementary bit line of the write module needs to be reasonably designed to make the data of the sense amplifier flip, so as to achieve successful data writing.

[0004] However, when the operating temperature of the sense amplifier changes, the data of the sense amplifier still cannot flip, resulting in a failed write data. SUMMARY

[0005] The present disclosure provides a sense amplifier, comprising:

[0006] a control module having an input end and an output end, configured to obtain temperature data of the write module, and to pulse-width adjust a first column selection signal received by the input end of the control module according to the temperature data, and output a second column selection signal;

[0007] a write module having a control end, wherein the control end of the write module is connected to the output end of the control module, and the write module is connected to a bit line and a complementary bit line, and is configured to drive a voltage difference between the bit line and the complementary bit line according to write data under the control of the second column selection signal in a write stage;

[0008] an amplification module connected to the bit line and the complementary bit line, and configured to amplify voltages of the bit line and the complementary bit line.

[0009] In some embodiments, the sense amplifier further comprises:

[0010] a drive module connected to an input-output line and a complementary input-output line, and configured to output write data with enhanced signals.

[0011] In some embodiments, the control module comprises:

[0012] a pulse-width parameter unit having an output end, and configured to generate a pulse-width adjustment signal according to the temperature data of the write module;

[0013] The pulse width adjusting unit is provided with an input end, an output end and a control end, the control end is connected with the output end of the pulse width parameter unit, the input end receives the first column selection signal, and the pulse width adjusting unit adjusts the pulse width of the first column selection signal according to the pulse width adjusting signal and outputs the second column selection signal.

[0014] In some embodiments, the pulse width parameter unit comprises a plurality of output ends, the pulse width adjusting signal comprises a plurality of selection signals, and the pulse width adjusting unit comprises:

[0015] a plurality of adjusting sub-units, the output end of each adjusting sub-unit is connected with a corresponding input end of the selection unit, and each adjusting sub-unit is used for adjusting the pulse width of the first column selection signal received by the input end thereof; wherein the pulse width adjusting amount of each adjusting sub-unit is different;

[0016] the selection unit, each control end of the selection unit is connected with the output end of a corresponding pulse width parameter unit and receives a corresponding selection signal; and the selection unit is used for selecting one output signal from the output signals of the plurality of adjusting sub-units under the control of the plurality of selection signals.

[0017] In some embodiments, the pulse width adjusting unit comprises three adjusting sub-units, which are marked as a first adjusting sub-unit, a second adjusting sub-unit and a third adjusting sub-unit; and the pulse width parameter unit is used for:

[0018] when the temperature data is located in the first temperature range, the output first selection signal is a valid value, the output second selection signal and the output third selection signal are invalid values, and the selection unit is controlled to select the output signal of the first adjusting sub-unit for output;

[0019] when the temperature data is located in the second temperature range, the output second selection signal is a valid value, the output first selection signal and the output third selection signal are invalid values, and the selection unit is controlled to select the output signal of the second adjusting sub-unit for output;

[0020] when the temperature data is located in the third temperature range, the output third selection signal is a valid value, the output first selection signal and the output second selection signal are invalid values, and the selection unit is controlled to select the output signal of the third adjusting sub-unit for output;

[0021] wherein, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the pulse width of the output signal of the first adjusting sub-unit is less than the pulse width of the output signal of the second adjusting sub-unit, and the pulse width of the output signal of the second adjusting sub-unit is less than the pulse width of the output signal of the third adjusting sub-unit.

[0022] In some embodiments, the first adjusting sub-unit comprises:

[0023] a first delay circuit having an input terminal receiving the first column selection signal and delaying the first column selection signal to output a first delay signal;

[0024] a first OR gate having a first input terminal receiving the first column selection signal and a second input terminal connected to an output terminal of the first delay circuit to receive the first delay signal and output a result of an OR operation of the first delay signal and the first column selection signal.

[0025] In some embodiments, the first delay circuit comprises:

[0026] a first buffer having an input terminal receiving the first column selection signal;

[0027] a second buffer having an input terminal connected to an output terminal of the first buffer and an output terminal outputting the first delay signal.

[0028] In some embodiments, the second adjusting subunit comprises:

[0029] a second delay circuit having an input terminal receiving the first column selection signal and delaying the first column selection signal to output a second delay signal, and the second delay circuit has a delay amount greater than a delay amount of the first delay circuit;

[0030] a second OR gate having a first input terminal receiving the first column selection signal and a second input terminal connected to an output terminal of the second delay circuit to receive the second delay signal and output a result of an OR operation of the second delay signal and the first column selection signal.

[0031] In some embodiments, the second delay circuit comprises:

[0032] a third buffer having an input terminal receiving the first column selection signal;

[0033] a fourth buffer having an input terminal connected to an output terminal of the third buffer;

[0034] a fifth buffer having an input terminal connected to an output terminal of the fourth buffer;

[0035] a sixth buffer having an input terminal connected to an output terminal of the fifth buffer and an output terminal outputting the second delay signal.

[0036] In some embodiments, the third adjusting subunit comprises:

[0037] a third delay circuit having an input terminal receiving the first column selection signal and delaying the first column selection signal to output a third delay signal, and the third delay circuit has a delay amount greater than a delay amount of the second delay circuit;

[0038] a third OR gate, a first input end of the third OR gate receiving the first column selection signal, a second input end of the third OR gate being connected with an output end of the third delay circuit to receive the third delay signal, and outputting a result of OR operation of the third delay signal and the first column selection signal.

[0039] In some embodiments, the third delay circuit comprises:

[0040] a seventh buffer, an input end of the seventh buffer being configured to receive the first column selection signal;

[0041] an eighth buffer, an input end of the eighth buffer being connected with an output end of the seventh buffer;

[0042] a ninth buffer, an input end of the ninth buffer being connected with an output end of the eighth buffer;

[0043] a tenth buffer, an input end of the tenth buffer being connected with an output end of the ninth buffer;

[0044] an eleventh buffer, an input end of the eleventh buffer being connected with an output end of the tenth buffer;

[0045] a twelfth buffer, an input end of the twelfth buffer being connected with an output end of the eleventh buffer, and an output end of the twelfth buffer outputting the third delay signal.

[0046] In some embodiments, the pulse width parameter unit comprises:

[0047] a temperature sensor, the temperature sensor being configured to detect temperature data of the write module, and generate temperature encoding data according to the temperature data;

[0048] a temperature decoder, an input end of the temperature decoder being connected with an output end of the temperature sensor, the temperature decoder being configured to generate a pulse width adjustment signal according to the temperature encoding data.

[0049] In some embodiments, the write module comprises:

[0050] a third N-type transistor, a second end of the third N-type transistor receiving the first write data, a first end of the third N-type transistor being connected with the bit line, and a gate of the third N-type transistor being connected with the column selection line to receive the second column selection signal;

[0051] a fourth N-type transistor, a second end of the fourth N-type transistor receiving the first complementary write data, a first end of the fourth N-type transistor being connected with the complementary bit line, and a gate of the fourth N-type transistor being connected with the column selection line to receive the second column selection signal;

[0052] wherein the write data comprises the first write data and the first complementary write data.

[0053] In some embodiments, the amplification module comprises:

[0054] a first P-type transistor, a source of the first P-type transistor being connected with a source of the second P-type transistor, a gate of the first P-type transistor being connected with a drain of the second P-type transistor, and a drain of the first P-type transistor being connected with a drain of the first N-type transistor;

[0055] The second P-type transistor has its gate connected to the drain of the first P-type transistor and its drain connected to the drain of the second N-type transistor.

[0056] The first N-type transistor has its gate connected to a complementary bit line, its gate connected to the drain of the second N-type transistor, and its source connected to the source of the second N-type transistor.

[0057] The second N-type transistor has its gate connected to the bit line, and its gate is connected to the drain of the first N-type transistor.

[0058] In some embodiments, the driver module includes:

[0059] The first inverter receives the first written data at its input.

[0060] The second inverter has its input connected to the output of the first inverter, and its output outputs the first written data after signal enhancement.

[0061] The third inverter receives the first complementary write data at its input.

[0062] The fourth inverter has its input connected to the output of the third inverter, and its output is the first complementary write data after signal enhancement.

[0063] One embodiment of this disclosure provides a semiconductor memory, including the sensitive amplifier described in the above embodiments.

[0064] This disclosure provides a sensitive amplifier and a semiconductor memory. The sensitive amplifier includes a control module, a write module, and an amplification module. The output terminal of the control module is connected to the control terminal of the write module. Both the write module and the amplification module are connected to bit lines and complementary bit lines. The control module is used to adjust the pulse width of the first column selection signal according to the temperature data of the write module to compensate for the change in the voltage drive capability of the write module with temperature changes, so that the write module drives the bit lines and complementary bit lines to reach the inversion point voltage at the expected time, ensuring successful data writing and improving the performance parameters of the write time. Attached Figure Description

[0065] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0066] Figure 1 This is a circuit diagram of a sensitive amplifier;

[0067] Figure 2A for Figure 1 The illustrated embodiment provides a schematic diagram of the working principle of a sensitive amplifier;

[0068] Figure 2B for Figure 1The embodiment shown provides another working principle diagram of the sensitive amplifier;

[0069] Figure 2C The circuit schematic diagram of the sensitive amplifier provided by an embodiment of the present disclosure is shown in FIG. 1; Figure 1 The embodiment shown provides another working principle diagram of the sensitive amplifier;

[0070] Figure 3 The circuit schematic diagram of the sensitive amplifier provided by an embodiment of the present disclosure is shown in FIG. 1;

[0071] Figure 4 The circuit schematic diagram of the control module provided by an embodiment of the present disclosure is shown in FIG. 2;

[0072] Figure 5A The circuit schematic diagram of the first adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 3;

[0073] Figure 5B The working principle diagram of the first adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 4;

[0074] Figure 6A The circuit schematic diagram of the second adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 5;

[0075] Figure 6B The working principle diagram of the second adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 6;

[0076] Figure 7A The circuit schematic diagram of the third adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 7;

[0077] Figure 7B The working principle diagram of the third adjusting subunit provided by an embodiment of the present disclosure is shown in FIG. 8;

[0078] Figure 8 The circuit schematic diagram of the control module provided by another embodiment of the present disclosure is shown in FIG. 9;

[0079] Figure 9A The circuit schematic diagram of the first adjusting subunit provided by another embodiment of the present disclosure is shown in FIG. 10;

[0080] Figure 9B The working principle diagram of the first adjusting subunit provided by another embodiment of the present disclosure is shown in FIG. 11;

[0081] Figure 10A The circuit schematic diagram of the second adjusting subunit provided by another embodiment of the present disclosure is shown in FIG. 12;

[0082] Figure 10B The working principle diagram of the second adjusting subunit provided by another embodiment of the present disclosure is shown in FIG. 13;

[0083] Figure 11A The circuit schematic diagram of the third adjusting subunit provided by another embodiment of the present disclosure is shown in FIG. 14;

[0084] Figure 11B A working principle diagram of the third adjusting sub-unit provided for another embodiment of the present disclosure;

[0085] Figure 12A A working principle diagram of a sensitive amplifier provided for an embodiment of the present disclosure;

[0086] Figure 12B Another working principle diagram of a sensitive amplifier provided for an embodiment of the present disclosure.

[0087] Reference signs:

[0088] 300, control module; 200, writing module; 100, amplification module; 400, driving module; 320, pulse width parameter unit; 310, pulse width adjusting unit; 311, first adjusting sub-unit; 312, second adjusting sub-unit; 313, third adjusting sub-unit; 314, selection unit; 315, fifth inverter; 321, temperature sensor; 322, temperature decoder; 401, first inverter; 402, second inverter; 403, third inverter; 404, fourth inverter; 510, first OR gate; 520, first delay circuit; 530, second OR gate; 540, second delay circuit; 550, third OR gate; 560, third delay circuit; 521, first buffer; 522, second buffer; 523, third buffer; 524, fourth buffer; 525, fifth buffer; 526, sixth buffer; 527, seventh buffer; 528, eighth buffer; 529, ninth buffer; 531, tenth buffer; 532, eleventh buffer; 533, twelfth buffer; 610, first AND gate; 620, second AND gate; 630, third AND gate.

[0089] The specific embodiments of the present disclosure have been shown through the above-described drawings, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present disclosure by any means, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0090] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals represent like elements, unless the context of use indicates otherwise. The following exemplary embodiments described are not representative of all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0091] As Figure 1As shown, a sensitive amplifier includes an amplification module 100, a writing module 200, and a driving module 400. The driving module 400 is connected to the input / output line I / O and the complementary input / output line I / O*. The writing module 200 is also connected to the bit line BL and the complementary bit line BLB. The amplification module 100 is connected to the bit line BL and the complementary bit line BLB.

[0092] The driving module 400 is used to enhance the written data. Under the control of the column selection signal CL0, the writing module 200 drives the bit line BL and the complementary bit line BLB according to the enhanced written data, generating a voltage difference on the bit line BL and the complementary bit line BLB. The amplification module 100 is used to amplify the voltage difference on the bit line BL and the complementary bit line BLB.

[0093] The amplification module 100 includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2. The drains of the first P-type transistor P1 and the first N-type transistor N1 are connected and then connected to the bit line BL. The drains of the second P-type transistor P2 and the second N-type transistor N2 are connected and then connected to the complementary bit line BLB. The first P-type transistor P1 and the first N-type transistor N1 form an inverter, and the second P-type transistor P2 and the second N-type transistor N2 form another inverter; these two inverters constitute a dual inverter.

[0094] The source of the first P-type transistor P1 and the source of the second P-type transistor P2 are connected together to form the first terminal ACT of the amplification module 100. The source of the first N-type transistor N1 and the source of the second N-type transistor N2 are connected together to form the second terminal NLAT* of the amplification module 100. The first terminal ACT of the amplification module 100 is connected to the first power supply terminal, and the second terminal NLAT* of the amplification module 100 is connected to the second power supply terminal.

[0095] The write module 200 includes a third N-type transistor N3 and a fourth N-type transistor N4. The first terminal of the third N-type transistor N3 is connected to the bit line BL, and the second terminal of the third N-type transistor N3 is connected to the input / output line I / O. The first terminal of the fourth N-type transistor N4 is connected to the complementary bit line BLB, and the second terminal of the fourth N-type transistor N4 is connected to the complementary input / output line I / O*.

[0096] The following is combined Figure 2A Describe the timing sequence of writing data into a storage unit, assuming the stored data is "1" and the written data is "0":

[0097] During the charge sharing phase, the word line signal on the word line is valid, the transistor in the memory cell is turned on, the capacitor in the memory cell shares charge with the bit line BL, and the voltage of the bit line BL increases.

[0098] In the sensing amplification phase T2, the amplification module 100 further drives the bit line BL and the complementary bit line BLB, so that the voltage of the bit line BL reaches the voltage VH of the first power supply end, and the voltage of the complementary bit line BLB reaches the voltage VL of the second power supply end.

[0099] In the write phase T1, the column selection signal CL0 on the column selection line CSEL is effective, the third N-type transistor N3 and the fourth N-type transistor N4 in the write module 200 are turned on, and the voltage of the bit line BL and the complementary bit line BLB driven by the enhanced write data is increased. Since the write data is different from the data in the storage unit, the voltage of the complementary bit line BLB is increased, and the voltage of the bit line BL is decreased. When the voltage of the bit line BL and the complementary bit line BLB reaches the voltage of the trip point (Vtrip) in the amplification module 100, positive feedback is formed in the amplification module 100.

[0100] In the recovery phase T3, the amplification module 100 further drives the voltage of the bit line BL and the complementary bit line BLB, so that the voltage of the complementary bit line BLB reaches the voltage VH of the first power supply end, and the voltage of the bit line BL reaches the voltage VL of the second power supply end. The capacitor in the storage unit discharges to the bit line BL, and the write data in the storage unit is realized.

[0101] In the write phase T1, the pulse width of the column selection signal CL0 affects the time when the write module 200 drives the bit line BL and the complementary bit line BLB. If the pulse width of the column selection signal CL0 is relatively small, the time when the write module 200 drives the bit line BL and the complementary bit line BLB is short, and the write module 200 has stopped driving the bit line BL and the complementary bit line BLB when the voltage on the bit line BL and the complementary bit line BLB has not reached the voltage of the trip point. Therefore, positive feedback cannot be formed in the amplification module 100, and data writing fails. If the pulse width of the column selection signal CL0 is relatively large, the time when the write module 200 drives the bit line BL and the complementary bit line BLB is long, and the write module 200 is still driving the bit line BL and the complementary bit line BLB when the voltage on the bit line BL and the complementary bit line BLB has reached the voltage of the trip point. Therefore, the parameter performance of the write time is lost.

[0102] Therefore, in the design of the sense amplifier, the pulse width of the column selection signal CL0 is designed reasonably. However, the voltage driving capability of the write module 200 changes with temperature. For example, Figure 2BAs shown, when the temperature decreases, that is, the sensitive amplifier works in low temperature conditions, the voltage driving ability of the write module 200 becomes stronger, which will make the bit line BL and the complementary bit line BLB reach the inversion point voltage in advance under the driving of the write module 200, that is, after the bit line BL and the complementary bit line BLB reach the inversion point voltage, the write module still continues to drive the bit line BL and the complementary bit line BLB, which loses the parameter performance of the write time. As shown in FIG. 2B, Figure 2C As shown, when the temperature increases, that is, the sensitive amplifier works in high temperature, the voltage driving ability of the write module 200 becomes weaker, which will make the bit line BL and the complementary bit line BLB unable to reach the inversion point voltage in the expected time under the driving of the write module 200, when the write module 200 stops driving the bit line BL and the complementary bit line BLB, the voltage of the bit line BL and the complementary bit line BLB does not reach the inversion point voltage, which causes the write data to fail.

[0103] To solve the above problems, the present disclosure provides a sensitive amplifier and a semiconductor memory, the sensitive amplifier comprising a control module 300, a write module 200 and an amplification module 100. The control module 300 adjusts the pulse width of the first column selection signal CL1 according to the temperature data of the write module 200, so as to compensate for the case that the voltage driving ability of the write module 200 changes with the temperature, so that the bit line BL and the complementary bit line BLB reach the inversion point voltage in the expected time under the driving of the write module 200, guaranteeing the successful write data and improving the performance parameter of the write time.

[0104] As shown in FIG. 1A, Figure 3 An embodiment of the present disclosure provides a sensitive amplifier, comprising a control module 300, a write module 200 and an amplification module 100. The control module 300 is provided with an input end and an output end, and the write module 200 is provided with a control end.

[0105] The control end of the write module 200 is connected to the output end of the control module 300, the input end of the control module 300 receives the first column selection signal CL1, the control module 300 acquires the temperature data of the write module 200, and adjusts the pulse width of the first column selection signal CL1 according to the temperature data to output the second column selection signal CL2. The write module 200 drives the voltage of the bit line BL and the complementary bit line BLB according to the write data under the control of the second column selection signal CL2 in the write stage T1, and the amplification module 100 amplifies the voltage difference of the bit line BL and the complementary bit line BLB.

[0106] In some embodiments, the control module 300 can directly detect the temperature data of the write module 200, and also can detect the temperature data of the amplification module 100, and take the temperature data of the amplification module 100 as the temperature data of the write module 200.

[0107] In some embodiments, when the temperature data of the write module 200 is high, the pulse width of the second column selection signal CL2 output by the control module 300 is relatively large, compensating for the situation that the voltage driving capability of the write module 200 becomes weak, so that the write module 200 has sufficient time to drive the voltage on the bit line BL and the complementary bit line BLB to the inversion point voltage, and ensures that the write module 200 stops driving the bit line BL and the complementary bit line BLB when the voltage on the bit line BL and the complementary bit line BLB reaches the inversion point voltage.

[0108] In some embodiments, when the temperature data of the write module 200 is high, the pulse width of the second column selection signal CL2 output by the control module 300 is relatively large, compensating for the situation that the voltage driving capability of the write module 200 becomes weak, so that the write module 200 has sufficient time to drive the voltage on the bit line BL and the complementary bit line BLB to the inversion point voltage, and ensures that the write module 200 stops driving the bit line BL and the complementary bit line BLB when the voltage on the bit line BL and the complementary bit line BLB reaches the inversion point voltage.

[0109] In the above technical solution, the sensitive amplifier is provided with the control module 300, the write module 200 and the amplification module 100, the output end of the control module 300 is connected with the control end of the write module 200, the write module 200 and the amplification module 100 are connected with the bit line BL and the complementary bit line BLB, the control module 300 adjusts the pulse width of the first column selection signal CL1 according to the temperature data of the write module 200, to compensate for the situation that the voltage driving capability of the write module 200 changes with temperature, so that the write module 200 drives the bit line BL and the complementary bit line BLB to reach the inversion point voltage at the expected time, ensures successful data writing, and improves the performance parameter of the write time.

[0110] In some embodiments, as shown in Figure 4 The control module 300 includes a pulse width parameter unit 320 and a pulse width adjusting unit 310, the pulse width parameter unit 320 includes an output end, the pulse width adjusting unit 310 includes an input end, an output end and a control end, and the control end of the pulse width adjusting unit 310 is connected with the output end of the pulse width parameter unit 320.

[0111] The pulse width parameter unit 320 obtains the temperature data of the write module 200, and generates a pulse width adjusting signal according to the temperature data of the write module 200. The input end of the pulse width adjusting unit 310 receives the first column selection signal CL1, the control end of the pulse width adjusting unit 310 receives the pulse width adjusting signal, and the pulse width adjusting unit 310 adjusts the pulse width of the first column selection signal CL1 under the control of the pulse width adjusting signal to output the second column selection signal CL2.

[0112] In some embodiments, when the temperature data of the write module 200 is relatively high, the pulse width adjustment signal controls the pulse width of the second column selection signal CL2 output by the pulse width adjustment unit 310 to be relatively large. When the temperature data of the write module 200 is relatively low, the pulse width adjustment signal controls the pulse width of the second column selection signal CL2 output by the pulse width adjustment unit 310 to be relatively small.

[0113] In the above technical solution, the control module 300 includes a pulse width parameter unit 320 and a pulse width adjustment unit 310. The pulse width parameter unit generates a pulse width adjustment signal according to the temperature data of the write module 200. The pulse width adjustment unit 310 adjusts the pulse width of the first column selection signal CL1 under the control of the pulse width adjustment signal to compensate for the change of the voltage driving capability of the write module 200 with temperature.

[0114] In some embodiments, as shown in Figure 4 The pulse width parameter unit 320 includes a temperature sensor 321 and a temperature decoder 322. The temperature sensor 321 is provided with an output terminal, and the temperature decoder 322 is provided with an input terminal and an output terminal. The output terminal of the temperature sensor 321 is connected to the input terminal of the temperature decoder 322. The temperature sensor 321 detects the temperature data of the write module 200 and encodes the temperature data to generate temperature encoded data. The temperature decoder 322 generates a pulse width adjustment signal according to the temperature encoded data.

[0115] In some embodiments, the temperature decoder 322 decodes the temperature encoded data, compares the decoding result with each temperature range to obtain the gear information corresponding to the temperature data, and generates the pulse width adjustment signal according to the gear information of the temperature data.

[0116] In some embodiments, the pulse width parameter unit 320 includes a plurality of output terminals, and the pulse width adjustment signal includes a plurality of gate signals. Each output terminal of the pulse width parameter unit 320 outputs one gate signal.

[0117] In some embodiments, the pulse width adjustment unit 310 includes a plurality of adjustment sub-units and a selection unit 314. The selection unit 314 is provided with a plurality of input terminals and a plurality of control terminals. The output terminal of each adjustment sub-unit is connected to the corresponding input terminal of the selection unit 314, and each control terminal of the selection unit 314 is connected to the corresponding output terminal of the pulse width parameter unit 320.

[0118] The input end of each adjusting sub-unit receives the first column selection signal CL1 and pulse width adjusts the first column selection signal CL1. The pulse width adjusting amount of each adjusting sub-unit is different, so that the pulse width of the signal output by each adjusting sub-unit is different. The control end of each selection unit 314 receives a corresponding selection signal, and the selection unit 314 selects an output from the output signals of the plurality of adjusting sub-units under the control of the plurality of selection signals, and the selection unit 314 outputs a signal to control the write module 200 to drive the voltage of the bit line BL and the complementary bit line BLB according to the write data.

[0119] In the above technical solution, the pulse width adjusting unit 310 is provided with a selection unit 314 and a plurality of adjusting sub-units, the output end of each adjusting sub-unit is connected with a corresponding input end of the selection unit 314, the pulse width of the signal output by each adjusting sub-unit is different, the pulse width parameter unit 320 generates a pulse width adjusting signal according to the temperature data of the write module 200, and the selection unit 314 selects an output from the output signals of each adjusting sub-unit according to the pulse width adjusting signal, so as to adjust the pulse width of the first column selection signal CL1 according to the temperature data.

[0120] In some embodiments, three temperature range ranges are provided, which are marked as a first temperature range, a second temperature range and a third temperature range. The upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range. For example, the first temperature range is T≤20℃, the second temperature range is 20℃<T≤60℃, and the third temperature range is T>60℃.

[0121] When the temperature data is in the first temperature range, the first selection signal output by the pulse width parameter unit 320 is a valid value, and the second selection signal and the third selection signal output by the pulse width parameter unit 320 are invalid values. When the temperature data is in the second temperature range, the second selection signal output by the pulse width parameter unit 320 is a valid value, and the first selection signal and the third selection signal output by the pulse width parameter unit 320 are invalid values. When the temperature data is in the third temperature range, the third selection signal output by the pulse width parameter unit 320 is a valid value, and the first selection signal and the second selection signal output by the pulse width parameter unit 320 are invalid values.

[0122] In some embodiments, as Figure 4As shown, the pulse width adjusting unit 310 includes three adjusting sub-units, marked as a first adjusting sub-unit 311, a second adjusting sub-unit 312 and a third adjusting sub-unit 313. The first adjusting sub-unit 311 pulse width adjusts the first column selection signal CL1 to output a third column selection signal CL3, the second adjusting sub-unit 312 pulse width adjusts the first column selection signal CL1 to output a fourth column selection signal CL4, and the third adjusting sub-unit 313 pulse width adjusts the first column selection signal CL1 to output a fifth column selection signal CL5.

[0123] The pulse width adjusting signals include three gate signals, a first gate signal controls the first adjusting sub-unit 311 to output a signal, a second gate signal controls the second adjusting sub-unit 312 to output a signal, and a third gate signal controls the third adjusting sub-unit 313 to output a signal.

[0124] In some embodiments, the pulse width of the output signal of the first adjusting sub-unit 311 is smaller than the pulse width of the output signal of the second adjusting sub-unit 312, and the pulse width of the output signal of the second adjusting sub-unit 312 is smaller than the pulse width of the output signal of the third adjusting sub-unit 313.

[0125] When the temperature data is in the first temperature range, the first gate signal output by the pulse width parameter unit 320 is a valid value, the second gate signal and the third gate signal output by the pulse width parameter unit 320 are invalid values, and the selection unit 314 selects the output signal of the first adjusting sub-unit 311 under the control of the three gate signals.

[0126] When the temperature data is in the second temperature range, the second gate signal output by the pulse width parameter unit 320 is a valid value, the first gate signal and the third gate signal output by the pulse width parameter unit 320 are invalid values, and the selection unit 314 selects the output signal of the second adjusting sub-unit 312 under the control of the three gate signals.

[0127] When the temperature data is in the third temperature range, the third gate signal output by the pulse width parameter unit 320 is a valid value, the first gate signal and the second gate signal output by the pulse width parameter unit 320 are invalid values, and the selection unit 314 selects the output signal of the third adjusting sub-unit 313 under the control of the three gate signals.

[0128] In the technical solution, the pulse width parameter unit 320 determines whether the three selection signals output from the output end of the pulse width parameter unit 320 are valid according to the temperature data of the write module 200, the selection unit 314 selects one output signal from the three adjustment sub-units under the control of the three selection signals, when the temperature data of the write module 200 is high, the output signal of the third adjustment sub-unit 313 is selected and output, and when the temperature data of the write module 200 is low, the output signal of the first adjustment sub-unit 311 is selected and output, so as to compensate the change of the voltage driving capability of the write module 200 with the change of the temperature data.

[0129] In some embodiments, as shown in Figure 5A The first adjustment sub-unit 311 includes a first delay circuit 520 and a first OR gate 510, the first delay circuit 520 is provided with an input end and an output end, the first OR gate 510 is provided with a first input end In1, a second input end In2 and an output end Out1, and the output end of the first delay circuit 520 is connected with the second input end In2 of the first OR gate 510.

[0130] The input end of the first delay circuit 520 receives the first column selection signal CL1, and the first delay circuit 520 delays and processes the first column selection signal CL1 to output a first delay signal. The first input end In1 of the first OR gate 510 receives the first column selection signal CL1, and the second input end In2 of the first OR gate 510 receives the first delay signal. After the first OR gate 510 performs OR operation on the first delay signal and the first column selection signal CL1, the third column selection signal CL3 is output via the output end Out1.

[0131] In some embodiments, as shown in Figure 5A The first delay circuit 520 includes a first buffer 521 and a second buffer 522, the input end of the first buffer 521 is used as the input end of the first delay circuit 520, and the output end of the first buffer 521 is connected with the input end of the second buffer 522. The input end of the first buffer 521 receives the first column selection signal CL1, and the first column selection signal CL1 is output after signal enhancement by the two buffers. The output first delay signal and the first column selection signal CL1 are low-level pulse signals or high-level pulse signals, the pulse width of the first delay signal is the same as that of the first column selection signal CL1, but the falling edge time of the first delay signal is later than that of the first column selection signal CL1, or the rising edge time of the first delay signal is later than that of the first column selection signal CL1.

[0132] The first column selection signal is a high-level pulse signal. As shown in Figure 5BAs shown, the first input end In1 of the first OR gate 510 receives the first column selection signal CL1, and the second input end In2 of the first OR gate 510 receives the first delay signal, and the time difference Δτ1 between the rising edge time of the first delay signal and the rising edge time of the first column selection signal CL1. After the first OR gate 510 performs OR operation, the third column selection signal CL3 is output via the output end Out1, the third column selection signal CL3 is still a high-level pulse signal, and the pulse width of the third column selection signal CL3 is greater than the pulse width of the first column selection signal CL1, and the increase of the pulse width is Δτ1.

[0133] In some embodiments, as shown in FIG. 5, the second adjusting subunit 312 includes a second delay circuit 540 and a second OR gate 530. The second delay circuit 540 is provided with an input end and an output end. The second OR gate 530 is provided with a first input end In3, a second input end In4, and an output end Out2. The second input end In4 of the second OR gate 530 is connected with the output end of the second delay circuit 540. Figure 6A

[0134] The input end of the second delay circuit 540 receives the first column selection signal CL1, and the second delay circuit 540 performs delay processing on the first column selection signal CL1 to output the second delay signal. The delay amount of the delay processing performed by the second delay circuit 540 is greater than the delay amount of the delay processing performed by the first delay circuit 520. That is, when the first delay signal is a high-level pulse signal, the time difference Δτ1 between the rising edge time of the first delay signal and the rising edge time of the first column selection signal CL1 is less than the time difference Δτ2 between the rising edge time of the second delay signal and the rising edge time of the first column selection signal CL1.

[0135] The first input end In3 of the second OR gate 530 receives the first column selection signal CL1, and the second input end In4 of the second OR gate 530 receives the second delay signal. After the second OR gate 530 performs OR operation on the second delay signal and the first column selection signal CL1, the fourth column selection signal CL4 is output via the output end Out2.

[0136] In some embodiments, as shown in FIG. 5, the second adjusting subunit 312 includes a second delay circuit 540 and a second OR gate 530. The second delay circuit 540 is provided with an input end and an output end. The second OR gate 530 is provided with a first input end In3, a second input end In4, and an output end Out2. The second input end In4 of the second OR gate 530 is connected with the output end of the second delay circuit 540. Figure 6A ​As shown, the second delay circuit 540 includes a third buffer 523, a fourth buffer 524, a fifth buffer 525, and a sixth buffer 526. The input end of the fourth buffer 524 is connected with the output end of the third buffer 523, the input end of the fifth buffer 525 is connected with the output end of the fourth buffer 524, and the input end of the sixth buffer 526 is connected with the output end of the fifth buffer 525. The input end of the third buffer 523 receives the first column selection signal CL1, and the first column selection signal CL1 is output after being enhanced by the four buffers. Compared with the delay amount of the first delay signal relative to the first column selection signal CL1, the delay amount of the output second delay signal relative to the first column selection signal CL1 is larger.

[0137] The first column selection signal is a high-level pulse signal. As shown in Figure 6B As shown, the first input end In3 of the second OR gate 530 receives the first column selection signal CL1, and the second input end In4 of the second OR gate 530 receives the second delay signal. The time difference Δτ2 between the rising edge time of the second delay signal and the rising edge time of the first column selection signal CL1. After the second OR gate 530 performs OR operation on the second delay signal and the first column selection signal CL1, the fourth column selection signal CL4 is output via the output end Out2. The fourth column selection signal CL4 is still a high-level pulse signal, and the pulse width of the fourth column selection signal CL4 is greater than the pulse width of the first column selection signal CL1. The increase amount of the pulse width is Δτ2, and the pulse width of the fourth column selection signal CL4 is greater than the pulse width of the third column selection signal CL3.

[0138] In some embodiments, as shown in Figure 7A As shown, the third adjustment subunit 313 includes a third delay circuit 560 and a third OR gate 550. The third delay circuit 560 includes an input end and an output end, and the third OR gate 550 is provided with a first input end In5, a second input end In6, and an output end Out3. The second input end In6 of the third OR gate 550 is connected with the output end of the third delay circuit 560. The input end of the third delay circuit 560 receives the first column selection signal CL1, the third delay circuit 560 performs delay processing on the first column selection signal CL1 to output a third delay signal, and the delay amount of the delay processing performed by the third delay circuit 560 is greater than the delay amount of the delay processing performed by the second delay circuit 540.

[0139] That is, when the second delay signal is a high-level pulse signal, the time difference Δτ2 between the rising edge time of the second delay signal and the rising edge time of the first column selection signal CL1 is less than the time difference Δτ3 between the rising edge time of the third delay signal and the rising edge time of the first column selection signal CL1.

[0140] The first input terminal In5 of the third OR gate 550 receives the first column selection signal CL1, and the second input terminal In6 of the third OR gate 550 receives the third delay signal. After performing an OR operation on the third delay signal and the first column selection signal CL1, the third OR gate 550 outputs the fifth column selection signal CL5 through the output terminal Out3.

[0141] In some embodiments, such as Figure 7A As shown, the third delay circuit 560 includes a seventh buffer 527, an eighth buffer 528, a ninth buffer 529, a tenth buffer 531, an eleventh buffer 532, and a twelfth buffer 533. The input terminal of the eighth buffer 528 is connected to the output terminal of the seventh buffer 527, the input terminal of the ninth buffer 529 is connected to the output terminal of the eighth buffer 528, the input terminal of the tenth buffer 531 is connected to the output terminal of the ninth buffer 529, the input terminal of the eleventh buffer 532 is connected to the output terminal of the tenth buffer 531, and the input terminal of the twelfth buffer 533 is connected to the output terminal of the eleventh buffer 532.

[0142] The input of the seventh buffer 527 receives the first column selection signal CL1. The first column selection signal CL1 is amplified by six buffers and then output. Compared with the delay of the second delay signal relative to the first column selection signal CL1, the delay of the output third delay signal is greater than that of the first column selection signal CL1.

[0143] The first column selection signal CL1 is a high-level pulse signal. For example... Figure 7B As shown, the first input terminal In5 of the third OR gate 550 receives the first column selection signal CL1, and the second input terminal In6 of the third OR gate 550 receives the third delayed signal. The time difference between the rising edge of the third delayed signal and the rising edge of the first column selection signal CL1 is Δτ3. After performing an OR operation on the first column selection signal CL1 and the third delayed signal, the third OR gate 550 outputs the fifth column selection signal CL5 via the output terminal Out3. The fifth column selection signal CL5 is still a high-level pulse signal, and the pulse width of the fifth column selection signal CL5 is greater than the pulse width of the first column selection signal CL1 by an increase of Δτ3. The pulse width of the fifth column selection signal CL5 is greater than the pulse width of the fourth column selection signal CL4.

[0144] In some embodiments, such as Figure 8 As shown, the control module 300 also includes a fifth inverter 315. The input terminal of the fifth inverter 315 is connected to the output terminal of the selection unit 314. The second column selection signal CL2 output by the selection unit 314 is not operated on and then output. The output signal of the fifth inverter 315 is used to control the write module 200 to drive the bit line BL and the complementary bit line BLB according to the write data.

[0145] In some embodiments, as shown in FIG. 5, the first adjusting subunit 311 includes a first delay circuit 520 and a first AND gate 610. The first AND gate 610 is provided with a first input end R1, a second input end R2, and an output end O1. The output end of the first delay circuit 520 is connected to the second input end R2 of the first AND gate 610. The first input end R1 of the first AND gate 610 receives the first column selection signal CL1, and the second input end R2 of the first AND gate 610 receives a first delay signal. The first AND gate 610 performs AND operation on the first delay signal and the first column selection signal CL1, and outputs a third column selection signal CL3 via the output end O1. Figure 9A The first column selection signal CL1 is a low-level pulse signal. After the first column selection signal CL1 is processed by the first delay circuit 520, the output first delay signal is still a low-level pulse signal, and the falling edge time of the first delay signal is later than the falling edge time of the first column selection signal CL1.

[0146] As shown in FIG. 5, the first input end R1 of the first AND gate 610 receives the first column selection signal CL1, and the second input end R2 of the first AND gate 610 receives the first delay signal. The first AND gate 610 performs AND operation on the first column selection signal CL1 and the first delay signal, and outputs the third column selection signal CL3. The third column selection signal CL3 is still a low-level pulse signal, and the pulse width of the third column selection signal CL3 is greater than the pulse width of the first column selection signal CL1. The increase in the pulse width is the time difference Δτ4 between the falling edge time of the first delay signal and the falling edge time of the first column selection signal CL1. When the selection unit 314 selects the third column selection signal CL3 for output, the fifth inverter 315 performs non-operation on the output signal of the selection unit 314, and outputs a high-level pulse signal. Figure 9B In some embodiments, as shown in FIG. 5, the second adjusting subunit 312 includes a second delay circuit 540 and a second AND gate 620. The second AND gate 620 is provided with a first input end R3, a second input end R4, and an output end O2. The output end of the second delay circuit 540 is connected to the second input end R4 of the second AND gate 620. The first input end R3 of the second AND gate 620 receives the first column selection signal CL1, and the second input end R4 of the second AND gate 620 receives a second delay signal. The second AND gate 620 performs AND operation on the second delay signal and the first column selection signal CL1, and outputs a fourth column selection signal CL4 via the output end O2.

[0147] Figure 10A As shown in FIG. 5, the first input end R1 of the first AND gate 610 receives the first column selection signal CL1, and the second input end R2 of the first AND gate 610 receives the first delay signal. The first AND gate 610 performs AND operation on the first column selection signal CL1 and the first delay signal, and outputs the third column selection signal CL3. The third column selection signal CL3 is still a low-level pulse signal, and the pulse width of the third column selection signal CL3 is greater than the pulse width of the first column selection signal CL1. The increase in the pulse width is the time difference Δτ4 between the falling edge time of the first delay signal and the falling edge time of the first column selection signal CL1. When the selection unit 314 selects the third column selection signal CL3 for output, the fifth inverter 315 performs non-operation on the output signal of the selection unit 314, and outputs a high-level pulse signal.

[0148] ​The first column selection signal CL1 is a low-level pulse signal. After being delayed by the second delay circuit 520, the output second delayed signal is still a low-level pulse signal, and the falling edge of the second delayed signal is later than the falling edge of the first column selection signal CL1. Furthermore, the time difference Δτ4 between the falling edge of the first delayed signal and the falling edge of the first column selection signal CL1 is less than the time difference Δτ5 between the falling edge of the second delayed signal and the falling edge of the first column selection signal CL1.

[0149] like Figure 10B As shown, the first input of the second AND gate 620 receives the first column selection signal CL1, and the second input receives the second delayed signal. The second AND gate 620 performs an AND operation on the second delayed signal and the first column selection signal CL1, outputting a fourth column selection signal CL4. The fourth column selection signal CL4 is still a low-level pulse signal, and its pulse width is greater than that of the first column selection signal CL1. The increase in pulse width is equal to the time difference Δτ5 between the falling edge of the second delayed signal and the falling edge of the first column selection signal CL1. When the selection unit 314 selects the fourth column selection signal CL4 for output, the fifth inverter 315 performs a NOT operation on the output signal of the selection unit 314, outputting a high-level pulse signal.

[0150] In some embodiments, such as Figure 11A As shown, the third adjustment subunit 313 includes a third delay circuit 560 and a third AND gate 630. The third AND gate 630 has a first input terminal R5, a second input terminal R6, and an output terminal O3. The output terminal of the third delay circuit 560 is connected to the second input terminal R6 of the third AND gate 630. The first input terminal R5 of the third AND gate 630 receives the first column selection signal CL1, and the second input terminal R6 of the third AND gate 630 receives the third delay signal. After performing an AND operation on the third delay signal and the first column selection signal CL1, the third AND gate 630 outputs the fifth column selection signal CL5 through the output terminal O3.

[0151] The first column selection signal CL1 is a low-level pulse signal. After being delayed by the first delay circuit 520, the output first delayed signal is still a low-level pulse signal, and the falling edge of the first delayed signal is later than the falling edge of the first column selection signal CL1. Furthermore, the time difference Δτ5 between the falling edge of the second delayed signal and the falling edge of the first column selection signal CL1 is less than the time difference Δτ6 between the falling edge of the third delayed signal and the falling edge of the first column selection signal CL1.

[0152] like Figure 11BAs shown, the first input end R5 of the third AND gate 630 receives the first column selection signal CL1, and the second input end R6 of the third AND gate 630 receives the third delay signal. The third AND gate 630 outputs the fifth column selection signal CL5 after performing AND operation on the third delay signal and the first column selection signal CL1. The fifth column selection signal CL5 is still a low-level pulse signal, and the pulse width of the fifth column selection signal CL5 is greater than the pulse width of the first column selection signal CL1. The increase of the pulse width is the time difference Δτ6 between the falling edge time of the third delay signal and the falling edge time of the first column selection signal CL1. When the selection unit 314 selects the fifth column selection signal CL5 to output, the selection unit 314 outputs a high-level pulse signal after the non-operation of the fifth inverter 315 on the selection unit 314 output signal.

[0153] In some embodiments, continuing to refer to Figure 3 , the sensitive amplifier further comprises a driving module 400. The driving module 400 comprises an input end and an output end. The write module 200 is connected with the input / output line I / O and the complementary input / output line I / O*. The output end of the driving module 400 is connected with the input / output line I / O and the complementary input / output line I / O*. The driving module 400 input end receives the write data. The driving module 400 outputs the write data after signal enhancement. The write module 200 receives the write data after signal enhancement from the input / output line I / O and the complementary input / output line I / O*, and drives the bit line BL and the complementary bit line BLB according to the write data after signal enhancement under the control of the second column selection signal CL2.

[0154] In some embodiments, the control end of the write module 200 is connected with the column selection line CSEL. The output end of the control module 300 is connected with the column selection line CSEL. The control module 300 transmits the second column selection signal CL2 to the control end of the write module through the column selection line CSEL.

[0155] In some embodiments, continuing to refer to Figure 3 , the amplification module 100 comprises a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1 and a second N-type transistor N2. The connection relationship among the transistors in the amplification module 100 has been described in Figure 1 , and will not be repeated here.

[0156] In some embodiments, the write data includes first write data D and first complementary write data D*, the write module 200 includes a third N-type transistor N3 and a fourth N-type transistor N4, the second end of the third N-type transistor N3 receives the first write data D, the first end of the third N-type transistor N3 is connected to the bit line BL, the gate of the third N-type transistor N3 serves as the control end of the write module 200 and receives the second column selection signal CL2. The second end of the fourth N-type transistor N4 receives the first complementary write data D*, the first end of the fourth N-type transistor N4 is connected to the complementary bit line BLB, and the gate of the fourth N-type transistor N4 serves as the control end of the write module 200 and receives the second column selection signal CL2.

[0157] In some embodiments, when the first end of the third N-type transistor N3 and the fourth N-type transistor N4 is a drain, the second end of the third N-type transistor N3 and the fourth N-type transistor N4 is a source. When the first end of the third N-type transistor N3 and the fourth N-type transistor N4 is a source, the second end of the third N-type transistor N3 and the fourth N-type transistor N4 is a drain.

[0158] In some embodiments, continuing to refer to Figure 3 , the drive module 400 includes a first inverter 401, a second inverter 402, a third inverter 403, and a fourth inverter 404. The output end of the first inverter 401 is connected to the input end of the second inverter 402, and the output end of the third inverter 403 is connected to the input end of the fourth inverter 404.

[0159] The input end of the first inverter 401 receives the first write data D, and after the first write data D is subjected to two NOT operations, the potential remains unchanged and the signal is enhanced. The input end of the third inverter 403 receives the first complementary write data D*, and after the first complementary write data D* is subjected to two NOT operations, the potential remains unchanged and the signal is enhanced.

[0160] In some embodiments, when the first column selection signal CL1 is a low-level pulse signal, the pulse width adjusting unit 310 is provided with a fifth inverter 315 to output the low-level pulse signal output by the selection unit 314 to the column selection line CSEL after being subjected to a NOT operation. When the first column selection signal CL1 is a high-level pulse signal, the pulse width adjusting unit 310 does not need to be provided with the fifth inverter 315, and the selection unit 314 outputs the high-level pulse signal to the column selection line CSEL.

[0161] The following describes the working timing when data is written into the storage unit under the condition that the storage data of the storage unit is "1" and the write data is "0":

[0162] In the charge sharing phase, the second column selection signal CL2 on the column selection line CSEL word line is low, the third N-type transistor N3 and the fourth N-type transistor N4 are turned off. And the first end ACT of the amplification module 100 is disconnected with the first power supply end, the second end NLAT* of the amplification module 100 is disconnected with the second power supply end. The word line signal is effective, the transistor in the storage unit is turned on, the capacitor in the storage unit shares the charge with the bit line BL, and the voltage of the bit line BL is raised.

[0163] In the sensing amplification phase T2, the second column selection signal CL2 on the column selection line CSEL word line is low, the third N-type transistor N3 and the fourth N-type transistor N4 are turned off. And the first end of the amplification module 100 is connected to the first power supply end ACT, the second end of the amplification module 100 is connected to the second power supply end NLAT*, and the amplification module 100 further drives the voltages on the bit line BL and the complementary bit line BLB to form a larger voltage difference on the bit line BL and the complementary bit line BLB.

[0164] In the write phase T1, the second column selection signal CL2 on the column selection line CSEL is high, the third N-type transistor N3 and the fourth N-type transistor N4 are turned on, and the enhanced first write data D and the first complementary write data D* drive the voltages of the bit line BL and the complementary bit line BLB through the third N-type transistor N3 and the fourth N-type transistor N4.

[0165] Because the write data is different from the data in the storage unit, the voltage of the complementary bit line BLB rises, and the voltage of the bit line BL drops, so that the voltages on the bit line BL and the complementary bit line BLB reach the inversion point voltage of the inverting pair in the amplification module 100. After the bit line BL and the complementary bit line BLB reach the inversion point voltage, a positive feedback is formed in the amplification module 100, and the amplification module 100 further drives the voltages of the bit line BL and the complementary bit line BLB, so that the voltage of the complementary bit line BLB reaches the voltage VH of the first power supply end, and the voltage of the bit line BL is the voltage VL of the second power supply end.

[0166] As shown in Figure 12A When the temperature data of the amplification module 100 is low, the selection unit 314 selects the output signal with smaller pulse width from the plurality of adjustment sub-units, that is, the third N-type transistor N3 and the fourth N-type transistor N4 are turned on for a shorter time, to compensate for the situation that the voltage driving capability of the third N-type transistor N3 and the fourth N-type transistor N4 is stronger due to the lower temperature data, so that the third N-type transistor N3 and the fourth N-type transistor N4 are turned off in time when the enhanced first write data D and the first complementary write data D* drive the bit line BL and the complementary bit line BLB to reach the inversion point voltage, and the performance parameter of the write time is improved.

[0167] As shown in Figure 12BAs shown, when the temperature data of the amplification module 100 is high, the selection unit 314 selects the output signal with a larger pulse width from the plurality of adjustment sub-units, that is, the third N-type transistor N3 and the fourth N-type transistor N4 have a longer conduction time, to compensate for the case that the voltage driving capability of the third N-type transistor N3 and the fourth N-type transistor N4 becomes weak due to the high temperature data, so that the enhanced first write data D and the first complementary write data D* have sufficient time to drive the bit line BL and the complementary bit line BLB to the inversion point voltage. When the third N-type transistor N3 and the fourth N-type transistor N4 are turned off, the bit line BL and the complementary bit line BLB reach the inversion point voltage, ensuring that the data is successfully written into the storage unit.

[0168] In the recovery phase T3, the second column selection signal CL2 on the column selection line CSEL is low, the third N-type transistor N3 and the fourth N-type transistor N4 are cut off, the first end of the amplification module 100 is connected to the first power supply end, the second end of the amplification module 100 is connected to the second power supply end, and the amplification module 100 further drives the voltage of the bit line BL and the complementary bit line BLB, so that the voltage of the complementary bit line BLB reaches the voltage VH of the first power supply end, and the voltage of the bit line BL is the voltage VL of the second power supply end. The storage unit discharges to the bit line BL, and the data is written in the storage unit.

[0169] In the above technical solution, the sensitive amplifier is provided with the control module 300, the write-in module 200 and the amplification module 100, the output end of the control module 300 is connected to the control end of the write-in module 200, the write-in module 200 and the amplification module 100 are connected to the bit line BL and the complementary bit line BLB, the control module 300 adjusts the pulse width of the first column selection signal CL1 according to the temperature data of the write-in module 200, to compensate for the case that the voltage driving capability of the write-in module 200 changes with the temperature, so that the write-in module 200 drives the bit line BL and the complementary bit line BLB to reach the inversion point voltage at the expected time, ensuring that the data is successfully written in, and improving the performance parameter of the write-in time.

[0170] An embodiment of the present disclosure provides a semiconductor memory including the sensitive amplifier related to the above-mentioned embodiments.

[0171] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the description herein, with the disclosure intended to cover any alternatives, modifications, and equivalents of the methods and compositions disclosed herein, as can be included within the spirit and scope of the disclosure as defined by the claims. The specification and examples are, therefore, to be considered as illustrative only, with the true scope and spirit of the disclosure being indicated by the following claims.

[0172] It should be understood that the present disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A sensitive amplifier, characterized in that, include: The control module has an input terminal and an output terminal. It is used to acquire the temperature data of the writing module, adjust the pulse width of the first column selection signal received at its input terminal according to the temperature data, and output the second column selection signal. The write module has a control terminal connected to the output terminal of the control module and connected to the bit line and the complementary bit line. Under the control of the second column selection signal, it drives the voltage of the bit line and the complementary bit line according to the write data during the write phase. Under the control of the second column selection signal, the write module drives the bit line and the complementary bit line to reach the inversion point voltage at a predetermined time. An amplification module, connected to the bit line and the complementary bit line, is used to amplify the voltage difference between the bit line and the complementary bit line.

2. The sensitive amplifier according to claim 1, characterized in that, The sensitive amplifier also includes: The driver module, which connects to the input / output lines and complementary input / output lines, is used to output the amplified written data.

3. The sensitive amplifier according to claim 1 or 2, characterized in that, The control module includes: The pulse width parameter unit has an output terminal for generating a pulse width adjustment signal based on the temperature data from the writing module. The pulse width adjustment unit has an input terminal, an output terminal, and a control terminal. The control terminal is connected to the output terminal of the pulse width parameter unit. The input terminal receives the first column selection signal and adjusts the pulse width of the first column selection signal according to the pulse width adjustment signal, and outputs the second column selection signal.

4. The sensitive amplifier according to claim 3, characterized in that, The pulse width parameter unit includes multiple output terminals, the pulse width adjustment signal includes multiple gating signals, and the pulse width adjustment unit includes: Multiple adjustment subunits are provided, and the output of each adjustment subunit is connected to the corresponding input of the selection unit. Each adjustment subunit is used to adjust the pulse width of the first column selection signal received at its input. The pulse width adjustment amount of each adjustment subunit is different. The selection unit has each control terminal connected to the output terminal of the corresponding pulse width parameter unit and receives the corresponding gating signal; it is used to select one output from the output signals of multiple adjustment subunits under the control of the multiple gating signals.

5. The sensitive amplifier according to claim 4, characterized in that, The pulse width adjustment unit includes three adjustment subunits, labeled as the first adjustment subunit, the second adjustment subunit, and the third adjustment unit; the pulse width parameter unit is used for: When the temperature data is within the first temperature range, the first strobe signal output is a valid value, while the second and third strobe signals output are invalid values; the selection unit is controlled to select the output signal of the first adjustment subunit for output; When the temperature data is within the second temperature range, the output second strobe signal is a valid value, while the output first and third strobe signals are invalid values; the selection unit is controlled to select the output signal of the second adjustment subunit for output; When the temperature data is within the third temperature range, the output third strobe signal is a valid value, while the output first strobe signal and second strobe signal are invalid values; the selection unit is controlled to select the output signal of the third adjustment subunit. Wherein, the upper limit of the first temperature range is less than or equal to the lower limit of the second temperature range, and the upper limit of the second temperature range is less than or equal to the lower limit of the third temperature range; the pulse width of the output signal of the first adjustment subunit is less than the pulse width of the output signal of the second adjustment subunit, and the pulse width of the output signal of the second adjustment subunit is less than the pulse width of the output signal of the third adjustment subunit.

6. The sensitive amplifier according to claim 4, characterized in that, The first adjustment subunit includes: The first delay circuit receives the first column selection signal at its input terminal and is used to perform delay processing on the first column selection signal to output a first delay signal. The first OR gate receives the first column selection signal at its first input terminal and is connected to the output terminal of the first delay circuit at its second input terminal. It receives the first delay signal and performs an OR operation on the first delay signal and the first column selection signal before outputting the result.

7. The sensitive amplifier according to claim 6, characterized in that, The first delay circuit includes: The first buffer has its input terminal used to receive the first column selection signal; The second buffer has its input connected to the output of the first buffer, and its output outputs the first delayed signal.

8. The sensitive amplifier according to claim 4, characterized in that, The second adjustment subunit includes: The second delay circuit receives the first column selection signal at its input terminal and performs delay processing on the first column selection signal to output a second delay signal; and the delay amount of the second delay circuit is greater than the delay amount of the first delay circuit. The second OR gate receives the first column selection signal at its first input terminal and is connected to the output terminal of the second delay circuit at its second input terminal. It receives the second delay signal and performs an OR operation on the second delay signal and the first column selection signal before outputting the result.

9. The sensitive amplifier according to claim 8, characterized in that, The second delay circuit includes: The third buffer has its input terminal used to receive the first column selection signal; The fourth buffer has its input terminal connected to the output terminal of the third buffer; The fifth buffer has its input terminal connected to the output terminal of the fourth buffer; The sixth buffer has its input connected to the output of the fifth buffer, and its output outputs the second delayed signal.

10. The sensitive amplifier according to claim 4, characterized in that, The third adjustment subunit includes: The third delay circuit receives the first column selection signal at its input terminal and performs delay processing on the first column selection signal to output a third delay signal; and the delay amount of the third delay circuit is greater than the delay amount of the second delay circuit. The third OR gate receives the first column selection signal at its first input terminal and is connected to the output terminal of the third delay circuit at its second input terminal. It receives the third delay signal and performs an OR operation on the third delay signal and the first column selection signal before outputting the result.

11. The sensitive amplifier according to claim 10, characterized in that, The third delay circuit includes: The seventh buffer has its input terminal used to receive the first column selection signal; The eighth buffer has its input terminal connected to the output terminal of the seventh buffer; The ninth buffer has its input terminal connected to the output terminal of the eighth buffer; The tenth buffer has its input terminal connected to the output terminal of the ninth buffer; The eleventh buffer has its input terminal connected to the output terminal of the tenth buffer. The twelfth buffer has its input connected to the output of the eleventh buffer, and its output outputs the third delayed signal.

12. The sensitive amplifier according to claim 3, characterized in that, The pulse width parameter unit includes: A temperature sensor is used to detect the temperature data of the writing module and generate temperature-coded data based on the temperature data; A temperature decoder, whose input is connected to the output of the temperature sensor, is used to generate the pulse width adjustment signal based on the temperature encoded data.

13. The sensitive amplifier according to claim 1, characterized in that, The writing module includes: The third N-type transistor has a second terminal that receives the first write data, a first terminal that is connected to the bit line, and a gate that is connected to the column select line to receive the second column select signal. The fourth N-type transistor has a second terminal that receives the first complementary write data, a first terminal that is connected to the complementary bit line, and a gate that is connected to the column select line to receive the second column select signal. The written data includes the first written data and the first complementary written data.

14. The sensitive amplifier according to claim 13, characterized in that, The amplification module includes: The source of the first P-type transistor is connected to the source of the second P-type transistor, the gate of the first P-type transistor is connected to the drain of the second P-type transistor, and the drain of the first N-type transistor is connected to the drain of the second P-type transistor. The second P-type transistor has its gate connected to the drain of the first P-type transistor and its drain connected to the drain of the second N-type transistor. The first N-type transistor has its gate connected to a complementary bit line, its gate connected to the drain of the second N-type transistor, and its source connected to the source of the second N-type transistor. The second N-type transistor has a gate connected to a bit line, and its gate is connected to the drain of the first N-type transistor.

15. The sensitive amplifier according to claim 2, characterized in that, The driving module includes: The first inverter receives the first written data at its input. The second inverter has its input terminal connected to the output terminal of the first inverter, and its output terminal outputs the first write data after signal enhancement. The third inverter receives the first complementary write data at its input. The fourth inverter has its input connected to the output of the third inverter, and its output is the first complementary write data after signal enhancement.

16. A semiconductor memory, characterized in that, Includes the sensitive amplifier as described in any one of claims 1 to 15.

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