Conditional drift cancellation operation for programming memory cells to store data

Abstract

This application relates to a conditional drift elimination operation for programming memory cells to store data. A memory device includes memory cells, a voltage driver, and a controller configured to determine, based on attributes of the memory cells, whether to apply a drift elimination pulse of opposite polarity to a programming pulse configured to place the memory cell in a state representing data bits. If the drift prediction of the state of the memory cell from a previous programming operation used to write data into the memory cell is insufficient to prevent selection of the memory cell during the application of the programming pulse, then the drift elimination pulse is skipped. Otherwise, the drift elimination pulse is applied of opposite polarity to the programming pulse.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein generally relate to programming memory cells to store data, and more specifically, but not limited to, to reducing energy consumption when programming memory cells. Background Technology

[0002] Memory integrated circuits may have one or more arrays of memory cells formed on an integrated circuit die made of semiconductor material. A memory cell is the smallest unit of memory that can be individually used or operated to store data. Generally, a memory cell can store one or more data bits.

[0003] Different types of memory cells have been developed for memory integrated circuits, such as random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and flash memory.

[0004] Some integrated circuit memory cells are volatile and require power to maintain the data stored in the cells. Examples of volatile memory include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).

[0005] Some integrated circuit memory cells are non-volatile and retain stored data even when no power is supplied. Examples of non-volatile memories include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). Flash memory includes NAND flash memory and NOR flash memory. NAND memory cells are based on NAND logic gates; and NOR memory cells are based on NOR logic gates.

[0006] Crosspoint memory (e.g., 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in crosspoint memory are transistorless. Each of these memory cells may have phase-change memory devices and selector devices stacked together as columns in an integrated circuit. These columns of memory cells are connected in the integrated circuit via two layers of wires extending in mutually perpendicular directions. One of the two layers is above the memory cells; and the other layer is below the column of memory elements. Therefore, each memory cell can be selected individually at the intersection of a wire on each of the two layers. Crosspoint memory devices are fast and non-volatile and can be used as a general-purpose memory pool for processing and storage.

[0007] During a programming / writing operation, a non-volatile integrated circuit memory cell is programmed to store data by applying a voltage or a voltage pattern to the memory cell. The programming / writing operation sets the memory cell in a state corresponding to the data being programmed / stored into the memory cell. Data stored in the memory cell can be retrieved during a read operation by checking the state of the memory cell. The read operation determines the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive at a voltage corresponding to a predefined state. Summary of the Invention

[0008] In one aspect, this application provides a method comprising: receiving a command to store data bits in a memory cell; in response to the command and based on attributes of the memory cell, determining whether to apply a drift elimination pulse to the memory cell before applying a programming pulse to the memory cell in a first polarity identified according to the data bits, wherein the drift elimination pulse is in a second polarity opposite to the first polarity; and programming the memory cell to store the data bits according to the result of the determination, wherein the programming includes: skipping the voltage elimination pulse in response to the result being a first option; or applying the voltage elimination pulse in response to the result being a second option.

[0009] In another aspect, this application provides an apparatus comprising: a plurality of memory cells; a plurality of voltage drivers including a first voltage driver connected to a respective memory cell among the plurality of memory cells and a second voltage driver connected to the memory cell, wherein the memory cell is configured to be in a first state via the first voltage driver and the second voltage driver driving a first voltage pulse on the memory cell in a first polarity, wherein the voltage driven by the first voltage driver is higher than the voltage driven by the second voltage driver; and a controller connected to the plurality of voltage drivers, wherein in response to a command configuring the memory cell to have a first state indicating that first data is stored in the memory cell, the controller is configured to determine, based on attributes of the memory cell, whether to apply a second voltage pulse to the memory cell in a second polarity opposite to the first polarity; and wherein the voltage driven by the first voltage driver is lower than the voltage driven by the second voltage driver in the second polarity.

[0010] In another aspect, this application provides an integrated circuit comprising: a plurality of bit line layers; a plurality of word line layers; a stack of a plurality of memory cells disposed in an array, each of the stacks being located between a bit line layer and a word line layer among the plurality of bit line layers, each of the bit line layers being connected to a row of memory cells in the array, and each of the word line layers being connected to a column of memory cells in the array; a bit line driver connected to the plurality of bit line layers; and a word line driver connected to the plurality of word line layers, wherein each corresponding memory cell in the stack is connected to both the bit line driver and the word line driver, wherein the bit line driver and the word line driver are configured to apply a voltage in positive polarity when a voltage driven by the bit line driver is higher than a voltage driven by the word line driver. The controller applies a voltage in the negative polarity when the voltage driven by the bit line driver is lower than the voltage driven by the word line; and a controller having a drift predictor configured to predict whether a memory cell has a drift in its current state based on the properties of the memory cell, the drift being sufficient to prevent the memory cell from being selected during a programming pulse applied by the bit line driver and the word line driver in a first polarity identified by the data bits to be stored in the memory cell; wherein, in response to the drift predictor determining that the drift is sufficient to prevent the memory cell from being selected during the programming pulse, the controller is configured to instruct the bit line driver and the word line driver to apply a drift cancellation pulse in a second polarity opposite to the first polarity before applying the programming pulse in the first polarity. Attached Figure Description

[0011] The embodiments are illustrated by way of example and not by way of limitation in the figures, in which similar references indicate similar elements.

[0012] Figure 1 A memory device configured with a drift predictor is shown according to one embodiment.

[0013] Figure 2 A memory cell having a bit line driver and a word line driver configured to apply voltage pulses is shown according to one embodiment.

[0014] Figures 3 to 6 This describes the voltage distribution on the memory cell and the current flowing through the memory cell during drift elimination and data programming operations according to one embodiment.

[0015] Figures 7 to 9 This describes some techniques, according to certain embodiments, to avoid polarity switching when programming memory cells.

[0016] Figure 10 A method for programming a memory cell is shown according to one embodiment. Detailed Implementation

[0017] At least some embodiments disclosed herein provide systems, methods, and apparatuses that reduce energy consumption when programming memory cells to store data by selectively skipping drift elimination operations before setting the state of memory cells according to the data to be stored.

[0018] For example, some implementations of cross-point memory use self-selecting memory cells with elements (e.g., unique elements) that act as both selector devices and memory devices. For instance, the memory cells may use a single-piece alloy with variable threshold capability. Read / write operations on such memory cells can be based on thresholding the memory cell while suppressing other cells in a subthreshold bias, similar to read / write operations on a memory cell having a first element acting as a selector device and a second element acting as a phase-change memory device, the memory cells stacked together in a column. A selector device that can be used to store information may be referred to as a selector / memory device.

[0019] Such self-selecting memory cells with selector / memory devices can be programmed in crosspoint memory to have a threshold voltage window. The threshold voltage window can be generated by applying programming pulses of opposite polarity to the selector / memory device of the memory cell. For example, the memory cell can be biased to have a positive voltage difference between the two sides of the selector / memory device, and alternatively, to have a negative voltage difference between the same two sides of the selector / memory device. When a positive voltage difference is considered positive polarity, a negative voltage difference is considered negative polarity. Reads can be performed with a given / fixed polarity. During programming, the memory cell has a low threshold (e.g., lower than a reset cell, or a cell programmed to have a high threshold) such that during a read operation, the read voltage can cause the set cell to jump and thus become conductive, while the reset cell remains non-conductive.

[0020] These memory cells can be configured (programmed, written to, or set) to have a low threshold in a given polarity. When a memory cell has this low threshold state (e.g., representing a state corresponding to a bit value stored as one) during a read in a given polarity, it can be called a set cell. Similarly, a memory cell can be configured (programmed, written to, or set) to have a high threshold in a given polarity (e.g., representing a state corresponding to a bit value stored as zero). When a memory cell has this high threshold state during a read in a given polarity, it can be called a reset cell.

[0021] After a memory cell is programmed as a set or reset cell, the state of the memory cell can drift. The threshold of the memory cell can change and move away from its initial state, where the memory cell was recently configured as a set or reset cell via a programming or write operation. For example, a read operation used to determine the state of the memory cell, and thus the data represented by the state of the memory, can cause the threshold of the memory cell to drift, and thus cause the state of the memory cell to drift. Some details and examples of this type of drift can be found in U.S. Patent Application Publication No. 2019 / 0206506, entitled "Drift Mitigation with Embedded Refresh".

[0022] Before applying a programming pulse to configure a memory cell as a set or reset cell, a drift elimination pulse of opposite polarity is typically applied to eliminate drift in the state of the memory cell (e.g., drift away from its previously programmed threshold state). The drift elimination operation makes it easier to switch memory cells on the programming pulse and thus select memory cells from the memory cell array for programming.

[0023] However, since a drift-removal pulse is applied in the opposite polarity of the programming pulse, there is a polarity reversal from the drift-removal pulse to the programming pulse. This polarity reversal consumes a significant amount of energy.

[0024] At least some aspects of this disclosure address the above and other deficiencies by selectively applying drift elimination pulses based on properties of the memory cell to be programmed.

[0025] When a voltage pulse is applied across a memory cell, the memory cell can jump, rapidly transitioning from a state that allows a small leakage current to pass through (e.g., a non-conductive state) to a state that allows current above a threshold to pass through (e.g., a conductive state). The voltage applied to the memory cell immediately before the jump is the threshold voltage for the memory cell. After the jump, if the voltage pulse is still driving the memory cell, the voltage across the memory cell drops significantly below the threshold but remains in the conductive state.

[0026] To set or reset a memory cell, a programming pulse is applied to the memory cell, causing the memory cell to switch and thus be selected for programming. The remainder of the programming pulse is configured to push a threshold of the memory cell to a set or reset state. To set a memory cell, the programming pulse is applied with one polarity; and to reset a memory cell, the programming pulse is applied with the opposite polarity.

[0027] Some memory cells in an integrated circuit device may exhibit drift, such that, without a drift cancellation pulse, the threshold of the memory cell is too high for the memory cell to transition during a programming pulse. If the memory cell fails to transition during a programming pulse, the programming pulse may fail to place the memory cell in a state representing data to be stored in the memory cell (e.g., a set state or a reset state).

[0028] However, other memory cells in an integrated circuit device may not have sufficient drift to prevent them from hopping under a programming pulse. Therefore, skipping the drift elimination operation for these memory cells can significantly reduce the energy consumption during the programming of memory cells to store data.

[0029] Predictive models can be used to determine whether the drift elimination operation can be skipped to program the memory cell to the set or reset cell.

[0030] For example, a predictive model can be configured to identify memory cells that may have drift that could prevent transitions during the programming pulse. Prediction can be based on attributes of the memory cell to be programmed, such as measurements of the electrical distance between the memory cell and its voltage driver, time intervals from previous write / programming operations, the memory cell's location / address, etc. For example, a predictive model can be built via relevant attributes of the memory cell and its state regarding whether it previously failed to transition during programming without drift elimination. For example, the predictive model can be used to estimate based on the attributes of the memory cell to be programmed, the probability that the memory cell failed to transition during programming without drift elimination, or an indication of whether the probability is above a threshold. In some implementations, empirical formulas (e.g., based on the electrical distance to the voltage driver) can be used to classify whether a memory cell is likely to fail to transition without drift elimination. If so, a drift elimination operation is performed; otherwise, the drift elimination operation is skipped.

[0031] Integrated circuit memory devices may have multiple memory cell stacks. Each stack has a layer of memory cells configured between two conductor layers (e.g., bit lines and word lines). Identification of the stack in which a memory cell resides can be used to predict whether to skip drift elimination operations when programming the memory cell.

[0032] For example, memory cell groups can be assigned to block groups based on the write cycle timing of memory cells. The write cycle timing attribute of block groups / groups can be used to predict whether to skip drift elimination operations when programming memory cells.

[0033] Figure 1 A memory device configured with a drift predictor is shown according to one embodiment.

[0034] exist Figure 1 In the memory device, there is an array 133 of memory cells (e.g., memory cells 101).

[0035] Figure 1 The memory device includes a controller 131 that operates a bit line driver 137 and a word line driver 135 to access individual memory cells (e.g., 101) in the array 133.

[0036] For example, it can be achieved through methods such as Figure 2 The voltage driven by the pair of bit line drivers 147 and word line drivers 145 described herein is used to access each memory cell (e.g., 101) in array 133.

[0037] The controller 131 includes a drift predictor 103. For example, the drift predictor 103 may be implemented via logic circuitry and / or microcode / instructions to determine whether the state drift of the memory cell 101 is above a certain level based on the properties of the memory cell 101, such that a drift elimination operation is required when the state of the memory cell 101 is programmed to represent data bits written into the memory cell 101.

[0038] For example, the attributes used to predict / determine memory cell 101 may include the electrical distance of memory cell 101 to its voltage driver, the identification of the stack in which memory cell 101 is located, the location or address of memory cell 101 in the memory device, and the write timing parameters or range of memory cell 101.

[0039] Figure 2 A memory cell 101 according to one embodiment is shown, having a bit line driver 147 and a word line driver 145 configured to apply voltage pulses. For example, the memory cell 101 may be... Figure 1 Typical memory cell 101 in memory cell array 133.

[0040] Figure 2The bit line driver 147 and word line driver 145 can drive voltages on the bit line 141 and word line 143, respectively, relative to ground. In drift elimination operation, the bit line driver 147 and word line driver 145 are controlled by the drift predictor 103 of the controller 131 to selectively apply drift elimination pulses to program the memory cell 101 to store data.

[0041] Bit line driver 147 and word line driver 145 can apply voltages of different polarities to memory cell 101.

[0042] For example, when a voltage of a polarity (e.g., positive polarity) is applied, bit line driver 147 drives a positive voltage relative to ground on bit lines 141 connected to rows of memory cells in array 133; and word line driver 145 drives a negative voltage relative to ground on word lines 143 connected to columns of memory cells in array 133.

[0043] When a voltage of opposite polarity (e.g., negative polarity) is applied, the bit line driver 147 drives a negative voltage relative to ground on the bit line 141; and the word line driver 145 drives a positive voltage relative to ground on the word line 143.

[0044] Memory cell 101 is located in a row connected to bit line 141 and a column connected to word line 143. Therefore, memory cell 101 experiences a voltage difference between the voltage driven by bit line driver 147 on bit line 141 and the voltage driven by word line driver 145 on word line 143. This voltage difference represents the voltage pulse driven onto memory cell 101.

[0045] Generally, when the voltage driven by the bit line driver 147 is higher than the voltage driven by the word line driver 145, the memory cell 101 experiences a voltage of one polarity (e.g., positive polarity); and when the voltage driven by the bit line driver 147 is lower than the voltage driven by the word line driver 145, the memory cell 101 experiences a voltage of the opposite polarity (e.g., negative polarity).

[0046] To program memory cell 101 into the reset unit, bit line driver 147 and word line driver 145 can drive programming pulses of voltage onto memory cell 101 in one polarity (e.g., positive polarity) to switch memory cell 101, causing memory cell 101 to be in a conductive state. While memory cell 101 is conductive, bit line driver 147 and word line driver 145 continue to drive programming pulses to reduce the threshold voltage of memory cell 101 in the positive polarity to a level designed for the reset unit. Reducing the threshold voltage of memory cell 101 in the positive polarity increases the threshold voltage of memory cell 101 in the negative polarity.

[0047] Similarly, to program memory cell 101 into the setting unit, bit line driver 147 and word line driver 145 can drive programming pulses of voltage onto memory cell 101 in opposite polarities (e.g., negative polarity) to switch memory cell 101, making it conductive. While memory cell 101 is conductive in the opposite polarity, bit line driver 147 and word line driver 145 continue to drive programming pulses to reduce the threshold voltage of memory cell 101 in the negative polarity to a level designed for the setting unit. Reducing the threshold voltage of memory cell 101 in the negative polarity increases the threshold voltage of memory cell 101 in the positive polarity.

[0048] Therefore, programming pulses applied in different polarities can generate a threshold window in a given polarity, which can depend on the state of read memory cell 101 and thus determine whether memory cell 101 is a set cell or a reset cell.

[0049] For example, after memory cell 101 is programmed into the reset unit via a programming pulse in the positive polarity, the threshold voltage of memory cell 101 in the positive polarity becomes low, while the threshold voltage of memory cell 101 in the negative polarity becomes high. Conversely, after memory cell 101 is programmed into the set unit via a programming pulse in the negative polarity, the threshold voltage of memory cell 101 in the negative polarity becomes low, while the threshold voltage of memory cell 101 in the positive polarity becomes high. Therefore, when checked / read in the negative polarity, the memory cell 101 programmed into the reset unit has a higher threshold voltage than the cell programmed into the set unit. Similarly, when checked / read in the positive polarity, the memory cell 101 programmed into the set unit has a higher threshold voltage than the cell programmed into the reset unit.

[0050] Therefore, when reading memory cell 101 in negative polarity, if the read voltage pulse changes memory cell 101 in negative polarity, then memory cell 101 is a setting unit; and if the read voltage fails to change memory cell 101 in negative polarity, then memory cell 101 is a reset unit.

[0051] Similarly, when reading memory cell 101 in positive polarity, if the read voltage changes to memory cell 101 in positive polarity, then memory cell 101 is a reset unit; and if the read voltage fails to change to memory cell 101 in positive polarity, then memory cell 101 is a set unit.

[0052] Figures 3 to 6 This describes the voltage distribution on the memory cell and the current flowing through the memory cell during drift elimination and data programming operations according to one embodiment.

[0053] exist Figures 3 to 6 During the application of the programming pulse, a bit line voltage 205 relative to ground is driven by a bit line driver 147 connected to bit line 141 of memory cell 101. During the application of the programming pulse, a word line voltage 206 relative to ground is driven by a word line driver 145 connected to word line 143 of memory cell 101.

[0054] exist Figure 3 and 4 In each of these pulses, the programming pulse is in polarity (e.g., positive polarity), where the bit line voltage 205 is higher than the word line voltage 206. While the bit line driver 147 and word line driver 145 drive the voltage amplitudes on bit line 141 and word line 143 in positive polarity, memory cell 101 transitions at time T2, causing the current through memory cell 101 to jump from a small leakage current to a selection current 207 higher than the threshold level used for cell selection. Because the bit line voltage 205 is higher than the word line voltage 206, the current through memory cell 101 is in the positive direction from bit line 141 through the memory cell to word line 143. The transition at time T2 during the programming pulse causes the voltage amplitudes on word line 143 and bit line 141 to decrease. After time T2, the bit line driver 147 and word line driver 145 continue to drive the voltage amplitudes on word line 143 and bit line 141 in positive polarity to produce a programming current 208 greater than the selection current 207. After the bit line driver 147 and word line driver 145 stop driving the programming pulse, the magnitude of the voltage on bit line 141 and word line 143 drops to zero for a period of time; and the current through memory cell 101 also decreases to zero (and memory cell 101 returns to a non-conductive state). After the programming pulse, memory cell 101 is in a reset state with a high threshold voltage in the negative polarity and a low threshold voltage in the positive polarity.

[0055] In comparison, Figure 5 and 6Each of the programming pulses described herein is in the opposite polarity (e.g., negative polarity), where the bit line voltage 205 is lower than the word line voltage 206. As the bit line driver 147 and word line driver 145 drive the voltage amplitudes on bit line 141 and word line 143 in the negative polarity, memory cell 101 jumps at time T2, causing the current through memory cell 101 to jump from a small leakage current to a selection current 207 higher than the threshold level used for cell selection. Because the bit line voltage 205 is lower than the word line voltage 206, the current through memory cell 101 is in the negative direction from word line 143 through the memory cell to bit line 141. The jump at time T2 during the programming pulse causes the voltage amplitudes on word line 143 and bit line 141 to decrease. After time T2, the bit line driver 147 and word line driver 145 continue to drive the voltage amplitudes on word line 143 and bit line 141 in the negative polarity to produce a programming current 208 with an amplitude greater than the selection current 207. After the bit line driver 147 and word line driver 145 stop driving the programming pulse, the magnitude of the voltage on bit line 141 and word line 143 drops to zero relative to ground; and the current through memory cell 101 also decreases to zero. After the programming pulse, memory cell 101 is in a set state with a high threshold voltage in the positive polarity and a low threshold voltage in the negative polarity.

[0056] After memory cell 101 is recently programmed to have a set or reset state, when a programming pulse is applied in positive or negative polarity, memory cell 101 may transition (e.g., at time T2) as the bit line driver 147 and word line driver 145 drive the voltage amplitude on bit line 141 and word line 143. When driving the programming pulse, bit line driver 147 and word line driver 145 are configured to drive the voltage amplitude on bit line 141 and word line 143 toward a predefined level (e.g., a voltage difference of 3.5V across memory cell 101 toward 7V).

[0057] However, after a period of time and when the memory cell 101 is reprogrammed, the state of the memory cell 101 may have drifted away from the recently programmed state, causing the memory cell 101 to fail to change during the programming pulse.

[0058] To eliminate drift that prevents memory cell 101 from jumping during the programming pulse, a drift elimination pulse can be applied in the opposite polarity of the programming pulse, such as... Figures 3 to 6 As explained in the text.

[0059] For example, in Figure 3 and 4In the programming pulse, the bit line voltage 205 is in positive polarity, where the bit line voltage 205 is higher than the word line voltage 206. A drift-eliminating pulse with bit line voltage 202 and word line voltage 201 is applied in negative polarity, where the bit line voltage 202 is lower than the word line voltage 201. When the drift-eliminating pulse is driven in negative polarity, bit line driver 147 and word line driver 145 are configured to drive the amplitude of the voltages on bit line 141 and word line 143 toward a reduced predefined level (e.g., 2.5V for a voltage difference across memory cell 101 toward 5V), said reduced predefined level being lower than a predefined level (e.g., 3.5V) used for the programming pulse.

[0060] Figure 3 This describes an instance where a drift cancellation pulse is applied to memory cell 101, which was previously programmed into a setup state with a low threshold in negative polarity. The drift cancellation pulse applied in negative polarity causes memory cell 101 to jump at time T1. This is similar to the jump at time T2 during the programming pulse. Figure 3 The transition of memory cell 101 at time T1 allows selection current 203 to pass through memory cell 101, which can optionally be sensed to determine that memory cell 101 is a setting cell. The transition of memory cell 101 at time T1 during the drift elimination pulse also has the benefit of clearing possible drift in memory cell 101 so that when a programming pulse is applied after the drift elimination pulse, memory cell 101 will transition at time T2.

[0061] Figure 4 This illustrates an instance where a drift cancellation pulse is applied to a memory cell 101 previously programmed into a reset state with a high threshold in negative polarity. Therefore, the memory cell 101 does not abruptly change during the drift cancellation pulse, which is applied in negative polarity and has a reduced amplitude compared to the programming pulse. Only a small leakage current 204 can pass through the memory cell 101 during the drift cancellation pulse. Optionally, the absence of the selection current 203 can be sensed to determine if the memory cell 101 is a reset cell. Since the memory cell 101 is already in a reset state, subsequent programming pulses used to place the memory cell in a quiescent state can optionally be skipped, such as... Figure 7 As explained in the document. Skipping programming pulses avoids drift and eliminates possible polarity reversals between the programming pulse and the programming pulse.

[0062] exist Figure 5 and 6In the programming pulse, the bit line voltage 205 is in negative polarity, where the bit line voltage 205 is lower than the word line voltage 206. A drift-eliminating pulse with bit line voltage 202 and word line voltage 201 is applied in positive polarity, where the bit line voltage 202 is higher than the word line voltage 201. When the drift-eliminating pulse is driven in positive polarity, the bit line driver 147 and word line driver 145 are configured to drive the amplitude of the voltages on the bit line 141 and word line 143 relative to ground toward a predefined level (e.g., 3.5V), which is the same as (or close to) the predefined level (e.g., 3.5V) used for the programming pulse.

[0063] Figure 5 This describes an instance of a drift-eliminating pulse applied to a memory cell 101 previously programmed into a setting state with a high threshold in positive polarity. The drift-eliminating pulse applied in positive polarity causes the memory cell 101 to... Figure 5 The transition occurs at time T1. Similar to the transition at time T2 during the programming pulse, the transition of memory cell 101 at time T1 allows selection current 203 to pass through memory cell 101. The transition of memory cell 101 at time T1 during the drift elimination pulse also has the benefit of clearing possible drift in memory cell 101 so that when a programming pulse is applied after the drift elimination pulse, memory cell 101 will transition at time T2.

[0064] Figure 6 This illustrates an instance where a drift cancellation pulse is applied to a memory cell 101 previously programmed into a reset state with a low threshold in positive polarity. Therefore, during the drift cancellation pulse applied in positive polarity, the memory cell 101... Figure 6 The transition at time T1 during the drift elimination pulse of memory cell 101 also has the following benefits: clearing any possible drift in memory cell 101 so that when a programming pulse is applied after the drift elimination pulse, memory cell 101 will transition at time T2.

[0065] Because a drift-eliminating pulse is applied in the opposite polarity of the subsequent programming pulse, a large amount of energy is consumed during the polarity reversal.

[0066] When the drift predictor 103 determines that the memory cell 101 has a drift that can prevent jumps during the programming pulse, the controller 131 can use the bit line driver 147 and the word line driver 145 to apply a drift cancellation pulse before the programming pulse, such as Figures 3 to 6 As described in [the document]. Otherwise, controller 131 may skip instructing bit line driver 147 and word line driver 145 to apply a drift cancellation pulse before the programming pulse. In at least some cases, the elimination of the drift cancellation pulse can result in a reduction in the power consumption of the memory device having memory cell array 133.

[0067] In some implementations, this is for applying a programmed pulse in the negative polarity (e.g., Figure 5 and 6 In order to program the memory cell 101 into the setting cell (e.g., not for programming pulses in positive polarity), a determination on whether to skip the drift elimination pulse is specifically performed.

[0068] In some implementations, the drift predictor 103 determines that skipping is possible. Figure 5 and 6 When the drift elimination pulse is applied, the controller 131 may optionally apply a read pulse of the same polarity as the programming pulse. The result of the read pulse can be used to determine whether to skip subsequent programming pulses, such as... Figure 8 and 9 As explained in [the document / reference]. Figure 8 and 9 In this context, the read pulse includes word line voltage 211 and bit line voltage 212 applied in the same negative polarity as the programming pulse to be applied to place memory cell 101 into a set state. When driving the read pulse, bit line driver 147 drives bit line voltage 212 on bit line 141 toward a predetermined amplitude (e.g., 2.5V) lower than the amplitude of the programming pulse (e.g., 3.5V); and similarly, word line driver 145 drives word line voltage 211 on bit line 141 toward a predetermined amplitude (e.g., 2.5V) lower than the corresponding amplitude of the programming pulse (e.g., 3.5V).

[0069] Figure 8 This illustrates an example where a read pulse is applied to a memory cell 101 that has been previously programmed into a set state, wherein the memory cell 101 has a low threshold in negative polarity. Therefore, a transition in the memory cell 101 at time T1 allows a selection current 203 to pass through the memory cell 101. The detection of the selection current 203 indicates that the memory cell 101 is in a set state; and therefore, the controller 131 can decide to skip subsequent programming pulses (e.g., ...). Figure 5 The programming pulse described in the document).

[0070] Figure 9This illustrates an example where a read pulse is applied to a memory cell 101 previously programmed into a reset state, wherein the memory cell 101 has a high threshold in negative polarity. The memory cell 101 does not jump during the read pulse. Only a small leakage current 204 passes through the memory cell 101. The absence of a selection current 203 indicates that the memory cell 101 is currently in a reset state; and therefore, the controller 131 can instruct the bit line driver 147 and the word line driver 145 to apply a programming pulse in negative polarity to place the memory cell 101 into a set state. Optionally, in response to determining that the memory cell 101 is currently in a reset state, the controller 131 instructs the bit line driver 147 and the word line driver 145 to switch to driving the programming pulse during the time interval between the read pulse and the programming pulse without stopping the driving of the bit line 141 and the word line 143. Therefore, the amplitudes of the bit line voltage 212 and the word line voltage 211 do not decrease before driving the programming pulse, as... Figure 9 As explained in the document; and the combination of read pulses and programming pulses reduces voltage sway during programming of memory cell 101, which reduces energy consumption. Alternatively, controller 131 may allow bit line driver 147 and word line driver 145 to stop driving the voltages on bit line voltage 212 and word line voltage 211 during the time period between read pulses and programming pulses.

[0071] Figure 10 A method for programming a memory cell is demonstrated according to one embodiment. For example, Figure 10 The method can be combined with the above. Figures 1 to 9 The drift predictor discussed in Figure 1 Implemented in a memory device.

[0072] At box 161, controller 131 receives a command to store data bits in memory cell 101.

[0073] At block 163, controller 131, in response to a command and based on the properties of memory cell 101, determines whether to apply a drift elimination pulse to memory cell 101 before applying a programming pulse to memory cell 101 in a first polarity identified according to data bits, wherein the drift elimination pulse is in a second polarity opposite to the first polarity.

[0074] For example, controller 131 may include drift predictor 103 configured to predict or classify whether memory cell 101 has drift in its current state based on attributes of memory cell 101, such drift being sufficient to prevent memory cell 101 from jumping and thus preventing it from being selected during the application of a programming pulse. If the drift is predicted / classified as sufficient to prevent memory cell 101 from jumping during the programming pulse, then a drift elimination pulse is applied; otherwise, the drift elimination pulse is skipped and optionally replaced with a read pulse of the same polarity as the programming pulse (e.g., ...). Figure 8 and 9 (As explained and discussed in the text).

[0075] For example, the attributes of the memory cell 101 used for prediction may be based at least in part on the location or address of the memory cell 101 in the memory device (e.g., identification of stacks, rows, and columns), the electrical distance from the memory cell 101 to its voltage drivers (the electrical distance between the bit line driver 147 and the word line driver 145), or the timing of a previous command to store data in the memory cell 101, or any combination thereof.

[0076] If the result at block 165 indicates the application of a drift cancellation pulse, then at block 167, controller 131 is configured to perform an operation to store the data bits in memory cell 101 without applying a voltage cancellation pulse. Otherwise, at block 169, controller 131 is configured to perform an operation to store the data bits in memory cell 101 by applying at least a voltage cancellation pulse.

[0077] For example, such as Figure 2 As described, memory cell 101 is coupled between two voltage drivers (bit line driver 147 and word line driver 145). Voltage pulses applied by the two voltage drivers are in a first polarity when the current through the memory cell (e.g., leakage current 204) is in a first direction, but in a second polarity when the current through the memory cell (e.g., leakage current 204) is in a second direction opposite to the first direction.

[0078] For example, the first polarity and the second polarity can be different from positive and negative polarities. For example, when driving the positive polarity, the bit line driver 147 drives the magnitude of a positive voltage relative to the grounded bit line 141; and the word line driver 145 drives the magnitude of a negative voltage relative to the grounded word line 143. In contrast, when driving the negative polarity, the bit line driver 147 drives the magnitude of a negative voltage relative to the grounded bit line 141; and the word line driver 145 drives the magnitude of a positive voltage relative to the grounded word line 143.

[0079] like Figure 8 and 9As described, when canceling the drift cancellation pulse, two voltage drivers (e.g., bit line driver 147 and word line driver 145) can drive the read pulse with a first polarity (the same polarity as the programming pulse selected based on the data bit to be stored). During the read pulse, a current sensor is configured to evaluate the magnitude of the current flowing through memory cell 101. If the magnitude is greater than a threshold, then memory cell 101 has transitioned during the read pulse, which allows controller 131 to skip the application of the programming pulse (since memory cell 101 already has a state representing data to be stored). Otherwise, controller 131 can instruct the two voltage drivers (e.g., bit line driver 147 and word line driver 145) to combine the read pulse and subsequent programming pulse.

[0080] In some implementations, a drift elimination pulse is selectively applied only to the programming pulse to store specific data bits in memory cell 101 (e.g., Figure 5 and 6 The programming pulse), wherein the cancellation pulse has an amplitude equal to (or similar to) the programming pulse. Therefore, whether to apply a programming pulse is determined in response to storing a specific data bit in memory cell 101. For example, when a command is received to store another data bit in memory cell 101, the operation of box 163 can be skipped; and a drift cancellation pulse can be applied without checking the properties of the memory cell 101 to be programmed, such as... Figure 3 and 4 (or as explained in 7).

[0081] In one embodiment, to apply a read pulse, bit line driver 147 and word line driver 145 are configured to drive the voltage difference across memory cell 101 toward a first predefined amplitude (e.g., 5V). To apply a programming pulse, bit line driver 147 and word line driver 145 are configured to drive the voltage difference across memory cell 101 toward a second predefined amplitude (e.g., 7V). Since the read pulse and programming pulse are in the same polarity, bit line driver 147 and word line driver 145 can be instructed to switch from driving the first predefined amplitude (e.g., 5V) to driving the second predefined amplitude (e.g., 7V) without stopping. Therefore, the amplitude of the voltage difference across memory cell 101 continues to increase until memory cell 101 transitions in the programming pulse, as... Figure 9 As explained in the text.

[0082] Controller 131 can be configured in an integrated circuit having multiple stacks of memory cells. Each stack can be sandwiched between bit line layers and word line layers; and the memory cells in the stack can be arranged in an array. Adjacent stacks of memory cells can share a bit line layer or a word line layer. Bit lines are arranged to extend parallel in one direction within their layers; and word lines are arranged to extend parallel in another direction orthogonal to the bit line direction within their layers. Each bit line is connected to a row of memory cells in the array; and each word line is connected to a column of memory cells in the array. Bit line drivers are connected to the bit lines in the stack; and word line drivers are connected to the word lines in the stack. Thus, a typical memory cell 101 is connected to bit line driver 147 and word line driver 145.

[0083] For example, memory cell 101 has a selector / memory device. The selector / memory device has a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). For example, the chalcogenide material may comprise a chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). The chalcogenide material may primarily comprise selenium (Se), arsenic (As), and germanium (Ge) and is referred to as a SAG alloy. The SAG alloy may comprise silicon (Si) and is referred to as a SiSAG alloy. In some embodiments, the chalcogenide glass may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form. The selector / memory device has a top side and a bottom side. A top electrode is formed on the top side of the selector / memory device for connection to bit line 141; and a bottom electrode is formed on the bottom side of the selector / memory device for connection to word line 143. For example, the top and bottom electrodes can be formed of carbon material. For example, the material of memory cell 101 can be in a crystalline or amorphous atomic configuration. The threshold voltage of memory cell 101 can depend on the ratio of the material in the crystalline configuration to the material in the amorphous configuration within memory cell 101. This ratio can vary under various conditions (e.g., allowing currents of different magnitudes and directions to pass through memory cell 101).

[0084] Figure 1 The memory device can be used in data processing systems.

[0085] A typical data processing system may contain interconnects (e.g., buses and system core logic) that interconnect microprocessors and memory. Microprocessors are typically coupled to cache memory.

[0086] Interconnectors link the microprocessor and memory together and also connect them to I / O devices via input / output (I / O) controllers. I / O devices may include display devices and / or peripheral devices such as mice, keyboards, modems, network interfaces, printers, scanners, cameras, and other devices known in the art. In one embodiment, when the data processing system is a server system, some of the I / O devices (e.g., printers, scanners, mice, and / or keyboards) are optional.

[0087] Interconnectors may include one or more buses that are interconnected to each other via various bridges, controllers, and / or adapters. In one embodiment, the I / O controller includes a USB adapter for controlling USB (Universal Serial Bus) peripherals and / or an IEEE-1394 bus adapter for controlling IEEE-1394 peripherals.

[0088] The memory may include one or more of the following: ROM (Read-Only Memory), volatile RAM (Random Access Memory), and non-volatile memory, such as hard disk drives, flash memory, etc.

[0089] Volatile RAM is typically implemented as dynamic RAM (DRAM) that requires continuous power to refresh or maintain data in the memory. Non-volatile memory is typically magnetic hard disk drives, magnetic optical disk drives, optical disk drives (e.g., DVDRAM), or other types of memory systems that retain data even after power is removed from the system. Non-volatile memory can also be random access memory.

[0090] Non-volatile memory can be a local device directly coupled to the rest of the data processing system. Alternatively, it can be a non-volatile memory located off-system, such as a network storage device coupled to the data processing system via a network interface, for example, a modem or Ethernet interface.

[0091] In this disclosure, some functions and operations are described as being executed by or caused by software code for the sake of simplicity. However, this expression is also used to indicate that the function is generated by a processor, such as a microprocessor, executing code / instructions.

[0092] Alternatively or in combination, the functions and operations described herein may be implemented using dedicated circuitry with or without software instructions, such as using application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments may also be implemented using hard-wired circuitry without software instructions or in combination with software instructions. Therefore, the technology is not limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by the data processing system.

[0093] While one embodiment may be implemented in a full-featured computer and computer system, various embodiments can be distributed as a variety of computing products and can be applied regardless of the specific type of machine or computer-readable medium actually used to implement the distribution.

[0094] At least some of the disclosed aspects may be embodied, at least in part, in software. That is, these techniques may be executed in a computer system or other data processing system in response to a processor (e.g., a microprocessor) executing a sequence of instructions contained in memory (e.g., ROM, volatile RAM, non-volatile memory, cache memory, or remote storage device).

[0095] The routines used to implement the embodiments can be implemented as part of an operating system or a particular application, component, program, object, module, or a sequence of instructions referred to as a "computer program." A computer program typically contains one or more sets of instructions at various times in various memories and storage devices in a computer, and when read and executed by one or more processors in the computer, the sets of instructions cause the computer to perform necessary operations to perform elements involving various aspects.

[0096] Machine-readable media can be used to store software and data that enable a data processing system to perform various methods when executed. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. A portion of such software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or within the same communication session. All data and instructions can be obtained before the application is executed. Alternatively, portions of data and instructions can be obtained dynamically and as needed for execution. Therefore, it is not required that all data and instructions be on the machine-readable media at any given moment.

[0097] Examples of computer-readable media include, but are not limited to, media of non-transitory recordable and non-recordable types, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, floppy and other removable disks, disk storage media, optical storage media (e.g., optical disc read-only memory (CDROM), digital versatile disc (DVD), etc.), and others. Computer-readable media can store instructions.

[0098] Instructions can also be embodied in digital and analog communication links for use with electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc. However, propagated signals such as carrier waves, infrared signals, digital signals, etc., are not tangible machine-readable media and cannot be configured to store instructions.

[0099] Generally, machine-readable media includes any entity that provides (i.e., stores and / or transmits) information in a form accessible by a machine (e.g., a computer, a network device, a personal digital assistant, a manufacturing tool, any device having one or more processors, etc.).

[0100] In various embodiments, hardwired circuitry can be used in combination with software instructions to implement the technology. Therefore, the technology is neither limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by the data processing system.

[0101] The above descriptions and figures are illustrative and should not be construed as limiting. Many specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are omitted to avoid obscuring the description. References to one or more embodiments in this disclosure do not necessarily refer to the same embodiment; and such references imply at least one.

[0102] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for memory operations, comprising: Receive a command to store data bits in a memory unit; In response to the command and based on the properties of the memory cell, it is determined whether to apply a drift elimination pulse to the memory cell before applying a programming pulse to the memory cell in a first polarity identified according to the data bits, wherein the drift elimination pulse is in a second polarity opposite to the first polarity; and The memory cell is programmed to store the data bits based on the result of the decision, wherein the programming includes: The drift elimination pulse is skipped in response to the result being the first option; or The drift elimination pulse is applied in response to the result being the second option.

2. The method of claim 1, wherein the memory cell is coupled between two voltage drivers; the first polarity causes current to flow through the memory cell in a first direction; Furthermore, the second polarity causes the current to pass through the memory cell in a second direction opposite to the first direction; The method further includes: In response to the result being the first option, the two voltage drivers are instructed to drive the read pulse in the first polarity; as well as Determine whether the current passing through the memory cell during the read pulse has an amplitude greater than a threshold.

3. The method according to claim 2, further comprising: The programming pulse is skipped in response to the amplitude of the current passing through the memory cell during the read pulse exceeding the threshold.

4. The method of claim 2, wherein the voltage driver is configured to drive the read pulse toward a first predefined amplitude and drive the programming pulse toward a second predefined amplitude greater than the first predefined amplitude; and the method further comprises: The voltage driver is instructed to switch from driving towards the first predefined amplitude to driving towards the second predefined amplitude without stopping the combination of the read pulse and the program pulse.

5. The method of claim 2, wherein the attribute is based at least in part on the location of the memory cell, the address of the memory cell, the electrical distance from the memory cell to the two voltage drivers, or the timing of a command to store data in the memory cell, or any combination thereof.

6. A semiconductor device comprising: Multiple memory units; A plurality of voltage drivers, comprising a first voltage driver connected to a respective memory cell in the plurality of memory cells and a second voltage driver connected to the memory cell, wherein the memory cell is configured to be in a first state via the first voltage driver and the second voltage driver driving a first voltage pulse on the memory cell in a first polarity, wherein the voltage driven by the first voltage driver is higher than the voltage driven by the second voltage driver; as well as A controller connected to the plurality of voltage drivers, wherein, in response to a command configuring the memory cell to have a first state indicating that a first data is stored in the memory cell, the controller is configured to determine, based on the properties of the memory cell, whether to apply a second voltage pulse to the memory cell in a second polarity opposite to the first polarity; and wherein the voltage driven by the first voltage driver is lower than the voltage driven by the second voltage driver in the second polarity.

7. The semiconductor device of claim 6, wherein the properties of the memory cell are based at least in part on the location of the memory cell in the semiconductor device.

8. The semiconductor device of claim 6, wherein the properties of the memory cell are based at least in part on the address of the memory cell in the semiconductor device.

9. The semiconductor device of claim 6, wherein the properties of the memory cell are based at least in part on indicators of electrical distances from the memory cell to the first voltage driver and the second voltage driver.

10. The semiconductor device of claim 6, wherein the property of the memory cell is based on the time range during which the memory cell was previously subjected to a voltage pulse to store data.

11. The semiconductor device of claim 6, wherein in response to the first state being a preselected state, the controller is further configured to determine whether to apply the second voltage pulse.

12. The semiconductor device of claim 11, wherein in response to the first state being an alternative state different from the preselected state, the controller instructs the first voltage driver and the second voltage driver to apply the second voltage pulse without determining whether to apply the second voltage pulse based on the attribute.

13. The semiconductor device of claim 12, wherein in the first polarity, the first voltage driver is configured to drive a positive voltage relative to ground, and the second voltage driver is configured to drive a negative voltage relative to the ground; and in the second polarity, the first voltage driver is configured to drive a negative voltage relative to the ground, and the second voltage driver is configured to drive a positive voltage relative to the ground. When driving the first voltage pulse, the first voltage driver and the second voltage driver are configured to drive the voltage to a first predetermined amplitude; Furthermore, when driving the second voltage pulse, if the first state is the preselected state, the first voltage driver and the second voltage driver are configured to drive the voltage to the first predetermined amplitude.

14. The semiconductor device of claim 13, wherein in response to determining that the second voltage pulse is skipped, the controller is further configured to indicate a third voltage pulse in the first polarity of the first voltage driver and the second voltage driver, and to determine whether a current above a threshold passes through the memory cell during the third voltage pulse.

15. The semiconductor device of claim 14, wherein in response to the current being higher than the threshold during the third voltage pulse, the semiconductor device is configured to skip the first voltage pulse after the third voltage pulse.

16. The semiconductor device of claim 14, wherein when driving the third voltage pulse, the first voltage driver and the second voltage driver are configured to drive the voltage to a second predetermined amplitude below the first predetermined amplitude; and in response to the current being below the threshold during the third voltage pulse, the controller is further configured to instruct the first voltage driver and the second voltage driver to change from driving the voltage to the second predetermined amplitude to driving the voltage to the first predetermined amplitude, without stopping the driving voltage.

17. An integrated circuit, comprising: Multiple bitline layers; Multiple word line layers; A stack of multiple memory cells is configured in an array, each of the stacks being located between a bit line layer and a word line layer among the multiple bit line layers, each of the bit line layers being connected to a row of memory cells in the array, and each of the word line layers being connected to a column of memory cells in the array. Bit line driver, which is connected to the plurality of bit line layers; A word line driver connected to the plurality of word line layers, wherein each corresponding memory cell in the stack is connected to a bit line driver and a word line driver, wherein the bit line driver and the word line driver are configured to apply a voltage in positive polarity when the voltage driven by the bit line driver is higher than the voltage driven by the word line driver, and to apply a voltage in negative polarity when the voltage driven by the bit line driver is lower than the voltage driven by the word line driver; as well as A controller having a drift predictor configured to predict whether the memory cell has a drift in the current state of the memory cell based on the properties of the memory cell, the drift being sufficient to prevent the memory cell from being selected during programming pulses applied by the bit line driver and the word line driver in a first polarity identified by the data bits to be stored in the memory cell; In response to the drift predictor determining that the drift is sufficient to prevent the memory cell from being selected during the programming pulse, the controller is configured to instruct the bit line driver and the word line driver to apply a drift cancellation pulse in a second polarity opposite to the first polarity before applying the programming pulse in the first polarity.

18. The integrated circuit of claim 17, wherein the attribute is based at least in part on identifying the stack in which the memory cell is configured, the electrical distance from the memory cell to the bit line driver and the word line driver, or the time of the previous write operation performed for the memory cell, or any combination thereof.

19. The integrated circuit of claim 18, wherein the memory cell has elements that function as both a selector device and a memory device.

20. The integrated circuit of claim 19, wherein the memory cell is selected during the programming pulse when the programming pulse makes the memory cell conductive and allows current exceeding a threshold amount to flow through the memory cell; and In response to the drift predictor determining that the drift is insufficient to prevent the memory cell from being selected during the programming pulse, the bit line driver and the word line driver are configured to skip the application of the drift elimination pulse in the opposite second polarity.

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