Semiconductor device and continuous readout method

Abstract

The present invention provides a semiconductor device and a continuous read method for suppressing fluctuations in a precharge voltage caused by an increase in a precharge time. The continuous read method of the NAND type flash memory of the present invention includes the following steps: applying a first voltage (VCLMP1 + Vth) to a gate of a transistor (BLCLAMP) connected to a bit line, and supplying a voltage to the bit line via the transistor (BLCLAMP) to start precharging of the bit line; and when a certain time has elapsed after a precharge time caused by the application of the first voltage, applying a second voltage (VCLMP1 + Vth - α) lower than the first voltage to the gate of the transistor (BLCLAMP).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a continuous read method, and more particularly to a read method for a NAND (Negative AND) type flash memory. Background Art

[0002] In a NAND type flash memory, a continuous read function (burst read function) for continuously reading multiple pages in response to an external command is provided. The page buffer / read circuit includes, for example, two latches. During a continuous read operation, while data read from the array is held in one latch, data held in the other latch can be output. Japanese Patent No. 6744950 discloses a continuous read method for further speeding up continuous reading. Summary of the Invention

[0003] In Figure 1 shows a schematic structure of a NAND type flash memory equipped with an on-chip Error Checking and Correction (ECC) function. The flash memory includes: a memory cell array 10 including NAND strings, a page buffer / read circuit 20, a data transfer circuit 30, a data transfer circuit 32, an error checking and correction circuit (hereinafter referred to as an ECC circuit) 40, and an input / output circuit 50. The page buffer / read circuit 20 includes two latches L1 and L2 (one latch is, for example, 4 KB) for holding read data or input data. The latch L1 and the latch L2 each include a cache C0 and a cache C1 (one cache is, for example, 2 KB). The data transfer circuits 30 and 32 can perform bidirectional data transfer of cache units between the page buffer / read circuit 20 and the ECC circuit and the input / output circuit 50.

[0004] In Figure 2 shows a timing chart during continuous reading of multiple pages disclosed in Japanese Patent No. 6744950. Data of page P0 read from the memory cell array 10 is held in the caches C0 and C1 of the latch L1 (P0C0, P0C1). Then, the data of page P0 held in the latch L1 is transferred to the caches C0 and C1 of the latch L2, and the data in the caches C0 and C1 is ECC decoded by the ECC circuit 40. In the case where an error is detected, the data in the caches C0 and C1 of the latch L2 is corrected.

[0005] Read the data of the next page P1 into the caches C0 and C1 of the latch L1. During this period, output the data of the cache C0 of the latch L2 synchronously with the external clock signal ExCLK through the input / output circuit 50. Next, output the data of the cache C1 of the latch L2 from the input / output circuit 50 synchronously with the external clock signal ExCLK. During this period, transfer the data of the page P1 of the first cache C0 of the latch L1 to the latch L2, and perform ECC processing by the ECC circuit 40. Next, transfer the data of the cache C1 of the latch L1 to the latch L2. During the period when the data of the cache C0 of the latch L2 is output from the input / output circuit 50, perform ECC processing on the data of the cache C1 of the latch L2. Subsequently, during the period when the data of the cache C1 of the latch L2 is output from the input / output circuit 50, read the data of the next page P2 into the caches C0 and C1 of the latch L1, transfer the data of the cache C0 to the latch L2, and perform ECC processing.

[0006] Figure 3(A) shows the operation flow of normal page reading of a NAND flash memory. When starting the read operation, first, reset the latch L1 before precharging the bit lines (S10). The reset of the latch L1 is used to accurately receive the charge from the read node. Next, start precharging the bit lines (S12). The precharging of the bit lines is performed by supplying voltage from the clamping transistor. Apply VCLMP1 + Vth (Vth is the threshold of the transistor) to the gate of the clamping transistor and supply voltage VCLMP1 to the bit lines. The clamping transistor is turned on during the precharging time T PR and then turned off (S14). After precharging the bit lines, to sense and select the memory cells, discharge the NAND string (S16), and then transfer the charge of the read node to the latch L1 (S18).

[0007] In Japanese Patent No. 6744950, in order to maximize the frequency of the external clock signal ExCLK to achieve high-speed reading, the start timing of the array reading is changed not to the end of the data transfer from the latch L1 to the latch L2, but to an earlier time point when the data of the cache C0 of the latch L1 is transferred to the latch L2. However, if the start timing of the array reading is advanced, there is a risk that the time for resetting the latch L1 cannot be sufficiently ensured. Therefore, the present inventor disclosed a method of resetting the latch L1 after precharging the bit lines in a previous application (Japanese Patent Application No. 2020-074503). The operation flow is shown in Figure 3(B). Start precharging the bit lines (S20), wait for the precharging time T PRAfter pre-charging is completed (S22), the latch L1 is then reset (S24), the NAND string is discharged (S26), and the charge of the read node is transferred to the latch L1 (S28).

[0008] In continuous reading, if the frequency of the external clock signal ExCLK is less than the lower limit value, the pre-charge time T PR is longer than the determined time, and the pre-charge voltage of the bit line is higher than the designed optimal level, thus there is a risk of misjudgment of the read data.

[0009] Figure 4 (A) is a timing diagram for continuous reading at a high speed frequency, Figure 4 (B) is a timing diagram for continuous reading at a low speed frequency. In the figure, "Precharge" represents the pre-charge of the selected bit line GBL (for example, even bit lines), "L1 SET L" represents the initialization of the latch L1, "Discharge" represents the sequence of turning on the source-side selection transistor to connect the NAND string to the source line, applying a read voltage to the selected memory cell, and applying a read-through voltage to the non-selected memory cell, and "SNS to L1" represents transferring the charge of the read node to the latch L1. T PR_NORMAL is the pre-charge time during normal reading or continuous reading at a high speed frequency, T PR_ADD is the excessive pre-charge time during continuous reading at a low speed frequency, and Top is the operating time.

[0010] In Figure 5 (A), the waveform of the pre-charge voltage is shown. The vertical axis is voltage and the horizontal axis is time. As Figure 5 (A) shows, when supplying the voltage VCLMP1 to the bit line, in order to saturate the pre-charge voltage of the bit line and make it constant, a certain amount of time is required. The reason is that the amount of current supplied from the clamping transistor to the bit line is small relative to the capacitance of the bit line. Therefore, the pre-charge voltage of the bit line is set at its level by specifying the pre-charge time.

[0011] Figure 5 (B) is Figure 5 an enlarged view of part A of PR_NORMAL (A). The pre-charge voltage at the end of the normal pre-charge time T PR_NORMAL is V PR_NORMAL , and the pre-charge voltage V Figure 4 is the optimal voltage designed in advance. On the other hand, in the case of reading at a low speed frequency as shown in PR_NORMAL (B), the pre-charge time T PR_ADD + T PR_NORMAL is longer than the normal pre-charge time TPR_ADD , becoming T PR_NORMAL < V PR_ADD . If the precharge voltage V PR_ADD is greater than the optimal precharge voltage V PR_NORMAL by more than necessary, during the discharge of the NAND string, even if the selected memory cell is turned on, the potential of the bit line will not drop sufficiently, and the readout node will hold more charge than assumed, resulting in a risk of misjudging the read data in the latch L1.

[0012] The precharge time T PR_NORMAL of the bit line may exceed or be extended not only during the continuous readout but also during a normal page readout as shown in FIG. 3(A). For example, when measuring the precharge voltage of the bit line in the operation analysis of a flash memory, if the readout sequence is temporarily stopped, the on-state of the clamping transistor continues, and as a result, the precharge voltage of the bit line rises. Then, a difference will occur between the measured precharge voltage and the actual precharge voltage, making it impossible to perform accurate operation analysis.

[0013] An object of the present invention is to solve such existing problems and provide a semiconductor device and a continuous readout method that suppress fluctuations in the precharge voltage caused by an increase in the precharge time.

[0014] The continuous readout method of the NAND-type flash memory of the present invention includes the following steps: applying a first voltage to the gate of a transistor connected to the bit line, supplying a voltage to the bit line via the transistor to start precharging of the bit line; and applying a second voltage lower than the first voltage to the gate of the transistor when a certain time has elapsed after the precharge time caused by the application of the first voltage.

[0015] In an embodiment of the present invention, the second voltage is a voltage level that limits the voltage pre-charged to the bit line within a certain range. In an embodiment of the present invention, the second voltage is a voltage level that prevents the pre-charged bit line from floating. In an embodiment of the present invention, the certain time is a time shorter than the pre-charge time, and the pre-charge time generates the optimal pre-charge voltage designed in the bit line by supplying the first voltage. In an embodiment of the present invention, the step of applying the second voltage is performed when the latch circuit that receives the charge of the readout node cannot be initialized. In an embodiment of the present invention, the step of applying the second voltage continues until the latch circuit can be initialized. In an embodiment of the present invention, the certain time is determined based on the time required to determine whether the latch circuit can be initialized. In an embodiment of the present invention, the continuous read method further includes a step of initializing the latch circuit after pre-charging the bit line. In an embodiment of the present invention, each step is performed during the continuous read of a page. In an embodiment of the present invention, the continuous read of a page includes: holding the data read from the selected page of the memory cell array in the latch circuit, transferring the data held in the latch circuit to another latch circuit, and then holding the data read from the next selected page in the latch circuit; synchronizing with an external clock signal to continuously output the data held in the other latch circuit to the outside; and performing error detection and correction on the data held in the other latch circuit.

[0016] The semiconductor device of the present invention includes: a NAND-type memory cell array; a readout component that reads data from a selected page of the memory cell array; and an output component that outputs the data read by the readout component to the outside. The readout component includes a page buffer / readout circuit connected to the memory cell array via a bit line. The page buffer / readout circuit includes a transistor for supplying a pre-charge voltage to the bit line. When pre-charging the bit line, the page buffer / readout circuit applies a first voltage to the gate of the transistor to start pre-charging, and when a certain time has elapsed during the pre-charge time, a second voltage lower than the first voltage is applied to the gate of the transistor.

[0017] In one embodiment of the present invention, the second voltage is a voltage level that limits the precharged voltage of the bit line within a certain range. In one embodiment of the present invention, the second voltage is a voltage level that prevents the precharged bit line from becoming a floating state. In one embodiment of the present invention, the certain time is a time shorter than the precharging time, and the precharging time generates the optimal precharging voltage designed in the bit line by supplying the first voltage. In one embodiment of the present invention, the page buffer / readout circuit applies the second voltage when the latch circuit that receives the charge of the readout node cannot be initialized, and the application of the second voltage continues until the initialization of the latch circuit can be performed. In one embodiment of the present invention, the certain time is determined based on the time required to determine whether the initialization of the latch circuit can be performed. In one embodiment of the present invention, the readout component also initializes the latch circuit after the precharging of the bit line. In one embodiment of the present invention, the readout component performs continuous reading of pages. In one embodiment of the present invention, the page buffer / readout circuit further includes another latch circuit that receives the data held in the latch circuit. When the readout component performs continuous reading, during the period of outputting the data of the other latch circuit, the latch circuit holds the data read from the next selected page of the memory cell array. In one embodiment of the present invention, the semiconductor device further includes an ECC circuit that performs error detection and correction of data. When the readout component performs continuous reading, during the period when the data held in the first part of the other latch circuit is subjected to ECC processing by the ECC circuit, the readout component outputs the ECC-processed data held in the second part of the other latch circuit.

[0018] According to the present invention, since the gate voltage of the transistor that supplies voltage to the bit line decreases when a certain time has elapsed after the precharging time of the bit line, even if the precharging time becomes longer, the precharging voltage of the bit line can be limited within a certain range, and misjudgment of the read data can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic structural diagram showing a conventional NAND-type flash memory;

[0020] Figure 2 is a timing diagram when continuous reading of pages is performed in a conventional NAND-type flash memory;

[0021] FIGS. 3(A) and 3(B) are flowcharts for explaining the read operation of a conventional NAND-type flash memory;

[0022] Figure 4 The (A) of... is a timing diagram when continuous reading is performed at a high speed frequency, Figure 4 The (B) of... is a timing diagram when continuous reading is performed at a low speed frequency;

[0023] Figure 5 The (A) of...Figure 5 (B) is an illustration of a transition waveform of a precharge voltage;

[0024] Figure 6 is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention;

[0025] Figure 7 is a diagram showing the structure of a bit line selection circuit of a flash memory according to an embodiment of the present invention;

[0026] Figure 8 is a diagram showing the structure of a page buffer / readout circuit of a flash memory according to an embodiment of the present invention;

[0027] Figure 9 is a flowchart for explaining the precharge operation of a bit line according to an embodiment of the present invention;

[0028] Figure 10 is a transition waveform of a precharge voltage based on an embodiment of the present invention;

[0029] Figure 11 is a timing diagram showing the reset operation of a latch circuit in a flash memory according to an embodiment of the present invention.

[0030] Description of symbols

[0031] 10, 110: Memory cell array

[0032] 20, 170: Page buffer / readout circuit

[0033] 30, 32: Data transfer circuit

[0034] 40, 130: Error detection and correction circuit (ECC circuit)

[0035] 50: Input / output circuit

[0036] 100: Flash memory

[0037] 120: Input / output circuit

[0038] 140: Address register

[0039] 150: Controller

[0040] 160: Word line selection circuit

[0041] 180: Column selection circuit

[0042] 190: Internal voltage generation circuit

[0043] 200: Bit line selection circuit

[0044] 210: Decision circuit

[0045] Ax: Row address information

[0046] Ay: Column address information

[0047] BLCD1, BLCD2, BLCLAMP, BLCN, BLPRE, BLSe, BLSo, CACHE, DTG, EQ, REG, RESET2, VG, YBLe, YBLo: Transistors

[0048] BLS, SLR1, SLR2, SLS1, SLS2, SNS, TOBL: Nodes

[0049] C0, C1: Caches

[0050] DL, / DL: Data lines

[0051] ExCLK: External clock signal

[0052] GBL: Select bit line

[0053] GBLe: Even bit line

[0054] GBLo: Odd bit line

[0055] GND: Ground level

[0056] L1, L2: Latches

[0057] LAT1: Latch enable signal

[0058] P0, P1, P2: Pages

[0059] S10, S12, S14, S16, S18, S20, S22, S24, S26, S28, S100, S110, S120, S130, S140, S150, S170: Steps

[0060] SA: Differential sense amplifier

[0061] SL: Source line

[0062] T PR 、T PR_ADD 、T PR_NORMAL : Precharge time

[0063] t1, t2, t3, t4, t5, t6, t7: Moments

[0064] V1, V2: Voltage supply nodes

[0065] VCLMP1: Clamping voltage (voltage)

[0066] VCLMP1 + Vth: First voltage (voltage)

[0067] VCLMP1 + Vth - α: Second voltage

[0068] VCLMP2: Readout voltage

[0069] Vdd: Supply voltage

[0070] Vers: Erase voltage

[0071] VIRPWR: Virtual power supply

[0072] Vpass: Pass voltage (voltage)

[0073] Vpgm: Programming voltage (write voltage)

[0074] Vread: Readout pass voltage

[0075] V PR_ADD 、V PR_NORMAL : Precharge voltage Detailed implementation manners

[0076] Next, the implementation manners of the present invention will be described in detail with reference to the accompanying drawings.

[0077] Figure 6FIG. 0 is a diagram showing the structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment includes the following components: a memory cell array 110 in which a plurality of memory cells are arranged in a matrix; an input / output circuit 120 connected to an external input / output terminal, responsive to an external clock signal ExCLK, and outputting read data to the outside or importing data input from the outside; an ECC circuit 130 that generates symbols of data to be programmed or performs error detection and correction of read data; an address register 140 that receives address data via the input / output circuit 120; a controller 150 that controls each part based on command data received via the input / output circuit 120 or a control signal applied to a terminal; a word line selection circuit 160 that receives row address information Ax from the address register 140, decodes the row address information Ax, and performs selection of a block or selection of a word line, etc. based on the decoding result; a page buffer / read circuit 170 that holds data read from a page selected by the word line selection circuit 160 or holds data to be programmed to the selected page; a column selection circuit 180 that receives column address information Ay from the address register 140, decodes the column address information Ay, and performs selection of a column in the page buffer / read circuit 170, etc. based on the decoding result; and an internal voltage generation circuit 190 that generates various voltages (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.) required for reading, programming, and erasing data.

[0078] The memory cell array 110 has, for example, m memory blocks BLK(0), BLK(1),..., BLK(m - 1) arranged in the column direction. A plurality of NAND strings are formed in one memory block, and the NAND strings are formed by connecting a plurality of memory cells in series. One NAND string includes a plurality of memory cells connected in series, a bit line side selection transistor, and a source line side selection transistor. The drain of the bit line side selection transistor is connected to a corresponding one of the bit lines, and the source of the source line side selection transistor is connected to a common source line. The control gate of the memory cell is connected to a word line, and the gates of the bit line side selection transistor and the source line side selection transistor are respectively connected to a selection gate line. The word line selection circuit 160 drives the bit line side selection transistor and the source line side selection transistor via the selection gate line based on the row address information Ax to select a block or a word. The NAND strings can be formed two-dimensionally on the substrate surface or three-dimensionally on the substrate surface. In addition, the memory cells can be single level cell (SLC) type that stores one bit (binary data) or multi level cell (MLC) type that stores multiple bits.

[0079] The structure of the bit line selection circuit is shown in Figure 7 FIG. Figure 7 An example of the bit line selection circuit 200 is illustrated. The bit line selection circuit 200 is connected to a page buffer / read circuit 170 shared by an even bit line GBLe and an odd bit line GBLo. The bit line selection circuit 200 includes: a transistor BLSe for selecting the even bit line GBLe, a transistor BLSo for selecting the odd bit line GBLo, a transistor YBLe for connecting the virtual power supply VIRPWR to the even bit line GBLe, and a transistor YBLo for connecting the virtual power supply VIRPWR to the odd bit line GBLo. A NAND string is connected between the even bit line GBLe and the source line SL, and a NAND string is connected between the odd bit line GBLo and the source line SL. For example, in the read operation, when the even bit line GBLe is selected, the odd bit line GBLo is not selected, and when the odd bit line GBLo is selected, the even bit line GBLe is not selected. The unselected bit line is connected to the ground (GND) level via the virtual power supply VIRPWR.

[0080] The structure of the page buffer / read circuit 170 is shown in Figure 8 FIG. Figure 8represents a page buffer / readout circuit. For convenience, the signal applied to the gate of the transistor is assumed to represent the transistor. The page buffer / readout circuit 170 includes two latches L1 and L2, and a transfer gate (transistor CACHE) is connected between the latch L1 and the latch L2. By turning on the transfer gate, bidirectional data transfer from the latch L1 to the latch L2 or from the latch L2 to the latch L1 can be performed.

[0081] The node SLR1 of the latch L1 is connected to the common source / drain (S / D) of the transistor BLCD1 and the transistor DTG, and the node SLS1 is connected to the determination circuit 210. The determination circuit 210 determines, for example, whether program verify or erase verify is qualified. When, in program verify or the like, the node SLR1 is selectively charged to Vdd or selectively discharged to GND from the voltage supply node V2, the transistor DTG is turned on. Furthermore, the latch L1 can short-circuit the node SLR1 and the node SLS1 through the transistor EQ.

[0082] The node SLR1 and the node SLS1 of the latch L1 are respectively connected to the node SLS2 and the node SLR2 of the latch L2 via the transistor CACHE. The node SLR2 of the latch L2 is connected to the readout node SNS via the transistor BLCD2, and the node SLS2 is connected to the transistor RESET2. When the latch L2 is reset, the transistor RESET2 is turned on. In addition, the node SLS2 and the node SLR2 are connected to the differential readout amplifier SA via the data line DL and the data line / DL, and the output of the differential readout amplifier SA is connected to the input / output circuit 120.

[0083] A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the readout node SNS, and the gate of the transistor VG is connected to the S / D of the transistor DTG. The voltage supply node V1 is connected to the readout node SNS via the transistor BLPRE. The voltage supply node V1 supplies the internal supply voltage Vdd when precharging the bit line and supplies the GND potential when resetting the latch L1. A transistor BLCN and a transistor BLCLAMP are connected in series between the readout node SNS and the node BLS of the bit line selection circuit 200.

[0084] The word line selection circuit 160 and the column selection circuit 180 select the read start position of the data within the page according to the row address information Ax and the column address information Ay, or automatically read the data from the beginning position of the page without using the row address and the column address. Furthermore, the word line selection circuit 160 and the column selection circuit 180 may include a row address counter and a column address counter that increment the row address and the column address in response to a clock signal.

[0085] In the read operation of the flash memory, a certain positive voltage is applied to the bit line, a certain voltage (e.g., 0 V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5 V) is applied to the non-selected word line to turn on the bit line side selection transistor and the source line side selection transistor, and 0 V is applied to the common source line. In the programming operation, a high programming voltage Vpgm (15 V to 20 V) is applied to the selected word line, an intermediate potential (e.g., 10 V) is applied to the non-selected word line to turn on the bit line side selection transistor and turn off the source line side selection transistor, and a potential corresponding to the data of "0" or "1" is supplied to the bit line. In the erase operation, 0 V is applied to the selected word line in the block, a high voltage (e.g., 20 V) is applied to the P-well, and data is erased in units of blocks by extracting electrons of the floating gate to the substrate.

[0086] Next, the precharge operation of the bit line of the flash memory 100 of the present embodiment will be described. Figure 9 It is a flowchart for explaining the precharge operation when resetting the latch L1 after precharging. For example, when performing array reading of the next page during continuous read operations of pages, the controller 150 first starts precharging of the bit line via the page buffer / read circuit 170 (S100).

[0087] The controller 150 switches the voltage supply node V1 to the supply voltage Vdd to turn on the transistor BLPRE and charge the read node SNS to the Vdd level. Next, a voltage VCLMP1 + Vth (Vth is the threshold of the transistor BLCLAMP) is applied to the gate of the transistor BLCLAMP, and the node TOBL is charged with the voltage VCLMP1. The transistor BLCN electrically connects the node TOBL and the node BLS, and the supply voltage Vdd is applied to the gate of the transistor BLCN to turn on the transistor BLCN and charge the node BLS with the voltage VCLMP1. Furthermore, the relationship of supply voltage Vdd ≧ VCLMP1 holds. In addition, the transistors BLCD1, BLCD2, and REG are non-conductive.

[0088] The controller 150 also precharges the selected bit line via the bit line selection circuit 200. Here, it is assumed that the even bit line GBLe is selected, the transistor BLSe is turned on, and the node BLS is electrically connected to the even bit line GBLe. In addition, the bit line side selection transistor of the NAND string connected to the even bit line GBLe is turned on, the source line side selection transistor is turned off, and the pass voltage is applied to the selected page and the non-selected page. Thereby, the voltage VCLMP1 is supplied to the even bit line GBLe (S110). On the other hand, the non-selected odd bit line GBLo is electrically connected to the GND of the virtual power supply VIRPWR via the transistor YBLo.

[0089] Next, after the supply of the voltage VCLMP1 to the selected bit line continues for a certain period of time, the controller 150 determines whether the latch L1 can be reset (S120). The certain period of time is a time slightly shorter than the precharge time T PR_NORMAL The precharge time T PR_NORMAL is used to generate the optimal precharge voltage V in the bit line PR_NORMAL (refer to Figure 4 (A) of Figure 4 (B) of Figure 5 (A) of Figure 5 (B) of). In one embodiment, the certain period of time is determined in consideration of the time T RST required to determine whether the latch L1 can be initialized. That is, the certain period of time is T PR_NORMAL -T RST . Thus, when the latch L1 can be reset after the certain period of time, the precharge time becomes the optimal precharge time T PR_NORMAL , and the optimal precharge time T PR_NORMAL is generated in the bit line. For example, when the optimal precharge time T PR_NORMAL is about 6 us, the time T RST required to determine whether the latch L1 can be initialized is about 0.2 us, and the certain period of time is about 5.8 us. The controller 150 can measure the certain period of time by counting, for example, an internal clock signal used to control the timing of the read operation.

[0090] There is no particular limitation on the method for determining whether the latch L1 can be reset. For example, when the transistor CACHE for transferring the data of the latch L1 to the latch L2 is turned on, it is determined that the latch L1 can be reset, or it is determined that the latch L1 can be reset by referring to a flag indicating the transfer of data from the latch L1 to the latch L2. By making the above determination, the latch L1 is initialized before the data stored in the latch L1 is transferred to the latch L2, thereby preventing data corruption.

[0091] In the case where it is determined that the latch L1 cannot be reset, that is, in the case where it is determined that the precharge time of the bit line exceeds the optimal precharge time T PR_NORMAL (S120), the controller 150 reduces the gate voltage of the transistor BLCLAMP to VCLMP1 + Vth - α (S130). Thereby, a voltage of VCLMP1 - α is supplied to the bit line, suppressing the increase in the precharge voltage of the bit line. If α is too small, the precharge voltage of the bit line increases. If α is too large, the precharge voltage of the bit line decreases, or the bit line becomes a floating state. Therefore, the magnitude of α is set such that even if the optimal precharge time T PR_NORMALThe precharge voltage generated in the bit line by the supply of the voltage VCLMP1 is also limited within a certain range.

[0092] Figure 10 Indicates the transition of the precharge voltage when the optimal α is set. When the precharge time T PR_NORMAL for obtaining the optimal precharge voltage V PR_NORMAL is exceeded, the precharge time T PR_NORMAL +T PR_ADD the precharge voltage V obtained PR_ADD is set in such a way that it becomes substantially constant, that is, |V PR_NORMAL -V PR_ADD | < a certain range. More preferably, V PR_NORMAL ≒V PR_ADD .

[0093] In addition, the precharge voltage of the bit line also depends on the operating temperature of the flash memory 100. In the case of a high operating temperature, compared with the low-temperature case, the increase in the precharge voltage of the bit line is larger. Therefore, it is desirable that α is larger at high temperatures than at low temperatures, and the gate voltage of the transistor BLCLAMP is further reduced. As an embodiment, the flash memory 100 is equipped with a temperature sensor, and the controller 150 can select α1 when the detected temperature of the temperature sensor exceeds the threshold, and select α2 (α1 > α2) when the detected temperature of the temperature sensor is below the threshold, and change the gate voltage of the transistor BLCLAMP according to the operating temperature. For example, α1 and α2 can be stored in the fuse memory that stores the operating conditions and the like.

[0094] After the controller 150 reduces the gate voltage of the transistor BLCLAMP to VCLMP1 + Vth - α, it stands by for a certain time (S140), and determines again whether the latch L1 can be reset (S120). The cycle continues until it is determined that the latch L1 can be reset. During this period, the precharge voltage of the bit line is maintained at a substantially constant level. When the controller 150 determines that the latch L1 can be reset, it turns off the transistor BLSe to separate the selected bit line from the node BLS, and after the precharge of the selected bit line is completed, it resets the latch L1 (S150). The reset of the latch L1 is performed by setting the node SLR1 to the L level (GND). The detailed operation will be described later.

[0095] After the latch L1 is reset, the controller 150 discharges the NAND string (S160) to sense the data of the selected memory cell. That is, the source-side select transistor is turned on to connect the NAND string to the source line, a read voltage is applied to the word line of the selected memory cell, and a read-through voltage is applied to the word line of the non-selected memory cell. At the same time, for sensing, the gate voltage of the transistor BLCLAMP is set to VCLMP2 + Vth, and VCLMP2 is set to the read voltage (in the relationship of VCLMP1 > VCLMP2). After the discharge time has elapsed, the transistor BLPRE is turned off, the transistors BLSe and BLCN are turned on, and then the source-side select transistor is turned off. Thus, when the selected memory cell is turned on, the charge of the selected bit line is discharged to the source line, and a voltage lower than the read voltage VCLMP2 is maintained at the read node SNS. On the other hand, when the selected memory cell is turned off, the charge of the bit line hardly changes and a voltage higher than the read voltage VCLMP2 is maintained, so Vdd is maintained at the read node SNS.

[0096] As Figure 4 shown in (B) of PR_NORMAL , when continuously reading with an external clock signal ExCLK at a low speed frequency, even if the optimal pre-charge time T PR_ADD is exceeded, the pre-charge voltage V PR_NORMAL of the selected bit line is also approximately equal to the optimal pre-charge voltage V

[0097] of the selected bit line. Therefore, when discharging the charge of the selected bit line, the potential of the selected bit line can be sufficiently reduced to a voltage lower than VCLMP2.

[0098] Next, the controller 150 turns on the transistor BLCD1 and transfers the charge of the read node SNS to the node SLR1 of the latch L1 (S170). If the transferred charge is above the threshold, the latch L1 determines the data as "1", and if it is less than the threshold, the latch L1 determines the data as "0" and holds the data. Even when the pre-charge time of the bit line is extended, the accurate charge is maintained at the read node SNS, so the latch L1 can accurately determine the data of the selected memory cell.

[0098] Next, refer to Figure 11The timing diagram of [0] illustrates the reset operation of the latch L1 after the precharge of the bit line. After the precharge of the bit line, the latch L1 is reset. During the reset period, the transistors BLPRE, BLCN, and BLCLAMP are in the conducting state. At time t1, the transistor BLSe is turned off, and the even bit line GBLe is electrically separated from the page buffer / readout circuit 170. Then, at time t2, the voltage supply node V1 changes to GND. As a result, the read node SNS drops from the supply voltage Vdd to the GND level, and the nodes TOBL and BLS drop from the clamping voltage VCLMP1 to the GND level.

[0099] Next, at time t3, the latch enable signal LAT1 for resetting the latch L1 changes from the H level to the L level, and the latch L1 is placed in a state where it can be reset. Then, at time t4, the transistor EQ is turned on for a certain period, and after the nodes SLR1 and SLS1 are short-circuited at the same potential, at time t5, the transistor BLCD1 is turned on for a certain period. As a result, the charge of the node SLR1 is discharged via the read node SNS to the GND of the voltage supply node V1, and the reset of the latch L1 is completed.

[0100] After the reset of the latch L1, the read node SNS and the like are restored. That is, the read node SNS, the nodes TOBL and BLS are recharged so that the voltages of these nodes are restored to the precharge state before the reset of the latch L1. At time t6, the voltage supply node V1 changes from GND to the supply voltage Vdd. As a result, the read node SNS is recharged to Vdd again, and the nodes TOBL and BLS are recharged to the clamping voltage VCLMP1 again. Then, at time t7, the transistor BLSe is turned on, and the even bit line GBLe is electrically connected to the page buffer / readout circuit 170. After the reset of the latch L1, the NAND string is discharged.

[0101] Next, other embodiments of the present invention will be described. In the above embodiment, the precharge operation during continuous readout in which the latch L1 is reset after the precharge of the bit line is illustrated, but the present invention can also be applied to the precharge operation during normal page readout. For example, when measuring the precharge voltage of the bit line in the operation analysis of the flash memory, if the read sequence is temporarily stopped, the transistor BLCLAMP remains in the conducting state, and the precharge time of the bit line exceeds the optimal precharge time T PR_NORMAL .

[0102] When the controller 150 exceeds the precharge time T PR_NORMAL as in the previous embodiment, the gate voltage of the transistor BLCLAMP is reduced from VCLMP1 + Vth to VCLMP1 + Vth - α to prevent the precharge voltage of the bit line from deviating from the optimal precharge voltage VPR_NORMAL Rise. Thus, in order to substantially eliminate the difference between the measured pre-charge voltage and the actual pre-charge voltage, accurate operation analysis can be performed.

[0103] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to specific embodiments and can be variously modified and changed within the scope of the gist of the present invention described in the claims.

Claims

1. A continuous reading method, which is a continuous reading method of a NAND flash memory, includes the following steps: Applying a first voltage to the gate of a transistor connected to a bit line, and supplying a voltage to the bit line via the transistor to start precharging of the bit line; And When a certain time has elapsed after the precharging time caused by applying the first voltage, applying a second voltage lower than the first voltage to the gate of the transistor, wherein the step of applying the second voltage is performed until the latch circuit that receives the charge of the read node can be initialized when the latch circuit cannot be initialized, and the certain time is determined based on the time required to determine whether the latch circuit can be initialized.

2. The continuous reading method according to claim 1, wherein The second voltage is a voltage level that limits the voltage precharged to the bit line within a certain range.

3. The continuous reading method according to claim 1, wherein, The second voltage is a voltage level that prevents the precharged bit line from becoming a floating state.

4. The continuous reading method according to claim 1, wherein, The certain time is a time shorter than the precharging time, and the precharging time generates the optimal precharging voltage designed in the bit line by supplying the first voltage.

5. The continuous reading method according to claim 1, wherein, The continuous reading method further includes a step of initializing the latch circuit after precharging the bit line.

6. The continuous reading method according to claim 5, wherein, Each of the above steps is implemented during continuous reading of a page, and the continuous reading of the page includes: holding the data read from the selected page of the memory cell array in the latch circuit, after transferring the data held in the latch circuit to another latch circuit, holding the data read from the next selected page in the latch circuit; Synchronizing with an external clock signal to continuously output the data held in the other latch circuit to the outside; and Performing error detection and correction on the data held in the other latch circuit.

7. A semiconductor device, including: A NAND-type memory cell array; A reading component that reads data from the selected page of the memory cell array; And An output component that outputs the data read by the reading component to the outside, The reading component includes a page buffer / read circuit connected to the memory cell array via a bit line, The page buffer / read circuit includes a transistor for supplying a precharging voltage to the bit line, When the page buffer / read circuit performs precharging of the bit line, it applies a first voltage to the gate of the transistor to start precharging, and when a certain time has elapsed after the precharging time, it applies a second voltage lower than the first voltage to the gate of the transistor, wherein the page buffer / read circuit applies the second voltage when the latch circuit that receives the charge of the read node cannot be initialized, and the application of the second voltage continues until the latch circuit can be initialized, and the certain time is determined based on the time required to determine whether the latch circuit can be initialized.

8. The semiconductor device according to claim 7, wherein, The second voltage is a voltage level that limits the precharged voltage of the bit line within a certain range.

9. The semiconductor device according to claim 7, wherein, The second voltage is a voltage level that prevents the precharged bit line from becoming a floating state.

10. The semiconductor device according to claim 7, wherein, The certain time is a time shorter than the precharging time, and the precharging time generates the optimal precharging voltage designed in the bit line by supplying the first voltage.

11. The semiconductor device according to claim 7, wherein, The read component further includes initializing the latch circuit after pre-charging the bit line.

12. The semiconductor device according to claim 7, wherein, The read component performs consecutive readouts of pages.

13. The semiconductor device according to claim 7, wherein The page buffer / read circuit further includes another latch circuit that receives the data held in the latch circuit. When the read component performs consecutive readouts, during the period of outputting the data of the other latch circuit, the latch circuit holds the data read from the next selected page of the memory cell array.

14. The semiconductor device according to claim 13, wherein, The semiconductor device further includes an error detection and correction circuit that performs error detection and correction of data. When the read component performs consecutive readouts, during the period in which the data held in the first part of the other latch circuit is subjected to error detection and correction processing by the error detection and correction circuit, the read component outputs the data subjected to error detection and correction processing held in the second part of the other latch circuit.

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