Semiconductor packaging method and semiconductor packaging structure

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: forming a first encapsulation structure and a second encapsulation structure; mounting the first encapsulation structure and the second encapsulation structure on a third carrier plate; forming a third encapsulation layer to obtain a third encapsulation structure; peeling off the third carrier plate; forming a through hole penetrating through the third encapsulation structure and forming a conductive structure in the through hole; arranging a third redistribution structure on a first surface of the third encapsulation structure and arranging a fourth redistribution structure on a second surface of the third encapsulation structure; the third redistribution structure is electrically connected with the fourth redistribution structure through the conductive structure; the first redistribution structure is electrically connected with a first redistribution structure of the first encapsulation structure and a second redistribution structure of the second encapsulation structure, respectively; and a passive component is arranged on a side of the fourth redistribution structure away from the second surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and semiconductor packaging structure. Background Technology

[0002] In semiconductor packaging technology, bare dies with different functions are often packaged in a package structure to form a specific function, resulting in a multi-chip module (MCM). Multi-chip modules have advantages such as high performance and multi-functionality.

[0003] With the miniaturization and weight reduction of electronic devices, compact and small multi-chip components are gaining increasing market favor. Therefore, reducing the size of multi-chip components has become a research hotspot. Summary of the Invention

[0004] A first aspect of this application provides a semiconductor packaging method. The semiconductor packaging method includes:

[0005] The process involves forming a first encapsulation structure and a second encapsulation structure. The first encapsulation structure includes: mounting a first die onto a first carrier plate, with the front side of the first die facing the first carrier plate and a plurality of first solder pads on the front side of the first die; forming a first encapsulation layer; peeling off the first carrier plate; and forming a first rewiring structure electrically connected to the first solder pads on the front side of the first die. The second encapsulation structure includes: mounting a second die onto a second carrier plate, with a plurality of second solder pads on the front side of the second die, and the front side of the second die facing the second carrier plate; forming a second encapsulation layer; peeling off the second carrier plate; and forming a second rewiring structure electrically connected to the second solder pads on the front side of the second die.

[0006] The first encapsulation structure and the second encapsulation structure are mounted on the third carrier board, with both the first rewiring structure and the second rewiring structure facing the carrier board.

[0007] A third encapsulation layer is formed, which encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation structure includes a first surface and a second surface opposite to the first surface, with the first surface facing the third carrier plate;

[0008] Peel off the third carrier plate;

[0009] A through-hole is formed that penetrates the third encapsulation structure and a conductive structure is formed within the through-hole. A third rewiring structure is provided on the first surface and a fourth rewiring structure is provided on the second surface. The third rewiring structure is electrically connected to the fourth rewiring structure through the conductive structure, and the third rewiring structure is electrically connected to both the first rewiring structure and the second rewiring structure.

[0010] A passive element is provided on the side of the fourth rewiring structure opposite to the second surface, and the passive element is electrically connected to the fourth rewiring structure.

[0011] In one embodiment, the semiconductor packaging method further includes: forming a first dielectric layer that completely covers the third redistribution structure, wherein the side of the third redistribution structure facing away from the first surface exposes the first dielectric layer.

[0012] In one embodiment, the semiconductor packaging method further includes:

[0013] A second dielectric layer is formed, which covers the fourth redistribution structure. The side of the fourth redistribution structure facing away from the second surface exposes the second dielectric layer, and the passive component is located on the side of the second dielectric layer facing away from the second surface.

[0014] In one embodiment, the fourth rewiring structure includes a prewiring substrate, the prewiring substrate including prewiring lines, the prewiring lines being electrically connected to the conductive structure and the passive component respectively.

[0015] In one embodiment, the orthographic projection of the first encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface; the orthographic projection of the second encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface.

[0016] In one embodiment, forming a through-hole penetrating the third encapsulation structure and forming a conductive structure within the through-hole, providing a third redistribution structure on the first surface, and providing a fourth redistribution structure on the second surface includes:

[0017] A third rewiring structure is provided on the first surface;

[0018] A through-hole is formed that penetrates the third encapsulation structure;

[0019] A conductive structure is formed within the through-hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure facing away from the first surface.

[0020] A fourth rewiring structure is provided on the second surface, and the fourth rewiring structure is electrically connected to the conductive structure.

[0021] A second aspect of this application provides a semiconductor packaging structure, the semiconductor packaging structure comprising:

[0022] A third encapsulation structure includes a first encapsulation structure, a second encapsulation structure, and a third encapsulation layer. The first encapsulation structure includes a first encapsulation layer, a first die, and a first rewiring structure. The first die has multiple first solder pads on its front side. The first encapsulation layer at least covers the side surface of the first die. The first rewiring structure is located on the front side of the first die and is electrically connected to the first solder pads. The second encapsulation structure includes a second encapsulation layer, a second die, and a second rewiring structure. The second die has multiple second solder pads on its front side. The second encapsulation layer at least covers the side surface of the second die. The second rewiring structure is located on the front side of the second die and is electrically connected to the second solder pads. The third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure. The third encapsulation structure includes a first surface and a second surface opposite to the first surface. The first rewiring structure and the second rewiring structure are respectively opposite to the second surface. The third encapsulation structure has through-holes penetrating the third encapsulation structure.

[0023] A conductive structure is located within the through hole;

[0024] A third rewiring structure is disposed on the first surface and is electrically connected to the first rewiring structure and the second rewiring structure, respectively.

[0025] A fourth rewiring structure is disposed on the second surface, and the third rewiring structure is electrically connected to the fourth rewiring structure through the conductive structure;

[0026] The passive component is disposed on the side of the fourth rewiring structure opposite to the second surface and is electrically connected to the fourth rewiring structure.

[0027] In one embodiment, the semiconductor package structure further includes a first dielectric layer that completely covers the third redistribution structure, with the side of the third redistribution structure facing away from the first surface exposing the first dielectric layer; and / or,

[0028] The semiconductor package structure further includes a second dielectric layer that covers the fourth redistribution structure. The side of the fourth redistribution structure facing away from the second surface exposes the second dielectric layer, and the passive component is located on the side of the second dielectric layer facing away from the second surface.

[0029] In one embodiment, the fourth rewiring structure includes a prewiring substrate, the prewiring substrate including prewiring lines, the prewiring lines being electrically connected to the conductive structure and the passive component respectively.

[0030] In one embodiment, the orthographic projection of the first encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface; the orthographic projection of the second encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface.

[0031] The semiconductor packaging method and semiconductor packaging structure provided in this application include a first die, a second die, and a passive component. The passive component is electrically connected to the first die and the second die through a fourth rewiring structure, a conductive structure, and a third rewiring structure, thereby enabling the semiconductor packaging structure to perform multiple functions. The first pad of the first die and the second pad of the second die are respectively electrically connected to the third rewiring structure located on the front side of the first die. The third rewiring structure is electrically connected to the fourth rewiring structure located on the side opposite to the front side of the first die through a conductive structure. Thus, the fourth rewiring structure leads the first pad of the first die and the second pad of the second die to the side of the semiconductor packaging structure opposite to the front side of the first die. On the other side, double-sided wiring of the packaging structure is achieved, and the external structure can be electrically connected to the side of the semiconductor packaging structure opposite to the front of the first die. The first and second dies are placed horizontally, making reasonable use of the horizontal space, which makes the semiconductor packaging structure relatively thin, small in size, and compact, making it suitable for small and lightweight electronic devices. Encapsulating the first and second dies before packaging can improve the reliability of the first and second die packaging. Moreover, after encapsulating the first and second dies, rewiring can be performed on the first and second dies respectively before forming the third encapsulation structure, which helps to achieve more complex wiring in the semiconductor packaging structure and improve the performance of the semiconductor packaging structure. Attached Figure Description

[0032] Figure 1 This is a flowchart of a semiconductor packaging method provided in an exemplary embodiment of this application;

[0033] Figure 2 This is a flowchart of forming an encapsulation structure provided in an exemplary embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of a silicon wafer used to prepare a first bare wafer, provided in an exemplary embodiment of this application;

[0035] Figure 4 yes Figure 3 The diagram shows a structure in which a protective film is formed on the active surface of a silicon wafer.

[0036] Figure 5 Yes Figure 4 The diagram shows the structure obtained by cutting a silicon wafer.

[0037] Figure 6 This is a schematic diagram of the structure of the first bare die provided in an exemplary embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the first intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0039] Figure 8 yes Figure 7 The top view of the first intermediate structure shown;

[0040] Figure 9 This is a schematic diagram of the second intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0041] Figure 10 This is a schematic diagram of the third intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0042] Figure 11 This is a schematic diagram of the fourth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0043] Figure 12 This is a schematic diagram of the fifth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0044] Figure 13 This is a schematic diagram of the structure of the first encapsulation structure provided in an exemplary embodiment of this application;

[0045] Figure 14 This is a schematic diagram of the second encapsulation structure provided in an exemplary embodiment of this application;

[0046] Figure 15 This is a schematic diagram of the sixth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0047] Figure 16 yes Figure 15 A top view of the sixth intermediate structure of the second encapsulation structure shown;

[0048] Figure 17 This is a schematic diagram of the seventh intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0049] Figure 18 This is a schematic diagram of the third encapsulation structure provided in an exemplary embodiment of this application;

[0050] Figure 19 This is a flowchart of a semiconductor packaging method provided in another exemplary embodiment of this application;

[0051] Figure 20 This is a schematic diagram of the eighth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0052] Figure 21 This is a schematic diagram of the ninth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0053] Figure 22 This is a schematic diagram of the tenth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0054] Figure 23 This is a schematic diagram of the eleventh intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0055] Figure 24 This is a schematic diagram of the twelfth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0056] Figure 25 This is a schematic diagram of the thirteenth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0057] Figure 26 This is a top view of a pre-wiring substrate provided in an exemplary embodiment of this application;

[0058] Figure 27 This is a cross-sectional view of a sub-region of a pre-wiring substrate provided in an exemplary embodiment of this application;

[0059] Figure 28 This is a schematic diagram of the thirteenth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0060] Figure 29 This is a schematic diagram of a semiconductor packaging structure provided in an exemplary embodiment of this application. Specific Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0062] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0063] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0064] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0065] This application provides a semiconductor packaging method. See also... Figure 1 The semiconductor packaging method includes the following steps 110 to 160.

[0066] In step 110, a first encapsulation structure and a second encapsulation structure are formed.

[0067] In one embodiment, see Figure 2 The process of forming the first encapsulation structure may include the following steps 111 to 114.

[0068] In step 111, a first die is mounted on a first carrier board. The first die has a front side facing the first carrier board, and the front side of the first die has a plurality of first solder pads.

[0069] In one embodiment, the first bare wafer can be prepared by the following process:

[0070] First, silicon wafers are provided, each with a specific function. See also... Figure 3 The silicon wafer 14 has an active surface, on which a first insulating layer 12 and a first bonding pad 11 are provided. The first insulating layer 12 can cover the edge of the first bonding pad 11. An opening is provided on the first insulating layer 12, exposing the first bonding pad 11. The first bonding pad 11 is used for electrical connection with external components.

[0071] Then see Figure 4A first protective layer 13 is formed on the active surface of the silicon wafer 14. The first protective layer 13 is one or more layers of insulating material, and the material of the first protective layer 13 can be a molding compound, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. The first protective layer 13 can be formed on the silicon wafer 14 by lamination, spin coating, printing, molding, or other suitable methods. Through this step, a product such as... Figure 4 The structure shown.

[0072] Subsequently, silicon wafer 14 is cut. It can be cut along... Figure 4 The silicon wafer 14 is cut at the location indicated by the dotted line. The silicon wafer 14 can be cut mechanically or by laser cutting. Optionally, before cutting the silicon wafer 14, a grinding machine can be used to grind the back side of the silicon wafer opposite the active side to achieve a specified thickness for the silicon wafer 14. This step yields the following result: Figure 5 The structure shown.

[0073] Subsequently, Figure 5 The first protective layer 13 of the structure shown is etched to form an opening 131, resulting in the structure shown. Figure 6 The first die 10 shown has a specific function. An opening 131 in the first protective layer 13 exposes the first bonding pad of the first die 10. The first bonding pad of the first die 10 is formed by conductive electrodes led from the internal circuitry of the die to the surface of the die. In some embodiments, if the first protective layer 13 is a laser-reactive material, the opening 131 can be formed by laser engraving; if the material of the first protective layer 13 is a photosensitive material, the opening 131 can be formed by photolithography using a mask.

[0074] In other embodiments, during the preparation of the first bare die 10, an opening 131 may also be formed on the first protective layer 13 before the silicon wafer 14 is cut.

[0075] Step 111 yields the following result: Figure 7 and Figure 8 The first intermediate structure shown. Figure 7 This illustration only shows one first bare die 10 mounted on the first carrier board 15. In reality, there are multiple first bare dies 10 mounted on the first carrier board 15, such as... Figure 8 As shown.

[0076] In one embodiment, the first substrate 15 may be circular, rectangular, or other shapes. The first substrate 15 may be a small-sized wafer substrate or a larger-sized substrate, such as a stainless steel substrate, a polymer substrate, etc.

[0077] In one embodiment, the first bare sheet 10 can be attached to the first carrier plate 15 by an adhesive layer, and the adhesive layer can be made of an easy-to-peel material so that the first carrier plate 15 can be peeled off from the first bare sheet 10 in the future. For example, the adhesive layer can be made of a heat-removing material that can be heated to lose its stickiness.

[0078] In one embodiment, a mounting device may be used to mount the first bare die 10 onto the first carrier board 15.

[0079] The process of mounting the first bare die 10 onto the first carrier plate 15 may include the following steps:

[0080] First, the first carrier board 15 is placed on the platform of the placement equipment. The first carrier board 15 has multiple placement areas, and each placement area has an alignment mark.

[0081] Subsequently, the camera device of the mounting equipment takes a picture of the first carrier board 15, and the controller of the mounting equipment determines the position of each mounting area based on the position of the alignment mark in the picture.

[0082] Subsequently, multiple robotic arms of the mounting equipment grab the first bare die 10, so that the opening 131 of the first bare die 10 faces the first carrier board 15;

[0083] Subsequently, the camera device of the mounting equipment takes pictures of the multiple first bare wafers 10 picked up by the robotic arm, and the controller of the mounting equipment determines the position of each first bare wafer 10 based on the position of the opening 131 in the captured pictures.

[0084] Subsequently, the controller of the mounting equipment determines whether the position of the first bare die 10 and the position of its corresponding mounting area correspond. If they do not correspond, the robotic arm of the mounting equipment moves the first bare die 10 so that the position of the first bare die 10 after the movement corresponds to the position of the corresponding mounting area.

[0085] Subsequently, the first bare die 10 is mounted on the corresponding mounting area of ​​the first carrier board 15.

[0086] During the process of mounting the first die 10 onto the first carrier board 15, the opening 131 of the first protective layer 13 serves as an alignment mark, which enables the first die 10 to be more accurately aligned with the corresponding mounting area, improving the mounting accuracy and thus improving the packaging accuracy. Furthermore, since the opening 131 of the first protective layer 13 serves as an alignment mark, it is not necessary to set an alignment mark pattern on the front side of the first die 10, which helps to simplify the complexity of the preparation process of the first die 10.

[0087] In step 112, the first encapsulation layer is formed.

[0088] In this step, the first encapsulation layer is formed and covers the first carrier plate, encapsulating the first die.

[0089] Step 112 yields the following result: Figure 9 The second intermediate structure shown includes a first carrier plate and an encapsulation structure located on the first carrier plate. See also... Figure 9 A first encapsulation layer 16 is formed on the first die 10 and the exposed first carrier plate 15 to completely encapsulate the first die 10, thereby reconstructing a planar structure so that after the first carrier plate 15 is peeled off, rewiring and encapsulation can continue on the reconstructed planar structure. During the formation of the first encapsulation layer 16, a first protective layer 13 located on the front side of the first die 10 protects the front side of the first die 10, preventing the material of the first encapsulation layer 16 from damaging the front side of the first die 10.

[0090] In one embodiment, before forming the first encapsulation layer 16, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surfaces of the first die 10 and the first carrier plate 15, so that the first encapsulation layer 16 can be more closely connected to the first die 10 and the first carrier plate 15, and delamination or cracking will not occur.

[0091] In one embodiment, the first encapsulation layer 16 can be a polymer, resin, resin composite material, or polymer composite material. For example, the first encapsulation layer 16 can be a resin with fillers, wherein the fillers are inorganic particles. The first encapsulation layer 16 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0092] In step 113, the first carrier plate is peeled off.

[0093] After peeling off the first carrier plate 15, the front side of the first bare die 10 is exposed, resulting in the following: Figure 10 The third intermediate structure shown.

[0094] In one embodiment, the first carrier plate 15 can be directly and mechanically peeled off from the first encapsulation layer 16 and the first bare sheet 10. In another embodiment, the first carrier plate 15 and the first bare sheet 10 are bonded together by an adhesive layer, and when the adhesive layer is made of a heat-removing material, the adhesive layer can be heated to reduce its stickiness, thereby allowing the first carrier plate 15 to be peeled off. After the first carrier plate 15 is peeled off, the front side of the first bare sheet 10 is exposed.

[0095] In the illustrated embodiment, the front of the first die 10 exposes the first encapsulation layer 16. In other embodiments, the front of the first die 10 may not expose the first encapsulation layer 16. For example, the first encapsulation layer 16 may have a cavity for accommodating the first die 10, the thickness of the first die 10 being less than the depth of the cavity, and the front of the first die 10 facing the opening of the cavity.

[0096] In step 114, a first rewiring structure electrically connected to the first solder pad is formed on the front side of the first die.

[0097] After forming the first rewiring structure on the front side of the first die 10, the following is obtained: Figure 11 The fourth intermediate structure shown. See also Figure 11 The first rewiring structure 17 includes a rewiring layer, which includes a first conductive trace 171 electrically connected to the first pad and a first conductive protrusion 172 located on the side of the first conductive trace 171 facing away from the first die 10. The first encapsulation structure may also include a first conductive portion 18 filled in the opening 231, through which the first conductive trace 171 is electrically connected to the first pad. In the illustrated embodiment, the first rewiring structure 17 includes only one rewiring layer. In other embodiments, the first rewiring structure may include two or more rewiring layers, with adjacent rewiring layers electrically connected. The first rewiring structure brings out the first pad of the first die 10, which can improve the reliability of the electrical connection between the first pad and the subsequently formed third rewiring structure; and the first rewiring structure is conducive to realizing more complex wiring in the semiconductor package structure, which helps to improve the performance of the semiconductor package structure.

[0098] In some embodiments, the first conductive portion 18 and the first conductive trace 171 can be formed in the same process step. This allows both the first conductive portion 18 and the first conductive trace 171 to be formed simultaneously in a single process step, simplifying the semiconductor packaging process. In other embodiments, the first conductive portion 18 and the first conductive trace 171 may not be formed simultaneously; the first conductive portion 18 may be formed first, followed by the first conductive trace 171.

[0099] In some embodiments, the first conductive portion 18, the first conductive trace 171, and the first conductive protrusion 172 may be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The materials of the first conductive portion 18, the first conductive trace 171, and the first conductive protrusion 172 may be metallic materials, such as copper.

[0100] In one embodiment, after forming the first rewiring structure, the step of forming the first encapsulation structure may further include: forming a first dielectric material layer, the first dielectric material layer covering the first rewiring structure, and the surface of the first conductive protrusion exposing the first dielectric material layer. After forming the first dielectric material layer, the following can be obtained: Figure 12 The fifth intermediate structure shown.

[0101] See Figure 12The first dielectric material layer 19 covers the first redistribution structure 17, and the first conductive protrusion 172 is exposed away from the surface of the first die 10. The first dielectric material layer 19 can protect the first redistribution structure 17 and prevent the first redistribution structure 17 from contacting the subsequently formed conductive structure and affecting the performance of the semiconductor package structure.

[0102] The distance from the side of the first dielectric material layer 19 away from the first die 10 to the first die 10 is approximately the same as the distance from the side of the first conductive protrusion 172 away from the first die 10 to the first die 10, so that the surface of the first conductive protrusion 172 just exposes the first dielectric material layer 19. During the formation of the first dielectric material layer 19, the initially formed first dielectric material layer 19 can cover the surface and sides of the first conductive protrusion 172, and then the first dielectric material layer 19 is thinned to expose the surface of the first conductive protrusion 172 away from the first die 10.

[0103] In one embodiment, the first dielectric material layer 19 is one or more layers of insulating material. The material of the first dielectric material layer 19 can be a molding compound, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties. The first dielectric material layer 19 can be formed by lamination, spin coating, printing, molding, or other suitable methods.

[0104] In obtaining Figure 12 After the fifth intermediate structure shown, the fifth intermediate structure is cut to obtain multiple [other structures]. Figure 13 The first encapsulation structure 101 is shown. Each first encapsulation structure 101 may include a first die 10.

[0105] In one embodiment, the step of forming the second encapsulation structure includes the following process:

[0106] First, the second die is mounted on the second carrier board. The front side of the second die has multiple second solder pads, and the front side of the second die faces the second carrier board.

[0107] Subsequently, a second sealing layer is formed;

[0108] Subsequently, the second carrier plate was peeled off;

[0109] Subsequently, a second rewiring structure electrically connected to the second solder pad is formed on the front side of the second die.

[0110] The process of forming the second encapsulation structure is similar to that of forming the first encapsulation structure and will not be described in detail here. The formed second encapsulation structure can be as follows: Figure 14 As shown.

[0111] See Figure 14The second encapsulation structure 201 includes a second die 20 and a second encapsulation layer 21. The second encapsulation layer 21 at least covers the side portion of the second die 20. In the illustrated embodiment, the second encapsulation layer 21 encapsulates the back and side portions of the second die 20. A second protective layer 25 is provided on one side of the front portion of the second die 20. An opening 251 is formed on the second protective layer 25 to expose the second solder pad of the second die 20. The second encapsulation structure 201 may also include a second conductive portion 23, which is located within the opening 251.

[0112] The second rewiring structure 22 is located on the side of the second protective layer 25 opposite to the second die 20. The second rewiring structure 22 is electrically connected to the second pad of the second die 20 through the second conductive portion 23. The second rewiring structure 22 includes a rewiring layer, which includes a second conductive trace 221 electrically connected to the second pad and a second conductive protrusion 222 located on the side of the second conductive trace 221 opposite to the first die 10. The second conductive trace 221 is electrically connected to the second pad through the second conductive portion 23. In the illustrated embodiment, the second rewiring structure 22 includes only one rewiring layer. In other embodiments, the second rewiring structure 22 may include two or more rewiring layers, with adjacent rewiring layers electrically connected. The second rewiring structure 22 leads out the second pad of the second die 20, which can improve the reliability of the electrical connection between the second pad and the subsequently formed third rewiring structure; and the second rewiring structure is conducive to realizing more complex wiring in the semiconductor package structure, which helps to improve the performance of the semiconductor package structure.

[0113] The second encapsulation structure 201 may further include a second dielectric material layer 24, which covers the second redistribution structure 22. The second conductive protrusions 222 are exposed away from the surface of the second die 20. The second dielectric material layer 24 protects the second redistribution structure 22 and prevents the second redistribution structure 22 from contacting with subsequently formed conductive structures, thus avoiding any impact on the performance of the semiconductor package structure.

[0114] In step 120, the first encapsulation structure and the second encapsulation structure are mounted on the third carrier board, with both the first rewiring structure and the second rewiring structure facing the carrier board.

[0115] Step 120 yields the following result: Figure 15 and Figure 16 The sixth intermediate structure shown.

[0116] In one embodiment, the third carrier board has a mounting area for mounting a first encapsulation structure and a mounting area for mounting a second encapsulation structure. The first encapsulation structure and the second encapsulation structure are respectively mounted in their respective mounting areas. Figure 15The illustration only takes an example of a third carrier board 30 with one first encapsulation structure 101 and one second encapsulation structure 201 mounted on it. In reality, the third carrier board 30 may have multiple first encapsulation structures 101 and multiple second encapsulation structures 201 mounted on it, such as... Figure 16 As shown. Each first encapsulation structure 101 corresponds to a second encapsulation structure 201, and the first encapsulation structure 101 and the corresponding second encapsulation structure 201 are arranged adjacent to each other.

[0117] In one embodiment, when mounting the first encapsulation structure 101 and the second encapsulation structure 201 onto the third carrier board 30, the first conductive protrusion 172 and the second conductive protrusion 222 can be used as alignment marking patterns. This allows for more accurate alignment of the first encapsulation structure 101 and the second encapsulation structure 201 with their corresponding mounting areas, improving mounting accuracy and thus encapsulation accuracy. Furthermore, the first encapsulation structure 101 and the second encapsulation structure 201 do not require alignment marking patterns, which helps simplify the complexity of the manufacturing process of the first encapsulation structure 101 and the second encapsulation structure 201.

[0118] In one embodiment, the first encapsulation structure 101 and the second encapsulation structure 201 can be attached to the third carrier plate 30 by an adhesive layer, and the adhesive layer can be made of an easy-to-peel material so that the third carrier plate 30 and the first encapsulation structure 101 and the second encapsulation structure 201 can be peeled off in the future. For example, the adhesive layer can be made of a heat-removing material that can lose its stickiness by heating.

[0119] In step 130, a third encapsulation layer is formed, which encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation structure includes a first surface and a second surface opposite to the first surface, with the first surface facing the third carrier plate.

[0120] Step 130 yields the following result: Figure 17 The seventh intermediate structure is shown. See also... Figure 17 The seventh intermediate structure includes a third carrier board 30 and a third encapsulation structure 301 located on the third carrier board 30. A third encapsulation layer 33 is formed on the first encapsulation structure 101, the second encapsulation structure 201, and the exposed third carrier board 30, completely encapsulating the first encapsulation structure 101 and the second encapsulation structure 201 to reconstruct the planar structure. This allows for rewiring and encapsulation on the reconstructed planar structure after the third carrier board 30 is peeled off. The first surface 311 of the third encapsulation structure 301 faces the third carrier board 30, and the second surface 312 faces away from the third carrier board 30.

[0121] In one embodiment, before forming the third encapsulation layer 33, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surfaces of the first encapsulation structure 101, the second encapsulation structure 201, and the third carrier plate 30, so that the first encapsulation structure 101, the second encapsulation structure 201, and the third carrier plate 30 can be more closely connected and there will be no delamination or cracking.

[0122] In one embodiment, the third encapsulation layer 33 can be a polymer, resin, resin composite material, or polymer composite material. For example, the third encapsulation layer 33 can be a resin with fillers, wherein the fillers are inorganic particles. The third encapsulation layer 33 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0123] In the illustrated embodiment, the third encapsulation structure 301 includes a first encapsulation structure and a second encapsulation structure. In other embodiments, the third encapsulation layer 33 of the third encapsulation structure 301 can encapsulate three or more encapsulation structures, that is, to encapsulate three or more bare dies.

[0124] In one embodiment, the thickness of the initially formed third encapsulation layer 33 may be greater than a specified thickness. After the third encapsulation layer 33 is formed, the semiconductor packaging method further includes: thinning the side of the third encapsulation layer away from the third substrate so that the thickness of the thinned third encapsulation layer is the specified thickness.

[0125] In step 140, the third carrier plate is peeled off.

[0126] Step 140 yields the following result: Figure 18 The third encapsulation structure is shown. See also... Figure 18 After the third carrier plate 30 is peeled off, the first conductive protrusion 172 of the first encapsulation structure 101 is exposed away from the surface of the first bare die 10, and the second conductive protrusion 222 of the second encapsulation structure 201 is exposed away from the surface of the second bare die 20.

[0127] In one embodiment, the third carrier plate 30 can be directly and mechanically peeled off from the third encapsulation structure 301. In another embodiment, the third carrier plate 30 is bonded to the third encapsulation structure 301 by an adhesive layer, and when the adhesive layer is made of a heat-removing material, the adhesive layer can be heated to reduce its stickiness, thereby allowing the third carrier plate 30 to be peeled off.

[0128] In step 150, a through-hole is formed penetrating the third encapsulation structure and a conductive structure is formed within the through-hole. A third rewiring structure is provided on the first surface and a fourth rewiring structure is provided on the second surface. The third rewiring structure and the fourth rewiring structure are electrically connected through the conductive structure. The third rewiring structure is also electrically connected to the first rewiring structure and the second rewiring structure.

[0129] In one embodiment, see Figure 19 Step 150 includes steps 151 to 154 as follows.

[0130] In step 151, a third rewiring structure is provided on the first surface.

[0131] In one embodiment, the semiconductor packaging method further includes: forming a first dielectric layer that covers the third redistribution structure, with the side of the third redistribution structure facing away from the first surface exposed by the first dielectric layer. The first dielectric layer protects the third redistribution structure. An external device can be electrically connected to the final semiconductor package structure through the surface of the third redistribution structure exposed by the first dielectric layer.

[0132] After forming the third rewiring structure and the first dielectric layer, the following can be obtained: Figure 20 The eighth intermediate structure shown. See also Figure 20 The third redistribution structure 40 includes a redistribution layer 41 and a redistribution layer 42 located on the side of the redistribution layer 41 facing away from the first surface 311. The redistribution layer 41 includes a third conductive trace 411 and a third conductive protrusion 412 located on the side of the third conductive trace 411 facing away from the first surface 311. The redistribution layer 42 includes a fourth conductive trace 421 located on the side of the third conductive protrusion 412 facing away from the first surface 311 and a fourth conductive protrusion 422 located on the side of the fourth conductive trace 421 facing away from the first surface 311. The side of the fourth conductive protrusion 422 facing away from the first surface 311 exposes the first dielectric layer. The third conductive trace 411 is electrically connected to the first solder pad and the second solder pad through the first redistribution structure 17. The third conductive trace 411 can electrically connect the first redistribution structure 17 and the second redistribution structure 22.

[0133] Figure 20In the illustrated embodiment, the third redistribution structure 40 includes two redistribution layers. The first dielectric layer 50 includes a first sub-dielectric layer 51 covering the redistribution layer 41 and a second sub-dielectric layer 52 covering the redistribution layer 42. The third conductive protrusion 412 of the redistribution layer 41 exposes the first sub-dielectric layer 51 on the surface away from the first surface 311, and the fourth conductive protrusion 422 of the redistribution layer 42 exposes the second sub-dielectric layer 52 on the surface away from the first surface 311. In other embodiments, the third redistribution structure 40 may include two or more redistribution layers, and each redistribution layer is covered by the first dielectric layer.

[0134] form Figure 20 The third redistribution structure shown, along with the formation of the first dielectric layer, includes the following processes:

[0135] First, a third conductive trace 411 and a third conductive protrusion 412 located on the side of the third conductive trace 411 facing away from the first die are formed on the first surface.

[0136] This step yields the following result: Figure 21 The ninth intermediate structure shown.

[0137] In this step, the third conductive trace 411 and the third conductive protrusion 412 can be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The material of the third conductive trace 411 and the third conductive protrusion 412 is a conductive material, such as metallic copper.

[0138] Subsequently, a first sub-dielectric layer 51 is formed, which covers the third conductive trace 411 and the third conductive protrusion 412. The side of the third conductive protrusion 412 facing away from the first surface 311 exposes the first sub-dielectric layer 51.

[0139] This step yields the following result: Figure 22 The tenth intermediate structure shown.

[0140] See Figure 22 The distance from the side of the first sub-dielectric layer 51 away from the first surface 311 to the first surface 311 is approximately the same as the distance from the side of the third conductive protrusion 412 away from the first surface 311 to the first surface 311, so that the surface of the third conductive protrusion 412 just exposes the first sub-dielectric layer 51. During the formation of the first sub-dielectric layer 51, the initially formed first sub-dielectric layer 51 can cover the surface and sides of the third conductive protrusion 412, and then the first sub-dielectric layer 51 is thinned to expose the surface of the third conductive protrusion 412.

[0141] The first sub-dielectric layer 51 is one or more layers of insulating material. The material of the first sub-dielectric layer 51 can be a molding film, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties. The first sub-dielectric layer 51 can be formed by lamination, spin coating, printing, molding, or other suitable methods.

[0142] Subsequently, a fourth conductive trace 421 and a fourth conductive protrusion 422 located on the side of the first sub-dielectric layer 51 opposite to the first surface 311 are formed.

[0143] This step yields the following result: Figure 23 The eleventh intermediate structure shown.

[0144] In this step, the fourth conductive trace 421 and the fourth conductive protrusion 422 can be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The material of the fourth conductive trace 421 and the fourth conductive protrusion 422 is a conductive material, such as metallic copper.

[0145] Subsequently, a second sub-dielectric layer 52 is formed, which covers the fourth conductive trace 421 and the fourth conductive protrusion 422. The side of the fourth conductive protrusion 422 facing away from the first surface exposes the second sub-dielectric layer 52.

[0146] This step yields the following result: Figure 20 The eighth intermediate structure shown.

[0147] The second sub-dielectric layer 52 can be one or more layers of insulating material. The material of the second sub-dielectric layer 52 can be a molding compound, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties. The second sub-dielectric layer 52 can be formed by lamination, spin coating, printing, molding, or other suitable methods.

[0148] In step 152, a through-hole is formed that penetrates the third encapsulation structure.

[0149] The number of through holes formed in this step can be multiple, and the through holes expose the third conductive trace 411.

[0150] In step 153, a conductive structure is formed in the through-hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure away from the first surface.

[0151] Step 153 yields the following result: Figure 24 The twelfth intermediate structure shown. See also... Figure 24 The number of conductive structures 60 is multiple.

[0152] In this step, a conductive structure 60 is formed by filling the through-hole with a conductive material. The conductive material is, for example, metallic copper. The conductive structure 60 is electrically connected to the first redistribution structure 40.

[0153] In one embodiment, see Figure 24 The orthographic projection of the first encapsulation structure 101 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311; the orthographic projection of the second encapsulation structure 201 on the first surface 311 is also outside the orthographic projection of the conductive structure 60 on the first surface 311. Thus, the conductive structure 60 is located between the first encapsulation structure 101 and the second encapsulation structure 201 of the third encapsulation structure 301, or on the side of the first encapsulation structure 101 and the second encapsulation structure 201, and the arrangement of the conductive structure 60 does not affect the first encapsulation structure 101 and the second encapsulation structure 201.

[0154] In step 154, a fourth rewiring structure is provided on the second surface, and the fourth rewiring structure is electrically connected to the conductive structure.

[0155] In one embodiment, the fourth rewiring structure is a prewiring substrate, and step 154 ​​can yield the following: Figure 25 The thirteenth intermediate structure is shown. See also... Figure 25 A pre-wiring substrate 84 is fixedly disposed on the second surface 312. The pre-wiring substrate 84 includes pre-wiring lines 841, which are electrically connected to the conductive structure 60.

[0156] See Figure 26 and Figure 27 The pre-wiring substrate 84 includes pre-wiring lines 841, which are relatively complex circuits. By setting the pre-wiring substrate on the second surface, compared to forming a redistribution layer on the second surface, it helps to reduce the probability of short circuits during the formation of the redistribution layer, thus improving product yield. Compared to forming a redistribution layer, the pre-wiring substrate reduces the complexity of the semiconductor packaging process and saves the time required to form the redistribution layer, thereby reducing the time required for the semiconductor packaging method. Furthermore, the pre-wiring substrate can be tested before packaging to avoid defects. The pre-wiring substrate includes relatively complex pre-wiring lines, and the pre-wiring substrate with complex multi-circuit redistribution rewires the intermediate packaging structure, improving the performance of the entire packaging structure.

[0157] The pre-wiring substrate 84 may also include an insulating material 842, in which pre-wiring lines 841 are formed. The insulating material 842 may include the pre-wiring lines 841 and give the pre-wiring lines 841 a fixed shape to facilitate the transfer of the pre-wiring lines.

[0158] The pre-wiring substrate 84 may include at least one sub-region 801, each sub-region 801 corresponding to a third encapsulation structure 301, and the pre-wiring lines 841 including sub-lines located within each sub-region 801. After the pre-wiring substrate is fixed on the second surface 312, each sub-region 801 corresponds to a third encapsulation structure 301, and the conductive structure 60 located in the third encapsulation structure 301 is electrically connected to the sub-lines in the corresponding sub-region 801.

[0159] Figure 19 The process shown in the embodiment is only one way to implement step 150. In other embodiments, the conductive structure 60 may be formed first, then the third rewiring structure may be set, and finally the fourth rewiring structure may be set; or, the conductive structure 60 may be formed first, then the fourth rewiring structure may be set, and finally the third rewiring structure may be set; or, the fourth rewiring structure may be set first, then the conductive structure 60 may be formed, and finally the first and third rewiring structures may be set. For details, please refer to steps 151 to 154, which will not be repeated here.

[0160] In one embodiment, after providing the fourth redistribution structure on the second surface, the semiconductor packaging method further includes:

[0161] A second dielectric layer is formed, which covers the fourth rewiring structure, with the second dielectric layer exposed on the side of the fourth rewiring structure opposite to the second surface.

[0162] When the fourth rewiring structure is a prewiring substrate, this step can achieve the following: Figure 28 The fifteenth intermediate structure shown. See also... Figure 28 The second dielectric layer 70 covers the pre-wiring substrate 84 and can protect the pre-wiring substrate 84.

[0163] In one embodiment, the second dielectric layer 70 is one or more layers of insulating material. The material of the second dielectric layer 70 can be a molding compound, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties. The second dielectric layer 70 can be formed by lamination, spin coating, printing, molding, or other suitable methods.

[0164] The distance from the side of the second dielectric layer 70 away from the second surface 312 to the second surface 312 is approximately the same as the distance from the side of the pre-wiring substrate 84 away from the second surface 312 to the second surface 312, so that the surface of the pre-wiring substrate 84 just exposes the second dielectric layer 70. During the formation of the second dielectric layer 70, the initially formed second dielectric layer 70 can cover the surface and sides of the pre-wiring substrate 84, and then the second dielectric layer 70 is thinned to expose the surface of the pre-wiring substrate 84 away from the second surface 312.

[0165] In step 160, a passive member is provided on the side of the fourth rewiring structure opposite to the second surface, and the passive member is electrically connected to the fourth rewiring structure.

[0166] This step yields the following result: Figure 29 The semiconductor packaging structure described above. See also... Figure 29 Multiple passive components 90 can be disposed on the side of the fourth rewiring structure opposite to the second surface 312. These passive components 90 can be identical or different. The passive components 90 are located on the side of the second dielectric layer 70 opposite to the second surface 312. When the fourth rewiring structure is a pre-wiring substrate 84, the passive components 90 are in direct contact and electrically connected to the pre-wiring lines 841. Conductive connection posts 90 are located on the side of the pre-wiring substrate 84 opposite to the second surface 312. The first solder pad of the first die 10 is electrically connected to the passive component 90 sequentially through the first rewiring structure 17, the third rewiring structure 40, the conductive structure 60, and the pre-wiring substrate 84. The second solder pad of the second die 20 is electrically connected to the passive component 90 sequentially through the second rewiring structure 22, the third rewiring structure 40, the conductive structure 60, and the pre-wiring substrate 84.

[0167] In one embodiment, the passive element 90 can be a capacitor, a resistor, an inductor, or the like.

[0168] An inductor is an electromagnetic conversion device. When the passive component 90 is an inductor, the semiconductor packaging structure can have the function of electromagnetic conversion, making the semiconductor packaging structure more functional.

[0169] When the passive component 90 is an inductor, step 160 of setting the passive component on the side of the fourth redistribution structure away from the second surface may include the following process: first, forming a seed layer on the side of the fourth redistribution structure away from the second surface; then, forming a metal layer on the side of the seed layer away from the second surface by electroplating; finally, patterning the seed layer and the metal layer to form an inductor.

[0170] In one embodiment, if the semiconductor package structure includes two or more third encapsulation structures, the semiconductor packaging method further includes: cutting the semiconductor package structure to obtain multiple sub-package structures, each sub-package structure including a third encapsulation structure.

[0171] The semiconductor packaging method provided in this application provides a semiconductor package structure including a first die, a second die, and a passive component. The passive component is electrically connected to the first and second dies through a fourth rewiring structure, a conductive structure, and a third rewiring structure, thereby enabling the semiconductor package structure to perform multiple functions. The first pad of the first die and the second pad of the second die are electrically connected to the third rewiring structure located on the front side of the first die. The third rewiring structure is electrically connected to the fourth rewiring structure located on the side opposite to the front side of the first die through a conductive structure. Thus, the fourth rewiring structure leads the first pad of the first die and the second pad of the second die to the side of the semiconductor package structure opposite to the front side of the first die, realizing double-sided wiring of the package structure. The external structure can be electrically connected to the side of the semiconductor package structure opposite to the front side of the first die. The first and second dies are placed horizontally, making reasonable use of the horizontal space, which makes the semiconductor package structure relatively thin, small in size, and compact in structure, making the semiconductor package structure suitable for small and lightweight electronic devices. Encapsulating the first and second dies before packaging can improve the reliability of the first and second die packaging.

[0172] This application also provides a semiconductor packaging structure. See [link to relevant documentation]. Figure 29 The semiconductor packaging structure includes:

[0173] The third encapsulation structure 301 includes a first encapsulation structure 101, a second encapsulation structure 201, and a third encapsulation layer 33. The first encapsulation structure 101 includes a first encapsulation layer 16, a first die 10, and a first rewiring structure 17. The first die 10 has a plurality of first solder pads on its front side. The first encapsulation layer 16 at least covers the sides of the first die 10. The first rewiring structure 17 is located on the front side of the first die 10 and is electrically connected to the first solder pads. The second encapsulation structure 201 includes a second encapsulation layer 21, a second die 20, and a second rewiring structure 22. The second die 20 has a plurality of second solder pads on its front side. The second encapsulation layer 21 at least covers the sides of the second die 20. The second rewiring structure 22 is located on the front side of the second die 20 and is electrically connected to the second solder pads. The third encapsulation layer 33 encapsulates the first encapsulation structure 101 and the second encapsulation structure 201; the third encapsulation structure 301 includes a first surface 311 and a second surface 312 opposite to the first surface 311, and the first redistribution structure 17 and the redistribution structure 22 are respectively away from the second surface 312. The third encapsulation structure 301 is provided with a through hole penetrating the third encapsulation structure;

[0174] The conductive structure 60 is located inside the through hole;

[0175] A third rewiring structure 40 is disposed on the first surface 311 and is electrically connected to the first rewiring structure and the second rewiring structure, respectively.

[0176] A fourth rewiring structure is disposed on the second surface 312, and the third rewiring structure 40 is electrically connected to the fourth rewiring structure through the conductive structure 60;

[0177] A passive component 90 is disposed on the side of the fourth rewiring structure opposite to the second surface 312, and the passive component 90 is electrically connected to the fourth rewiring structure.

[0178] In one embodiment, the fourth rewiring structure includes a prewiring substrate 84, which includes prewiring lines 841, which are electrically connected to the conductive structure 60 and the passive component 90, respectively.

[0179] In one embodiment, the semiconductor package structure further includes a first dielectric layer 50 that completely covers the third redistribution structure 40, with the first dielectric layer 50 exposed on the side of the third redistribution structure 40 facing away from the first surface 311.

[0180] In one embodiment, the semiconductor package structure further includes a second dielectric layer 70 that covers the fourth redistribution structure, with the side of the fourth redistribution structure facing away from the second surface 312 exposing the second dielectric layer 70. When the second semiconductor encapsulation structure includes a pre-wiring substrate 84, the second dielectric layer 70 covers the pre-wiring substrate 84, with the side of the pre-wiring lines 841 of the pre-wiring substrate 84 facing away from the second surface 312 exposing the second dielectric layer 70.

[0181] In one embodiment, the orthographic projection of the first encapsulation structure 101 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311; the orthographic projection of the second encapsulation structure 201 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311.

[0182] In one embodiment, the semiconductor package structure further includes a first dielectric material layer 19, which covers a first redistribution structure 17, with the first redistribution structure 17 exposing the first dielectric material layer 19 on a surface away from the first die 10.

[0183] In one embodiment, the semiconductor package structure further includes a second dielectric layer 24, which covers the second redistribution structure 22, and exposes the second dielectric layer 24 on the surface of the second die 20 away from the second die 20.

[0184] In one embodiment, the passive element 90 can be a capacitor, a resistor, an inductor, or the like.

[0185] The semiconductor packaging method and semiconductor packaging structure provided in the embodiments of this application belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0186] In this application, the device embodiments and method embodiments can complement each other without conflict. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0187] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor packaging method, characterized in that, The semiconductor packaging method includes: The process involves forming a first encapsulation structure and a second encapsulation structure. The first encapsulation structure includes: mounting a first die onto a first carrier plate, with the front side of the first die facing the first carrier plate and a plurality of first solder pads on the front side of the first die; forming a first encapsulation layer; peeling off the first carrier plate; and forming a first rewiring structure electrically connected to the first solder pads on the front side of the first die. The second encapsulation structure includes: mounting a second die onto a second carrier plate, with a plurality of second solder pads on the front side of the second die, and the front side of the second die facing the second carrier plate; forming a second encapsulation layer; peeling off the second carrier plate; and forming a second rewiring structure electrically connected to the second solder pads on the front side of the second die. The first die has a first protective layer on its front side, with openings that expose the first solder pads. When mounting the first die onto the first carrier plate, the openings in the first protective layer are used as alignment markers. The first encapsulation structure and the second encapsulation structure are mounted on the third carrier board, with both the first rewiring structure and the second rewiring structure facing the carrier board. A third encapsulation layer is formed, which encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation structure includes a first surface and a second surface opposite to the first surface, with the first surface facing the third carrier plate; Peel off the third carrier plate; A plurality of through-holes penetrating the third encapsulation structure are formed, and a conductive structure is formed within each of the through-holes. A third rewiring structure is disposed on the first surface, and a fourth rewiring structure is disposed on the second surface. The third rewiring structure is electrically connected to the fourth rewiring structure through the conductive structure, and the third rewiring structure is electrically connected to both the first and second rewiring structures. The fourth rewiring structure is a prewiring substrate, and the prewiring substrate includes prewiring lines. The step of forming the conductive structure is performed after the step of disposing the fourth rewiring structure on the second surface. A passive component is provided on the side of the fourth rewiring structure opposite to the second surface, and the passive component is electrically connected to the fourth rewiring structure; the pre-wiring lines are electrically connected to the conductive structure and the passive component respectively.

2. The semiconductor packaging method according to claim 1, characterized in that, The semiconductor packaging method further includes: forming a first dielectric layer, wherein the first dielectric layer completely covers the third redistribution structure, and the side of the third redistribution structure opposite to the first surface exposes the first dielectric layer.

3. The semiconductor packaging method according to claim 1, characterized in that, The semiconductor packaging method further includes: A second dielectric layer is formed, which covers the fourth redistribution structure. The side of the fourth redistribution structure facing away from the second surface exposes the second dielectric layer, and the passive component is located on the side of the second dielectric layer facing away from the second surface.

4. The semiconductor packaging method according to claim 1, characterized in that, The orthographic projection of the first encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface; The orthographic projection of the second encapsulation structure onto the first surface lies outside the orthographic projection of the conductive structure onto the first surface.

5. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure is prepared using the semiconductor packaging method according to any one of claims 1 to 4; the semiconductor packaging structure includes: A third encapsulation structure includes a first encapsulation structure, a second encapsulation structure, and a third encapsulation layer. The first encapsulation structure includes a first encapsulation layer, a first die, and a first rewiring structure. The first die has multiple first solder pads on its front side. The first encapsulation layer at least covers the side surface of the first die. The first rewiring structure is located on the front side of the first die and is electrically connected to the first solder pads. The second encapsulation structure includes a second encapsulation layer, a second die, and a second rewiring structure. The second die has multiple second solder pads on its front side. The second encapsulation layer at least covers the side surface of the second die. The second rewiring structure is located on the front side of the second die and is electrically connected to the second solder pads. The third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure. The third encapsulation structure includes a first surface and a second surface opposite to the first surface. The first rewiring structure and the second rewiring structure are respectively opposite to the second surface. The third encapsulation structure has through-holes penetrating the third encapsulation structure. A conductive structure is located within the through hole; A third rewiring structure is disposed on the first surface and is electrically connected to the first rewiring structure and the second rewiring structure, respectively. A fourth rewiring structure is disposed on the second surface, and the third rewiring structure is electrically connected to the fourth rewiring structure through the conductive structure; the fourth rewiring structure is a prewiring substrate, and the prewiring substrate includes prewiring lines. The passive component is disposed on the side of the fourth rewiring structure opposite to the second surface and is electrically connected to the fourth rewiring structure; the pre-wiring lines are electrically connected to the conductive structure and the passive component respectively.

6. The semiconductor packaging structure according to claim 5, characterized in that, The semiconductor packaging structure further includes a first dielectric layer, which completely covers the third redistribution structure, with the first dielectric layer exposed on the side of the third redistribution structure facing away from the first surface. And / or, The semiconductor package structure further includes a second dielectric layer that covers the fourth redistribution structure. The side of the fourth redistribution structure facing away from the second surface exposes the second dielectric layer, and the passive component is located on the side of the second dielectric layer facing away from the second surface.

7. The semiconductor packaging structure according to claim 5, characterized in that, The orthographic projection of the first encapsulation structure onto the first surface is located outside the orthographic projection of the conductive structure onto the first surface; The orthographic projection of the second encapsulation structure onto the first surface lies outside the orthographic projection of the conductive structure onto the first surface.

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