Display device

Abstract

A display device includes: a first transistor, comprising an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first transparent conductive layer, arranged on at least one first insulating layer on the first transistor, including an area overlapping with the gate wiring, and contacting the oxide semiconductor layer at a first contact area outside the gate wiring; a second transparent conductive layer, arranged on the second insulating layer on the first transparent conductive layer, and contacting the first transparent conductive layer at a second contact area overlapping with the gate wiring; a third transparent conductive layer, arranged between the second transparent conductive layer and at least one second insulating layer; a fourth transparent conductive layer, arranged on the second transparent conductive layer; a third insulating layer between the second transparent conductive layer and the third transparent conductive layer; and a fourth insulating layer between the second transparent conductive layer and the fourth transparent conductive layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. Background Art

[0002] Recently, the development of transistors using oxide semiconductors for channels has been advancing in place of amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon (e.g., Japanese Patent Publication No. 2014-146819 and Japanese Patent Publication No. 2015-159315). Like transistors using amorphous silicon for channels, transistors using oxide semiconductors for channels have a simple structure and are formed by a low-temperature process. It is known that transistors using oxide semiconductors for channels have higher mobility than transistors using amorphous silicon for channels, and have very low cutoff current.

[0003] In recent years, the pixel size reduction of display devices has been continuously promoted. Along with the reduction of pixel size, the reduction of wiring width and transistor size is being studied. However, there are limits to these reductions, which are caused by the configuration of the metal layer and semiconductor layer constituting the pixel circuit, and the aperture ratio becomes smaller. Therefore, the development of transistors using oxide semiconductor layers for channels for pixel circuits is underway, and the oxide semiconductor can obtain the characteristics of fully driving the pixel circuit even if the transistor size is small. Summary of the invention

[0004] Technical problem to be solved by the invention

[0005] As the pixel size of display devices decreases, pixel electrodes are easily affected by capacitive coupling of signal lines. If the reduced pixel size is driven at high speed, the influence of crosstalk caused by the change in the potential of the pixel electrode due to the potential of the signal line may become significant.

[0006] One of the purposes of one embodiment of the present invention is to reduce crosstalk in miniaturized pixels in a display device.

[0007] Solutions for solving technical problems

[0008] A display device according to one embodiment of the present invention includes: a first transistor having an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first transparent conductive layer, arranged on at least one first insulating layer on the first transistor, including an area overlapping with the gate wiring, and contacting the oxide semiconductor layer at a first contact area outside the gate wiring; a second transparent conductive layer, arranged on at least one second insulating layer on the first transparent conductive layer, and contacting the first transparent conductive layer at a second contact area overlapping with the gate wiring; a third transparent conductive layer, arranged between the second transparent conductive layer and at least one second insulating layer; a fourth transparent conductive layer, arranged on the second transparent conductive layer; a third insulating layer between the second transparent conductive layer and the third transparent conductive layer; and a fourth insulating layer between the second transparent conductive layer and the fourth transparent conductive layer, the third insulating layer including an opening pattern overlapping with the second contact area.

[0009] A display device according to one embodiment of the present invention includes: a first transistor having an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first transparent conductive layer, arranged on the first insulating layer on the first transistor, and in contact with the oxide semiconductor layer in a first contact region; a second transparent conductive layer, arranged on the second insulating layer on the first transparent conductive layer, and electrically connected to the first transparent conductive layer in a second contact region overlapping with the gate wiring; and an island electrode, in contact with the first transparent conductive layer in the second contact region, and in contact with the second transparent conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0011] Figure 2 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0012] Figure 3 yes Figure 2 A cross-sectional view of the display device shown is taken along line A1 - A2 .

[0013] Figure 4 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0014] Figure 5 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0015] Figure 6 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0016] Figure 7 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0017] Figure 8 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0018] Fig. 9 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0019] Fig.10 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0020] Fig.11 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0021] Fig.12 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0022] Fig.13 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0023] Fig.14 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0024] Fig.15 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0025] Fig.16 It is a plan view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0026] Fig.17 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0027] Fig.18 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0028] Fig.19 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0029] Fig. 20 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0030] Fig.21 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0031] Fig. 22 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0032] Fig.23 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0033] Fig.24 This is a plan view schematically showing a display device according to an embodiment of the present invention.

[0034] Fig.25 This is a block diagram showing a circuit configuration of a display device according to one embodiment of the present invention.

[0035] Fig.26 : is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0036] Below, various embodiments of the present invention are described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by maintaining the gist of the invention and appropriately changing the configuration of the embodiment is of course also included in the scope of the present invention. In order to make the description clearer, the drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual way. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same configuration as the above-mentioned configuration related to the already appeared figure is added with letters after the same symbol, and the detailed description is sometimes appropriately omitted.

[0037] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. On the contrary, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for the sake of convenience, the terms such as up or below are used for description, but for example, the up-down relationship between the substrate and the oxide semiconductor layer may be configured in a different direction than that shown in the figure. In the following description, for example, the representation of the oxide semiconductor layer on the substrate only illustrates the up-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Up or down refers to the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode vertically above a transistor, it refers to a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0038] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as a polarization component, a backlight source, a touch panel, etc.) are installed relative to a display unit. In the "electro-optical layer", as long as there is no technical contradiction, a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer may be included. Therefore, with respect to the embodiments described below, a liquid crystal display device including a liquid crystal layer is described as an example of a display device, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0039] In this specification, expressions such as “α includes A, B or C”, “α includes any one of A, B and C”, and “α includes one selected from the group consisting of A, B and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. In addition, these expressions do not exclude the case where α includes other elements.

[0040] In addition, the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0041] [1. First embodiment]

[0042] [1-1. Configuration of Display Device 10]

[0043] use Figures 1 to 16 , a configuration of a display device 10 according to an embodiment of the present invention is described. Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0044] like Figure 1 As shown, the display device 10 includes a substrate SUB. In addition, the display device 10 has above the substrate SUB: a transistor Tr1, a transistor Tr2, a wiring W, a connecting electrode ZTCO, a pixel electrode PTCO, a common electrode CTCO1, a common auxiliary electrode CMTL and a common electrode CTCO2. In addition, TCO is an abbreviation of Transparent Conductive Oxide. Transistor Tr1 is a transistor included in the pixel circuit of the display device 10. Transistor Tr2 is a transistor included in the peripheral circuit. In addition, the details will be described later, and the peripheral circuit is a circuit that drives the pixel circuit. In addition, Figure 1 The cross-sectional view is a diagram for explaining the layer structure of the display device 10, and shows the peripheral circuit and the pixel circuit adjacent to each other, but it can be considered that the pixel circuit is actually arranged in the display area, and the peripheral circuit is arranged in the frame area outside the display area, and these circuits are arranged separately from each other. In addition, especially in Figure 1In the pixel circuit in FIG. 1 , the pixel area is shown with the contact hole periphery in the pixel area as the center, and only a part of the transmissive area (opening area) that contributes to the display is shown. Figure 3 The transmissive region is shown.

[0045] [1-2. Configuration of transistor Tr1]

[0046] The transistor Tr1 includes an oxide semiconductor layer OS, a gate insulating layer GI1, and a gate electrode GL1. The gate electrode GL1 is opposite to the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided on the side closer to the substrate SUB than the gate electrode GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is opposite may also be used.

[0047] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is a region overlapping with the gate electrode GL1 in a plan view. The oxide semiconductor layer OS1 functions as a semiconductor layer, and switches between a conductive state and a non-conductive state according to a voltage supplied to the gate electrode GL1. That is, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are formed of the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is a region whose resistance is reduced by doping a layer having the same physical properties as the oxide semiconductor layer OS1 with impurities.

[0048] An insulating layer IL2 is provided on the gate electrode GL1. A wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. The area where the wiring W1 contacts the oxide semiconductor layer OS2 is called the third contact area CON3. The third contact area CON3 is provided in the opening WCON. The wiring W1 contacts the oxide semiconductor layer OS2 in the third contact area CON3 that does not overlap with the gate electrode GL1 in a plan view. A data signal related to the grayscale of the pixel is transmitted to the wiring W1. An insulating layer IL3 is provided on the insulating layer IL2 and the wiring W1. A connecting electrode ZTCO (also referred to as a first transparent conductive layer) is provided on the insulating layer IL3. The connecting electrode ZTCO is connected to the oxide semiconductor layer OS2 via an opening ZCON provided in the insulating layers IL3, IL2 and the gate insulating layer GI1. The connecting electrode ZTCO contacts the oxide semiconductor layer OS2 in the bottom of the opening ZCON. The connecting electrode ZTCO is a transparent conductive layer.

[0049] The area where the connection electrode ZTCO contacts the oxide semiconductor layer OS2 is called the first contact area CON1. ​​The first contact area CON1 is provided in the opening ZCON. The details will be described later. The connection electrode ZTCO contacts the oxide semiconductor layer OS2 in the first contact area CON1 that does not overlap with the gate electrode GL1 and the wiring W1 in a plan view. In addition, the first contact area CON1 is included in the display area of ​​the pixel in a plan view. In addition, the connection electrode ZTCO does not overlap with the third contact area CON3.

[0050] For example, if a transparent conductive layer such as an ITO layer is formed to contact a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by the process gas and oxygen ions during the ITO film formation. Since the oxide layer formed on the surface of the semiconductor layer is high-resistance, the contact resistance between the semiconductor layer and the transparent conductive layer becomes high. As a result, the electrical contact between the semiconductor layer and the transparent conductive layer is poor. On the other hand, even if the above-mentioned transparent conductive layer is formed to contact the oxide semiconductor layer, the above-mentioned high-resistance oxide layer will not be formed on the surface of the oxide semiconductor layer. Therefore, the electrical contact between the oxide semiconductor layer and the transparent conductive layer will not be poor.

[0051] An insulating layer IL4 is provided on the connection electrode ZTCO. The insulating layer IL4 mitigates the height difference formed by the structure provided at a lower layer than the insulating layer IL4. The insulating layer IL4 is sometimes referred to as a planarization film. A common electrode CTCO1 (also referred to as a third transparent conductive layer) is provided on the insulating layer IL4. Figure 1 In the figure, a common electrode CTCO1 is provided in the driving circuit, but the common electrode CTCO1 is also provided in the pixel. The common electrode CTCO1 provided in the pixel will be described in detail later. An insulating layer IL5 (also referred to as a first insulating layer) is provided on the common electrode CTCO1. A pixel electrode PTCO (also referred to as a second transparent conductive layer) is provided on the insulating layer IL5. The common electrode CTCO1 and the pixel electrode PTCO are opposite to each other through the insulating layer IL5, thereby forming a holding capacitor (refer to Figure 3 ). The pixel electrode PTCO is connected to the connecting electrode ZTCO via the opening ACON provided in the insulating layer IL5 and the PCON provided in the insulating layer IL4. The area where the connecting electrode ZTCO contacts the pixel electrode PTCO is called the second contact area CON2. The second contact area CON2 is provided in the area where the opening PCON overlaps with the opening ACON. The second contact area CON2 overlaps with the gate electrode GL1 in a plan view. The pixel electrode PTCO is a transparent conductive layer. An insulating layer IL6 is provided on the pixel electrode PTCO. Here, the film thickness of the insulating layer IL6 is smaller than the film thickness of the insulating layer IL5. In addition, the film thickness of the insulating layer IL6 may also be substantially the same as the film thickness of the insulating layer IL5.

[0052] A common auxiliary electrode CMTL and a common electrode CTCO2 (also referred to as a fourth transparent conductive layer) are provided on the insulating layer IL6. The details will be described later. The common auxiliary electrode CMTL and the common electrode CTCO2 have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO2 is a transparent conductive layer. The common electrode CTCO2 and the pixel electrode PTCO are opposite to each other through the insulating layer IL6, thereby forming a holding capacitor (refer to Figure 3 ). The resistance of the common auxiliary electrode CMTL is lower than the resistance of the common electrode CTCO2. In addition, the common auxiliary electrode CMTL also functions as a light shielding layer. For example, the light from adjacent pixels is shielded by the common auxiliary electrode CMTL to suppress color mixing between adjacent pixels. In addition, the common electrode CTCO2 is electrically connected to the common electrode CTCO1 in the peripheral area. A spacer SP is provided on the common electrode CTCO2. The spacer SP overlaps with at least the second contact area CON2 and fills the second contact area CON2. The spacer SP may also overlap with the gate electrode GL1 and the pixel electrode PTCO.

[0053] In addition, the same potential is supplied to the common electrode CTCO1, the common auxiliary electrode CMTL, and the common electrode CTCO2. This potential is preferably a reference potential relative to the pixel potential supplied to the pixel electrode PTCO. Fig.16 ), an electric field is formed between the pixel electrode PTCO and the common electrode CTCO2, and as described above, a holding capacitance based on the pixel potential is formed between the pixel electrode PTCO and the common electrodes CTCO1 and CTCO2 that are opposite to each other.

[0054] The spacer SP is provided in a part of the pixels. For example, the spacer SP can be provided in any one of the blue pixel, the red pixel, and the green pixel. However, the spacer SP can also be provided in all pixels. The height of the spacer SP is half the height of the cell gap. The spacer is also provided on the opposing substrate, and the spacer of the opposing substrate overlaps with the above-mentioned spacer SP in a plan view.

[0055] In addition, the spacer SP may have not only the above-described structure but also a structure having a height corresponding to the cell gap or a structure simply filling the second contact region CON2 .

[0056] A light shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In the present embodiment, light shielding layers LS1 and LS2 are provided as the light shielding layer LS. However, the light shielding layer LS may be formed only by the light shielding layer LS1 or only by the light shielding layer LS2. In a plan view, the light shielding layer LS is provided in a region where the gate electrode GL1 overlaps with the oxide semiconductor layer OS. That is, in a plan view, the light shielding layer LS is provided in a region overlapping with the oxide semiconductor layer OS1. The light shielding layer LS inhibits light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light shielding layer LS, a voltage may be applied to the light shielding layer LS to control the oxide semiconductor layer OS1. When a voltage is applied to the light shielding layer LS, the light shielding layer LS and the gate electrode GL1 may be connected in a peripheral region of the pixel circuit. In a plan view, the third contact region CON3 and the first contact region CON1 are provided in a region that does not overlap with the light shielding layer LS and the gate electrode GL1.

[0057] [1-3. Configuration of transistor Tr2]

[0058] The transistor Tr2 includes a p-type transistor Tr2 - 1 and an n-type transistor Tr2 - 2 .

[0059] The p-type transistor Tr2-1 and the n-type transistor Tr2-2 each have a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 is opposite to the semiconductor layer S. The gate insulating layer GI2 is disposed between the semiconductor layer S and the gate electrode GL2. In the present embodiment, a bottom-gate transistor having a gate electrode GL2 disposed on the side closer to the substrate SUB than the semiconductor layer S is exemplified, but a top-gate transistor having a reverse positional relationship between the semiconductor layer S and the gate electrode GL2 may also be used.

[0060] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor layer in a region overlapping with the gate electrode GL2 in a plan view. The semiconductor layer S1 functions as a channel of the transistor Tr2-1. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer having a higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers invading the semiconductor layer S1.

[0061] An insulating layer IL1 and a gate insulating layer GI1 are provided on the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 functions only as an interlayer film. A wiring W2 is provided on these insulating layers. The wiring W2 is connected to the semiconductor layer S via openings provided in the insulating layer IL1 and the gate insulating layer GI1. An insulating layer IL2 is provided on the wiring W2. A wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the wiring W2 via an opening provided in the insulating layer IL2.

[0062] The gate electrode GL2 and the light shielding layer LS2 are in the same layer. The wiring W2 and the gate electrode GL1 are in the same layer. The same layer means that a plurality of components are formed by patterning one layer.

[0063] [1-4. Planar Layout of Display Device 10]

[0064] use Figure 2 , Figures 4 to 16 , illustrating the planar layout of pixels of the display device 10. Figure 3 Cut off the A1-A2 line Figure 2 A cross-sectional view of the display device 10 is shown. Figure 2 In the figure, the common auxiliary electrode CMTL, the common electrode CTCO2 and the spacer SP are omitted. Figure 14 to Figure 16 The planar layouts of the pixel electrode PTCO, the common auxiliary electrode CMTL and the common electrode CTCO2 are shown respectively. Figure 2 to Figure 16 , positions where openings are provided in the insulating layers IL1 to IL6 are shown.

[0065] like Figure 2 and Figure 4 As shown, the light shielding layer LS extends in the D1 direction. The light shielding layer LS may have a different shape depending on the pixel. In the present embodiment, a protrusion PJT is provided which protrudes from a part of the light shielding layer LS extending in the D1 direction toward the D2 direction.

[0066] like Figure 2 and Figure 5 As shown, the oxide semiconductor layer OS extends in the direction D2. The gate electrode GL1 extends in the direction D1 so as to intersect the oxide semiconductor layer OS.

[0067] like Figure 2 and Figure 6 As shown in FIG. 1 , the pattern of the gate electrode GL1 is disposed inside the pattern of the light shielding layer LS. In other words, the oxide semiconductor layer OS is formed in a strip shape intersecting the gate electrode GL1. Figure 6 As shown, the light shielding layer LS is provided in a region including a region where the gate electrode GL1 overlaps with the oxide semiconductor layer OS in a plan view. In addition, the gate electrode GL1 may also be referred to as a "gate line".

[0068] like Figure 2 and Figure 7 As shown, the opening WCON is provided near the upper end of the pattern of the oxide semiconductor layer OS. The opening WCON is provided in the gate insulating layer GI1 and the insulating layer IL2. The opening WCON is provided in a region overlapping with the pattern of the oxide semiconductor layer OS and not overlapping with the gate electrode GL1.

[0069] like Figure 2 and Figure 8 As shown, a plurality of wirings W1 extend in the D2 direction. The wiring W1 is provided in an area (third contact area CON3) overlapping with the oxide semiconductor layer OS in the opening WCON. When it is necessary to distinguish and describe adjacent wirings separately, the adjacent wirings W1 are referred to as wirings W1-1 (first wiring) and wirings W1-2 (second wiring). In this case, a main portion of the oxide semiconductor layer OS extends in the D2 direction between the first wiring W1-1 and the second wiring W1-2 and intersects with the gate electrode GL1. A main portion of the pattern of the oxide semiconductor layer OS extends in the D2 direction between adjacent wirings W1. In addition, the remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion to the area of ​​the opening WCON in a direction inclined relative to the D1 direction and the D2 direction.

[0070] like Figure 2 and Fig. 9 As shown, the opening ZCON is provided near the lower end of the pattern of the oxide semiconductor layer OS. The opening ZCON is provided in the gate insulating layer GI1, the insulating layer IL2, and the insulating layer IL3. The opening ZCON is provided in a region overlapping with the pattern of the oxide semiconductor layer OS and not overlapping with the gate electrode GL1. The oxide semiconductor layer OS contacts the wiring W1 on the side opposite to the opening ZCON (first contact region CON1) with respect to the gate electrode GL1. In addition, the opening ZCON (first contact region CON1) does not overlap with the light shielding layer LS.

[0071] Regarding the above configuration, in other words, the oxide semiconductor layer OS is connected to the connection electrode ZTCO at the other end of the long side direction of the oxide semiconductor layer OS. The connection electrode ZTCO is formed into a strip extending in the D2 direction similarly to the oxide semiconductor layer OS. In the D1 direction, the width of the connection electrode ZTCO is smaller than the width of the oxide semiconductor layer OS.

[0072] like Figure 2 and Fig.10As shown, the connection electrode ZTCO is provided in a region overlapping with the opening ZCON. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between the wiring W1-1 and the wiring W1-2. Thus, the connection electrode ZTCO contacts the oxide semiconductor layer OS in the opening ZCON (first contact region CON1) that does not overlap with the gate electrode GL1.

[0073] like Figure 2 and Fig.11 As shown, the opening PCON is provided near the upper end of the pattern of the connection electrode ZTCO. The opening PCON is provided in the insulating layer IL4. The opening PCON is provided in a region overlapping with the pattern of the gate electrode GL1 and the pattern of the connection electrode ZTCO.

[0074] like Figure 2 and Fig.12 As shown, the common electrode CTCO1 has a plurality of stripe-shaped patterns in the display area. The common electrode CTCO1 is arranged to overlap with the wiring W1-1 and the wiring W1-2 along the D1 direction. The common electrode CTCO1 overlaps with the opening WCON (third contact area CON3). The plurality of stripe-shaped common electrodes CTCO1 are electrically connected to the peripheral area where the driving circuit is arranged in the display device 10.

[0075] like Figure 2 and Fig.13 As shown, the opening ACON is provided to overlap with the opening PCON. The opening ACON is provided in the insulating layer IL5. The opening ACON is provided to overlap with the gate electrode GL1 in at least a portion.

[0076] like Figure 2 and Fig.14 As shown, the pixel electrode PTCO overlaps the gate electrode GL1, the oxide semiconductor layer OS and the connection electrode ZTCO between the wiring W1-1 and the wiring W1-2. The pixel electrode PTCO contacts the connection electrode ZTCO in the opening PCON (second contact area CON2) overlapping the gate electrode GL1. In addition, the pixel electrode PTCO overlaps the common electrode CTCO1 via the insulating layer IL5. The pixel electrode PTCO, the insulating layer IL5 and the connection electrode ZTCO form a holding capacitor.

[0077] like Figure 2 and Fig.15As shown, the common auxiliary electrode CMTL is arranged in a grid shape in a manner surrounding the periphery of the pixel area. That is, the common auxiliary electrode CMTL is arranged in common with respect to a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is arranged to expose the pixel electrode PTCO. The pattern of the opening OP is arranged on the inner side of the pattern of the pixel electrode PTCO. In addition, the area where the opening OP is provided corresponds to the display area of ​​each pixel. That is, the opening ZCON (first contact area CON1) is included in the display area. In addition, the display area of ​​each pixel refers to an area where the user can visually confirm the light from the pixel. For example, an area that is shielded by a metal layer and the user cannot visually confirm the light is not included in the display area. That is, the display area of ​​each pixel mentioned above is sometimes referred to as a "light-transmitting area". In addition, the area of ​​the common auxiliary electrode CMTL extending along the D1 direction overlaps with the opening PCON. Here, as shown in Figure 3 As shown, the pixel electrode PTCO overlaps with the common electrode CTCO1 via the insulating layer IL5. The region where the pixel electrode PTCO overlaps with the common electrode CTCO1 via the insulating layer IL5 functions as a storage capacitor.

[0078] like Figure 2 and Fig.16 As shown, the common electrode CTCO2 is provided in common with respect to a plurality of pixels. A slit SL is provided in a region corresponding to the opening OP. The slit SL has a curved shape (a longitudinally long S-shape). The front end of the slit SL has a shape in which the width is reduced orthogonal to the extension direction of the front end. Figure 2 and Fig.16 The common electrode CTCO2 has a slit SL at a position opposite to the pixel electrode PTCO (second transparent conductive layer). The common electrode CTCO2 overlaps with the pixel electrode PTCO via the insulating layer IL6. The area where the common electrode CTCO2 overlaps with the pixel electrode via the insulating layer IL6 functions as a holding capacitor (refer to Figure 3 ).

[0079] [1-5. Materials of Components of Display Device 10]

[0080] As the substrate SUB, a glass substrate, a quartz substrate, a sapphire substrate, or other rigid substrate having light transmittance and no flexibility can be used. On the other hand, when the substrate SUB needs to be flexible, a flexible substrate containing resin and having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane-based substrate, or a fluororesin substrate can be used as the substrate SUB. In order to improve the heat resistance of the substrate SUB, impurities may be introduced into the above-mentioned resin.

[0081] As the gate electrodes GL1, GL2, the wirings W1, W2, the light shielding layer LS and the common auxiliary electrode CMTL, general metal materials can be used. For example, as these electrodes and other components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi) and silver (Ag), or their alloys or compounds are used. As the above-mentioned electrodes and other components, the above-mentioned materials can be used in a single layer or in a stacked manner.

[0082] For example, a stacked structure of Ti / Al / Ti is used as the gate electrode GL1. In the present embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the stacked structure is a forward tapered shape.

[0083] The gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL5 can be made of a general insulating layer material. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), Silicon Nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum oxynitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers. As these insulating layers, insulating layers with few defects can be used. As the insulating layer IL4, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin or siloxane resin can be used. The above-mentioned organic insulating materials can also be used as gate insulating layers GI1, GI2 and insulating layers IL1~IL3, IL5, IL6. As the above-mentioned insulating layers and other components, the above-mentioned insulating materials can be used as a single layer or in a stacked manner.

[0084] As an example of the insulating layer, SiO2 having a thickness of 100 nm is used as the gate insulating layer GI1. x As the insulating layer IL1, SiO with a total thickness of 600nm to 700nm is used. x / SiN x / SiO x As the gate insulating layer GI2, SiO2 with a total thickness of 60 to 100 nm is used. x / SiN x As the insulating layer IL2, SiO2 with a total thickness of 300 nm to 500 nm is used. x / SiN x / SiO x As the insulating layer IL3, SiO with a total thickness of 200nm to 500nm is used. x (Single layer), SiN x (single layer) or a stack of these. An organic layer with a thickness of 2 μm to 4 μm is used as the insulating layer IL4. SiN with a thickness of 50 nm to 150 nm is used as the insulating layer IL5. x (Single layer).

[0085] The above SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio smaller than that of nitrogen (x>y).

[0086] As the oxide semiconductor layer OS, an oxide metal having semiconductor properties can be used. The oxide semiconductor layer OS is light-transmitting. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a composition different from the above can be used. For example, in order to improve the mobility, the ratio of In can also be made larger than the above. In addition, in order to increase the band gap and reduce the influence caused by light irradiation, the ratio of Ga can also be made larger than the above.

[0087] Other elements may be added to the oxide semiconductor containing In, Ga, Zn and O. For example, metal elements such as Al and Sn may also be added to the oxide semiconductor. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn and Zn (ITZO), and an oxide semiconductor containing In and W may also be used as the oxide semiconductor layer OS. The oxide semiconductor layer OS may be amorphous or crystalline. The oxide semiconductor layer OS may also be a mixed phase of amorphous and crystalline.

[0088] A transparent conductive layer is used as the connection electrode ZTCO, the common electrode CTCO1, the pixel electrode PTCO, and the common electrode CTCO2. A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer. Materials other than the above can also be used as the transparent conductive layer.

[0089] As described above, according to the display device 10 of this embodiment, by making the oxide semiconductor layer OS of the transistor Tr1 directly contact the connection electrode ZTCO, the conduction between the two can be ensured. Therefore, there is no need to set a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO. According to this configuration, since light is not blocked in the opening ZCON (first contact area CON1), the reduction in the aperture ratio can be suppressed. In addition, the layer exposed in the display area is an oxide semiconductor layer OS that is light-transmissive and is not prone to uneven transmission of light like a silicon layer, so the generation of display unevenness can be suppressed.

[0090] Furthermore, as the pixel size of display devices decreases, pixel electrodes are easily affected by capacitive coupling of signal lines. If the reduced pixel size is driven at high speed, the influence of crosstalk caused by the change in the potential of the pixel electrode due to the potential of the signal line may become significant.

[0091] In a display device 10 of an embodiment of the present invention, a common electrode CTCO1 is provided in a manner intersecting with the wiring W1-1 and the wiring W1-2 extending in the D2 direction. The common electrode CTCO1 is provided along the D1 direction in a manner crossing a plurality of pixels. Thus, the wirings W1-1 and 1-2 and the pixel electrode PTCO can be shielded by the common electrode CTCO1. Thus, the capacitive coupling between the wirings W1-1 and 1-2 and the pixel electrode can be reduced. In addition, in the display area of ​​the pixel, the holding capacitance formed by the pixel electrode PTCO, the insulating layer IL6 and the common electrode CTCO2 can be added to the holding capacitance formed by the pixel electrode PTCO, the insulating layer IL5 and the common electrode CTCO1. Thus, the holding capacitance can be increased, and thus the influence of the capacitive coupling on the potential can be reduced. Thus, in the display device 10, in the reduced pixel, the influence of the capacitive coupling on the potential can be reduced, and thus the crosstalk can be reduced.

[0092] [2. Second Embodiment]

[0093] use Figure 17 to Figure 19 , a configuration of a display device 10A according to an embodiment of the present invention is described. Fig.17 It is a cross-sectional view showing a display device 10A according to one embodiment of the present invention. Fig.18 is a planar layout of pixels of the display device 10A. Fig.18In the figure, the common auxiliary electrode CMTL, the common electrode CTCO2 and the spacer SP are omitted. Fig.19 This is the planar layout of the common electrodes CTCO1 - 1 to CTCO1 - 4 . Figure 17 to Figure 19 The display device 10A shown in FIG. Figure 1 The display device 10 shown is similar, but the configuration of the electrodes in the opening PCON is different. In addition, the same reference numerals are given to the same components as those of the display device 10, and the description thereof is omitted.

[0094] like Fig.17 As shown, an island-shaped common electrode CTCO1-2 (also called a fifth transparent conductive layer) can be provided inside the opening PCON. The common electrode CTCO1-2 is provided between the connecting electrode ZTCO and the pixel electrode PTCO. The common electrode CTCO1-2 is formed of the same transparent conductive film as the common electrode CTCO1-1. The common electrode CTCO1-2 is provided in contact with the insulating layer IL4 in the opening PCON. The common electrode CTCO1-2 is connected to the connecting electrode ZTCO via the opening PCON. The area where the common electrode CTCO1-2 contacts the connecting electrode ZTCO is called the fourth contact area CON4. The fourth contact area CON4 is provided in the opening PCON. The fourth contact area CON4 is provided in the area overlapping with the gate electrode GL1. As shown in FIG. Fig.18 and Fig.19 As shown, the common electrodes CTCO1-1, CTCO1-3, and CTCO1-4 are arranged along the D1 direction to overlap with the wiring W1-1 and the wiring W1-2. The common electrode CTCO1-2 is arranged separately from the common electrode CTCO1-1. In addition, the common electrodes CTCO1-1, CTCO1-3, and CTCO1-4 are supplied with a prescribed reference potential together with the common electrode CTCO2. On the other hand, the common electrode CTCO1-2 is arranged separately from the other common electrodes and does not serve as a reference potential. In view of this aspect, the common electrode CTCO1-2 can also be called an island electrode. In addition, the common electrode CTCO1-2 is connected to the connecting electrode ZTCO and the pixel electrode PTCO as described above, and therefore has a prescribed pixel potential.

[0095] An insulating layer IL5 is provided on the common electrodes CTCO1-1 and CTCO1-2. In addition, a pixel electrode PTCO is provided on the insulating layer IL5. The pixel electrode PTCO is connected to the common electrode CTCO1-2 via an opening ACON provided in the insulating layer IL5. In addition, the pixel electrode PTCO is opposite to the common electrode CTCO1-1 with the insulating layer IL4 sandwiched in the middle. That is, in the opening ACON, the area where the pixel electrode PTCO contacts the common electrode CTCO1-2 is called the fifth contact area CON5. The fifth contact area CON5 is provided in the opening ACON. As described above, the pixel electrode PTCO may also be provided above the common electrode CTCO2. A portion of the opening ACON is provided to overlap with the opening PCON. That is, the fifth contact area CON5 overlaps at least a portion of the fourth contact area CON4. In addition, the fifth contact area CON5 is provided on the gate electrode GL1. The common electrode CTCO1-2 overlaps with the gate electrode GL1. By providing the fifth contact region CON5 and the common electrode CTCO1 - 2 on the gate electrode GL1 , light is not blocked in the opening ACON, and thus a decrease in the aperture ratio can be suppressed.

[0096] An insulating layer IL6 is provided on the pixel electrode PTCO. In addition, the common electrode CTCO1-1 faces the common electrode CTCO2 via the insulating layer IL6. The opening OP of the common electrode CTCO2 overlaps with the opening ACON and the opening PCON.

[0097] According to the display device 10A of this embodiment, the same effect as the display device 10 of the first embodiment can be obtained. In addition, in the display device 10A, the common electrode CTCO1-2 is provided inside the opening PCON provided in the insulating layer IL4. The common electrode CTCO1-2 provided inside the opening PCON plays a role in blocking hydrogen intruding from the outside. Thus, it is possible to suppress hydrogen from intruding into the oxide semiconductor layer OS. Therefore, it is possible to suppress the characteristics of the transistor Tr1 from changing due to hydrogen intruding into the oxide semiconductor layer OS.

[0098] [3. Third embodiment]

[0099] use Figure 20-21 , a configuration of a display device 10B according to an embodiment of the present invention is described. Fig. 20 This is a cross-sectional view showing a display device according to an embodiment of the present invention. Fig.21 is the planar layout of the pixels of the display device 10B. Fig.21 The common auxiliary electrode CMTL, the common electrode CTCO2 and the spacer SP are omitted. Figure 20-21 The display device 10B shown is Fig.17The display device 10 shown is similar, but the configuration of the electrodes in the opening PCON is different. In addition, the same reference numerals are given to the same components as those of the display device 10, and the description thereof is omitted.

[0100] Figure 20-21 As shown, a common electrode CTCO1-2 is provided inside the opening PCON. An insulating layer IL5 is provided on the common electrodes CTCO1-1 and CTCO1-2. The insulating layer IL5 has an opening ACON. The pixel electrode PTCO is connected to the common electrode CTCO1-2 via the opening ACON. The opening ACON is provided in an overlapping manner inside the opening PCON. Therefore, the fourth contact area CON4 where the connecting electrode ZTCO overlaps with the common electrode CTCO1-2 overlaps with the fifth contact area CON5 where the common electrode CTCO1-2 overlaps with the pixel electrode PTCO. Compared with the display device 10, the fourth contact area CON4 and the fifth contact area CON5 in the display area can be further separated from the common electrode CTCO1-1. As a result, the area of ​​the common electrodes CTCO1-1, CTCO1-3, and CTCO1-4 extending in the D1 direction can be further increased. By increasing the area of ​​the common electrodes CTCO1-1, CTCO1-3, and CTCO1-4, the shielding properties of the common electrodes CTCO1-1, CTCO1-3, and CTCO1-4 can be further improved.

[0101] According to the display device 10B of the present embodiment, it is possible to obtain the same effects as those of the display device 10 of the first embodiment.

[0102] [4. Fourth embodiment]

[0103] use Fig. 22 , a configuration of a display device 10C according to an embodiment of the present invention is described. Fig. 22 is the planar layout of the pixels of the display device 10C. Fig. 22 The common auxiliary electrode CMTL, the common electrode CTCO2 and the spacer SP are omitted. Fig. 22 The display device 10C shown is Fig.17 The display device 10B shown is similar, but the shape of the common electrode CTCO1 - 1 is different. In addition, the same reference numerals are attached to the same components as those of the display device 10 , and the description thereof is omitted.

[0104] like Fig. 22As shown, the common electrode CTCO1 has a first region extending in the D1 direction and a second region extending in the D2 direction. The first region is a region extending in the D1 direction overlapping with the wiring W1 and the wiring W2. In addition, the second region is a region extending along the wiring W1 and the wiring W2. The second region is arranged to overlap with the wiring W1. In addition, the width in the D1 direction in the second region is arranged to be smaller than the width of the wiring W1, but may also be arranged to be larger than the width of the wiring W1.

[0105] According to the display device 10C of this embodiment, the same effect as that of the display device 10 of the first embodiment can be obtained. In addition, by providing the second region on the common electrode CTCO1, the overall resistance of the common electrode CTCO1 can be reduced. In addition, by providing the second region on the common electrode CTCO1, the influence of the potential on the pixel electrode PTCO from the wiring W1 and the wiring W2 can be reduced.

[0106] [5. Fifth embodiment]

[0107] use Fig.23 , a configuration of a display device 10D according to an embodiment of the present invention is described. Fig.23 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention. Fig.23 The display device 10D shown is Figure 1 The display device 10 shown is similar, but the positional relationship between the pixel electrode PTCO and the common electrode CTCO2 is different.

[0108] like Fig.23 As shown, an insulating layer IL6 is provided on the common auxiliary electrode CMTL and the common electrode CTCO2. A pixel electrode PTCO is provided on the insulating layer IL6. The pixel electrode PTCO is connected to the connection electrode ZTCO via an opening PCON provided in the insulating layers IL4 and IL6. As described above, the pixel electrode PTCO may also be provided above the common electrode CTCO2.

[0109] According to the display device 10D of the present embodiment, it is possible to obtain the same effects as those of the display device 10 of the first embodiment.

[0110] [6. Sixth embodiment]

[0111] use Figure 24 to Figure 26 , describing the overall structure of the display device described in the above-mentioned first embodiment and second embodiment.

[0112] [6-1. Overview of Display Device 20B]

[0113] Fig.24 1 is a top view showing an overview of a display device according to an embodiment of the present invention. Fig.24 As shown, the display device 20B has an array substrate 300B, a sealing portion 400B, an opposing substrate 500B, a flexible printed circuit substrate 600B (FPC600B) and an IC chip 700B. The array substrate 300B and the opposing substrate 500B are bonded by the sealing portion 400B. In the liquid crystal region 22B surrounded by the sealing portion 400B, a plurality of pixel circuits 310B are arranged in a matrix. The liquid crystal region 22B is an area that overlaps with the liquid crystal element 410B described later when viewed from above. The liquid crystal region 22B is an area that contributes to display. The liquid crystal region 22B is sometimes referred to as a "display region". The above-mentioned transistor Tr1 is arranged in the liquid crystal region 22B (display region).

[0114] The sealing area 24B provided with the sealing portion 400B is the area around the liquid crystal area 22B. The FPC 600B is provided in the terminal area 26B. The terminal area 26B is the area where the array substrate 300B is exposed from the opposing substrate 500B, and is provided outside the sealing area 24B. In addition, the outside of the sealing area 24B refers to the area provided with the sealing portion 400B and the outside of the area surrounded by the sealing portion 400B. The IC chip 700B is provided on the FPC 600B. The IC chip 700B supplies a signal for driving each pixel circuit 310B. The sealing area 24B or the area combining the sealing area 24B and the terminal area 26B is the area surrounding the liquid crystal area 22B (display area). These areas are sometimes referred to as "frame areas". The above-mentioned transistor Tr2 is provided in the frame area.

[0115] [6-2. Circuit Configuration of Display Device 20B]

[0116] Fig.25 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. Fig.25 As shown, a source driving circuit 320B is provided at a position adjacent to the liquid crystal region 22B in the D1 direction (column direction) with respect to the pixel circuit 310B, and a gate driving circuit 330B is provided at a position adjacent to the liquid crystal region 22B in the D2 direction (row direction). The source driving circuit 320B and the gate driving circuit 330B are provided in the above-mentioned sealing region 24B. However, the region where the source driving circuit 320B and the gate driving circuit 330B are provided is not limited to the sealing region 24B, and may be any region as long as it is outside the region where the pixel circuit 310B is provided.

[0117] The source wiring 321B extends from the source driver circuit 320B in the direction D1 and is connected to a plurality of pixel circuits 310B arranged in the direction D1. The gate wiring 331B extends from the gate driver circuit 330B in the direction D2 and is connected to a plurality of pixel circuits 310B arranged in the direction D2.

[0118] The terminal region 26B is provided with a terminal portion 333B. The terminal portion 333B is connected to the source driver circuit 320B via a connection wiring 341B. Similarly, the terminal portion 333B is connected to the gate driver circuit 330B via a connection wiring 341B. The external device connected to the FPC 600B is connected to the display device 20B through the FPC 600B connected to the terminal portion 333B, and each pixel circuit 310B provided in the display device 20B is driven by a signal from the external device.

[0119] The transistor Tr1 described in the first and second embodiments is used in the pixel circuit 310B. The transistor Tr2 described in the first and second embodiments is applied to transistors included in the source driver circuit 320B and the gate driver circuit 330B.

[0120] [Pixel Circuit 310B of Display Device 20B]

[0121] Fig.26 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Fig.26 As shown, the pixel circuit 310B includes a transistor 800B, a holding capacitor 890B, and a liquid crystal element 410B. The transistor 800B has a first gate electrode 810B, a first source electrode 830B, and a first drain electrode 840B. The first gate electrode 810B is connected to the gate wiring 331B. The first source electrode 830B is connected to the source wiring 321B. The first drain electrode 840B is connected to the holding capacitor 890B and the liquid crystal element 410B. The transistor Tr1 shown in the first embodiment and the second embodiment is applied to Fig.26 The transistor 800B shown in FIG. 8A is shown in FIG. 8B. In addition, the holding capacitor 890B includes a holding capacitor formed by the pixel electrode and the common electrode CTCO1, and a holding capacitor formed by the pixel electrode and the common electrode CTCO2. In addition, in order to form the holding capacitor, the common electrode CTCO1 and the common electrode CTCO2 are supplied with the same reference potential, but the reference potential may be a predetermined fixed potential or a pulse wave (AC rectangular wave) with a certain period.

[0122] In this embodiment, for convenience of explanation, 830B is referred to as a source electrode and 840B is referred to as a drain electrode. However, the functions of the source electrode and the drain electrode may be interchanged between the electrodes.

[0123] As embodiments of the present invention, the above embodiments can be appropriately combined and implemented as long as they are not contradictory. In addition, based on the display device of each embodiment, a device in which a person skilled in the art appropriately adds, deletes or changes the design of components, or adds, omits or changes the conditions of processes is included in the scope of the present invention as long as it has the gist of the present invention.

[0124] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, the effects that are clear from the description of this specification or the effects that can be easily predicted by those skilled in the art are of course understood as the effects brought about by the present invention.

[0125] Explanation of symbols

[0126] 10…display device; 20B…display device; 22B…liquid crystal region; 24B…sealing region; 26B…terminal region; 300B…array substrate; 310B…pixel circuit; 320B…source driver circuit; 321B…source wiring; 330B…gate driver circuit; 331B…gate wiring; 333B…terminal portion; 341B…connection wiring; 400B…sealing portion; 410B…liquid crystal element; 500B…counter substrate; 600B…flexible printed circuit substrate; 700B…chip; 800B…transistor; 810B…first gate electrode; 830B…first source electrode; 840B…first drain electrode; 890B…holding capacitor; CMTL… Common auxiliary electrode; CON1…first contact region; CON2…second contact region; CON3…third contact region; CON4…fourth contact region; CON5…fifth contact region; CTCO1, CTCO2…common electrode; GI1, GI2…gate insulating layer; GL1, GL2…gate electrode; IL1~IL5…insulating layer; LS…light shielding layer; OP…opening; OS…oxide semiconductor layer; PCON, WCON, ZCON…opening; PJT…protrusion; PTCO…pixel electrode; S…semiconductor layer; SL…slit; SP…spacer; SUB…substrate; Tr1, Tr2…transistor; W…wiring; ZTCO…connecting electrode.

Claims

1. A display device, characterized in that: include: A first transistor including an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; A first transparent conductive layer is provided on at least one first insulating layer on the first transistor, includes a region overlapping with the gate wiring, and contacts the oxide semiconductor layer at a first contact region outside the gate wiring; a second transparent conductive layer, disposed on at least one second insulating layer on the first transparent conductive layer, and contacting the first transparent conductive layer at a second contact region overlapping the gate wiring; a third transparent conductive layer, disposed between the second transparent conductive layer and the second insulating layer; a fourth transparent conductive layer, disposed on the second transparent conductive layer; a third insulating layer between the second transparent conductive layer and the third transparent conductive layer; as well as a fourth insulating layer between the second transparent conductive layer and the fourth transparent conductive layer, The third insulating layer includes an opening pattern overlapping the second contact region.

2. The display device according to claim 1, characterized in that The third transparent conductive layer has a striped pattern, The fourth transparent conductive layer includes a slit pattern at least partially overlapping the stripe pattern.

3. The display device according to claim 2, characterized in that: The display device further includes a first wiring connected to the oxide semiconductor layer at a third contact region outside the gate wiring. The stripe pattern of the third transparent conductive layer is arranged along a first direction, The first wiring extends along a second direction intersecting the first direction.

4. The display device according to claim 3, characterized in that: The display device also has a spacer overlapping at least the second contact area.

5. The display device according to claim 4, characterized in that: The first transparent conductive layer does not overlap with the third contact region.

6. The display device according to claim 5, characterized in that: A fifth transparent conductive layer is further provided between the first transparent conductive layer and the second transparent conductive layer. The fifth transparent conductive layer is formed of the same transparent conductive film as the third transparent conductive layer.

7. The display device according to claim 6, characterized in that: The fifth transparent conductive layer is connected to the first transparent conductive layer at a fourth contact region overlapping the gate wiring.

8. The display device according to claim 7, characterized in that: In the opening pattern provided in the third insulating layer, the second transparent conductive layer is connected to the fifth transparent conductive layer in a fifth contact region.

9. The display device according to claim 8, characterized in that: The fifth contact region overlaps a portion of the fourth contact region.

10. The display device according to claim 1, characterized in that The third insulating layer has a thickness greater than that of the fourth insulating layer.

11. The display device according to claim 1, characterized in that: The thickness of the third insulating layer is the same as the thickness of the fourth insulating layer.

12. The display device according to claim 3, characterized in that: The third transparent conductive layer has a first region extending along the first direction and a second region overlapping the first wiring and extending along the second direction.

13. A display device, characterized in that: have: A first transistor including an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first transparent conductive layer, disposed on the first insulating layer on the first transistor and contacting the oxide semiconductor layer in a first contact region; a second transparent conductive layer, disposed on the second insulating layer on the first transparent conductive layer, and electrically connected to the first transparent conductive layer at a second contact region overlapping the gate wiring; as well as an island-shaped electrode, contacting the first transparent conductive layer in the second contact region and contacting the second transparent conductive layer, The second contact region is provided on the gate wiring, and the island-shaped electrode overlaps with the gate wiring.

14. The display device according to claim 13, characterized in that: The display device further includes a third transparent conductive layer, which is disposed below the second insulating layer and faces the second transparent conductive layer via the third insulating layer.

15. The display device according to claim 14, characterized in that: The third transparent conductive layer and the island-shaped electrode are the same layer.

16. The display device according to claim 13, characterized in that: A fourth insulating layer is provided on the second transparent conductive layer, and a fourth transparent conductive layer is further provided which faces the second transparent conductive layer via the fourth insulating layer.

17. The display device according to claim 14, characterized in that: A fourth insulating layer is provided on the second transparent conductive layer, and a fourth transparent conductive layer is further provided which faces the third transparent conductive layer via the fourth insulating layer.

18. The display device according to claim 17, characterized in that: The third transparent conductive layer has a striped pattern, The fourth transparent conductive layer includes a slit pattern at least a portion of which overlaps with the stripe pattern.

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