Power semiconductor device and method of manufacturing the power semiconductor device

Abstract

A power semiconductor device and a method of manufacturing the power semiconductor device are disclosed, wherein the method includes forming a channel separation pattern on a substrate, forming a passivation layer on the substrate and the channel separation pattern, simultaneously forming a gate hole, a source hole, and a drain hole that penetrate the passivation layer, and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern can be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern can have a step difference.

Description

Technical Field

[0001] This disclosure relates to power semiconductor devices and / or methods of manufacturing such power semiconductor devices. Background Technology

[0002] Power semiconductor devices are used for power conversion and / or power control. Power semiconductor devices typically require high withstand voltage, high current, and high-speed switching characteristics. An example of a power semiconductor device is the high electron mobility transistor (HEMT). HEMTs comprise a heterojunction structure in which layers of semiconductor material with different band gaps are formed adjacent to each other. Because the materials with different band gaps form a heterojunction structure, a two-dimensional electron gas (2DEG) layer is induced in the semiconductor material layer with the smaller band gap, thereby increasing the electron mobility. Summary of the Invention

[0003] This disclosure provides a power semiconductor device with improved electrical characteristics.

[0004] This disclosure provides a method for manufacturing a power semiconductor device with improved electrical characteristics.

[0005] This disclosure provides a method for manufacturing power semiconductor devices with improved process efficiency.

[0006] However, this disclosure is not limited thereto.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one embodiment, a method of manufacturing a power semiconductor device may include: forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern that penetrate the passivation layer. The gate electrode pattern may be formed on the channel separation pattern, and the side surface of the gate electrode pattern and the side surface of the channel separation pattern may have a step difference.

[0009] In some embodiments, forming the gate electrode pattern, source electrode pattern, and drain electrode pattern may include: forming a gate hole, source hole, and drain hole that penetrate the passivation layer; filling the gate hole, source hole, and drain hole by depositing a conductive material layer on the passivation layer; and patterning the conductive material layer. The gate electrode pattern, source electrode pattern, and drain electrode pattern may be formed in the gate hole, source hole, and drain hole, respectively.

[0010] In some embodiments, the gate electrode pattern may include an electric field relaxation region extending along the upper surface of the passivation layer toward the drain electrode pattern, and the distance between the electric field relaxation region and the drain electrode pattern may be smaller than the distance between the channel separation pattern and the drain electrode pattern.

[0011] In some embodiments, the method may further include forming a Schottky barrier metal pattern between the channel separation pattern and the gate electrode pattern.

[0012] In some implementations, the Schottky barrier metal pattern can extend between the gate electrode pattern and the passivation layer.

[0013] In some embodiments, the method may further include forming an electric field relaxation pattern between the gate electrode pattern and the drain electrode pattern; the electric field relaxation pattern may be formed simultaneously with the gate electrode pattern, the source electrode pattern, and the drain electrode pattern.

[0014] In some embodiments, simultaneously forming a gate electrode pattern, a source electrode pattern, a drain electrode pattern, and an electric field relaxation pattern may include: forming a gate hole, a source hole, and a drain hole that penetrate the passivation layer; filling the gate hole, source hole, and drain hole by depositing a conductive material layer on the passivation layer; and patterning the conductive material layer.

[0015] In some implementations, the gate electrode pattern, source electrode pattern, and drain electrode pattern may include the same conductive material.

[0016] In some implementations, the channel separation pattern may include p-type gallium nitride (GaN).

[0017] According to one embodiment, a method of manufacturing a power semiconductor device may include: forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate via, a source via, and a drain via penetrating the passivation layer; forming a Schottky barrier metal pattern in the gate via; and simultaneously forming a source electrode pattern and a drain electrode pattern in the source via and the drain via. The channel separation pattern may be exposed through the gate via. The Schottky barrier metal pattern may be electrically connected to the channel separation pattern. The side surface of the Schottky barrier metal pattern and the side surface of the channel separation pattern may have a step difference.

[0018] In some embodiments, the method may further include forming additional source electrode patterns and additional drain electrode patterns on the source electrode pattern and the drain electrode pattern, respectively; the additional source electrode patterns and additional drain electrode patterns may be formed simultaneously with the Schottky barrier metal pattern.

[0019] In some implementations, the additional source electrode pattern and the additional drain electrode pattern may comprise the same conductive material as the Schottky barrier metal pattern.

[0020] In some implementations, the additional source electrode pattern and the additional drain electrode pattern may completely cover the source electrode pattern and the drain electrode pattern, respectively.

[0021] In some implementations, the additional source electrode pattern and the additional drain electrode pattern may partially cover the source electrode pattern and the drain electrode pattern, respectively.

[0022] In some implementations, a portion of the source electrode pattern may be exposed between the additional source electrode pattern and the passivation layer, and a portion of the drain electrode pattern may be exposed between the additional drain electrode pattern and the passivation layer.

[0023] In some implementations, the Schottky barrier metal pattern may include an electric field relaxation region extending along the upper surface of the passivation layer toward the drain electrode pattern, and the distance between the electric field relaxation region and the drain electrode pattern may be smaller than the distance between the channel separation pattern and the drain electrode pattern.

[0024] In some implementations, the channel separation pattern may include p-type gallium nitride (GaN).

[0025] In some implementations, the formation of the Schottky barrier metal pattern can be performed before the formation of the source electrode pattern and the drain electrode pattern.

[0026] In some implementations, the formation of the source electrode pattern and the drain electrode pattern can be performed before the formation of the Schottky barrier metal pattern.

[0027] According to one embodiment, a power semiconductor device may include: a substrate including a channel; a channel separation pattern on the substrate; a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate hole, a source hole, and a drain hole penetrating the passivation layer; and a gate electrode pattern, a source electrode pattern, and a drain electrode pattern, respectively, in the gate hole, the source hole, and the drain hole, and extending to the upper surface of the passivation layer. The side surface of the gate electrode pattern in the gate hole and the side surface of the channel separation pattern may have a step difference.

[0028] In some implementations, the gate electrode pattern, source electrode pattern, and drain electrode pattern may include the same conductive material.

[0029] In some embodiments, the power semiconductor device may further include a Schottky barrier metal pattern between the gate electrode pattern and the channel separation pattern, and the Schottky barrier metal pattern may include a conductive material different from the conductive material of the gate electrode pattern, the source electrode pattern, and the drain electrode pattern.

[0030] In some implementations, the channel separation pattern may include p-type gallium nitride (GaN).

[0031] According to one embodiment, a power semiconductor device may include: a substrate including a channel; a channel separation pattern on the substrate; a passivation layer on the substrate and the channel separation pattern; the passivation layer includes a gate hole, a source hole, and a drain hole penetrating the passivation layer; and a Schottky barrier metal pattern, a source electrode pattern, and a drain electrode pattern, respectively, in the gate hole, the source hole, and the drain hole, and extending to the upper surface of the passivation layer. The side surface of the Schottky barrier metal pattern in the gate hole and the side surface of the channel separation pattern may have a step difference.

[0032] In some embodiments, the power semiconductor device may further include additional source electrode patterns and additional drain electrode patterns on the source electrode pattern and drain electrode pattern, respectively; the additional source electrode patterns and additional drain electrode patterns may include the same conductive material as the Schottky barrier metal pattern.

[0033] In some implementations, the channel separation pattern may include p-type gallium nitride (GaN).

[0034] According to one example embodiment, a power semiconductor device may include: a substrate including a channel; a channel separation pattern on the substrate; a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate via, a source via, and a drain via penetrating the passivation layer; and a gate structure, a source electrode pattern, and a drain electrode pattern, respectively, in the gate via, the source via, and the drain via, and extending to the upper surface of the passivation layer. The width of the bottom surface of the gate structure in a first direction may be smaller than the width of the upper surface of the channel separation pattern in the first direction.

[0035] In some embodiments, the gate structure may include a gate electrode pattern that directly contacts the channel separation pattern. The side surface of the portion of the gate electrode pattern in the gate aperture and the side surface of the channel separation pattern may have a step difference.

[0036] In some implementations, the gate structure may include a Schottky barrier metal pattern on a channel separation pattern.

[0037] In some implementations, the side surface of the portion of the Schottky barrier metal pattern in the gate aperture and the side surface of the channel separation pattern may have a step difference.

[0038] In some implementations, the channel separation pattern may include p-type gallium nitride (GaN). Attached Figure Description

[0039] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 This is a top view of a power semiconductor device according to one embodiment;

[0041] Figure 2 It is along Figure 1 A cross-sectional view of a power semiconductor device taken by line I-I';

[0042] Figures 3 to 8 It corresponds to Figure 1 A cross-sectional view of a power semiconductor device along line I-I', used to describe the manufacturing process. Figure 1 and Figure 2 Methods for power semiconductor devices;

[0043] Figure 9 This is a top view of a power semiconductor device according to one embodiment;

[0044] Figure 10 It is along Figure 9 A cross-sectional view of a power semiconductor device taken from line II-II';

[0045] Figure 11 It corresponds to Figure 9 A cross-sectional view of a power semiconductor device along line II-II', used to describe the fabrication process. Figure 9 and Figure 10 Methods for power semiconductor devices;

[0046] Figure 12 This is a top view of a power semiconductor device according to one embodiment;

[0047] Figure 13 It is along Figure 12 A cross-sectional view of a power semiconductor device taken from line III-III';

[0048] Figures 14 to 16 It corresponds to Figure 12 A cross-sectional view of a power semiconductor device along line III-III', used to describe the manufacturing process. Figure 12 and Figure 13 Methods for power semiconductor devices;

[0049] Figure 17 This is a top view of a power semiconductor device according to one embodiment;

[0050] Figure 18 It is along Figure 17 A cross-sectional view of a power semiconductor device taken along line IV-IV';

[0051] Figures 19 to 21 It corresponds to Figure 17 A cross-sectional view of a power semiconductor device along line IV-IV', used to describe the manufacturing process. Figure 17 and Figure 18 Methods for power semiconductor devices;

[0052] Figure 22This is a top view of a power semiconductor device according to one embodiment;

[0053] Figure 23 It is along Figure 22 A cross-sectional view of a power semiconductor device taken by line V-V';

[0054] Figure 24 It corresponds to Figure 22 A cross-sectional view of a power semiconductor device along line V-V', used to describe the manufacturing process. Figure 22 and Figure 23 Methods for power semiconductor devices;

[0055] Figure 25 This is a top view of a power semiconductor device according to one embodiment;

[0056] Figure 26 It is along Figure 25 A cross-sectional view of a power semiconductor device taken by line VI-VI';

[0057] Figure 27 It corresponds to Figure 25 A cross-sectional view of a power semiconductor device along line VI-VI', used to describe the manufacturing process. Figure 25 and Figure 26 Methods for power semiconductor devices;

[0058] Figure 28 It corresponds to Figure 9 A cross-sectional view of a power semiconductor device along line II-II', used to describe a power semiconductor device according to one embodiment;

[0059] Figure 29 This is a top view of a power semiconductor device according to one embodiment;

[0060] Figure 30 It is along Figure 29 A cross-sectional view of a power semiconductor device taken by line VII-VII';

[0061] Figure 31 This is a top view of a power semiconductor device according to one embodiment;

[0062] Figure 32 It is along Figure 31 A cross-sectional view of a power semiconductor device taken by line VIII-VIII';

[0063] Figure 33 This is a top view of a power semiconductor device according to one embodiment;

[0064] Figure 34 It is along Figure 33 A cross-sectional view of a power semiconductor device taken along line IX-IX'; and

[0065] Figure 35 This is a schematic diagram of an electronic device according to one embodiment. Detailed Implementation

[0066] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the given embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate various aspects. When used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements without modifying individual elements within that list when following a list of elements. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, or a combination thereof” can be interpreted to cover any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0067] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same elements, and the dimensions of each element may be exaggerated for clarity and convenience. However, the embodiments described below are merely examples, and various modifications can be made from these embodiments.

[0068] In the following text, objects referred to as “on” an element may include those that are in contact with and directly above the element, as well as those that are above the element but not in contact with it.

[0069] A singular expression may include a plural expression unless the context clearly indicates otherwise. Furthermore, when a part “includes” an element, it may indicate, unless otherwise stated, that another element may be included, without excluding that element.

[0070] In addition, terms such as “…unit”, “…part”, “…module”, etc., described in the specification refer to a unit that processes at least one function or operation.

[0071] Figure 1 This is a top view of a power semiconductor device according to one embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a power semiconductor device taken by line I-I'.

[0072] Reference Figure 1 and Figure 2Power semiconductor device 10 may be provided. For example, power semiconductor device 10 may include a high electron mobility transistor (HEMT). Power semiconductor device 10 may include a substrate 100, a channel separation pattern 210, a gate electrode pattern 410, a passivation layer 310, a source electrode pattern 420, and a drain electrode pattern 430. Substrate 100 may include a channel layer 110 and a channel supply layer 120. Channel layer 110 may include a III-V compound semiconductor. For example, channel layer 110 may include gallium nitride (GaN). Substrate 100 may include an active region AR in which power semiconductor device 10 is formed.

[0073] A channel supply layer 120 may be provided on the channel layer 110. The channel supply layer 120 may be a semiconductor layer different from the channel layer 110. A two-dimensional electron gas (2DEG) layer 130 may be formed in the channel layer 110. For example, the 2DEG layer 130 may include a channel of the power semiconductor device 10. The 2DEG layer 130 may be formed in the channel layer 110 adjacent to the interface between the channel supply layer 120 and the channel layer 110. For example, the 2DEG layer 130 may extend in a first direction DR1 parallel to the upper surface of the substrate 100. The channel supply layer 120 may differ from the channel layer 110 in at least one aspect of polarization characteristics, band gap, and lattice constant. For example, the channel supply layer 120 may have at least one of a larger polarization and band gap than the channel layer 110. The channel supply layer 120 may include one or more materials selected from nitrides comprising at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B). For example, the channel supply layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The channel supply layer 120 may have a single-layer structure or a multi-layer structure.

[0074] A channel separation pattern 210 can be provided on the channel supply layer 120. The channel separation pattern 210 can increase the energy band of the adjacent channel supply layer 120. Therefore, a depletion region 132 can be formed in the 2DEG layer 130 adjacent to the channel separation pattern 210. The depletion region 132 can refer to the region in which the 2DEG layer 130 is not formed. For example, the depletion region 132 can overlap with the channel separation pattern 210 in a second direction DR2 perpendicular to the upper surface of the substrate 100. Therefore, the power semiconductor device 10 can have normally-off characteristics.

[0075] The channel separation pattern 210 may include a III-V group nitride semiconductor. For example, the channel separation pattern 210 may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. The channel separation pattern 210 may include a p-type semiconductor layer or a layer doped with p-type impurities. For example, the channel separation pattern 210 may include a p-type GaN layer or a p-type AlGaN layer doped with p-type impurities such as magnesium (Mg).

[0076] A passivation layer 310 may be provided on the substrate 100 and the channel separation pattern 210. The passivation layer 310 may extend along the surfaces of the substrate 100 and the channel separation pattern 210. The passivation layer 310 may include an insulating material. For example, the passivation layer 310 may include an oxide, a nitride, or a combination thereof. For example, the passivation layer 310 may include silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), hafnium oxide (e.g., HfO2), and silicon nitride (SiO2). x N y At least one of the following.

[0077] Gate via GH, source via SH, and drain via DH can be provided in passivation layer 310. Gate via GH can penetrate passivation layer 310 to expose channel separation pattern 210. The width of gate via GH in the first direction DR1 can be smaller than the width of channel separation pattern 210 in the first direction.

[0078] The source via SH and drain via DH can penetrate the passivation layer 310 to expose the substrate 100. The source via SH and drain via DH can be separated from each other, with the gate via GH between them. The drain via DH can be separated from the source via SH in the first direction DR1. Although it is shown that the source via SH and drain via DH do not penetrate the channel supply layer 120, this is only an example. In another example, the source via SH and / or drain via DH can penetrate the channel supply layer 120 to expose the channel layer 110.

[0079] A gate electrode pattern 410 can be provided on the channel separation pattern 210. The gate electrode pattern 410 can fill the gate hole GH and extend onto the passivation layer 310. The width of the gate electrode pattern 410 in the gate hole GH can be smaller than the width of the channel separation pattern 210. The width of the gate electrode pattern 410 immediately adjacent to the channel separation pattern 210 can be smaller than the width of the channel separation pattern 210. For example, the width of the lowermost end of the gate electrode pattern 410 can be smaller than the width of the channel separation pattern 210. Therefore, the gate electrode pattern 410 and the channel separation pattern 210 can have a step difference. The structure in which the gate electrode pattern 410 and the channel separation pattern 210 have a step difference can be referred to as a stepped gate structure. Because the gate electrode pattern 410 in the gate hole GH has a width smaller than the width of the channel separation pattern 210, the leakage current flowing along the side surface of the gate electrode pattern 410 and the side surface of the channel separation pattern 210 can be reduced, and the electric field concentration on the side surface of the gate electrode pattern 410 can be limited and / or prevented. The gate electrode pattern 410 may include a conductive material. For example, the gate electrode pattern 410 may include at least one selected from titanium nitride (TiN), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), Al, nickel (Ni), and gold (Au). The gate electrode pattern 410 may have a single-layer structure or a multi-layer structure.

[0080] The gate electrode pattern 410 may include an electric field relaxation region 410R protruding from the side surface of the gate electrode pattern 410 in the gate aperture GH along the first direction DR1. The electric field relaxation region 410R may extend along the upper surface of the passivation layer 310. The electric field relaxation region 410R may be arranged closer to the drain electrode pattern 430 than the channel separation pattern 210. The distance between the electric field relaxation region 410R and the drain electrode pattern 430 in the first direction DR1 may be smaller than the distance between the channel separation pattern 210 and the drain electrode pattern 430 in the first direction DR1. The electric field relaxation region 410R may reduce the electric field concentration at the junction portion between the gate aperture GH and the channel separation pattern 210.

[0081] The source electrode pattern 420 and the drain electrode pattern 430 may be separated from each other, with the gate electrode pattern 410 therebetween. For example, the drain electrode pattern 430 may be separated from the source electrode pattern 420 in a first direction DR1. The source electrode pattern 420 and the drain electrode pattern 430 may fill the source via SH and the drain via DH, respectively, and extend onto the passivation layer 310. The source electrode pattern 420 and the drain electrode pattern 430 may penetrate the passivation layer 310. Although the source electrode pattern 420 and the drain electrode pattern 430 are shown to be separated from the channel layer 110 by the channel supply layer 120, this is only an example. In another example, the source electrode pattern 420 and / or the drain electrode pattern 430 may penetrate the channel supply layer 120 to contact the channel layer 110. For example, the source electrode pattern 420 and / or the drain electrode pattern 430 penetrating the channel supply layer 120 may extend to a depth that directly contacts the 2DEG layer 130. The source electrode pattern 420 and drain electrode pattern 430 can make ohmic contact with the channel supply layer 120. An ohmic contact layer (not shown) can be interposed between the source electrode pattern 420 and the channel supply layer 120, and between the drain electrode pattern 430 and the channel supply layer 120, as needed. The source electrode pattern 420 and drain electrode pattern 430 can have a single-layer or multi-layer structure. The source electrode pattern 420 and drain electrode pattern 430 can include materials substantially the same as those used in the gate electrode pattern 410. For example, the source electrode pattern 420 and drain electrode pattern 430 can include at least one of TiN, Pt, Pd, W, Ti, Al, Ni, and Au.

[0082] In this disclosure, leakage current flowing along the side surfaces of the gate electrode pattern 410 and the channel separation pattern 210 can be reduced, and the power semiconductor device 10 can be provided to limit and / or prevent electric field concentration on the side surfaces of the gate electrode pattern 410. This disclosure can provide a power semiconductor device 10 in which the electric field is limited and / or prevented from concentrating on the junction portion between the gate via GH and the channel separation pattern 210.

[0083] Figures 3 to 8 It corresponds to Figure 1 A cross-sectional view of a power semiconductor device along line I-I', used to describe the manufacturing process. Figure 1 and Figure 2 Methods for developing power semiconductor devices.

[0084] Reference Figure 3The channel layer 110 and the channel supply layer 120 can be stacked sequentially. The channel layer 110 and the channel supply layer 120 can constitute the substrate 100. For example, the channel layer 110 and the channel supply layer 120 can be formed on a deposition substrate (e.g., a silicon substrate, a silicon carbide (SiC) substrate, a GaN substrate, a diamond substrate, or a sapphire substrate) by an epitaxial growth process. For example, the epitaxial growth process can include at least one of metal-organic chemical vapor deposition, liquid phase epitaxy, hydride vapor phase epitaxy, molecular beam epitaxy, or metal-organic vapor phase epitaxy.

[0085] The channel layer 110 may include a III-V compound semiconductor. For example, the channel layer 110 may include GaN. The channel supply layer 120 may be a semiconductor layer different from the channel layer 110. The channel supply layer 120 may differ from the channel layer 110 in at least one of the following aspects: polarization characteristics, band gap, and lattice constant. The channel supply layer 120 may include one or more materials selected from nitrides comprising at least one of Al, Ga, In, and B. For example, the channel supply layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The channel supply layer 120 may have a monolayer structure or a multilayer structure.

[0086] The channel supply layer 120 may form a 2DEG layer 130 within the channel layer 110. The 2DEG layer 130 may be formed within the channel layer 110 adjacent to the interface between the channel supply layer 120 and the channel layer 110. The 2DEG layer 130 may extend in a first direction DR1 parallel to the upper surface of the substrate 100.

[0087] Reference Figure 4 A channel separation layer 200 can be formed on the channel supply layer 120. For example, the channel separation layer 200 can be formed on the channel supply layer 120 by an epitaxial growth process. The channel separation layer 200 can include a III-V compound semiconductor. For example, the channel separation layer 200 can include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. The channel separation layer 200 can include a p-type semiconductor layer or a layer doped with p-type impurities. For example, the channel separation layer 200 can be doped with a p-type impurity such as Mg. For example, the channel separation layer 200 can include a p-type GaN layer or a p-type AlGaN layer.

[0088] A mask pattern EM can be formed on the channel separation layer 200. For example, the mask pattern EM may include a photoresist pattern.

[0089] Reference Figure 5The channel separation layer 200 can be patterned using an etching process that uses a mask pattern EM as an etching mask, thereby forming a channel separation pattern 210. An etching process can be performed on the channel separation layer 200 to expose the substrate 100. The channel separation pattern 210 can increase the energy band of the adjacent channel supply layer 120. A depletion region 132, in which no 2DEG layer 130 is formed, can be formed in the channel layer adjacent to the channel separation pattern 210. Therefore, the power semiconductor device 10 can have normally-off characteristics. The mask pattern EM can be removed during or after the etching process.

[0090] Reference Figure 6 A passivation layer 310 can be formed on the substrate 100 and the channel separation pattern 210. The process for forming the passivation layer 310 may include depositing an insulating material on the substrate 100 and the channel separation pattern 210. For example, the passivation layer 310 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, the passivation layer 310 may include oxides, nitrides, or combinations thereof. For example, the passivation layer 310 may include SiO2, Al2O3, HfO2, and Si... x N y At least one of them.

[0091] A mask pattern EM can be formed on the passivation layer 310 to form the gate via GH, source via SH, and drain via DH. For example, the mask pattern EM may include a photoresist pattern. The mask pattern EM can expose portions of the passivation layer 310 where the gate via GH, source via SH, and drain via DH will be formed.

[0092] Reference Figure 7 The passivation layer 310 can be patterned using an etching process that employs a mask pattern EM as an etching mask, thereby forming the gate via GH, source via SH, and drain via DH. The etching process can be performed to expose the substrate 100 and the channel separation pattern 210. The mask pattern EM can be removed during or after the etching process.

[0093] Reference Figure 8A conductive material layer 400 can be formed on the passivation layer 310. The conductive material layer 400 can extend along the passivation layer 310 and can fill the gate via GH, source via SH, and drain via DH. Although the conductive material layer 400 is shown to completely fill the gate via GH, source via SH, and drain via DH, this is only an example. In another example, the conductive material layer 400 can partially fill the gate via GH, source via SH, and / or drain via DH. The conductive material layer 400 can be in direct contact with the substrate 100 and the channel separation pattern 210. The process for forming the conductive material layer 400 can include depositing a conductive material (e.g., at least one of TiN, Pt, Pd, W, Ti, Al, Ni, and Au) on the passivation layer 310. For example, the conductive material layer 400 can be formed by a CVD process, a PVD process, or an ALD process.

[0094] The mask pattern EM can be formed on the conductive material layer 400. For example, the mask pattern EM may include a photoresist pattern. The mask pattern EM can be formed to overlap with the gate via GH, source via SH, and drain via DH in the second direction DR2.

[0095] Refer again Figure 2 The conductive material layer 400 can be patterned using an etching process that employs a mask pattern EM as the etching mask, thereby forming the gate electrode pattern 410, the source electrode pattern 420, and the drain electrode pattern 430. The mask pattern EM can be removed during or after the etching process. Because the gate electrode pattern 410, the source electrode pattern 420, and the drain electrode pattern 430 are formed simultaneously, the process time and cost can be reduced compared to the case where the gate electrode pattern 410, the source electrode pattern 420, and the drain electrode pattern 430 are formed separately.

[0096] Figure 9 This is a top view of a power semiconductor device according to one embodiment. Figure 10 It is along Figure 9 A cross-sectional view of a power semiconductor device taken along line II-II'. For the sake of brevity, refer to the above references. Figure 1 and Figure 2 Descriptions that are essentially the same can be omitted.

[0097] Reference Figure 9 and Figure 10 A power semiconductor device 11 may be provided. The power semiconductor device 11 may include a substrate 100, a channel separation pattern 210, a gate electrode pattern 410, a passivation layer 310, a source electrode pattern 420, a drain electrode pattern 430, and an electric field relaxation pattern 440. The substrate 100, channel separation pattern 210, gate electrode pattern 410, passivation layer 310, source electrode pattern 420, and drain electrode pattern 430 may be referenced. Figure 1 and Figure 2 The descriptions are basically the same.

[0098] An electric field relaxation pattern 440 may be located between the gate electrode pattern 410 and the drain electrode pattern 430. The electric field relaxation pattern 440 may be spaced apart from the gate electrode pattern 410 and the drain electrode pattern 430. The electric field relaxation pattern 440 may be provided on the passivation layer 310. The electric field relaxation pattern 440 may include a conductive material. The electric field relaxation pattern 440 may include a material substantially the same as that of the gate electrode pattern 410, the source electrode pattern 420, and the drain electrode pattern 430. For example, the electric field relaxation pattern 440 may include at least one of TiN, Pt, Pd, W, Ti, Al, Ni, and Au.

[0099] When the power semiconductor device 11 is operating, a voltage can be applied to the electric field relaxation pattern 440. For example, the voltage applied to the electric field relaxation pattern 440 can be the same as the voltage applied to the source electrode pattern 420. For example, conductive paths and conductive lines can be present between the electric field relaxation pattern 440 and the source electrode pattern 420 to electrically connect the electric field relaxation pattern 440 to the source electrode pattern 420.

[0100] The electric field relaxation pattern 440 in this disclosure can reduce the electric field concentration at the junction portion between the gate aperture GH and the channel separation pattern 210. Therefore, the power semiconductor device 11 can have improved electrical characteristics.

[0101] Figure 11 It corresponds to Figure 9 A cross-sectional view of a power semiconductor device along line II-II', used to describe the manufacturing process. Figure 9 and Figure 10 Methods for power semiconductor devices. For the sake of brevity, refer to the above. Figures 3 to 8 Descriptions that are essentially the same can be omitted.

[0102] Reference Figure 11 The channel separation pattern 210, passivation layer 310, conductive material layer 400, and mask pattern EM can be compared with a reference. Figures 3 to 8 The process described is substantially the same as that used in the reference process, and is formed on substrate 100. However, compared with the reference process... Figure 8 Different from the described examples, the mask pattern EM may further include a mask pattern EM for generating an electric field relaxation pattern 440 between a pattern formed to overlap with the gate via GH and a pattern formed to overlap with the drain via DH.

[0103] Refer again Figure 10The conductive material layer 400 can be patterned using an etching process that employs a mask pattern EM as the etching mask, thereby forming a gate electrode pattern 410, a source electrode pattern 420, a drain electrode pattern 430, and an electric field relaxation pattern 440. The mask pattern EM can be removed during or after the etching process. Because the gate electrode pattern 410, source electrode pattern 420, drain electrode pattern 430, and electric field relaxation pattern 440 are formed simultaneously, the process time and cost can be reduced compared to the case where the gate electrode pattern 410, source electrode pattern 420, drain electrode pattern 430, and electric field relaxation pattern 440 are formed separately.

[0104] Figure 12 This is a top view of a power semiconductor device according to one embodiment. Figure 13 It is along Figure 12 A cross-sectional view of a power semiconductor device taken along line III-III'. For the sake of brevity, refer to the above references. Figure 1 and Figure 2 Descriptions that are essentially the same can be omitted.

[0105] Reference Figure 12 and Figure 13 Power semiconductor device 12 can be provided. Power semiconductor device 12 may include substrate 100, channel separation pattern 210, Schottky barrier metal pattern 510, gate electrode pattern 410, passivation layer 310, source electrode pattern 420, and drain electrode pattern 430. Substrate 100, channel separation pattern 210, gate electrode pattern 410, passivation layer 310, source electrode pattern 420, and drain electrode pattern 430 can be referenced. Figure 1 and Figure 2 The descriptions are basically the same.

[0106] The Schottky barrier metal pattern 510 can be located between the passivation layer 310 and the gate electrode pattern 410, and between the channel separation pattern 210 and the gate electrode pattern 410. The Schottky barrier metal pattern 510 can be in direct contact with the gate electrode pattern 410. The side surface of the Schottky barrier metal pattern 510 on the upper surface of the passivation layer 310 can be coplanar with the side surface of the gate electrode pattern 410. For example, the side surface of the Schottky barrier metal pattern 510 and the side surface of the gate electrode pattern 410 can extend on the upper surface of the passivation layer 310 in the second direction DR2.

[0107] The Schottky barrier metal pattern 510 can have a high work function. For example, the Schottky barrier metal pattern 510 can include TiN, tantalum nitride (TaN), ruthenium (Ru), Mo, Al, tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum silicide (TaSi2), or nickel silicide (NiSi2). The resistance between the Schottky barrier metal pattern 510 and the channel separation pattern 210 can be higher than the resistance between the gate electrode pattern 410 and the channel separation pattern 210.

[0108] This disclosure can provide a power semiconductor device 12 that has improved electrical characteristics by including a Schottky barrier metal pattern 510 having a Schottky barrier with respect to the channel separation pattern 210.

[0109] Figures 14 to 16 It corresponds to Figure 12 A cross-sectional view of a power semiconductor device along line III-III', used to describe the manufacturing process. Figure 12 and Figure 13 Methods for power semiconductor devices. For the sake of brevity, refer to the above. Figures 3 to 8 Descriptions that are essentially the same can be omitted.

[0110] Reference Figure 14 It can be compared with the reference Figures 3 to 7 The process described is essentially the same as that used to form a channel separation pattern 210 and a passivation layer 310 on a substrate 100.

[0111] A Schottky barrier metal layer 500 can be formed on the passivation layer 310. The Schottky barrier metal layer 500 can extend along the surface of the passivation layer 310, the surface of the channel separation pattern 210 exposed through the gate via GH, the source via SH, the drain via DH, and the surface of the substrate 100. The formation of the Schottky barrier metal layer 500 can include depositing a Schottky barrier metal on the passivation layer 310 (e.g., CVD, PVD, or ALD process). For example, the Schottky barrier metal can include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, or NiSi2.

[0112] A mask pattern EM can be formed on the Schottky barrier metal layer 500. For example, the mask pattern EM may include a photoresist pattern. The mask pattern EM can be formed on the channel separation pattern 210. The mask pattern EM can be formed to overlap with the channel separation pattern 210 in the second direction DR2.

[0113] Reference Figure 15The Schottky barrier metal layer 500 can be patterned using an etching process that employs a mask pattern EM as an etching mask, thereby forming a Schottky barrier metal pattern 510. The mask pattern EM can be removed during or after the etching process. The Schottky barrier metal pattern 510 can be compared with a reference... Figure 12 and Figure 13 The descriptions are basically the same.

[0114] Reference Figure 16 It can be compared with the reference Figure 8 The process described is substantially the same as that described above, forming a conductive material layer 400 and a mask pattern EM on a passivation layer 310 and a Schottky barrier metal pattern 510. The conductive material layer 400 may cover the passivation layer 310 and the Schottky barrier metal pattern 510, and may fill the gate via GH, source via SH, and drain via DH. Although it is shown that the conductive material layer 400 completely fills the gate via GH, source via SH, and drain via DH, this is only an example. In another example, the conductive material layer 400 may partially fill the gate via GH, source via SH, and / or drain via DH. The conductive material layer 400 may be in direct contact with the substrate 100 and the Schottky barrier metal pattern 510. The mask pattern EM may completely overlap with the Schottky barrier metal pattern 510 in the second direction DR2. For example, the mask pattern EM may be completely included in the region overlapping with the Schottky barrier metal pattern 510 in the second direction DR2.

[0115] Refer again Figure 13 The conductive material layer 400 can be patterned using an etching process that employs a mask pattern EM as an etching mask, thereby forming the gate electrode pattern 410, source electrode pattern 420, and drain electrode pattern 430. The mask pattern EM can be removed during or after the etching process. For example, a portion of the Schottky barrier metal pattern 510 can be etched together during the etching process of the conductive material layer 400. Therefore, the side surfaces of the gate electrode pattern 410 and the Schottky barrier metal pattern 510 can be coplanar on the upper surface of the passivation layer 310.

[0116] Figure 17 This is a top view of a power semiconductor device according to one embodiment. Figure 18 It is along Figure 17 A cross-sectional view of a power semiconductor device taken along line IV-IV'. For the sake of brevity, refer to the above references. Figure 12 and Figure 13 Descriptions that are essentially the same can be omitted.

[0117] Reference Figure 17 and Figure 18 Power semiconductor device 13 may be provided. Power semiconductor device 13 may include, in addition to those referenced, Figure 12 and Figure 13 Other elements besides the gate electrode pattern 410 in the power semiconductor device 12 described. In the power semiconductor device 13, the Schottky barrier metal pattern 510 may function as a gate electrode.

[0118] This disclosure can provide a power semiconductor device 13 that has improved electrical characteristics by including a Schottky barrier metal pattern 510 having a Schottky barrier with respect to the channel separation pattern 210.

[0119] Figures 19 to 21 It corresponds to power semiconductor devices Figure 17 A cross-sectional view along line IV-IV', used to describe the manufacturing process. Figure 17 and Figure 18 Methods for power semiconductor devices. For the sake of brevity, refer to the above. Figures 3 to 8 The given description and the above references Figure 14 Descriptions that are essentially the same can be omitted.

[0120] Reference Figure 19 It can be compared with the reference Figures 3 to 8 The process described is essentially the same as that used to form a channel separation pattern 210, a passivation layer 310, a conductive material layer 400, and a mask pattern EM on a substrate 100. (Similar to...) Figure 8 The diagram in the image is different, so a mask pattern EM may not be formed on the gate aperture GH.

[0121] Reference Figure 20 The conductive material layer 400 can be patterned using an etching process that uses a mask pattern EM as an etching mask, thereby forming the source electrode pattern 420 and the drain electrode pattern 430. The mask pattern EM can be removed during or after the etching process. Because the mask pattern EM is not formed on the gate via GH, the conductive material layer 400 in the gate via GH can be removed. The channel separation pattern 210 can be exposed through the gate via GH.

[0122] Reference Figure 21 It can be compared with the reference Figure 14 The process described is substantially the same as that used to form the Schottky barrier metal layer 500 and the mask pattern EM. The Schottky barrier metal layer 500 may extend along the surface of the passivation layer 310 and the surface of the channel separation pattern 210 exposed through the gate via GH. The mask pattern EM may be provided on the channel separation pattern 210. The mask pattern EM may not be formed on the source electrode pattern 420 and the drain electrode pattern 430.

[0123] Refer again Figure 18The Schottky barrier metal layer 500 can be patterned using an etching process that employs a mask pattern EM as an etching mask, thereby forming a Schottky barrier metal pattern 510. The Schottky barrier metal layer 500 on the source electrode pattern 420 and the drain electrode pattern 430 can be removed to expose the source electrode pattern 420 and the drain electrode pattern 430. The mask pattern EM can be removed during the etching process or after the etching process is completed.

[0124] Figure 22 This is a top view of a power semiconductor device according to one embodiment. Figure 23 It is along Figure 22 A cross-sectional view of a power semiconductor device taken along line V-V'. For the sake of brevity, refer to the above reference. Figure 17 and Figure 18 Descriptions that are essentially the same can be omitted.

[0125] Reference Figure 22 and Figure 23 Power semiconductor device 14 may be provided. Power semiconductor device 14 may include reference to Figure 17 and Figure 18 All elements of the power semiconductor device 13 described herein may further include an additional source electrode pattern 520 and an additional drain electrode pattern 530.

[0126] An additional source electrode pattern 520 may be provided on the source electrode pattern 420. The additional source electrode pattern 520 may completely cover the upper surface and exposed side surfaces of the source electrode pattern 420. The additional source electrode pattern 520 may extend from the source electrode pattern 420 onto the passivation layer 310.

[0127] An additional drain electrode pattern 530 may be provided on the drain electrode pattern 430. The additional drain electrode pattern 530 may completely cover the upper surface and exposed side surfaces of the drain electrode pattern 430. The additional drain electrode pattern 530 may extend from the drain electrode pattern 430 onto the passivation layer 310.

[0128] Figure 24 It corresponds to Figure 22 A cross-sectional view of a power semiconductor device along line V-V', used to describe the manufacturing process. Figure 22 and Figure 23 Methods for power semiconductor devices. For the sake of brevity, refer to the above. Figures 19 to 21 Descriptions that are essentially the same can be omitted.

[0129] Reference Figure 24 It can be compared with the reference Figures 19 to 21The process described is essentially the same as that described above, forming a channel separation pattern 210, a passivation layer 310, a source electrode pattern 420, a drain electrode pattern 430, a Schottky barrier metal layer 500, and a mask pattern EM on a substrate 100. Figure 21 Unlike the illustrations, the mask pattern EM can be formed on the channel separation pattern 210, the source electrode pattern 420, and the drain electrode pattern 430. The mask pattern EM on the source electrode pattern 420 and the drain electrode pattern 430 can completely cover the source electrode pattern 420 and the drain electrode pattern 430. The mask pattern EM on the source electrode pattern 420 can extend from the upper surface of the source electrode pattern 420 to its exposed side surface. The mask pattern EM on the drain electrode pattern 430 can extend from the upper surface of the drain electrode pattern 430 to its exposed side surface.

[0130] Refer again Figure 23 The Schottky barrier metal layer 500 can be patterned using an etching process that employs a mask pattern EM as the etching mask, thereby forming a Schottky barrier metal pattern 510, an additional source electrode pattern 520, and an additional drain electrode pattern 530. The Schottky barrier metal pattern 510, the additional source electrode pattern 520, and the additional drain electrode pattern 530 can be compared with a reference... Figure 22 and Figure 23 The descriptions are essentially the same. The mask pattern EM can be removed during the etching process or after the etching process is complete.

[0131] Figure 25 This is a top view of a power semiconductor device according to one embodiment. Figure 26 It is along Figure 25 A cross-sectional view of a power semiconductor device taken along line VI-VI'. For the sake of brevity, refer to the above references. Figure 22 and Figure 23 Descriptions that are essentially the same can be omitted.

[0132] Reference Figure 25 and Figure 26 Power semiconductor device 15 can be provided. Power semiconductor device 15 can be compared with reference to... Figure 22 and Figure 23 The power semiconductor device 14 described is substantially the same, except for the shapes of the additional source electrode pattern 520 and the additional drain electrode pattern 530.

[0133] With reference Figure 22 and Figure 23 The description differs; the additional source electrode pattern 520 may not be provided on the side surface of the source electrode pattern 420. The additional source electrode pattern 520 may be provided on the top surface of the source electrode pattern 420. Although Figure 25The example shown illustrates that the additional source electrode pattern 520 is smaller than the source electrode pattern 420, but this is merely an example. In another example, the additional source electrode pattern 520 and the source electrode pattern 420 may completely overlap each other. In other words, the upper surface of the additional source electrode pattern 520 and the upper surface of the source electrode pattern 420 may have the same area. A portion of the source electrode pattern 420 may be exposed between the additional source electrode pattern 520 and the passivation layer 310.

[0134] With reference Figure 22 and Figure 23 The description differs; the additional drain electrode pattern 530 may not be provided on the side surface of the drain electrode pattern 430. The additional drain electrode pattern 530 may be provided on the top surface of the drain electrode pattern 430. Although Figure 25 The additional drain electrode pattern 530 is shown to be smaller than the drain electrode pattern 430, but this is only an example. In another example, the additional drain electrode pattern 530 and the drain electrode pattern 430 may completely overlap each other. In other words, the upper surface of the additional drain electrode pattern 530 and the upper surface of the drain electrode pattern 430 may have the same area. A portion of the drain electrode pattern 430 may be exposed between the additional drain electrode pattern 530 and the passivation layer 310.

[0135] Figure 27 It corresponds to Figure 25 A cross-sectional view of a power semiconductor device along line VI-VI', used to describe the manufacturing process. Figure 25 and Figure 26 Methods for power semiconductor devices. For the sake of brevity, refer to the above. Figure 24 Descriptions that are essentially the same can be omitted.

[0136] Reference Figure 27 It can be compared with the reference Figure 24 The process described is essentially the same as that described above, forming a channel separation pattern 210, a passivation layer 310, a source electrode pattern 420, a drain electrode pattern 430, a Schottky barrier metal layer 500, and a mask pattern EM on a substrate 100. Figure 24 Unlike the illustrations, the mask pattern EM may not be formed to completely cover the source electrode pattern 420 and the drain electrode pattern 430. The mask pattern EM may be formed on the upper surface of the source electrode pattern 420 and the upper surface of the drain electrode pattern 430. The mask pattern EM may not be formed on the side surfaces of the source electrode pattern 420 and the side surfaces of the drain electrode pattern 430.

[0137] Refer again Figure 26The Schottky barrier metal layer 500 can be patterned using an etching process that employs a mask pattern EM as the etching mask, thereby forming a Schottky barrier metal pattern 510, an additional source electrode pattern 520, and an additional drain electrode pattern 530. The Schottky barrier metal pattern 510, the additional source electrode pattern 520, and the additional drain electrode pattern 530 can be compared with a reference... Figure 22 and Figure 23 The descriptions are essentially the same. The mask pattern EM can be removed during the etching process or after the etching process is complete.

[0138] Figure 28 It corresponds to Figure 9 The image shown is a cross-sectional view of a power semiconductor device along line II-II', used to describe a power semiconductor device according to one embodiment. For the sake of brevity, it is referenced above. Figure 12 and Figure 13 The given description and reference Figure 9 and Figure 10 Descriptions that are essentially the same can be omitted.

[0139] Reference Figure 28 Power semiconductor device 16 may be provided. Power semiconductor device 16 may include substrate 100, channel separation pattern 210, Schottky barrier metal pattern 510, gate electrode pattern 410, passivation layer 310, source electrode pattern 420, drain electrode pattern 430 and electric field relaxation pattern 440.

[0140] The substrate 100, channel separation pattern 210, gate electrode pattern 410, passivation layer 310, source electrode pattern 420, drain electrode pattern 430, and electric field relaxation pattern 440 can be compared with a reference. Figure 9 and Figure 10 The descriptions are basically the same.

[0141] The electric field relaxation pattern 440 can be compared with the reference. Figure 9 and Figure 10 The electric field relaxation patterns described are basically the same, except for the position of electric field relaxation pattern 440 relative to Schottky barrier metal pattern 510.

[0142] The electric field relaxation pattern 440 can be located between the Schottky barrier metal pattern 510 and the drain electrode pattern 430. The electric field relaxation pattern 440 can be spaced apart from the Schottky barrier metal pattern 510 and the drain electrode pattern 430.

[0143] When the power semiconductor device 16 is operating, a voltage can be applied to the electric field relaxation pattern 440. For example, the voltage applied to the electric field relaxation pattern 440 can be the same as the voltage applied to the source electrode pattern 420. For example, conductive paths and conductive lines can be present between the electric field relaxation pattern 440 and the source electrode pattern 420 to electrically connect the electric field relaxation pattern 440 to the source electrode pattern 420.

[0144] The electric field relaxation pattern 440 in this disclosure can reduce the electric field concentration at the junction portion between the gate aperture GH and the channel separation pattern 210. Therefore, a power semiconductor device 16 with improved electrical characteristics can be provided.

[0145] Figure 29 This is a top view of a power semiconductor device according to one embodiment. Figure 30 It is along Figure 29 A cross-sectional view of a power semiconductor device taken along line VII-VII'. For the sake of brevity, refer to the above references. Figure 28 Descriptions that are essentially the same can be omitted.

[0146] Reference Figure 29 and Figure 30 Power semiconductor device 17 may be provided. Power semiconductor device 17 may include reference to Figure 28 The power semiconductor device 16 described includes elements other than the gate electrode pattern 410. In the power semiconductor device 17, the Schottky barrier metal pattern 510 can function as a gate electrode.

[0147] This disclosure can provide a power semiconductor device 17 that has improved electrical characteristics by including a Schottky barrier metal pattern 510 having a Schottky barrier with respect to the channel separation pattern 210.

[0148] Figure 31 This is a top view of a power semiconductor device according to one embodiment. Figure 32 It is along Figure 31 A cross-sectional view of a power semiconductor device taken along line VIII-VIII'. For the sake of brevity, refer to the above references. Figure 29 and Figure 30 Descriptions that are essentially the same can be omitted.

[0149] Reference Figure 31 and Figure 32 Power semiconductor device 18 may be provided. Power semiconductor device 18 may include reference to Figure 29 and Figure 30 All elements of the power semiconductor device 17 described herein may further include an additional source electrode pattern 520 and an additional drain electrode pattern 530.

[0150] An additional source electrode pattern 520 may be provided on the source electrode pattern 420. The additional source electrode pattern 520 may completely cover the upper surface and exposed side surfaces of the source electrode pattern 420. The additional source electrode pattern 520 may extend from the source electrode pattern 420 onto the passivation layer 310.

[0151] An additional drain electrode pattern 530 may be provided on the drain electrode pattern 430. The additional drain electrode pattern 530 may completely cover the upper surface and exposed side surfaces of the drain electrode pattern 430. The additional drain electrode pattern 530 may extend from the drain electrode pattern 430 onto the passivation layer 310. The additional drain electrode pattern 530 may be spaced apart from the electric field relaxation pattern 440. The electric field relaxation pattern 440 may be located between the additional drain electrode pattern 530 and the Schottky barrier metal pattern 510.

[0152] This disclosure can provide a power semiconductor device 18 with improved electrical characteristics.

[0153] Figure 33 This is a top view of a power semiconductor device according to one embodiment. Figure 34 It is along Figure 33 The image shows a cross-sectional view of a power semiconductor device taken along line IX-IX'. For the sake of brevity, refer to the above references. Figure 31 and Figure 32 Descriptions that are essentially the same can be omitted.

[0154] Reference Figure 33 and Figure 34 Power semiconductor device 19 can be provided. Power semiconductor device 19 can be used with reference to... Figure 31 and Figure 32 The power semiconductor device 18 described is substantially the same, except for the shapes of the additional source electrode pattern 520 and the additional drain electrode pattern 530.

[0155] With reference Figure 31 and Figure 32 Depending on the given description, the additional source electrode pattern 520 may not be provided on the side surface of the source electrode pattern 420. The additional source electrode pattern 520 may only be provided on the top surface of the source electrode pattern 420. Although in Figure 33 The diagram shows that the additional source electrode pattern 520 is smaller than the source electrode pattern 420, but this is only an example. In another example, the additional source electrode pattern 520 and the source electrode pattern 420 may completely overlap each other. In other words, the upper surface of the additional source electrode pattern 520 and the upper surface of the source electrode pattern 420 may have the same area. A portion of the source electrode pattern 420 may be exposed between the additional source electrode pattern 520 and the passivation layer 310.

[0156] The additional drain electrode pattern 530 may not be provided on the side surface of the drain electrode pattern 430. The additional drain electrode pattern 530 may be provided only on the top surface of the drain electrode pattern 430. Although in Figure 33 The diagram shows an additional drain electrode pattern 530 smaller than the drain electrode pattern 430, but this is only an example. In another example, the additional drain electrode pattern 530 and the drain electrode pattern 430 may completely overlap each other. In other words, the upper surface of the additional drain electrode pattern 530 and the upper surface of the drain electrode pattern 430 may have the same area. A portion of the drain electrode pattern 430 may be exposed between the additional drain electrode pattern 530 and the passivation layer 310.

[0157] This disclosure can provide a power semiconductor device 19 with improved electrical characteristics.

[0158] This disclosure can provide power semiconductor devices with improved electrical characteristics.

[0159] This disclosure provides a method for manufacturing power semiconductor devices with improved electrical characteristics.

[0160] This disclosure provides a method for manufacturing power semiconductor devices with improved process efficiency.

[0161] In the embodiments discussed above, the gate electrode pattern 410 and the Schottky barrier metal pattern 510 can be referred to individually or in combination as the gate structure.

[0162] Figure 35 This is a schematic diagram of an electronic device according to one embodiment.

[0163] Reference Figure 35 The electronic device 1000 includes one or more electronic device components, including a processor (e.g., processing circuitry) 1020 and a memory 1030 that are communicatively connected together via a bus 1010.

[0164] Processing circuitry 1020 may be included in one or more instances of processing circuitry, and may include one or more instances of processing circuitry and / or may be implemented by one or more instances of processing circuitry, wherein the one or more instances of processing circuitry are hardware including logic circuitry, hardware / software combinations such as processors executing software, or combinations thereof. For example, processing circuitry 1020 may include, but is not limited to, a central processing unit (CPU), application processor (AP), arithmetic logic unit (ALU), graphics processing unit (GPU), digital signal processor, microcomputer, field programmable gate array (FPGA), system-on-chip (SoC), programmable logic unit, microprocessor, or application-specific integrated circuit (ASIC), etc. In some example embodiments, memory 1030 may include a non-transitory computer-readable storage device storing instruction programs, such as a solid-state drive (SSD), and processing circuitry 1020 may be configured to execute instruction programs to implement the functions of electronic device 1000.

[0165] In some example embodiments, electronic device 1000 may include one or more additional components 1040 coupled to bus 1010, which may include, for example, power supply, light sensor, light-emitting device, any combination thereof, etc. In some example embodiments, processing circuitry 1020, memory 1030, or one or more of the additional components 1040 may include any power semiconductor devices 10 to 19 according to any of the example embodiments described herein.

[0166] However, the effects of this disclosure are not limited thereto.

[0167] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0168] This application is based on and claims priority to Korean Patent Application No. 10-2021-0041267 filed with the Korean Intellectual Property Office on March 30, 2021, and Korean Patent Application No. 10-2021-0054645 filed with the Korean Intellectual Property Office on April 27, 2021, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A method for manufacturing a power semiconductor device, the method comprising: A channel separation pattern is formed on the substrate; A passivation layer is formed on the substrate and the channel separation pattern; Forming gate holes, source holes, and drain holes that penetrate the passivation layer; Both source electrode patterns and drain electrode patterns are formed simultaneously in the source via and the drain via. A Schottky barrier metal pattern is formed in the gate aperture; as well as Additional source electrode patterns and additional drain electrode patterns are formed on the source electrode pattern and the drain electrode pattern, respectively. The channel separation pattern is exposed through the gate via. The Schottky barrier metal pattern is electrically connected to the channel separation pattern to form a Schottky barrier with the channel separation pattern, and The side surfaces of the Schottky barrier metal pattern and the channel separation pattern have a step difference. The additional source electrode pattern and the additional drain electrode pattern are formed simultaneously with the Schottky barrier metal pattern.

2. The method as described in claim 1, The additional source electrode pattern and the additional drain electrode pattern comprise the same conductive material as the Schottky barrier metal pattern.

3. The method as described in claim 1, The additional source electrode pattern and the additional drain electrode pattern completely cover the source electrode pattern and the drain electrode pattern, respectively.

4. The method as described in claim 1, The additional source electrode pattern and the additional drain electrode pattern partially cover the source electrode pattern and the drain electrode pattern, respectively.

5. The method as described in claim 4, A portion of the source electrode pattern is exposed between the additional source electrode pattern and the passivation layer, and A portion of the drain electrode pattern is exposed between the additional drain electrode pattern and the passivation layer.

6. The method as described in claim 1, The Schottky barrier metal pattern includes an electric field relaxation region extending along the upper surface of the passivation layer toward the drain electrode pattern, and The distance between the electric field relaxation region and the drain electrode pattern is less than the distance between the channel separation pattern and the drain electrode pattern.

7. The method as described in claim 1, The channel separation pattern mentioned above includes p-type gallium nitride (GaN).

8. A power semiconductor device, comprising: Substrate including channels; Channel separation pattern on the substrate; A passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate via, a source via and a drain via penetrating the passivation layer; Schottky barrier metal patterns, source electrode patterns, and drain electrode patterns are respectively located in the gate hole, the source hole, and the drain hole and extend to the upper surface of the passivation layer; as well as Additional source electrode patterns and additional drain electrode patterns respectively on the source electrode pattern and the drain electrode pattern, The side surfaces of the Schottky barrier metal pattern in the gate aperture and the side surfaces of the channel separation pattern have a step difference. The Schottky barrier metal pattern is electrically connected to the channel separation pattern to form a Schottky barrier with the channel separation pattern, and The additional source electrode pattern and the additional drain electrode pattern comprise the same conductive material as the Schottky barrier metal pattern and are formed simultaneously with the Schottky barrier metal pattern.

9. The power semiconductor device as described in claim 8, The channel separation pattern mentioned above includes p-type gallium nitride (GaN).

10. A power semiconductor device, comprising: Substrate including channels; Channel separation pattern on the substrate; A passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate via, a source via and a drain via penetrating the passivation layer; A gate structure, a source electrode pattern, and a drain electrode pattern are respectively located in the gate hole, the source hole, and the drain hole and extend to the upper surface of the passivation layer; Additional source electrode patterns and additional drain electrode patterns respectively on the source electrode pattern and the drain electrode pattern, The width of the bottom surface of the gate structure in the first direction is smaller than the width of the upper surface of the channel separation pattern in the first direction. The gate structure includes a Schottky barrier metal pattern on the channel separation pattern, and The Schottky barrier metal pattern is electrically connected to the channel separation pattern to form a Schottky barrier with the channel separation pattern, and The additional source electrode pattern and the additional drain electrode pattern comprise the same conductive material as the Schottky barrier metal pattern and are formed simultaneously with the Schottky barrier metal pattern.

11. The power semiconductor device as claimed in claim 10, The gate structure includes a gate electrode pattern directly on the Schottky barrier metal pattern, and The side surface of the portion of the gate electrode pattern in the gate hole and the side surface of the channel separation pattern have a step difference.

12. The power semiconductor device of claim 10, wherein... The side surface of the portion of the Schottky barrier metal pattern in the gate aperture and the side surface of the channel separation pattern have a step difference.

13. The power semiconductor device as described in claim 10, The channel separation pattern mentioned above includes p-type gallium nitride (GaN).

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