A metal chalcogenophosphate dielectric layer transistor device and a preparation method thereof

Abstract

The present invention provides a metal chalcogenophosphate dielectric layer transistor device and a preparation method thereof, including a substrate; an insulating encapsulation layer, a conductive channel, a dielectric layer, and a gate disposed on the substrate; and source and drain electrodes disposed on both sides of the conductive channel; the dielectric layer is a multi-layer or few-layer metal chalcogenophosphate prepared by a mechanical exfoliation method or a chemical vapor deposition method (CVD). Using the few-layer metal chalcogenophosphate material obtained by mechanical exfoliation as the dielectric layer of the field effect transistor device and using PDMS dry transfer to build a heterostructure composed of two-dimensional material stacks can effectively reduce the leakage current and improve the gate control effect. It solves the problems of reduced on-state current and short-channel effect existing after the size of the existing traditional silicon-based field effect transistor is reduced to nanodots and the problem of small dielectric constant of the two-dimensional dielectric layer h-BN.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor devices, and particularly to a metal chalcogenophosphate dielectric layer transistor device and a preparation method thereof. Background Art

[0002] Since the invention of integrated circuits in the late 1950s, silicon-based semiconductors have been dominating the development of microelectronics research and production. The field-effect transistor is the most fundamental and core element in the semiconductor electronics field. Whether it is a microelectronic device or a large-scale integrated circuit such as a high-frequency switch, an operational amplifier, or an artificial neural network, individual control of the transistor is required, which demands the use of a gate dielectric material with suitable performance to assemble top-gate or bottom-gate transistor devices.

[0003] The highly dense, uniform, and insulating SiO2 layer obtained by the self-oxidation of silicon can be used both as a hard mask to prevent silicon wafer contamination and as a good gate dielectric for silicon-based field-effect transistors (FETs). However, when the size of silicon-based field-effect transistors is reduced to less than 10 nm, traditional SiO2 dielectrics begin to face various challenges, the most significant of which are the reduction of on-state current and the occurrence of short-channel effects. Therefore, the semiconductor industry is now facing a crucial turning point - the "post-Moore" era. To ensure good control of the channel by the gate and thus the electrical performance of the device, SiO2 is no longer applicable. Researchers are seeking new solutions, studying new device structures or looking for alternatives to silicon materials to further maintain Moore's Law and promote the sustainable development of the industry.

[0004] The rise of two-dimensional materials provides a new solution to the existing problems. Two-dimensional materials are rich in variety, having a layered crystal structure with strong in-plane covalent bonds and atomic-level surface flatness, and no dangling bonds on the surface. Therefore, they can exhibit excellent electrical and optical properties even at the single-atom limit thickness. The two-dimensional materials are coupled together by weak van der Waals (vdW) forces between layers, which can maintain close contact between layers. By stacking different two-dimensional materials, a rich variety of heterostructures can be formed. Moreover, two-dimensional van der Waals layered materials such as semi-metallic graphene, N-type molybdenum disulfide, and P-type black phosphorus have high carrier mobility and ultra-thin thickness, which can better suppress the "short-channel effect".

[0005] Two-dimensional semiconductor materials may outperform silicon at the ultimate scaling limit, but field-effect transistors (FETs) with dimensions reduced to a few atomic layers also require a suitable insulator as the dielectric. Extensive research has shown that h-BN (hexagonal boron nitride) can form a clean van der Waals interface with two-dimensional semiconductors and has great potential when used as the substrate and gate insulator in FETs, being regarded as the most promising two-dimensional van der Waals layered dielectric. However, the current field-effect transistor structure using h-BN as the dielectric and MoS2 as the channel still needs improvement. The h-BN dielectric has a low gate control efficiency (it is experimentally obtained that the h-BN dielectric field-effect transistor has a large subthreshold swing SS≈167.5 mV / decade); and h-BN has a medium-sized bandgap (Eg≈6 eV) and a relatively small relative dielectric constant (≈5.0). Therefore, in order to achieve a large capacitance and good gate control ability, a thin layer needs to be used as the dielectric layer. In addition, the defects in h-BN will greatly increase the leakage current of the thin h-BN dielectric layer of the transistor through trap-assisted tunneling (TAT).

[0006] With the further reduction of physical dimensions, the reduction of on-state current, the short-channel effect, and the increase of gate leakage current generate a large amount of static power consumption, which becomes an urgent problem to be solved. Therefore, exploring a new two-dimensional dielectric material with excellent gate control performance and low leakage current that can replace SiO2 and h-BN will play a promoting role in the further development of the entire field. Summary of the Invention

[0007] To solve the above technical problems, the purpose of the present invention is to provide a metal chalcogenophosphate dielectric layer transistor device and its preparation method. A few-layer metal chalcogenophosphate material obtained by mechanical exfoliation is used as the dielectric layer of the field-effect transistor device, and a heterogeneous structure composed of two-dimensional material stacking is built by PDMS dry transfer, which can effectively reduce the leakage current, improve the gate control effect, and solve the problems of reduced on-state current and short-channel effect existing in the existing silicon-based field-effect transistors after the size is reduced to nanodots, as well as the leakage current problem of the two-dimensional dielectric layer h-BN.

[0008] To achieve the above purpose, the technical solution of the present invention is as follows.

[0009] A metal chalcogenophosphate dielectric layer transistor device includes:

[0010] A substrate;

[0011] An insulating encapsulation layer, a conductive channel, a dielectric layer, and a gate disposed on the substrate; and

[0012] Source and drain electrodes disposed on both sides of the conductive channel;

[0013] The dielectric layer is prepared into a multi-layer or few-layer metal chalcogenophosphate dielectric layer by mechanical exfoliation or chemical vapor deposition (CVD).

[0014] Furthermore, the material of the metal chalcogenophosphate dielectric layer is a metal chalcogenophosphate crystal material; the metal chalcogenophosphate crystal material is GeP2S6, GeP2Se6, GeP2Te6, SnP2S6, SnP2Se6 or SnP2Te6. The metal chalcogenophosphate layered crystal material is a stable two-dimensional semiconductor material with excellent electrical properties.

[0015] Furthermore, the thickness of the dielectric layer is 10 - 50 nm, preferably 20 nm, 30 nm or 50 nm.

[0016] Furthermore, the gate includes a graphene gate and a metal gate, which are sequentially disposed on the dielectric layer.

[0017] Furthermore, the substrate is a Si / SiO2 substrate. Among them, the Si / SiO2 substrate is prepared by attaching the SiO2 substrate to the Si substrate. The thickness of the substrate is 200 - 290 nm, preferably 285 nm.

[0018] Furthermore, the material of the insulating encapsulation layer is h-BN; of course, other insulating materials can also be selected.

[0019] Furthermore, the material of the conductive channel is MoS2 or graphene; of course, other conductive semiconductor materials can also be selected. The thickness of the conductive channel is 1 - 15 layers.

[0020] Furthermore, the source-drain electrodes include a metal source and a metal drain. The metal source and the metal drain are respectively disposed on both sides of the conductive channel and are in close connection with the conductive channel to form an ohmic contact. In the present invention, the materials of the metal source, the metal drain, and the metal gate can be any one or a combination of Ti, Cr, Au, and Pd; of course, other metal materials can also be selected.

[0021] The present invention also provides a preparation method for a metal chalcogenophosphate dielectric layer transistor device, including the following steps:

[0022] S1. Prepare a multi-layer or few-layer metal chalcogenophosphate dielectric layer by mechanical exfoliation or chemical vapor deposition.

[0023] S2. Prepare a few-layer insulating encapsulation layer, a few-layer conductive channel, and a few-layer graphene gate according to the method of S1.

[0024] S3. Using PDMS as the medium, under a microscope, the substrate, insulating encapsulation layer, conductive channel, dielectric layer, and graphene gate are stacked through a transfer stage using a PC dry transfer film to construct a heterostructure device, obtaining a device sample with a PC film attached.

[0025] S4. Using an electron beam lithography machine, thermal evaporation coating equipment, and lift-off process, source-drain electrodes and metal gates are fabricated on the device sample in S3, and the source-drain electrodes and metal gates are respectively connected to metal electrodes to obtain a transistor device with good metal-semiconductor contact.

[0026] Furthermore, the specific preparation process of the device sample with a PC film attached is as follows:

[0027] S301. Heat the sample stage to 40 - 60 °C. With the assistance of a microscope and a three-micrometer displacement platform, use a PC dry transfer film to attach it around the graphene. After heating to 70 - 90 °C, press down the PC film and cover it on the graphene. After cooling, the PC film lifts the graphene used as the gate, and repeat the operation 1 - 3 times.

[0028] S302. Using the graphene on the PC film as the target area, sequentially attach the metal chalcogenide phosphate crystal material used as the dielectric layer, the material used as the conductive channel, and the material used as the insulating encapsulation layer to the PC film to obtain a heterostructure device attached to the PC film.

[0029] S303. Heat to 190 - 210 °C and melt the PC film and the heterostructure device attached to the PC film flatly on the substrate to obtain a device sample with a PC film attached.

[0030] Advantages of the present invention:

[0031] 1. The metal chalcogenide phosphate dielectric layer transistor device of the present invention uses metal chalcogenide phosphates such as GeP2S6, GeP2Se6, GeP2Te6, SnP2S6, SnP2Se6, SnP2Te6, etc. as a new dielectric layer to achieve the regulation of the conductive channel. During the preparation process, few-layer metal chalcogenide phosphate materials obtained by mechanical exfoliation are used as the dielectric layer of the field-effect transistor device, and PDMS dry transfer is used to build a heterostructure composed of two-dimensional material stacking, which can effectively reduce the leakage current, improve the gate control effect, and solve the problems of reduced on-state current and short-channel effect existing after the size of the existing silicon-based field-effect transistor is reduced to nanodots, as well as the leakage current problem of the two-dimensional dielectric layer h-BN.

[0032] 2. The present invention uses a metal chalcogenophosphate layered material with a high dielectric constant as the dielectric layer to construct a field-effect transistor, and the dielectric constant is as high as 23. The fabricated transistor device has good electrical properties, and can achieve atomic-level controllable precision. The subthreshold swing SS value (69.4 mV·dec -1 ) of the device is close to the theoretical limit value, and it has excellent properties such as a high on / off ratio (10 7 ), low leakage current (10 -13 order of magnitude), low threshold voltage, small hysteresis of the transfer characteristic curve, and small threshold voltage shift. Thus, while achieving a rapid switching state conversion, it reduces logic errors, lowers static power consumption, and increases the stability and reliability of the device.

[0033] 3. Each part of the field-effect transistor of the present invention is constructed using two-dimensional materials. Taking advantage of the flat surface and absence of dangling bonds of two-dimensional materials, the tight contact between them encapsulates the heterojunction in a relatively enclosed environment, reducing the instability caused by interface defects. In addition, the atomic-level thickness and quantum confinement effect of two-dimensional materials themselves can effectively improve the device integration level, suppress the problem of short-channel effect, and provide the possibility for further realizing large-scale integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. is a schematic structural diagram of a metal chalcogenophosphate dielectric layer transistor device. In the figure, 1. Si substrate; 2. SiO2 substrate; 3. Insulating encapsulation layer; 4. Conductive channel; 5. Metal chalcogenophosphate dielectric layer; 6. Graphene gate; 7. Metal source; 8. Metal drain; 9. Metal gate.

[0035] Figure 2 FIG. is the output characteristic curve of the SnP2S6 field-effect transistor device.

[0036] Figure 3 FIG. is the transfer characteristic curve of the SnP2S6 field-effect transistor device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0038] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0039] Unless otherwise specified, the experimental methods described in the following embodiments are all conventional methods; the reagents and materials, unless otherwise specified, can all be purchased on the market.

[0040] Example 1

[0041] Please refer to Figure 1 , a metal chalcogenophosphate dielectric layer transistor device, including an Si substrate 1, an SiO2 substrate 2, an insulating encapsulation layer 3, a conductive channel 4, a metal chalcogenophosphate dielectric layer 5, a graphene gate 6, a metal source 7, a metal drain 8, and a metal gate 9.

[0042] The SiO2 substrate 2 is attached to the Si substrate 1 to form an Si / SiO2 substrate; the insulating encapsulation layer 3, the conductive channel 4, the metal chalcogenophosphate dielectric layer 5, the graphene gate 6, and the metal gate 9 are vertically distributed in sequence from bottom to top on the Si / SiO2 substrate; the metal source 7 and the metal drain 8 are distributed on both sides of the conductive channel 4 and are tightly connected to the conductive channel 4 to form an ohmic contact.

[0043] In this embodiment, the thickness of the Si / SiO2 substrate is 285 nm; the material of the insulating encapsulation layer 3 is selected as h-BN; the material of the conductive channel is selected as MoS2, and the thickness is 1 - 15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material SnP2S6, with a thickness of about 50 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is selected as graphene, with a thickness of 1 - 15 layers; the materials of the metal source 7, the metal drain 8, and the metal gate 9 are selected as Ti and Au.

[0044] A preparation method of a MoS2 channel field effect transistor device based on an SnP2S6 dielectric layer includes the following steps:

[0045] S1. Preparation of the transistor channel material and the metal chalcogenophosphate dielectric layer

[0046] Use the mechanical exfoliation method to obtain few-layer MoS2 channel materials and metal chalcogenophosphate SnP2S6 samples, then find samples with appropriate size and thickness under the assistance of a microscope, and make position marks.

[0047] S2. Preparation of the bottom insulating encapsulation layer h-BN and the graphene electrode

[0048] Select Si / SiO2 as the support substrate, use the mechanical exfoliation method to obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals; then find samples with appropriate size and thickness under the assistance of a microscope and make position marks.

[0049] S3. Preparation of the PC dry transfer film

[0050] First, prepare a PC particle / chloroform solution in a ratio of 1:12 and let it stand until completely dissolved. Then, pipette an appropriate amount of the solution and evenly drip it between two cleaned glass slides. Quickly slide the upper glass slide to obtain a PC film with a certain thickness. Use a blade to cut a PC film piece approximately 3 mm × 3 mm in size and pick it up with a transparent tape with a hole in the center. Using polydimethylsiloxane (PDMS) as a transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flat-side up on the PDMS substrate at one end of the transparent glass slide. Finally, obtain a PC dry transfer film.

[0051] S4. Dry transfer of the transistor heterostructure

[0052] First, heat the sample stage to 50 °C. With the assistance of a microscope and a three-micrometer displacement platform, slowly and evenly attach one corner of the PC dry transfer film around the target graphene on the SiO2 substrate. Heat to 80 °C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling, and the PC film will lift the graphene thin layer serving as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, successively lift the SnP2S6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h-BN used as the insulating bottom encapsulation layer onto the PC film. Heat up to 200 °C and evenly melt the PC film and the adhered heterostructure onto the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0053] S5. Preparation of metal lead electrodes

[0054] First, immerse the sample in chloroform, wash it with deionized water, take it out, and blow it dry with nitrogen to remove the PC film. After spin-coating on the silicon wafer for fabricating the device, expose and etch the geometric pattern structure of the electrode, and develop in the developer to obtain a lead electrode pattern of 100 × 100 μm. Then, use a thermal evaporation coating equipment to deposit and prepare a metal film of Ti(5 nm) / Au(50 nm) at a rate of . Subsequently, immerse the sample in an N-methylpyrrolidone solution for lift-off to obtain a patterned metal lead electrode, completing the fabrication of the device.

[0055] Example 2

[0056] A metal chalcogenophosphate dielectric layer transistor device, which is basically the same as the transistor device in Embodiment 1, except that the thickness of the Si / SiO2 substrate is 290 nm; the material of the insulating encapsulation layer 3 is h-BN; the material of the conductive channel is MoS2, and the thickness is 1-15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material GeP2S6, with a thickness of about 30 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is graphene, and the thickness is 1-15 layers; the materials of the metal source 7, metal drain 8 and metal gate 9 are Ti and Au.

[0057] A preparation method of a MoS2 channel field effect transistor device based on a GeP2S6 dielectric layer includes the following steps:

[0058] S1. Preparation of transistor channel material and metal chalcogenophosphate dielectric layer

[0059] Obtain few-layer MoS2 channel material and metal chalcogenophosphate GeP2S6 samples by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0060] S2. Preparation of bottom insulating encapsulation layer h-BN and graphene electrode

[0061] Select Si / SiO2 as the supporting substrate, obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0062] S3. Preparation of PC dry transfer film

[0063] First, prepare a PC particle / chloroform solution according to a ratio of 1:12, and let it stand until completely dissolved; then suck an appropriate amount of the solution and evenly drop it between two cleaned cover glasses, and quickly scrape the upper cover glass to obtain a PC film with a certain thickness; use a blade to cut a PC film with a size of about 3 mm×3 mm, and pick it up with a transparent tape with a hole in the center. Use polydimethylsiloxane (PDMS) as the transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flatly on the PDMS substrate at one end of the transparent glass sheet, and finally obtain a PC dry transfer film.

[0064] S4. Dry transfer of transistor heterostructure

[0065] First, heat the sample stage to 50 °C. With the assistance of a microscope and a three-dimensional displacement platform, slowly and evenly attach one corner of the PC dry transfer film to the periphery of the target graphene on the SiO2 substrate. Heat it to 80 °C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling, and the PC film will lift the graphene thin layer serving as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, lift the GeP2S6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h-BN used as the insulating bottom encapsulation layer onto the PC film in sequence. Heat to 200 °C and melt the PC film and the adhered heterostructure flatly onto the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0066] S5. Preparation of metal lead electrodes

[0067] First, soak the sample in chloroform, take it out after washing with deionized water, and blow it dry with nitrogen to remove the PC film. After spin-coating on the silicon wafer for fabricating the device, expose and engrave the geometric pattern structure of the electrode, and develop in the developer to obtain a lead electrode pattern of 100×100 μm. Then use a thermal evaporation coating equipment to deposit a metal film of Ti(5 nm) / Au(50 nm) at a rate. Subsequently, immerse the sample in an N-methylpyrrolidone solution for lift-off to obtain a patterned metal lead electrode, and complete the fabrication of the device.

[0068] Example 3

[0069] A metal chalcogenophosphate dielectric layer transistor device is basically the same as the transistor device in Example 1, except that the thickness of the Si / SiO2 substrate is 260 nm; the material of the insulating encapsulation layer 3 is selected as h-BN; the material of the conductive channel is selected as MoS2 and its thickness is 1 - 15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material SnP2Se6, with a thickness of about 40 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is selected as graphene, with a thickness of 1 - 15 layers; the materials of the metal source electrode 7, the metal drain electrode 8, and the metal gate 9 are selected as Ti and Au.

[0070] A preparation method for a MoS2 channel field-effect transistor device based on an SnP2Se6 dielectric layer includes the following steps:

[0071] S1. Preparation of the transistor channel material and the metal chalcogenophosphate dielectric layer

[0072] Obtain few-layer MoS2 channel material and metal chalcogenophosphate SnP2Se6 samples by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0073] S2. Preparation of Bottom Insulating Encapsulation Layer h-BN and Graphene Electrodes

[0074] Select Si / SiO2 as the supporting substrate. Use the mechanical exfoliation method to obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals. Under the assistance of a microscope, find samples with appropriate size and thickness and mark their positions.

[0075] S3. Preparation of PC Dry Transfer Film

[0076] First, prepare a PC particle / chloroform solution in a ratio of 1:12 and let it stand until completely dissolved. Then, suck an appropriate amount of the solution and evenly drip it between two cleaned carrier slides. Quickly scrape the upper carrier slide to obtain a PC film with a certain thickness. Use a blade to cut a PC film with a size of about 3 mm × 3 mm and pick it up with a transparent tape with a hole in the center. Use polydimethylsiloxane (PDMS) as the transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flat-side up on the PDMS substrate at one end of the transparent glass slide. Finally, obtain the PC dry transfer film.

[0077] S4. Dry Transfer of Transistor Heterostructure

[0078] First, heat the sample stage to 50 °C. Under the assistance of a microscope and a three-micro displacement platform, slowly and evenly attach one corner of the PC dry transfer film to the periphery of the target graphene on the SiO2 substrate. Heat to 80 °C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling, and the PC film will lift the graphene thin layer used as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, lift the SnP2Se6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h-BN used as the insulating bottom encapsulation layer onto the PC film in sequence. Heat to 200 °C and melt the PC film and the adhered heterostructure flatly on the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0079] S5. Preparation of Metal Lead-Out Electrodes

[0080] First, soak the sample in chloroform, wash it with deionized water, take it out and dry it with nitrogen to remove the PC film. Spin-coat the silicon wafer on which the device is made, expose and engrave the geometric graphic structure of the electrode, and develop it in the developer to obtain a lead-out electrode pattern of 100 × 100 um. Then use a thermal evaporation coating equipment to deposit a metal film of Ti(5 nm) / Au(50 nm) at a rate. Subsequently, immerse the sample in an N-methylpyrrolidone solution for lift-off to obtain a patterned metal lead-out electrode, completing the preparation of the device.

[0081] Example 4

[0082] A metal chalcogenophosphate dielectric layer transistor device, which is basically the same as the transistor device in Embodiment 1, except that the thickness of the Si / SiO2 substrate is 230 nm; the material of the insulating encapsulation layer 3 is selected as h-BN; the material of the conductive channel is selected as MoS2, and the thickness is 1 - 15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material SnP2Te6, with a thickness of about 20 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is selected as graphene, and the thickness is 1 - 15 layers; the materials of the metal source 7, metal drain 8 and metal gate 9 are selected as Ti and Au.

[0083] A preparation method of a MoS2 channel field effect transistor device based on a SnP2Te6 dielectric layer, comprising the following steps:

[0084] S1. Preparation of the transistor channel material and the metal chalcogenophosphate dielectric layer

[0085] Use the mechanical exfoliation method to obtain few-layer MoS2 channel material and metal chalcogenophosphate SnP2Te6 samples. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0086] S2. Preparation of the bottom insulating encapsulation layer h-BN and the graphene electrode

[0087] Select Si / SiO2 as the support substrate. Use the mechanical exfoliation method to obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0088] S3. Preparation of the PC dry transfer film

[0089] First, prepare a PC particle / chloroform solution in a ratio of 1:10, and let it stand until completely dissolved; then suck an appropriate amount of the solution and evenly drip it between two cleaned cover glasses, and quickly scrape the upper cover glass to obtain a PC film with a certain thickness; use a blade to cut a PC film with a size of about 3 mm × 3 mm, and pick it up with a transparent tape with a hole in the center. Use polydimethylsiloxane (PDMS) as the transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flat on the PDMS substrate at one end of the transparent glass sheet, and finally obtain the PC dry transfer film.

[0090] S4. Dry transfer of the transistor heterostructure

[0091] First, heat the sample stage to 40 °C. With the assistance of a microscope and a three - dimensional displacement platform, slowly and evenly attach one corner of the PC dry - transfer film around the target graphene on the SiO2 substrate. Heat it to 90 °C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling, and the PC film will lift the graphene thin layer serving as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, lift the SnP2Te6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h - BN used as the insulating bottom encapsulation layer onto the PC film in sequence. Heat up to 210 °C and melt the PC film and the adhered heterostructure flatly on the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0092] S5. Preparation of metal lead - out electrodes

[0093] First, immerse the sample in chloroform, wash it with deionized water, take it out and dry it with nitrogen to remove the PC film. After spin - coating on the silicon wafer for making the device, expose and engrave the geometric pattern structure of the electrode, and develop in the developer to obtain a lead - out electrode pattern of 100×100 um. Then use a thermal evaporation coating equipment to deposit a metal film of Ti(5 nm) / Au(50 nm) at a certain rate; subsequently, immerse the sample in an N - methylpyrrolidone solution for lift - off to obtain a patterned metal lead - out electrode, and complete the preparation of the device.

[0094] Example 5

[0095] A metal chalcogenophosphate dielectric layer transistor device is basically the same as the transistor device in Example 1, except that the thickness of the Si / SiO2 substrate is 200 nm; the material of the insulating encapsulation layer 3 is selected as h - BN; the material of the conductive channel is selected as MoS2, and the thickness is 1 - 15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material GeP2Se6, with a thickness of about 10 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is selected as graphene, and the thickness is 1 - 15 layers; the materials of the metal source electrode 7, the metal drain electrode 8 and the metal gate 9 are selected as Ti and Au.

[0096] A preparation method of a MoS2 channel field - effect transistor device based on a GeP2Se6 dielectric layer includes the following steps:

[0097] S1. Preparation of the transistor channel material and the metal chalcogenophosphate dielectric layer

[0098] Obtain few - layer MoS2 channel material and metal chalcogenophosphate GeP2Se6 samples by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0099] S2. Preparation of Bottom Insulating Encapsulation Layer h-BN and Graphene Electrodes

[0100] Select Si / SiO2 as the supporting substrate, and use the mechanical exfoliation method to obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0101] S3. Preparation of PC Dry Transfer Film

[0102] First, prepare a PC particle / chloroform solution in a ratio of 1:11, and let it stand until completely dissolved. Then, suck an appropriate amount of the solution and evenly drip it between two cleaned carrier slides. Quickly scrape the upper carrier slide to obtain a PC film with a certain thickness. Use a blade to cut a PC film with a size of about 3mm×3mm, and pick it up with a transparent tape with a hole in the center. Use polydimethylsiloxane (PDMS) as the transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flat-side up on the PDMS substrate at one end of the transparent glass slide. Finally, obtain the PC dry transfer film.

[0103] S4. Dry Transfer of Transistor Heterostructure

[0104] First, heat the sample stage to 60°C. Under the assistance of a microscope and a three-micrometer displacement platform, slowly and evenly attach one corner of the PC dry transfer film around the target graphene on the SiO2 substrate. Heat to 70°C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling, and the PC film will lift the graphene thin layer used as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, lift the GeP2Se6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h-BN used as the insulating bottom encapsulation layer onto the PC film in sequence. Heat to 190°C, and melt the PC film and the adhered heterostructure flatly on the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0105] S5. Preparation of Metal Lead-Out Electrodes

[0106] First, soak the sample in chloroform, wash it with deionized water, take it out, and dry it with nitrogen to remove the PC film. After spin-coating on the silicon wafer for making the device, expose and engrave the geometric pattern structure of the electrode, and develop it in the developer to obtain a lead-out electrode pattern of 100×100um. Then use a thermal evaporation coating equipment to deposit a metal film of Ti(5nm) / Au(50nm) at a rate of . Subsequently, immerse the sample in an N-methylpyrrolidone solution for lift-off to obtain a patterned metal lead-out electrode, and complete the preparation of the device.

[0107] Example 6

[0108] A metal chalcogenophosphate dielectric layer transistor device, which is basically the same as the transistor device in Example 1, except that the thickness of the Si / SiO2 substrate is 280 nm; the material of the insulating encapsulation layer 3 is selected as h-BN; the material of the conductive channel is selected as MoS2, and the thickness is 1 to 15 layers; the material of the metal chalcogenophosphate dielectric layer 5 is the metal chalcogenophosphate layered crystal material GeP2Te6, with a thickness of about 37 nm, obtained by mechanical exfoliation; the material of the graphene gate 6 is selected as graphene, and the thickness is 1 to 15 layers; the materials of the metal source 7, metal drain 8 and metal gate 9 are selected as Ti and Au.

[0109] A preparation method of a MoS2 channel field effect transistor device based on a GeP2Te6 dielectric layer includes the following steps:

[0110] S1. Preparation of the transistor channel material and the metal chalcogenophosphate dielectric layer

[0111] Obtain few-layer MoS2 channel material and metal chalcogenophosphate GeP2Te6 samples by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0112] S2. Preparation of the bottom insulating encapsulation layer h-BN and the graphene electrode

[0113] Select Si / SiO2 as the support substrate. Obtain few-layer h-BN samples from h-BN crystals and few-layer graphene samples from graphite layered crystals by mechanical exfoliation method. Under the assistance of a microscope, find samples with appropriate size and thickness, and make position marks.

[0114] S3. Preparation of the PC dry transfer film

[0115] First, prepare a PC particle / chloroform solution according to a ratio of 1:13, and let it stand until completely dissolved; then suck an appropriate amount of the solution and evenly drip it between two cleaned carrier slides, and quickly scrape the upper carrier slide to obtain a PC film with a certain thickness; use a blade to cut a PC film with a size of about 3 mm × 3 mm, and pick it up with a transparent tape with a hole in the center. Use polydimethylsiloxane (PDMS) as the transfer medium, align the hole of the PC film on the tape with the PDMS, and place it flat on the PDMS substrate at one end of the transparent glass sheet, and finally obtain the PC dry transfer film.

[0116] S4. Dry transfer of the transistor heterostructure

[0117] First, heat the sample stage to 55°C. With the assistance of a microscope and a three-dimensional displacement platform, slowly and evenly attach one corner of the PC dry transfer film to the periphery of the target graphene on the SiO2 substrate. Heat it to 85°C, slowly press down the PC film. After completely covering the target sample, slowly lift the glass slide while cooling. The PC film will lift the graphene thin layer serving as the top gate. Then repeat the operation twice. Using the graphene on the PC film as the target area, lift the GeP2Te6 sample used as the dielectric layer, the MoS2 material used as the channel, and the h-BN used as the insulating bottom encapsulation layer onto the PC film in sequence. Heat up to 200°C and evenly fuse the PC film and the adhered heterostructure onto the Si / SiO2 substrate to obtain a device sample with the PC film attached.

[0118] S5. Preparation of Metal Lead-Out Electrodes

[0119] First, soak the sample in chloroform, wash it with deionized water, take it out, and dry it with nitrogen to remove the PC film. After spin-coating on the silicon wafer for fabricating the device, expose and engrave the geometric pattern structure of the electrodes, and develop in the developer to obtain a lead-out electrode pattern of 100×100 μm. Then use a thermal evaporation coating equipment to deposit a metal film of Ti(5 nm) / Au(50 nm) at a rate; subsequently, immerse the sample in an N-methylpyrrolidone solution for lift-off to obtain a patterned metal lead-out electrode, thus completing the fabrication of the device.

[0120] The performances of the transistor devices prepared in Examples 1 to 6 are basically the same. Therefore, only the MoS2 channel field-effect transistor device with the SnP2S6 dielectric layer prepared in Example 1 is used for detection.

[0121] 1. Output Characteristic Curve (I ds -V ds ) Test

[0122] Test the output characteristic curve (I ds -V ds ) of the MoS2 channel field-effect transistor device with the SnP2S6 dielectric layer in Example 1. The results under different gate voltages (-3 V to 3 V) are as Figure 2 shown.

[0123] As can be seen from Figure 2 , the I ds -V ds curve is linear, indicating that the MoS2 channel field-effect transistor device with the SnP2S6 dielectric layer in Example 1 exhibits good ohmic contact.

[0124] 2. Transfer Characteristic Curve (I ds -V tg ) Test

[0125] The transfer characteristic curve (I ds -V tg ) of the MoS2 channel field-effect transistor device with the SnP2S6 dielectric layer of Example 1 was tested, and the gate voltage was scanned from -3V to 1V and then returned. The results are as shown in Figure 3 .

[0126] It can be seen from Figure 3 that the subthreshold swing SS value of the MoS2 channel field-effect transistor device with the SnP2S6 dielectric layer of Example 1 was calculated to be 69.4 mV·dec -1 , close to the theoretical limit value, and has excellent performance with a high on-off ratio (10 7 ) and a low leakage current (on the order of 10 -13 ). The threshold voltage of the device is low (≈2.3V), the hysteresis of the transfer characteristic curve and the threshold voltage offset (ΔVth = 0.08V) are small, and the stability is high. This shows that the metal chalcogenophosphate dielectric layer has an obvious effect on improving the gate control ability of the transistor device and reducing the leakage current.

[0127] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A metal chalcogenophosphate dielectric layer transistor device, characterized in that Including: A substrate; An insulating encapsulation layer, a conductive channel, a dielectric layer, and a gate disposed on the substrate; And Source-drain electrodes disposed on both sides of the conductive channel; The dielectric layer is a few-layer metal chalcogenophosphate dielectric layer prepared by a mechanical exfoliation method or a chemical vapor deposition method; The material of the metal chalcogenophosphate dielectric layer is a metal chalcogenophosphate crystal material; the metal chalcogenophosphate crystal material is any one of GeP2S6, GeP2Se6, GeP2Te6, SnP2S6, SnP2Se6, and SnP2Te6.

2. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, wherein The thickness of the dielectric layer is 10 - 50 nm.

3. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, wherein The gate includes a graphene gate and a metal gate, and they are sequentially disposed on the dielectric layer.

4. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, wherein The substrate is a Si / SiO2 substrate.

5. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, characterized in that, The material of the insulating encapsulation layer is h-BN.

6. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, wherein The material of the conductive channel is MoS2 or graphene.

7. The metal chalcogenophosphate dielectric layer transistor device according to claim 1, wherein The source-drain electrodes include a metal source electrode and a metal drain electrode. The metal source electrode and the metal drain electrode are respectively disposed on both sides of the conductive channel and are in close connection with the conductive channel to form an ohmic contact.

8. A method for preparing a metal chalcogenophosphate dielectric layer transistor device according to claim 1, characterized in that, Including the following steps: S1. Prepare a few-layer metal chalcogenophosphate dielectric layer by a mechanical exfoliation method or a chemical vapor deposition method; S2. Prepare a few-layer h-BN insulating encapsulation layer, a few-layer MoS2 or graphene conductive channel, and a few-layer graphene gate according to the method of S1; S3. Using PDMS as a medium, stack the substrate, the insulating encapsulation layer, the conductive channel, the dielectric layer, and the graphene gate by using a PC dry transfer film through a transfer stage under a microscope, build a heterostructure device sample with a PC film attached, soak it in chloroform to remove the attached PC film, and obtain a device sample; S4. Use an electron beam lithography machine, a thermal evaporation coating device, and a lift-off process to prepare source-drain metal electrodes and a metal gate on the device sample of S3, and connect the source-drain electrodes and the metal gate to the conductive channel and the graphene gate respectively to obtain a transistor device with good metal-semiconductor contact.

9. The method for preparing a metal chalcogenophosphate dielectric layer transistor device according to claim 8, wherein, The specific preparation process of the device sample with a PC film attached is as follows: S301. Heat the sample stage to 40 - 60 °C. With the assistance of a microscope and a three-micro displacement platform, attach the PC dry transfer film around the graphene. After heating to 70 - 90 °C, press down the PC film and slowly cover it on the graphene. After cooling, the PC film will lift the graphene used as the gate; repeat the operation 1 - 3 times; S302. Using the graphene on the PC film as the target area, sequentially attach the metal chalcogenophosphate crystal material used as the dielectric layer, the material used as the conductive channel, and the material used as the insulating encapsulation layer to the target area on the PC film to obtain a heterostructure device attached to the PC film; S303. Heat to 190 - 210 °C and melt the PC film and the heterostructure device attached to the PC film flatly on the substrate to obtain a device sample with a PC film attached.

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