Control circuit, corresponding electronic converter device and method of operating the same

Abstract

The present disclosure relates to a control circuit, a corresponding electronic converter device, and an operating method thereof. A control circuit for controlling a switching stage of an electronic converter includes a first terminal configured to provide a drive signal and a second terminal configured to receive a first feedback signal. A third terminal receives a second feedback signal, and a driver circuit provides the drive signal based on a PWM signal. A PWM signal generator circuit generates a PWM signal based on the first feedback signal, a reference threshold, and either a second feedback signal or a slope compensation signal. The control circuit is configured to sense an input signal, provide a first compensation parameter, and provide the first compensation signal based on a power of the input sense signal.

Description

Technical Field

[0001] The present description relates to electronic converter circuits having various circuit topologies, such as a flyback topology or a buck-boost topology.

[0002] One or more embodiments may be suitable for regulating the output voltage of a converter circuit over a wide range of values. This may be the case, for example, in a set of applications that envisage a substantial variability in the value of the electrical load to which the power is provided. Background Art

[0003] Power supply circuits such as AC / DC or DC / DC switching mode power supplies are well known in the art. There are many types of electronic converters, which are mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. In contrast, isolated converters are, for example, "flyback," "forward," "half-bridge," and "full-bridge" type converters. These types of converters are well known to those skilled in the art, as demonstrated, for example, in application note AN 513 / 0393 "Topologies for Switched Mode Power Supplies" (L. Wuidart, 1999, ST Microelectronics).

[0004] Different DC-DC converter topologies can be selected depending on the specific application area. Some application areas, such as LED control devices and smart charging (for example, in the USB-PD protocol), can experience wide variations in output voltage regulation due to the inherent variability of the electrical load.

[0005] Flyback and buck-boost types are suitable for applications where they absorb energy from the input voltage and transfer it to the load, for example via a transformer.

[0006] Likewise, depending on the application, in order to provide sufficient efficiency and performance levels, the converter circuit can operate in different modes (e.g., continuous conduction mode (CCM), discontinuous conduction mode (DCM), asynchronous mode, synchronous mode, etc.) and operate reliably under different conditions. In this case, the design of the DC-DC converter is quite complex, especially in terms of power quality and maximum power transfer quality factor.

[0007] Under possible overload conditions, the flyback topology can show the following variations: maximum input power, as it depends on the input voltage amplitude, waveform shape, and output voltage;

[0008] Input current distortion when a variable input voltage is applied.

[0009] For example, various applications may involve safety arrangements such as galvanic isolation and input power limiting. The latter may be specifically designed to prevent excessive overheating, address the risk of failure, and ultimately, the generation of smoke and gas emissions in the event of combustion.

[0010] Existing solutions for limiting the maximum input power in a flyback converter may exhibit one or more of the following disadvantages:

[0011] Limiting input power takes into account the waveform shape of the input voltage and peak current, the latter of which varies with overload;

[0012] The peak current waveform is difficult to compensate because it varies with overload,

[0013] lack of non-empirical equilibrium methods;

[0014] The solution is valid only for one unique configuration of input waveform shape and output with predictable duty cycle;

[0015] Different power limits depending on input voltage shape or output voltage variation. Summary of the Invention

[0016] One or more embodiments contribute to overcoming the above-mentioned disadvantages.

[0017] According to one or more embodiments, technical benefits may be realized by a control circuit having the features set forth herein.

[0018] A control circuit comprising processing circuitry configured to limit input power to a power converter, eg to control power absorption during an overload of an electronic converter, may be an example of such a circuit.

[0019] One or more embodiments may relate to a corresponding electronic converter device. A flyback or buck-boost electronic converter may be examples of such a device.

[0020] One or more embodiments may be directed to a method of achieving high power factor, HPF, and low input current distortion (THDi) in an electronic converter.

[0021] One or more embodiments may make the power absorption from the line constant or uniform under both normal and overload conditions, thereby counteracting stress on the board.

[0022] One or more embodiments may facilitate reconciling opposing performance requirements, facilitating meeting high standards regarding power quality and regarding maximum power delivery.

[0023] One or more embodiments facilitate providing a constant maximum power limit level that is independent of other parameters, such as input / output voltage magnitude or shape and transformer design.

[0024] One or more embodiments may provide adequate power quality close to optimal levels during maximum power limiting.

[0025] One or more embodiments may facilitate obtaining an input power limit that is independent of input voltage amplitude, input voltage shape, and operating duty cycle.

[0026] One or more embodiments may be applied to HPF flyback or buck-boost topologies and different control schemes thereof.

[0027] One or more embodiments may use dedicated circuit blocks to detect the waveform of the input voltage and / or adapt the output level according to the detected source type.

[0028] One or more embodiments may be used in conjunction with a microcontroller to facilitate real-time integral calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0030] Figure 1 is an exemplary circuit diagram of an electronic converter;

[0031] Figure 2 and Figure 3 yes Figure 1 An exemplary diagram of a control circuit block of an electronic converter;

[0032] Figure 4 is configured to limit Figure 1 An exemplary circuit diagram of an electronic converter input power level;

[0033] Figures 5 to 8 is an exemplary diagram of a control circuit according to the present disclosure; and

[0034] Figures 9 to 12 yes Figures 5 to 8 An exemplary diagram of a possible implementation of a circuit block. DETAILED DESCRIPTION

[0035] In the following description, one or more specific details are provided to provide a deeper understanding of the examples of the embodiments of this specification. The embodiments may be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or illustrated in detail so as not to obscure certain aspects of the embodiments.

[0036] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification are not necessarily referring to one and the same embodiment.

[0037] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] In all the drawings attached hereto, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding descriptions will not be repeated for the sake of brevity.

[0039] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0040] For simplicity, the same names may be used throughout this document to designate certain circuit nodes and the signals that appear at those nodes.

[0041] Figure 1 An electronic converter 10 having a conventional flyback topology is shown, comprising:

[0042] Input nodes 100a, 100b are configured to be coupled to a (primary) source 100 of alternating current (AC) power to receive an input signal V therefrom. IN ;

[0043] Output nodes 102a, 102b are configured to be coupled to a load Z L To provide it with an output signal V OUT ,

[0044] The rectifier bridge 12 is coupled to the input nodes 100a, 100b and is configured to IN performing rectification to provide a rectified signal as an output;

[0045] Transformer L P 、L S , whose primary side is coupled to at least one input node 100a and whose secondary side is coupled to output nodes 102a, 102b, the transformer L P 、L S On the primary side, there is a first number of turns and a first inductance L P and has a second number of turns and a second inductance L at the secondary side S , where the ratio of the first number of turns to the second number of turns is equal to n; transformer L S 、L PThe magnetic core stores energy from the primary side and releases it to the secondary side;

[0046] A controlled switch 14, such as a transistor fabricated in any known semiconductor technology, is coupled to the transformer L. S 、L P The switch 14 is configured to switch between a first state and a second state based on a control signal GD applied to a control terminal thereof, and the switch 14 is configured to activate energy from the main source 100 in the transformer L when in the first (eg, ON) state. P 、L S The primary inductance L P The switch has a complete cycle T, in which the energy storage phase lasts for a time interval T. ON , referring to the corresponding “ON” state of the switch 14, for example, T=T ON +T OFF ;

[0047] Rectifier D OUT , such as a diode or an active structure (eg, a synchronous rectifier), is coupled to the second inductor L S and output nodes 102a, 102b, rectifier D OUT is configured to become active during the release of energy to the secondary side, while the transformer L P 、L S The energy storage stage of the primary side T ON suppressed;

[0048] Output capacitor C OUT , is coupled to the rectifier D OUT and output nodes 102a, 102b, capacitor C OUT is configured to filter the switching activity of the switch 14 to L Provides continuous voltage (or current) V OUT ;

[0049] The error amplifier 18 is coupled to the rectifier D OUT and output node V OUT The error amplifier 18 is configured to measure an output value (e.g., voltage or current) and compare it with a reference value VREF to provide an error signal FB to the controller circuit 20; the error amplifier 18 may be coupled to a compensation network 19, such as an RC network, which is configured to compensate for the loop response to improve stability and bandwidth;

[0050] The control circuit 20 includes a plurality of input / output terminals or nodes HV, ZCD, FB, CS, and GD.

[0051] In particular, Figure 1 The control circuit 20 shown includes:

[0052] The first input node HV is coupled to the rectifier bridge 12 to receive the indicative input signal V IN For example, the first signal HV may be a rectified sinusoidal waveform, wherein the peak value of such a waveform is the RMS input voltage V RMS function, that is, Vpk=√2*VRMS;

[0053] The second input node ZCD is coupled to the transformer L S 、L P and is configured to receive a second signal ZCD to perform an operation sequence as described below;

[0054] The third input node CS′ is configured to receive a third signal CS, which indicates a switching activity of the converter circuit 10 , for example, indicating the current flowing through the transformer L P 、L S The first inductor L on the primary side P Current;

[0055] A feedback node FB is coupled to the error amplifier 18 on the secondary side (eg via an optocoupler OC, in a manner known per se) to receive therefrom an error / feedback signal FB,

[0056] The output node GD is configured to control the switch 14 via one or more control signals GD applied thereto.

[0057] The buck-boost or flyback electronic converter 10 can operate in a discontinuous mode known as “boundary mode.” In this operating mode, the converter 10 can provide a power factor close to unity when provided with an input signal (eg, a sine wave).

[0058] like Figure 1 As shown, the converter 10 may include an auxiliary winding L AUX , the auxiliary winding L AUX With transformer L S 、L P coupled and configured to detect the current flowing into the rectifier D OUT The occurrence of zero current in the control circuit 20 provides a second signal ZCD at the corresponding node of the control circuit 20. In the boundary mode, the control circuit 20 can use the second signal ZCD as a synchronization signal to drive the switch 14 to change state while sensing the current flowing into the rectifier D OUT The current L AUX Reset to zero.

[0059] like Figure 1 As shown, the shunt resistor R Sis coupled in series to the switch 14 and to the control circuit 20, the resistor R S is configured to read the current CS flowing in the switch 14 and provide a third signal to a corresponding node CS of the control circuit 20 .

[0060] Figure 1 The input power Pin of the circuit shown can be expressed as:

[0061]

[0062] in:

[0063] L P is the transformer L P 、L S The first inductor on the primary side

[0064] I PK By R S The peak switch current sensed,

[0065] fsw is the operating frequency, i.e., fsw = 1 / T(t),

[0066] Figure 1 The energy balance condition for the circuit shown can be expressed as:

[0067] V IN (t)·T_ON(t)=n·V OUT T_OFF(t)

[0068] in:

[0069] V IN (t) is the input voltage as a function of time,

[0070] T ON (t) is the duration of the on-state of the switch 14 as a function of time,

[0071] n is the transformer L P 、L S The turns ratio,

[0072] T OFF (t) is the off-state duration of the switch 14 as a function of time.

[0073] Taking into account the definition of inductance and the definition of duty cycle δ, the input power Pin can also be expressed as:

[0074]

[0075] in is the duty cycle as a function of time.

[0076] For simplicity, one or more embodiments are discussed below primarily with respect to a flyback circuit topology. It should be understood that this topology is purely exemplary and not limiting. One or more embodiments can be applied to any theoretically high power factor converter circuit. In particular, a buck-boost circuit topology may be suitable because it can be modeled as a flyback converter comprising a lossless transformer with a single turns ratio.

[0077] like Figure 1 The converter circuit shown is equipped with the control circuit 20 of the first configuration 20a or the second configuration 20b with a peak current I PK (t), peak current I PK (t) can be expressed as V IN Taking this into account, the input power can be expressed as:

[0078]

[0079] in:

[0080] Γ(t) is a general waveform function indicating the waveform type (e.g., sinusoidal, triangular, trapezoidal, or DC) of the input voltage / current evolution over time,

[0081] pedis "max" indicates the maximum value of the corresponding parameter.

[0082] Assume that the general waveform function Γ(t) is periodic and the waveform period is T IN , then the average input power It can be expressed as:

[0083]

[0084] As can be seen from the equation above, limiting the input power can be challenging because it is based on the evolution of the waveform function Γ(t) over time.

[0085] Figure 2 and Figure 3 is an exemplary diagram of a conventional configuration of the control circuit block 20, wherein:

[0086] Figure 2 is an exemplary diagram of a voltage control mode (VCM) configuration 20 a of the control circuit 20 , wherein the duration T of the energy storage period is determined based on the error signal FB from the error amplifier 18 . ON ,as well as

[0087] Figure 3 is an exemplary diagram of a peak current mode (PCM) configuration 20b of the control circuit 20, wherein the energy storage period T is determined ON is based on the shunt resistor RS The sensed current signal CS reaches a certain threshold value M′, for example, based on the error signal FB from the error amplifier 18 .

[0088] like Figure 2 As shown, the control circuit of the VCM configuration 20a includes:

[0089] The logic circuit block 22 is coupled to the second input node ZCD and is configured to receive the detection signal ZCD therefrom to provide a first signal F (eg, a square wave signal),

[0090] The ramp generator circuit block 23 is coupled to the logic circuit block 22 and is configured to provide a ramp signal H based on the first drive signal F (eg, a sawtooth wave signal obtained by integrating the first signal F).

[0091] a scaling circuit block 24, coupled to the feedback node FB to receive the error signal FB therefrom and configured to provide a threshold value M (e.g., the error signal FB multiplied by a scaling factor Km, i.e., added to itself a number of times equal to the scaling factor Km),

[0092] a comparator circuit block 26 having an inverting input node 260 a coupled to the scaling circuit 24 to receive the threshold value M therefrom, a non-inverting input node 260 b coupled to the ramp generator circuit block 23 to receive the ramp signal H therefrom, and an output node 260 c for providing an output signal based on the threshold value M and the received ramp signal R,

[0093] The memory circuit block 28, such as a flip-flop, is coupled to the logic circuit block 22 to receive the first signal F therefrom, and is coupled to the output node 260c of the comparator circuit block 26 to receive the output signal therefrom. The memory circuit block 28 is coupled to the output node GD and is configured to provide the control signal GD thereto.

[0094] like Figure 3 As shown, the control circuit with PCM configuration 20b is Figure 2 The differences in the VCM configuration 20a are:

[0095] The scaling circuit block 24 is also coupled to the input node HV and is configured to provide a threshold value M′ to the inverting input node 260 a of the comparator circuit 26 (eg, as a product of the error signal FB and the input signal HV scaled by the scaling factor Km);

[0096] Since the ramp signal H is replaced by the signal CS at the third input node CS, the ramp generator circuit block 23 does not exist; such a signal CS can be represented as R S *I PK (t);

[0097] The non-inverting input node 260b of the comparator circuit block 26 is coupled to the third input node CS to receive the current from the shunt resistor R S The sensed current signal CS.

[0098] Figure 4 is configured to limit the input power P IN FIG. 4 is an exemplary diagram of a conventional power limiting circuit block 40 that may be integrated into a control circuit 20 having both a VCM 20 a and a PCM 20 b configuration.

[0099] like Figure 4 As shown, the power limiting circuit 40 includes:

[0100] The input node 41 is configured to be coupled to the input voltage node HV of the control circuit 20,

[0101] Peak detector circuit block 42, having (eg, adjustable) gain Kff and hold time interval T HOLD , for example, T HOLD >>T IN , the peak detector is configured to detect a peak value P of the input voltage HV (eg, P=Kff*max(VIN)),

[0102] The divider circuit block 44 is configured to receive the detected peak value P and calculate its inverse value P -1 ,

[0103] The regulator circuit block 46 is configured to adjust the value of the detected peak value P in a manner known per se based on the calculated inverse P -1 The maximum (power) level is adjusted (eg, automatically).

[0104] For example, the output node 48 of the power limiting circuit block 40 is coupled to the inverting node 260 a of the VCM 20 a or PCM 20 b configuration for the control circuit 20 , where the power limiting is applied to the feedback signal FB in the first case 20 a and to the third signal CS in the second case 20 b ;

[0105] For example, output node 48 of power limiting circuit block 40 is coupled to error signal node FB of PCM arrangement 20 b for control circuit 20 , where power limiting is applied to feedback signal FB.

[0106] like Figure 4 The power limiting arrangement 40 shown may have some disadvantages, including:

[0107] When the controller 20 is in the PCM configuration 20b and the output node 48 of the power limiting circuit block 40 is coupled to the inverting node 260a of the amplifier comparator circuit block 26, the power limit may limit the switch current level I of the sensed current CS. PK (t), resulting in significant distortion of the input current, which causes the input current and input voltage V IN The assumption of sharing the same waveform Γ(t) is no longer valid;

[0108] The conventional compensation of the imposed limitation introduced (e.g. from the input voltage V IN The peak start) is empirical and its equilibrium is complex;

[0109] When the controller is in the VCM configuration 20a and the output node 48 of the power limiting circuit block 40 is coupled to the inverting node 260a of the amplifier 260 or to the feedback node FB, the loop response may be significantly slower than the time interval T IN ; As a result, although the peak current I PK The waveform of (t) remains the same as the input voltage V IN The waveform function Γ(t) has the same waveform as that of , but its power limit may change undesirably based on the input voltage waveform or output voltage changes.

[0110] like Figure 5 and Figure 6 One or more of the illustrated embodiments may overcome the aforementioned disadvantages.

[0111] For simplicity, one or more embodiments are discussed below mainly for the improved solution of the PCM control circuit configuration 20 b . It should be understood that one or more embodiments can be applied to the control circuit 20 a of the VCM configuration when necessary.

[0112] One or more embodiments may utilize power level limiting independent of input voltage shape (pr waveform), input voltage amplitude, and operating duty cycle. This may be based on the following observation: the maximum input power P INmax The factors involved in the expression can be redefined so that:

[0113] The input voltage HV can be expressed as the maximum input voltage V INmax (optionally, its power i) times the product of the shape factor Γ(t),

[0114] The threshold M' can be expressed as the product of the input voltage HV, the error signal FB and the scaling factor Km,

[0115] Peak current I PK (t) is expressed as the threshold M' and the current detection resistor R S The ratio.

[0116] Therefore, the peak current I PK (t) The expression becomes:

[0117]

[0118] From this expression, we can get I PKmax The expression can be used to convert the average maximum input power P INmax Redefine as:

[0119]

[0120] in

[0121] (V INmax )^i+1 is the input voltage V IN The maximum value of (optionally scaled by a customizable factor Kff) and raised to the (i+1)th power;

[0122] It is the square of the input waveform Γ(t) multiplied by the duty cycle δ(t) during the waveform period T IN The points on .

[0123] In such Figure 5 and Figure 6 In one or more of the embodiments shown, the control circuit 20 may be modified to implement a method for compensating for "variable" factors and for providing a maximum input power P INmax Provides a "constant" controllable value, as discussed below.

[0124] like Figure 5 As shown, the control circuit 20 in the PCM configuration 20b may include:

[0125] The first compensation stage 201 , 202 , 203 is coupled to the input node HV to receive the input signal HV therefrom. The first compensation stage 201 , 202 , 203 is configured to provide a first compensation signal α based on the input signal HV, for example, α=K ff ·(V INmax ) i+1 ;

[0126] The second compensation stage 204 , 205 , 206 , 207 is coupled to the input node HV to receive the input signal HV therefrom. The second compensation stage 204 , 205 , 206 , 207 is configured to provide a second compensation signal β based on the input signal HV, for example,

[0127] The third compensation stage 208, 209 is coupled to the first compensation stage 201, 202, 203 to receive the first compensation signal α therefrom and is coupled to the second compensation stage 204, 205, 206, 207 to receive the second compensation signal β therefrom, and is configured to provide a third compensation signal γ, which is the inverse of the product of the first compensation signal α and the second compensation signal β, e.g. The third compensation signal γ represents the upper limit of the error signal FB.

[0128] a fourth compensation stage 210 coupled to the memory circuit block 28 to receive the output signal GD therefrom and to apply a duty cycle modulation to the input signal, e.g., the third compensation signal γ, based on the output signal GD;

[0129] Regulator circuit block 211 (which can be used Figure 4 A regulator circuit block 46 ) is coupled to the error node FB, the scaling circuit block 24 and the third compensation stage 208 , 209 , the regulator circuit block 46 being configured to regulate the maximum (power) level, for example automatically, in a manner known per se (eg feedforward).

[0130] like Figure 5 and Figure 6 As shown, the scaling circuit block 24 can calculate the product of the input voltage HV multiplied by the scaling factor Km multiplied by the third compensation signal γ to generate a power threshold T. The power threshold T can be expressed as

[0131]

[0132] Where V FBmax is the maximum value of the feedback signal FB.

[0133] Thus, one or more embodiments provide a method of generating a limit value for the threshold T at the input node of the error amplifier 26 .

[0134] Figure 6 Shows about Figure 5 An alternative embodiment is shown in which the fourth compensation stage 210 may apply a duty cycle modulation to the power threshold T as an input signal instead of the third compensation signal γ.

[0135] like Figure 5 and Figure 6 As shown, the first compensation stages 201, 202, 203 may include:

[0136] Peak detector circuit blocks 201, 202 (which may correspond to Figure 4 The peak detector circuit block 42 has a circuit configured to provide a gain value Kff and a holding time interval T HOLDThe adjustable gain block 201 (eg, a programmable register or a voltage divider), such as T HOLD >>T IN The peak detector is configured to detect the peak value P of the input voltage HV (eg, P=Kff*max(V IN )),

[0137] The power calculator circuit block 203 is configured to boost the detected peak value to power (i+1).

[0138] Figure 9 FIG. 2 shows a circuit diagram of another possible embodiment of the first compensation stage 201, 202, 203. Figure 9 As shown, the first compensation stages 201, 202, 203 may include:

[0139] Peak detector circuit blocks 201, 202, comprising a (resistive) voltage divider 201 providing Kff and comprising a maximum input value V coupled to a diode to provide an input signal HV. INmax The operational amplifier,

[0140] The multiplier circuit block 203 has a number (i+1) of input nodes coupled to the outputs of the peak detector circuit blocks 201, 202, and is configured to provide a maximum input value V boosted to a power (i+1). INmax , where i is an integer that can be selected based on the application of the electronic converter circuit 10 .

[0141] In one or more embodiments, the peak detectors 201, 202 may also use ideal diodes coupled to the ADC and a storage V INmax The memory circuit block of the digital value is implemented, for example, as an ADC converter and the logic to find and store the maximum value in the data collected by the ADC.

[0142] like Figure 5 and Figure 6 As shown, the second compensation stages 204, 205, 206, 207 may include:

[0143] The level adjustment circuit block 204, such as a resistor divider,

[0144] Normalization processing circuit blocks 204, 205, configured to apply normalization processing to the input signal HV to provide a normalized signal having a waveform Γ(t) equal to the waveform of the input signal HV and having a single (maximum) amplitude,

[0145] The power calculator circuit block 206 (eg, a multiplier circuit block) is configured to provide the square power of the normalized signal obtained by squaring the waveform, eg, Γ 2 (t),

[0146] Integrator circuit block 207 (eg, a low-pass filter) is configured to provide the square of waveform Γ(t) over a time interval T. IN The integral on , for example,

[0147] Figure 10 An embodiment of the second compensation stage 204, 205, 206, 207 is shown, wherein a real-time calculation of the integral of the square of the waveform Γ(t) is performed.

[0148] Get the square of the waveform Γ(t) at time interval T IN Alternative methods for the integral value on can include, for example Figure 11 As shown:

[0149] precalculate a set of integer values and store them in a lookup table (LUT) with a plurality of memory registers 207A as entries,

[0150] detecting 206A the “shape” of the waveform Γ(t) of the normalized signal, and

[0151] The value corresponding to the detected waveform shape is selected 207B (eg, via a digital multiplexer or an analog selector) among the pre-calculated values in the lookup table entry 207A.

[0152] For example, detecting 206A the shape of the waveform Γ(t) of the normalized signal may use a shape observer circuit block 206A that is configured to compare some predefined parameters of the normalized signal (e.g., peak-to-average ratio, periodic threshold crossings or absence of threshold crossings, time periods between different level crossings), where each predefined parameter value is associated with an entry of a stored LUT of integrated values 207A.

[0153] like Figure 5 and Figure 6 As shown, the third compensation stage 208 , 209 includes a multiplier circuit block 208 and an inverter circuit block 209 .

[0154] In one or more embodiments, when the control circuit 20 of the PCM configuration 20 b is used, the scaling circuit block 24 may be configured to perform the operations of the third compensation stages 208 , 209 to advantageously reduce the area occupied by the circuit.

[0155] Figure 12 Shown as Figure 5 and Figure 6 An exemplary circuit diagram of the fourth compensation circuit block 210 is shown.

[0156] like Figure 12 As shown, the fourth compensation stage 210 includes:

[0157] The current converter circuit block 210a is configured to receive an input signal Vx and convert it into a current signal Ix.

[0158] a resistor branch 210 b including a resistor R d coupled to a switch 210 c connected to a reference potential (e.g., ground), the switch 210 c being configured to be driven by an output signal GD provided from the memory block 28 to provide duty cycle modulation,

[0159] The capacitor branch 210d is connected in parallel with the resistor branch 210b to provide an average voltage output signal, for example, (Vx / δc)*Gd*Rd.

[0160] Figure 7 and Figure 8 An embodiment of the control circuit 20 is shown configured in configuration 20a. For the sake of brevity, detailed descriptions of circuit blocks having the same reference numerals as previously discussed will not be repeated here, as the descriptions of these blocks in the previous discussion are also applicable to the present invention. Figure 7 and Figure 8 .

[0161] As shown herein, a method for controlling a switching stage (eg, L) of an electronic converter (eg, 10) P 、L S , 14) of the control circuit (eg, 20, 20a, 20b), the electronic converter is configured to receive an input voltage (eg, V IN ) and provides an output voltage (e.g., V OUT ), the switching stage includes an inductor (eg, L S 、L P ), the control circuit comprises:

[0162] One or more first terminals configured to provide one or more corresponding drive signals (e.g., GD) to one or more electronic switches (e.g., 14) of the switching stage;

[0163] a second terminal configured to receive a first feedback signal (e.g., FB) proportional to the output voltage from a feedback circuit (e.g., OC);

[0164] The third terminal is configured to receive a current from a current sensor (e.g., R S ) receives the inductance of the above-mentioned switching stage (for example, L P ) in a second feedback signal (e.g., CS);

[0165] a driver circuit (e.g., 28) configured to provide the one or more drive signals according to a pulse width modulation (PWM) signal;

[0166] a PWM signal generator circuit (e.g., 26) configured to generate the PWM signal based on the first feedback signal, a reference threshold, and the second feedback signal or the slope compensation signal (e.g., H), wherein the PWM signal generator circuit includes a comparator circuit configured to compare one of the second feedback signal or the slope compensation signal with the threshold and provide the PWM signal (e.g., VM) as a result of the comparison;

[0167] The control circuit includes a processing circuit device (e.g., 201, 202, 203, 204, 205, 206, 207, 208, 209, 210), and the processing circuit device is configured to:

[0168] In response to receiving the AC input signal at the input terminal, sensing (or receiving, acquiring) an input sensing signal (eg, HV),

[0169] providing a first compensation parameter i and providing a first compensation signal (e.g., α) according to a power of the input sense signal, the power being equal to the incremented first compensation parameter i+1;

[0170] providing a second compensation signal (eg, β) based on the input sense signal, the second compensation signal indicating a waveform (Γ) of the input sense signal,

[0171] providing a third compensation signal (e.g., γ), the third compensation signal being the inverse of a product of the first compensation signal and the second compensation signal, the third compensation signal indicating a maximum value of the first feedback signal;

[0172] applying duty cycle modulation to the third compensation signal based on the control signal,

[0173] The maximum power level of the input sensing signal is adjusted based on the third compensation signal.

[0174] As shown herein, the control circuit includes a multiplier circuit block (e.g., 24) coupled to the first terminal to receive the input sense signal therefrom and coupled to the processing circuit device to receive the third compensation signal therefrom, the multiplier circuit block having a scaling factor (e.g., Km) and configured to provide a product of the input voltage multiplied by the scaling factor multiplied by the third compensation signal to obtain a threshold value (e.g., T) of the power of the input signal.

[0175] As shown in this article, the input signal (V IN ) is expressed as Where V FBmaxis the maximum value of the first feedback signal, Km is the scaling factor, Kff is another scaling factor, R S is the resistance of the above current sensor.

[0176] As shown herein, the processing circuit device configured to provide the first compensation signal includes:

[0177] A peak detector circuit block (e.g., 201, 202) configured to detect a peak value of an input sense signal, the peak detector having an adjustable gain block (e.g., 201, Kff) and a hold time interval,

[0178] The power calculator circuit block (eg, 203 ) is configured to multiply the detected peak value of the input sensing signal by itself by a number equal to the incremented first compensation parameter i+1.

[0179] As shown herein, the processing circuit arrangement (configured to provide the above-mentioned second compensation signal) comprises:

[0180] A normalization processing circuit block (e.g., 204, 205) is configured to apply normalization processing to the input sense signal to provide a normalized signal having a single amplitude, the normalized signal indicating the waveform of the input sense signal (e.g., Γ(t)).

[0181] A power calculator circuit block (eg, 206) is configured to receive the normalized signal and provide its power spectrum (eg, Γ 2 (t)),

[0182] An integrator circuit block (eg, 207), preferably a low-pass filter, is configured to receive the power spectrum of the normalized signal and apply an integration process thereto to provide an integrated signal over time.

[0183] As shown herein, the processing circuit device configured to provide the second compensation signal includes:

[0184] A normalization processing circuit block (e.g., 204, 205) is configured to apply normalization processing to the input sense signal to provide a normalized signal having a single amplitude, the normalized signal indicating the waveform of the input sense signal (e.g., Γ(t)).

[0185] a plurality of memory registers (e.g., 207A) configured to store a set of integrated signal values indicating the integration of squared power of at least two different waveforms over time,

[0186] a waveform detection circuit block (e.g., 206A) configured to perform a comparison of a set of parameters of the normalized signal with a threshold value, wherein each parameter value in the set of parameters is associated with an integrated signal value stored in a plurality of memory registers, and provide a selection signal as a result of the comparison; and

[0187] The selection circuit block (eg, 207B), preferably a multiplexer, is configured to access a memory register among the plurality of memory registers based on the acquired selection signal, the accessed memory register being associated with the waveform of the detected input sense signal.

[0188] As shown herein, the set of parameters of the normalized signal includes at least one of: a peak-to-average ratio of the normalized signal, (the presence of) one or more periodic threshold crossings, and time periods between threshold crossings of different levels.

[0189] As shown herein, a processing circuit arrangement configured to apply duty cycle modulation to a third compensation signal based on the above-mentioned control signal comprises:

[0190] A converter circuit block (eg, 210 a ) configured to receive an input voltage signal (eg, Vx, γ) and convert it into a current signal (eg, Ix),

[0191] A resistor branch (e.g., 210b, Rd) coupled to a switch circuit (e.g., 210c), the switch circuit being configured to be driven to perform switching based on the output signal,

[0192] The capacitor branch (eg, 210d) is arranged in parallel with the resistor branch to provide an average value of the switching voltage as the output signal.

[0193] As shown herein, an electronic converter (e.g., 10), preferably a flyback converter, includes:

[0194] a switching stage including an inductor (eg, L) and configured to receive an input voltage at its input terminal and provide an output voltage at its output terminal, and

[0195] A control circuit (eg, 20, 20a, 20b) according to one or more embodiments.

[0196] As shown herein, a method of controlling a switching stage of an electronic converter includes driving the switching stage via a control circuit according to one or more embodiments.

[0197] It will be further understood that the various individual implementation options shown in the drawings accompanying this specification are not necessarily intended to be employed in the same combinations shown in the drawings. Thus, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations shown in the drawings.

[0198] Without prejudice to the underlying principle, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection.

[0199] A switching stage (L) for controlling an electronic converter (10) P 、L S , 14), the electronic converter (10) being configured to receive an input voltage (V IN ) and provides an output voltage (V OUT ), the above switch level (L P 、L S , 14) including inductance (L S 、L P ), the control circuit (20, 20a, 20b) can be summarized as comprising:

[0200] One or more first terminals, configured to provide power to the above switching stage (L P 、L S , 14) one or more electronic switches (14) provide one or more corresponding drive signals (GD);

[0201] The second terminal is configured to receive the output voltage (V OUT ) is proportional to a first feedback signal (FB);

[0202] The third terminal is configured to be connected to the current sensor (R S ) receives and switches the stage (L P 、L S 、14) inductance (L P ) in proportion to the current in the second feedback signal (CS);

[0203] A driver circuit (28) configured to provide the one or more drive signals (GD) according to a pulse width modulation (PWM) signal (VM);

[0204] a PWM signal generator circuit (26) configured to generate the PWM signal according to the first feedback signal (FB), a reference threshold (T), and the second feedback signal (CS) or the slope compensation signal (H), wherein the PWM signal generator circuit includes a comparator circuit (26) configured to compare one of the second feedback signal (CS) or the slope compensation signal (H) with the threshold (T), and provide the PWM signal (VM) as a result of the comparison;

[0205] The control circuit (20, 20a, 20b) includes a processing circuit device (201, 202, 203, 204, 205, 206, 207, 208, 209, 210), and the processing circuit device is configured to:

[0206] In response to receiving the AC input signal (V IN ), sensing input sensing signal (HV);

[0207] providing a first compensation parameter i and providing a first compensation signal (α) based on the input sense signal raised to a power equal to the incremented first compensation parameter i+1;

[0208] providing a second compensation signal (β) based on the input sense signal (HV), the second compensation signal (β) indicating a waveform (Γ) of the input sense signal (HV);

[0209] providing a third compensation signal (γ) as the inverse of a product of the first compensation signal (α) and the second compensation signal (β), the third compensation signal (γ) indicating a maximum value of the first feedback signal (FB);

[0210] applying duty cycle modulation to the third compensation signal (γ) based on the control signal (GD);

[0211] The maximum power level of the input sensing signal (HV) is adjusted according to the third compensation signal (γ).

[0212] The multiplier circuit block (24) can be coupled to the first terminal (HV) to receive the input sense signal therefrom and coupled to the processing circuit device (201, 202, 203, 204, 205, 206, 207, 208, 209, 210) to receive the third compensation signal (γ) therefrom, the multiplier circuit block (24) having a scaling factor (Km) and configured to provide a product of the input voltage (HV) multiplied by the scaling factor (Km) multiplied by the third compensation signal (γ) to obtain the input signal (V IN ) power threshold (T).

[0213] Input signal (V IN) can be expressed as

[0214]

[0215] Where: V FBmax is the maximum value of the first feedback signal (FB); Km is the scaling factor; Kff is another scaling factor; R S is the resistance of the above current sensor.

[0216] The processing circuit arrangement (201, 202, 203, 204, 205, 206, 207, 208, 209, 210) may include:

[0217] A peak detector circuit block (201, 202) configured to detect an input sense signal (HV), the peak detector having an adjustable gain block (201, Kff) and a hold time interval;

[0218] The power calculator circuit block (203) is configured to multiply the peak value of the detected input sense signal (HV) by itself a number equal to the incremented first compensation parameter i+1.

[0219] The processing circuit arrangement (201, 202, 203, 204, 205, 206, 207, 208, 209, 210) may include:

[0220] a normalization processing circuit block (204, 205) configured to apply normalization processing to the input sense signal (HV) to provide a normalized signal having a single amplitude, the normalized signal indicating a waveform (Γ(t)) of the input sense signal (HV);

[0221] A power calculator circuit block (206) is configured to receive the normalized signal and provide its power spectrum (Γ 2 (t));

[0222] An integrator circuit block (207), preferably a low pass filter, is configured to receive the power spectrum of the normalized signal and apply an integration process thereto to provide an integrated signal over time.

[0223] The processing circuit arrangement (201, 202, 203, 204, 205, 206, 207, 208, 209, 210) may include:

[0224] a normalization processing circuit block (204, 205) configured to apply normalization processing to the input sense signal (HV) to provide a normalized signal having a single amplitude, the normalized signal indicating a waveform (Γ(t)) of the input sense signal (HV);

[0225] a plurality of memory registers (207A) configured to store a set of integrated signal values indicative of an integral of squared power of at least two different waveforms over time;

[0226] a waveform detection circuit block (206A) configured to perform a comparison of a set of parameters of the normalized signal with a threshold value, and provide a selection signal as a result of the comparison, wherein each parameter value in the set of parameters is associated with an integrated signal value stored in a plurality of memory registers (207A);

[0227] The selection circuit block (207B), preferably a multiplexer, is configured to access a memory register among the plurality of memory registers (207A) based on the acquired selection signal, the accessed memory register being associated with the waveform of the detected input sense signal (high voltage).

[0228] The set of parameters of the normalized signal may include at least one of: a peak-to-average ratio of the normalized signal; one or more periodic threshold crossings; and time periods between threshold crossings of different levels.

[0229] The processing circuit arrangement (201, 202, 203, 204, 205, 206, 207, 208, 209, 210) may include:

[0230] A converter circuit block (210a) configured to receive an input voltage signal (Vx, γ) and convert it into a current signal (Ix);

[0231] a resistor branch (210b, Rd) coupled to a switch circuit (210c), the switch circuit being configured to be driven to perform switching based on the output signal (GD);

[0232] The capacitor branch (210d) is arranged in parallel with the resistor branch (210b) to provide an average value of the switching voltage as an output signal.

[0233] An electronic converter (10), preferably a flyback converter, can be summarized as comprising:

[0234] Switching level (L S 、L P , 14), including an inductor (L) and configured to receive an input voltage (V IN ) and provides an output voltage (V OUT );as well as

[0235] The control circuit (20, 20a, 20b) is coupled to the above-mentioned switching stage (L S 、LP , 14).

[0236] A switching stage (L) for controlling an electronic converter (10) P 、L S , 14), which can be summarized as comprising driving the above-mentioned switching stage (L) via a control circuit (20, 20a, 20b) P 、L S , 14).

[0237] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments and the full scope to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A control circuit for controlling a switching stage of an electronic converter, the electronic converter being configured to receive an input voltage at an input terminal of the electronic converter and to provide an output voltage at an output terminal of the electronic converter, the switching stage comprising an inductor, the control circuit comprising: a first terminal configured to provide a drive signal to an electronic switch of the switching stage; a second terminal configured to receive a first feedback signal proportional to the output voltage from a feedback circuit; a third terminal configured to receive a second feedback signal proportional to a current in an inductor of the switching stage from a current sensor; A driver circuit configured to provide the driving signal according to a pulse width modulation (PWM) signal; as well as a PWM signal generator circuit configured to generate the PWM signal according to the first feedback signal, a reference threshold, and the second feedback signal or a slope compensation signal, wherein the control circuit comprises a processing circuit device, the processing circuit device being configured to: sensing an input signal in response to receiving the input voltage at the input terminal; as well as A first compensation parameter is provided, and a first compensation signal is provided based on the input signal being raised to a power equal to the incremented first compensation parameter.

2. The control circuit of claim 1 , wherein the PWM signal generator circuit comprises a comparator circuit configured to perform a comparison of one of the second feedback signal or the slope compensation signal with the threshold value, and the PWM signal generator circuit is configured to generate the PWM signal based on the comparison.

3. The control circuit of claim 1 , wherein the processing circuit device is configured to: providing a second compensation signal based on the input signal, the second compensation signal indicating a waveform of the input signal; providing a third compensation signal, the third compensation signal being the inverse of a product of the first compensation signal and the second compensation signal, the third compensation signal indicating a maximum value of the first feedback signal; applying duty cycle modulation to the third compensation signal based on the drive signal; as well as The maximum power level of the input signal is adjusted based on the third compensation signal.

4. The control circuit of claim 3 , comprising a multiplier circuit block configured to receive the input signal, and coupled to the processing circuit device and configured to receive the third compensation signal from the processing circuit device, the multiplier circuit block having a scaling factor and configured to provide a product of the input voltage multiplied by the scaling factor multiplied by the third compensation signal to obtain a threshold value for the power of the input signal.

5. The control circuit according to claim 4, wherein the threshold value of the power of the input signal is expressed as in: VFBmax is the maximum value of the first feedback signal; Km is the scaling factor; Kff is another scaling factor; RS is the resistance of the current sensor.

6. The control circuit of claim 1 , wherein the processing circuit device comprises: a peak detector circuit block configured to detect a peak value of the input signal, the peak detector having an adjustable gain block and a hold time interval; as well as A power calculator circuit block is configured to multiply the detected peak value of the input signal by itself by a number equal to the incremented first compensation parameter.

7. The control circuit of claim 1 , wherein the processing circuit device comprises: a normalization processing circuit block configured to apply normalization processing to the input signal to provide a normalized signal having a single amplitude, the normalized signal indicating a waveform of the input signal; a power calculator circuit block configured to receive the normalized signal and provide a power spectrum of the normalized signal; as well as An integrator circuit block is configured to receive the power spectrum of the normalized signal and apply an integration process to the power spectrum to provide an integrated signal over time.

8. The control circuit of claim 7, wherein the integrator circuit block comprises a low-pass filter.

9. The control circuit of claim 1 , wherein the processing circuitry comprises: a normalization processing circuit block configured to apply normalization processing to the input signal to provide a normalized signal having a single amplitude, the normalized signal indicating a waveform of the input signal; a plurality of memory registers configured to store a set of integrated signal values indicative of an integral of squared power of at least two different waveforms over time; a waveform detection circuit block configured to perform a comparison of a set of parameters of the normalized signal with a threshold value to provide a selection signal as a result of the comparison, wherein each parameter value in the set of parameters is associated with an integrated signal value stored in the plurality of memory registers; as well as A selection circuit block is configured to access a memory register among the plurality of memory registers based on the acquired selection signal, the accessed memory register being associated with the detected waveform of the input signal.

10. The control circuit of claim 9, wherein the selection circuit block comprises a multiplexer.

11. The control circuit according to claim 9, wherein the parameter set of the normalized signal comprises at least one of the following: The peak-to-average ratio of the normalized signal; One or more periodic threshold crossings; and The time period between threshold crossings of different levels.

12. The control circuit of claim 1 , wherein the processing circuitry comprises: a converter circuit block configured to receive an input voltage signal and convert the input voltage signal into a current signal; a resistive branch coupled to a switching circuit, the switching circuit being configured to be driven to perform switching based on the driving signal; as well as A capacitor branch is arranged in parallel with the resistor branch to provide an average value of the switch voltage as an output signal.

13. An electronic converter comprising: an input terminal configured to receive an input voltage; an output terminal configured to provide an output voltage; the switching stage, including the inductor; as well as a control circuit coupled to the switching stage, the control circuit comprising: a first terminal configured to provide a drive signal to an electronic switch of the switching stage; a second terminal configured to receive a first feedback signal proportional to the output voltage from a feedback circuit; a third terminal configured to receive a second feedback signal proportional to a current in an inductor of the switching stage from a current sensor; a driver circuit configured to provide the driving signal according to a pulse width modulation (PWM) signal; and a PWM signal generator circuit configured to generate the PWM signal according to the first feedback signal, a reference threshold, and the second feedback signal or a slope compensation signal, wherein the control circuit comprises a processing circuit device, the processing circuit device being configured to: in response to receiving the input voltage at the input terminal, sensing an input signal; and A first compensation parameter is provided and a first compensation signal is provided based on the input signal raised to a power equal to the incremented first compensation parameter.

14. The electronic converter of claim 13 , wherein the PWM signal generator circuit comprises a comparator circuit configured to perform a comparison of one of the second feedback signal or the slope compensation signal with the threshold value, and the PWM signal generator circuit is configured to generate the PWM signal based on the comparison.

15. The electronic converter of claim 14 , wherein the processing circuitry is configured to: providing a second compensation signal based on the input signal, the second compensation signal indicating a waveform of the input signal; providing a third compensation signal, the third compensation signal being the inverse of a product of the first compensation signal and the second compensation signal, the third compensation signal indicating a maximum value of the first feedback signal; applying duty cycle modulation to the third compensation signal based on the drive signal; as well as The maximum power level of the input signal is adjusted based on the third compensation signal.

16. The electronic converter of claim 15 , wherein the control circuit further comprises a multiplier circuit block configured to receive the input signal, and coupled to the processing circuitry and configured to receive the third compensation signal from the processing circuitry, the multiplier circuit block having a scaling factor and configured to provide a product of the input voltage multiplied by the scaling factor multiplied by the third compensation signal to obtain a threshold value for the power of the input signal.

17. A method of controlling a switching stage of an electronic converter, the electronic converter having an input terminal configured to receive an input voltage and an output terminal configured to provide an output voltage, the switching stage comprising an inductor, the method comprising: providing, at a first terminal of the control circuit, a drive signal to an electronic switch of the switching stage; receiving, at a second terminal of the control circuit, a first feedback signal proportional to the output voltage; receiving, at a third terminal of the control circuit, a second feedback signal proportional to a current in an inductor of the switching stage; The driver circuit of the control circuit provides the driving signal according to a pulse width modulation (PWM) signal; as well as generating the PWM signal by a PWM signal generator circuit of the control circuit according to the first feedback signal, a reference threshold, and the second feedback signal or a slope compensation signal; sensing an input signal by processing circuitry of the control circuit in response to the input voltage received at the input terminal; as well as A first compensation parameter is provided by the processing circuitry and a first compensation signal is provided based on the input signal raised to a power equal to the incremented first compensation parameter.

18. The method of claim 17, wherein generating the PWM signal comprises: Comparison of one of the second feedback signal or the slope compensation signal with the threshold is performed by a comparator circuit, and the PWM signal generator circuit is configured to generate the PWM signal based on the comparison.

19. The method according to claim 17, further comprising: providing, by the processing circuit device, a second compensation signal based on the input signal, wherein the second compensation signal indicates a waveform of the input signal; providing, by the processing circuit device, a third compensation signal, the third compensation signal being the inverse of a product of the first compensation signal and the second compensation signal, the third compensation signal indicating a maximum value of the first feedback signal; applying, by the processing circuitry, duty cycle modulation to the third compensation signal based on the drive signal; as well as The maximum power level of the input signal is adjusted by the processing circuitry based on the third compensation signal.

20. The method according to claim 19, further comprising: receiving the input signal and the third compensation signal by a multiplier circuit block of the control circuit; as well as The multiplier circuit block provides a threshold value of the input power, where the threshold value of the power is a product of the input voltage multiplied by a scaling factor multiplied by the third compensation signal.

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