envelope detector circuit, corresponding receiver circuit and galvanic isolator device

Abstract

Embodiments of the present disclosure relate to envelope detector circuits, corresponding receiver circuits and current isolator devices. A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio frequency amplitude modulated signal. A rectified signal representative of an envelope of the radio frequency amplitude modulated signal is generated at the intermediate node. An amplifier stage coupled to the intermediate node generates an amplified rectified signal indicative of the envelope of the radio frequency amplitude modulated signal at an output node. The rectifier stage includes a resistive element coupled in parallel with the load circuit between the intermediate node and the supply voltage node.

Description

[0001] CLAIM

[0002] This application claims priority to Italian Patent Application No. 102021000007844 filed March 30, 2021, the contents of which are incorporated herein in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present specification relates to envelope detector circuits and related devices.

[0004] One or more embodiments can apply to current isolators. BACKGROUND

[0005] In recent years, several applications have taken advantage of galvanic isolation, for example, to improve safety and reliability, especially in adverse environments. Galvanic isolation is a desirable feature in certain automotive applications (e.g., drive devices for electric and hybrid vehicles), in industrial environments (e.g., motor control, automation, etc.), in medical devices, in consumer products (e.g., home appliances), in gate drivers for power devices (e.g., power MOS, silicon carbide, or gallium nitride devices), and even in communication networks. Current isolators facilitate data transfer across a galvanic barrier and allow bidirectional communication between two isolated interfaces.

[0006] Figure 1 A conventional galvanic isolation system 10 is illustrated, which can be known from the document Ragonese et al., “A CMOS data transfer system based on Planar RF Coupling for reinforced galvanic isolation with 25-kV surge voltage and 250-kV / μs CMTI,” Electronics, 2020; 9(6):943, DOI: 10.3390 / electronics9060943 (incorporated by reference and referred to as Ragonese et al.). The isolation system 10 includes a first device 1001 and a second device 1002. The first device 1001 includes, for example, a human / data interface, a bus controller, a network controller, a microcontroller unit(s), and generally any component that can be used to provide an interface of the system 10 to an environment (e.g., a user). Depending on the application, the second device 1002 includes, for example, a sensor interface, a door driver, a medical device, a communication network, and generally any component that can be used for operation of the system 10. The first device 1001 is coupled between a first power supply terminal 1021 and a first reference terminal GND1 (e.g., ground or a ground reference) to receive a first power supply voltage VDD1. The second device 1002 is coupled between a second power supply terminal 1022 and a second reference terminal GND2 (e.g., ground or a ground reference) to receive a second power supply voltage VDD2. The first and second devices 1001, 1002 are coupled together via a galvanic isolation barrier 1010. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second devices 1001, 1002. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second power supply terminals 1021, 1022. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second reference terminals GND1, GND2. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second devices 1001, 1002. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second power supply terminals 1021, 1022. The galvanic isolation barrier 1010 is configured to prevent a direct galvanic connection between the first and second reference terminals GND1, GND2. DD1and the second device 1002 is coupled between the second power supply terminal 1022 and the second reference terminal GND2 to receive the second supply voltage V DD2 . The first device 1001 and the second device 1002 are galvanically isolated by a galvanic isolation barrier 104 and contain means for transferring power 106 and / or data 108 between the two devices, i.e. across the isolation barrier 104.

[0007] Known galvanic isolators are typically based on electromagnetic coupling (e.g. capacitive or inductive coupling) across a dielectric layer, i.e. a galvanic barrier. In some cases, galvanic isolation can be obtained by providing a package level isolation barrier. In other words, radio frequency (RF) coupling between packaging / assembly technology and micro-antennas can be used to provide isolation and data communication. For example, as disclosed in US Patent No. 8,364,195 B2 (incorporated herein by reference), some RF galvanic isolators utilize wireless transmission between two stacked dies through silicon integrated near-field antennas. To reduce the distance between the stacked antennas, dies can also be assembled face-to-face at the expense of manufacturing through-hole vias (THVs) with backside connections. However, chip assembly complexity and packaging costs are not conducive to widespread adoption of this isolation technology. These drawbacks can be mitigated if two integrated circuit dies are placed side-by-side on a package substrate with magnetic coupling between co-planar antennas. In this case, the physical channel for data communication relies on weak near-field coupling between two micro-antennas integrated on two side-by-side co-packaged chips, as shown in Figure 2 .

[0008] As shown in Figure 2 , the isolation system 20 comprises a first integrated circuit chip 2001 and a second integrated circuit chip 2002 arranged on galvanic isolation die pads 2021 and 2022, respectively, in a (molded) package 203. Each of the chips 2001, 2002 comprises a respective planar micro-antenna 2041, 2042. In this approach, the insulation distance (DTI) that determines the insulation level can be increased. Standard mold compounds have a dielectric strength (E M ) of at least 50 V / μm and thus a DTI of about 400 μm to 500 μm, a higher than 20 kV isolation level can be achieved. Moreover, the intrinsic parasitic capacitance of the isolation channel can be reduced if compared to conventional chip-level barriers, i.e. isolation capacitors or stacked transformers, thus reducing common mode (CM) currents generated by fast ground shifts, i.e. CM transients.

[0009] Figure 3 (also known from the previously cited Ragonese et al.) is a simplified circuit diagram of an isolation data transmission channel of an exemplary isolation system (e.g. 10 or 20), and Figure 4is an example of a possible temporal behavior of an electrical signal in the system.

[0010] Data transmission across the galvanic isolation barrier can rely on amplitude modulation of a radio frequency (RF) carrier, in particular on on-off keying (OOK) pulse width modulation (PWM) of the RF carrier. The transmission chip 2001 comprises an input pin 3001 for receiving an input digital signal IN carrying input data (e.g., a sequence of “0” or “1” bits), and a baseband interface (BBIF) 3021 (e.g., a PWM modulator circuit) that receives the input digital signal IN and generates a corresponding input PWM signal PWM IN for driving a transmission front-end circuit 3041. IN For example, the signal PWM IN includes periods with low duty cycle (e.g., 25% or less) to encode “0” bit values, and periods with high duty cycle (e.g., 75% or more) to encode “1” bit values, as shown in Figure 4 The transmission front-end circuit 3041 modulates the amplitude of a radio frequency carrier according to the PWM signal PWM RF (e.g., applying ASK modulation, in particular OOK modulation), to generate a transmission signal S RF that is then transmitted by a transmit antenna 2041 coupled to the transmission front-end circuit 3041. The receive chip 2002 on the other side of the isolation barrier 306 comprises a receive front-end circuit 3042 coupled to a receive antenna 2042 to receive the transmission signal S RF from it. The receive front-end circuit 3042 comprises an envelope detector circuit that detects the envelope of the transmission signal S RF to generate an output PWM signal PWM OUT . The output PWM signal PWM OUT is provided to a baseband interface 3022 (e.g., a PWM demodulator circuit) for data demodulation, which generates an output digital signal OUT at an output pin 3002.

[0011] The front-end circuit 3042 in the receive chip 2002 is thus configured to rectify (e.g., perform envelope detection) and amplify the received low-level radio frequency signal S RF so as to convert it into a PWM low-frequency signal PWM OUT , allowing for inter-chip communication with two micro-antennas respectively transmitting and receiving the carrier signal.

[0012] The previously cited contribution by Ragonese et al. provides an example of such a receive front-end circuit, as shown in Figure 5 and 6 . Figure 5 is a simplified circuit block diagram example of an isolated data transmission channel,Figure 6 is an example of a circuit diagram of a part of a corresponding receive front-end circuit.

[0013] As shown in Figure 5 , the receive front-end circuit 3042 comprises a gain stage 50, a mixer stage 52 coupled to the output of the gain stage 50, and a low-pass filter stage 54 coupled to the output of the mixer stage 52. The received radio frequency signal S RF is first amplified at the gain stage 50 to obtain a signal having an amplitude suitable for driving a rectifier (e.g. amplifying the signal from an amplitude of about 80 mV to an amplitude of about 400 mV). Then, the mixer stage 52 and the low-pass filter stage 54 (together they can be referred to as rectifier stage in the context of the present specification) detect the envelope of the (amplified) input RF signal S RF and generate an envelope signal ENV OUT . The rectified (envelope) signal ENV OUT is then compared with a threshold to generate an output PWM signal PWM OUT (not visible in the attached figures here).

[0014] Figure 6 is an exemplary circuit diagram of a rectifier stage known from Ragonese et al. It comprises a differential amplifier with resistive load, with a double-balanced mixer based on a Gilbert cell. The output RC load of the mixer stage provides low-pass filtering to clean the RX signal envelope. Ragonese et al. disclose this solution. The prior cited is affected by high current consumption due to RF amplification and frequency limitation in the mixer-based rectifier.

[0015] Reference is made to Fiore et al. “Low-power ASK Detector for low modulation indexs and rail-to-rail input range”, IEEE Transactions on Circuits and Systems II: Express briefs, vol. 63, no. 5, pp. 458-462, May 2016, doi: 10.1109 / TCSII.2015.2503651 (hereinafter incorporated herein by reference and referred to as Fiore et al.) discloses another example of an envelope detector circuit. However, this solution is not practical for use at low data rates as it cannot be fully integrated and requires external components.

[0016] Therefore, there is a need in the art to provide an envelope detector circuit capable of converting a low-level radio frequency carrier signal into a low-frequency PWM signal, in particular for low data rate applications. SUMMARY

[0017] One or more embodiments provide an improved envelope detection circuit, e.g., for use in a current isolator, which can be fully integrated and operate at low data rates.

[0018] One or more embodiments relate to a circuit, e.g., an envelope detection circuit.

[0019] One or more embodiments relate to a corresponding receiver circuit.

[0020] One or more embodiments relate to a corresponding current isolator device.

[0021] In one or more embodiments, a circuit includes a rectifier stage including a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load coupled between the intermediate node and a supply voltage node. The differential input transistor pair is configured to receive a radio frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio frequency amplitude modulated signal is generated at the intermediate node. The circuit includes an amplifier stage coupled to the intermediate node to receive the rectified signal, and the amplifier stage is configured to generate an amplified rectified signal indicative of the envelope of the radio frequency amplitude modulated signal at an output node. The rectifier stage includes a first resistive element coupled in parallel between the intermediate node and the supply voltage node.

[0022] Thus, one or more embodiments provide an envelope detector circuit which can operate at low data rates and which can be fully integrated into a semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings in which:

[0024] Figure 1 A conventional current isolation system is shown;

[0025] Figure 2 An isolation system including a first integrated circuit chip and a second integrated circuit chip is shown;

[0026] Figure 3 is a simplified circuit diagram example of an isolation data transmission channel of the isolation system;

[0027] Figure 4 is an example of a possible time behavior of an electrical signal in the system of Figure 3

[0028] Figure 5 A receive front-end circuit is shown;

[0029] Figure 6 is an exemplary circuit diagram of a rectifier stage; ​

[0030] Figure 7 is a circuit diagram example of an envelope detector circuit; and

[0031] Figure 8 is an exemplary circuit diagram of an envelope detector circuit according to one or more embodiments of the present description. DETAILED DESCRIPTION

[0032] In the following description, one or more specific details are described to provide an example of the embodiments of the present description. One or more of the embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail in order to avoid obscuring some aspects of the embodiments.

[0033] Reference within the framework of the present description to "an embodiment" or "one embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in relation to this embodiment is included in at least one embodiment. Thus, the presence of such phrases in one or more points of the present description does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular conformation, structure or feature can be combined in any appropriate manner.

[0034] The headings / references used herein are provided only for convenience and thus do not limit the scope of protection or the scope of the embodiments.

[0035] In the attached drawings herein, the same parts or elements are denoted by the same reference signs / numbers, and for the sake of brevity, the corresponding description will not be repeated.

[0036] By way of introduction to the detailed description of the exemplary embodiments, reference can first be made to Figure 7 , Figure 7 is an exemplary circuit diagram of a two-stage envelope detector circuit 70 suitable for use in an amplitude shift keying (ASK) detector.

[0037] As shown in Figure 7 , the envelope detector circuit 70 comprises an input stage 71 and an output stage 72.

[0038] The input stage 71 comprises an input differential pair comprising two transistors (e.g. n-channel MOS transistors) M1 and M2. An input radio frequency signal S RF is applied between the (gate) control terminals of the two transistors M1 and M2 of the differential pair. The source terminals of the transistors M1, M2 are coupled to a reference voltage node GND, and their drain terminals are coupled to a common intermediate node 710.

[0039] The input stage 71 comprises a load coupled between a common intermediate node 710 and a supply node providing a supply voltage V CC . For example, as shown in Figure 7 , the load comprises an active (e.g. self-biased) load comprising a transistor M3 and a low-pass filter R F , C F . The current path of the transistor M3 (e.g. a p-channel MOS transistor) is arranged between the common intermediate node 710 and the supply node V CC . The low-pass filter comprises a resistive element (e.g. a resistor R F ) coupled between the common intermediate node 710 and the (gate) control terminal of the transistor M3, and a capacitive element (e.g. a capacitor C CC ) coupled between the (gate) control terminal of the transistor M3 and the supply node V F .

[0040] The output stage 72 comprises a common-source or common-emitter arrangement comprising a transistor M4 and a resistive load R L , the transistor M4 and the resistive load R L being coupled in series between the supply node V CC and a reference voltage node GND. The transistor M4 has a (gate) control terminal coupled to the common intermediate node 710 (acting as an output node of the first stage 71). The output node 720 between the transistor M4 and the resistive load R L provides the envelope output signal ENV OUT . In particular, the transistor M4 is a p-channel MOS transistor having a source terminal coupled to the supply node V CC and a drain terminal coupled to the output node 720, and the resistive load R L is coupled between the drain terminal of the transistor M4 and the reference voltage node GND.

[0041] Thus, in the envelope detector circuit 70 as shown in Figure 7 , the (on-off) modulated differential input signal S RF is first rectified and then amplified to produce the envelope signal ENV OUT . The output node 720 of the envelope detector circuit 70 is coupled to a comparator circuit (not visible in the figure) such that the envelope signal ENV OUT is converted into a single-ended rail-to-rail PWM data signal PWM OUT .

[0042] Note that Figure 7 the circuit as shown can be (only) fully integrated in a silicon die for high data rate communication. The small signal loop gain T and the loop gain bandwidth product f GBWThe high data rate f

[0043]

[0044]

[0045] As an example, assume that the high data rate f BR = 100 Mb / s, then f GBW = f BR / 25 = 4 MHz, and further assume that R F = 10 kΩ, which results in C F = 120 pF, which is a high value, but still can be integrated into a silicon die.

[0046] As an alternative, again as an example, assume that the low data rate f BR = 400 kb / s, then f GBW = f BR / 25 = 16 kHz, and further assume that R F = 75 kΩ, which results in C F = 4 nF, C F = 4 nF is a too high capacitance value to be integrated into a silicon die.

[0047] Hence, at low data rates, the envelope detector circuit as exemplified in Figure 7 requires external components (e.g. an external capacitor C F ).

[0048] One or more embodiments relate to an improved envelope detector circuit suitable for use (also) at low data rates, as exemplified in Figure 8 , which is a circuit diagram example of a three-stage envelope detector circuit 80 suitable for amplitude shift keying (ASK) detection. Figure 8

[0049] As exemplified in Figure 8 , the envelope detector circuit 80 comprises an input stage 81, an intermediate stage 82 and an output stage 83.

[0050] The input stage 81 comprises an input differential pair comprising two transistors (e.g. n-channel MOS transistors) M1 and M2. An input radio frequency signal S RF is applied between the (gate or base) control terminals of the two transistors M1 and M2 of the differential pair. The source or emitter terminals of the transistors M1, M2 are coupled to a reference voltage node GND, while their drain or collector terminals are coupled to a common intermediate node 810. The input stage 81 further comprises a load coupled between the common intermediate node 810 and a power supply node providing a supply voltage V CC . For example, as exemplified in Figure 8 ​The load includes an active (e.g., self-biased) load including transistor M3 and low-pass filter R F , C F . Transistor M3 (e.g., a p-channel MOS transistor) has a current path disposed between common intermediate node 810 and power supply node V CC . The low-pass filter includes a resistive element (e.g., resistor R F ) coupled between common intermediate node 810 and the (gate or base) control terminal of transistor M3, and a capacitive element (e.g., capacitor C CC ) coupled between the (gate or base) control terminal of transistor M3 and power supply node V F .

[0051] As shown, input stage 81 further includes a resistive element R L1 , e.g., coupled between common intermediate node 810 and power supply node V CC , coupled in parallel with the active load. Another resistive element R L1 is disposed in input stage 81. The additional degree of freedom in the design of envelope detector circuit 80 enables resistive element R F to be disposed (e.g., dimensioned) to reduce loop gain-bandwidth product f GBW , which in turn facilitates implementation of capacitive element C F as an integrated component, while R L1 can be disposed (e.g., dimensioned) to determine the gain and output pole frequency of input stage 81, thereby mitigating (e.g., avoiding) edge distortion on the output PWM signal.

[0052] Intermediate stage 82 includes current matching circuitry. As exemplified in Figure 8 , intermediate stage 82 includes transistor M4 (e.g., a p-channel MOS transistor) having a current path disposed between power supply node V CC and bias source 822, and a control (gate or base) terminal coupled to intermediate node 810 of input stage 81. Current I4 flows through transistor M4. For example, transistor M4 has a source or emitter terminal coupled to power supply node V CC and a drain or collector terminal coupled to another intermediate node 820, and bias source 822 includes a current generator disposed between intermediate node 820 and reference voltage node GND to sink bias current I b from intermediate node 820 to reference voltage node GND.

[0053] In addition, intermediate stage 82 includes a resistive element R L2 , e.g., coupled between intermediate node 820 and power supply node V CC , coupled in parallel with the current path of transistor M4.CC Between. A resistor element R is set in intermediate stage 82. L2 It helps to restore the first stage 81 (transistor M3 and resistor R) L1 ) and the second stage 82 (transistor M4 and resistor R) L2 The matching conditions between the two are improved to enhance the accuracy of the bias current I5 of the output stage 83.

[0054] Output stage 83 includes amplifier stages, such as folded amplifier stages. Figure 8 As illustrated, output stage 83 includes a current mirror device comprising a first transistor M5 (e.g., a p-channel MOS transistor) and a second transistor M6 (e.g., a p-channel MOS transistor). The first transistor M5 has a current mirror located at power node V. CC The current path between the intermediate node 820 and the intermediate node is I5 = I b - I4 flows through this current path. The second transistor M6 is connected to the power node V. CC The output load R between the reference voltage node GND and the reference voltage node L3 (For example, a resistive load) arranged in series, such that a copy of the current I5 flows through M6 and R. L3 Thus, in transistor M6 and load R L3 The middle node 830 provides a single-ended output signal ENV. OUT .

[0055] In the single-pole output signal ENV OUT Within the range of positive voltage, the folded amplifier, including transistors M5 and M6, allows for an increase in load R. L3 The resistance value is adjusted, thus increasing the gain of the second stage. Therefore, the output bias voltage can be set to be close to V. CC The value of . Purely as a non-restricted instance, in V CC With a voltage of 3.5V, the resistor R L3 It is a standard configuration (e.g., Figure 7 R in L It doubles the output load, thus providing an additional gain of approximately 6dB.

[0056] The output node 830 of the envelope detector circuit 80 is coupled to the comparator circuit (not visible in the figure), causing the envelope signal ENV to... OUT It is converted into a single-ended rail-to-rail PWM data signal. OUT .

[0057] Notice, Figure 8 One or more embodiments illustrated herein can be fully integrated into a silicon die for (also) low data rate communication. The small-signal loop gain T and the loop gain-bandwidth product f GBW It can be calculated according to the following equation:

[0058]

[0059]

[0060] As an example, assume that the low data rate is equal to f BR = 400 kb / s, then f GBW = f BR / 25 = 16 kHz, and further assume that R F = 2 MΩ and R L1 = 75 kΩ, which results in C F = 50 pF, which is a capacitance value that can be integrated into a silicon die.

[0061] One or more embodiments can be applied in a package level current isolator device (e.g., as shown in FIG. 1), where current isolation can be achieved without using specific high voltage components, the inter-chip communication channel can be achieved through wireless radio frequency transmission, and appropriately selecting the distance between the two chips helps to achieve a high isolation level (e.g., 10 to 12 kV for enhanced isolation) and / or a higher common mode transient immunity CMTI (e.g., higher than 100 kV). Figure 2

[0062] However, the skilled person will appreciate that the reference to a package level current isolator device is only by way of example, and one or more embodiments are generally applicable to any kind of current isolator device.

[0063] One or more embodiments have been disclosed herein with reference to a specific implementation using complementary MOS technology. The skilled person will appreciate that bipolar (BJT) technology can also be employed as an implementation technique for one or more embodiments, as long as complementary transistors are included.

[0064] One or more embodiments can thus provide an envelope detector circuit that can be (also) fully integrated in a single chip for use at low data rates, e.g., without using passive discrete components to operate the circuit at low data rates. As an example, such an envelope detector circuit can operate at frequencies lower than 1 MHz (e.g., in certain applications such as gate drivers for electric motor control).

[0065] One or more embodiments can additionally provide one or more of the following advantages: high immunity to common mode transients, low current consumption, high gain, and low cost.

[0066] ​As exemplified herein, a circuit (e.g., 80) includes a rectifier stage (e.g., 81) including a differential input transistor pair (e.g., M1, M2) coupled between a reference voltage node (e.g., GND) and an intermediate node (e.g., 810), and a load (e.g., M3, R CC , C F ) coupled between the intermediate node and a supply voltage node (e.g., V F ). The differential input transistor pair is configured to receive a radio frequency amplitude modulated signal (e.g., S RF+ , S RF－ ). A rectified signal representative of an envelope of the radio frequency amplitude modulated signal is produced at the intermediate node. The circuit includes an amplifier stage (e.g., 82; 83) coupled to the intermediate node to receive the rectified signal, and configured to produce an amplified rectified signal (e.g., ENV OUT ) indicative of the envelope of the radio frequency amplitude modulated signal at an output node (e.g., 830). The rectifier stage further includes a first resistive element (e.g., R L1 ) coupled in parallel between the intermediate node and the supply voltage node.

[0067] As exemplified herein, the load includes an active load including a load transistor (e.g., M3) and a low pass filter (e.g., R F , C F ).

[0068] As exemplified herein, the active load includes the load transistor having a current path coupled between the intermediate node and the supply voltage node, a second resistive element (e.g., R F ) coupled between the intermediate node and a control terminal of the load transistor, and a capacitive element (e.g., C F ) coupled between the control terminal of the load transistor and the supply voltage node.

[0069] As exemplified herein, the first resistive element has a resistance value in a range of 25 kΩ to 50 kΩ, and the second resistive element has a resistance value in a range of 1 MΩ to 3 MΩ. For example, the first resistive element is sized to properly polarize the transistors M1, M2, and defines a gain of the first stage together with a bias current (e.g., 2*Id1,2, where Id is a current flowing through one of the transistors M1, M2). For example, an amplitude gain in a range of 2 to 3 is obtained.

[0070] As exemplified herein, the capacitive element has a capacitance value in a range of 50 pF to 150 pF.

[0071] As exemplified herein, the differential input transistor pair comprises a first input transistor (e.g., M1) and a second input transistor (e.g., M2) having current paths therethrough arranged in parallel between a reference voltage node and an intermediate node, and control terminals of the first and second input transistors are configured to receive a radio frequency amplitude modulated signal therebetween.

[0072] As exemplified herein, the amplifier stage comprises an output transistor (e.g., M6) arranged in a common source or common emitter configuration and an output load (e.g., R L3 ) coupled between a drain or collector terminal of the output transistor and the reference voltage node, and an output node intermediate the drain or collector terminal of the output transistor and the output load.

[0073] As exemplified herein, the amplifier stage comprises:

[0074] - a current matching transistor (e.g., M4) having a current path arranged between a supply voltage node and a current control node (e.g., 820), and a control terminal coupled to the intermediate node;

[0075] - a bias source (e.g., 822) coupled between the current control node and the reference voltage node to sink current (e.g., I b ) from the current control node, and - a current mirror transistor (e.g., M5) having a current path set between the supply voltage node and the current control node, and having a drain or collector terminal coupled to its control terminal.

[0076] As exemplified herein, the control terminal of the current mirror transistor is coupled to the control terminal of the output transistor.

[0077] As exemplified herein, the circuit comprises a current matching resistive element (e.g., R L2 ) coupled between the supply voltage node and the current control node.

[0078] As exemplified herein, the current matching resistive element has a resistance value in the range of 25kQ to 50kQ. For example, the current matching resistive element is sized to properly polarize transistor M4, and it defines, together with the bias current I b , the gain of the second stage.

[0079] As exemplified herein, the circuit comprises a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse width modulated output signal (e.g., PWM_OUT) indicative of an envelope of the radio frequency amplitude modulated signal.

[0080] As exemplified herein, a receiver circuit (e.g., 2002) comprises:

[0081] - a radio frequency antenna (e.g., 2042) configured to receive a radio frequency amplitude modulated signal (e.g., S RF );

[0082] - an envelope detector circuit according to one or more embodiments configured to receive the radio frequency amplitude modulated signal from the antenna and generate a pulse width modulated output signal indicative of an envelope of the received radio frequency amplitude modulated signal; and

[0083] - a PWM demodulator circuit (e.g., 3022) configured to demodulate the pulse width modulated output signal to generate an output digital data signal (e.g., OUT).

[0084] As exemplified herein, an isolator device (e.g., 20) comprises a transmitter circuit (e.g., 2001) configured to transmit a radio frequency amplitude modulated signal, and a receiver circuit according to one or more embodiments, and the transmitter circuit and the receiver circuit are isolated by a galvanic isolation barrier (e.g., 306).

[0085] As exemplified herein, the transmitter circuit and the receiver circuit are provided as separate chips arranged on respective galvanically isolated die pads (e.g., 2021, 2022), and the isolator device further comprises a molded package (e.g., 203) providing the galvanic isolation barrier.

[0086] Details and embodiments can vary significantly with respect to what is described by way of example only, without departing from the scope of protection, without departing from the scope of protection.

[0087] The claims are an integral part of the technical teaching provided herein with respect to the embodiments.

[0088] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: a rectifier stage comprising: a differential input transistor pair coupled between a reference voltage node and an intermediate node, the differential input transistor pair configured to receive a radio frequency amplitude modulated signal; a load circuit coupled between the intermediate node and a supply voltage node; and a first resistive element coupled in parallel with the load circuit between the intermediate node and the supply voltage node; wherein a rectified signal indicative of an envelope of the radio frequency amplitude modulated signal is generated at the intermediate node; and an amplifier stage coupled to receive the rectified signal from the intermediate node and configured to generate an amplified rectified signal at an output node, wherein the amplifier stage comprises: an output transistor and an output load coupled between a conductive terminal of the output transistor and the reference voltage node, and wherein the output node is intermediate the conductive terminal of the output transistor and the output load; a current matching transistor having a current path arranged between the supply voltage node and a current control node, and a control terminal coupled to the intermediate node; a bias source coupled between the current control node and the reference voltage node to sink current from the current control node; and a current mirror transistor having a current path arranged between the supply voltage node and the current control node, a control terminal, and a drain terminal or a collector terminal coupled to the control terminal; wherein the control terminal of the current mirror transistor is coupled to the control terminal of the output transistor.

2. The circuit of claim 1, wherein the load circuit is an active load circuit comprising a load transistor and a low pass circuit.

3. The circuit of claim 2, wherein the load transistor has a current path coupled between the intermediate node and the supply voltage node, and wherein the low pass circuit comprises: a second resistive element coupled between the intermediate node and a control terminal of the load transistor, and a capacitive element coupled between the control terminal of the load transistor and the supply voltage node.

4. The circuit of claim 3, wherein the first resistive element has a resistance value in a range of 25 kΩ to 50 kΩ, and wherein the second resistive element has a resistance value in a range of 1 MΩ to 3 MΩ.

5. The circuit of claim 1, wherein the differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between the reference voltage node and the intermediate node, and wherein control terminals of the first and second input transistors are configured to receive the radio frequency amplitude modulated signal.

6. The circuit of claim 1, further comprising a current matching resistive element coupled between the supply voltage node and the current control node.

7. The circuit of claim 6, wherein the current matching resistive element has a resistance value in a range of 25 kΩ to 50 kΩ.

8. The circuit of claim 1, wherein the output transistor is arranged in one of a common source or a common emitter configuration, wherein the conductive terminal comprises one of a drain or a collector, respectively.

9. The circuit of claim 1, further comprising: a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse width modulated output signal indicative of the envelope of the radio frequency amplitude modulated signal.

10. The circuit of claim 9, further comprising: a radio frequency antenna configured to receive the radio frequency amplitude modulated signal; and a PWM demodulator circuit configured to demodulate the pulse width modulated output signal to generate an output digital data signal.

11. The circuit of claim 8, further comprising: a transmitter circuit configured to transmit the radio frequency amplitude modulated signal; and wherein the transmitter circuit is isolated from a receiver circuit, including the rectifier stage, the amplifier stage, and comparator circuit, by a galvanic isolation barrier.

12. The circuit of claim 11, wherein the transmitter circuit and the receiver circuit are provided as separate chips arranged on respective electrically isolated die pads, and wherein the galvanic isolation barrier is provided by a molded package on the separate chips.

13. A circuit, comprising: a rectifier stage, including: a differential input transistor pair coupled between a reference voltage node and a first intermediate node, the differential input transistor pair configured to receive a radio frequency amplitude modulated signal; an active load circuit, including: a load transistor having a current path coupled between the first intermediate node and a supply voltage node; and a low pass circuit including a series circuit formed by a resistor and a capacitor coupled in series between the first intermediate node and the supply voltage node, wherein a second intermediate node of the series circuit is connected to a control terminal of the load transistor; and a resistive element coupled in parallel with the load circuit between the intermediate node and the supply voltage node; wherein a rectified signal indicative of an envelope of the radio frequency amplitude modulated signal is produced at the intermediate node; and an amplifier stage coupled to receive the rectified signal from the intermediate node and configured to produce an amplified rectified signal at an output node, wherein the amplifier stage includes: an output transistor and an output load coupled between a conductive terminal of the output transistor and the reference voltage node, and wherein the output node is intermediate the conductive terminal of the output transistor and the output load; a current matching transistor having a current path arranged between the supply voltage node and a current control node, and a control terminal coupled to the intermediate node; a bias source coupled between the current control node and the reference voltage node to sink current from the current control node; and a current mirror transistor having a current path arranged between the supply voltage node and the current control node, a control terminal, and a drain terminal or a collector terminal coupled to the control terminal; wherein the control terminal of the current mirror transistor is coupled to the control terminal of the output transistor.

14. The circuit of claim 13, wherein the resistor of the series circuit is connected between the first intermediate node and the second intermediate node, and wherein the capacitor of the series circuit is connected between the second intermediate node and the supply voltage node.

15. The circuit of claim 13, wherein the resistive element has a resistance value in a range of 25 kQ to 50 kQ, and wherein the resistor of the series circuit has a resistance value in a range of 1 MQ to 3 MQ.

16. The circuit of claim 13, wherein the differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between the reference voltage node and the intermediate node, and wherein control terminals of the first input transistor and the second input transistor are configured to receive the radio frequency amplitude modulated signal.

17. The circuit of claim 13, further comprising: a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse width modulated output signal indicative of the envelope of the radio frequency amplitude modulated signal.

18. A circuit comprising: a rectifier stage comprising: a differential input transistor pair coupled between a reference voltage node and an intermediate node, the differential input transistor pair configured to receive a radio frequency amplitude modulated signal; a load circuit coupled between the intermediate node and a supply voltage node; and a resistive element coupled in parallel with the load circuit between the intermediate node and the supply voltage node; wherein a rectified signal indicative of an envelope of the radio frequency amplitude modulated signal is produced at the intermediate node; and an amplifier stage comprising: a current matching transistor having a current path arranged between the supply voltage node and a current control node, and a control terminal coupled to the intermediate node; a bias source coupled between the current control node and the reference voltage node to sink current from the current control node; and a current mirror circuit having an input current path arranged between the supply voltage node and the current control node, and having an output current path arranged between the supply voltage node and an output node at which an amplified rectified signal is produced.

19. The circuit of claim 18, further comprising: a current matching resistive element coupled between the supply voltage node and the current control node.

20. The circuit of claim 19, wherein the resistive element has a resistance value in a range of 25 kQ to 50 kQ, and wherein the current matching resistive element has a resistance value in a range of 25 kQ to 50 kQ.

21. The circuit of claim 18, wherein the differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between the reference voltage node and the intermediate node, and wherein control terminals of the first input transistor and the second input transistor are configured to receive the radio frequency amplitude modulated signal.

22. The circuit of claim 18, further comprising: a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse width modulated output signal indicative of the envelope of the radio frequency amplitude modulated signal.

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