Counting circuit, readout circuit, and image sensor

Abstract

The application provides a counting circuit, which comprises a NAND gate, at least one Gray code counter and at least one conversion circuit, the NAND gate is used for receiving a clock signal and a counting control signal, the Gray code counters are in a cascade relationship, a clock end of a lower-stage Gray code counter is connected with a carry output end of an upper-stage Gray code counter, and a clock end of the uppermost-stage Gray code counter is connected with an output end of the NAND gate; the conversion circuit is connected with a Gray code output end of the Gray code counter one by one, is used for receiving a Gray code, and then converts the Gray code into a binary code, the Gray code counter is adopted, the number of flips is reduced, and then the power consumption is reduced. The application further provides a reading-out circuit and an image sensor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a counting circuit, a readout circuit and an image sensor. BACKGROUND

[0002] In a CMOS image sensor, an analog-to-digital converter (ADC) circuit is usually needed to convert an analog voltage signal into a digital signal after the light signal is converted into the analog voltage signal by a photosensitive unit, and the converted digital signal is finally transmitted to the outside of the chip. Since the photosensitive unit is usually in an array form, in order to improve the frame rate, a column of ADC circuit is usually connected to each column of photosensitive unit, and all columns of ADCs perform analog-to-digital conversion at the same time, greatly improving the overall chip conversion rate. The digital code converted by the ADC is read out through a storage unit and a column selection circuit.

[0003] The analog-to-digital converter now usually adopts a SS ADC (Signle Slope ADC) structure, which mainly consists of a coupling capacitor, a reset switch, a comparator circuit, a counting circuit and the like. Since the SS ADC circuit has a simple structure, low noise and is easy to be integrated as a column-level ADC, the conversion rate is greatly improved after being integrated as a column-level ADC. Among them, the counting circuit is a digital circuit, and its power consumption is basically contributed by the dynamic power consumption caused by signal flipping. Such a large number of flipping times leads to excessive dynamic power consumption of the binary counting circuit, especially when the counting clock frequency is high and the number of bits of the counting circuit is large.

[0004] Therefore, it is necessary to provide a new type of counting circuit, readout circuit and image sensor to solve the above problems existing in the prior art. SUMMARY

[0005] The present application aims to provide a counting circuit, a readout circuit and an image sensor, which reduces the number of flips and reduces power consumption.

[0006] To achieve the above-mentioned purpose, the counting circuit of the present application comprises:

[0007] The NAND gate is used to receive a clock signal and a counting control signal.

[0008] The at least one Gray code counter is in a cascaded relationship, the clock terminal of the lower level Gray code counter is connected to the carry output terminal of the upper level Gray code counter, and the clock terminal of the uppermost level Gray code counter is connected to the output terminal of the NAND gate; and

[0009] At least one conversion circuit is connected to the gray code output of the gray code counter one by one, for receiving the gray code and then converting the gray code into binary code.

[0010] The counting circuit has the beneficial effect of using the gray code counter to reduce the number of flips and thus reduce power consumption.

[0011] Optionally, the counting circuit is N-bit, the gray code counter is m-bit, the number of the gray code counters is N / m, and N, m and N / m are all natural numbers greater than 0.

[0012] Optionally, the gray code counter is a gray code plus 1 counter.

[0013] Optionally, the gray code counter comprises at least two D flip-flops and a logic circuit, and the D flip-flops are all connected to the logic circuit.

[0014] Optionally, the gray code counter is 2-bit, the gray code counter comprises two D flip-flops and a logic circuit, the two D flip-flops comprise a first D flip-flop and a second D flip-flop, the logic circuit comprises an NOR gate, the clock end of the first D flip-flop and the clock end of the second D flip-flop are connected as the clock end of the gray code counter, the positive phase output end of the first D flip-flop is connected with the data input end of the second D flip-flop and the second input end of the NOR gate, and the data input end of the first D flip-flop is connected with the inverse phase output end of the second D flip-flop and the first input end of the NOR gate.

[0015] Optionally, the Gray code counter is 3-bit, the Gray code counter comprises three D flip-flops and a logic circuit, the three D flip-flops comprise a first D flip-flop, a second D flip-flop and a third D flip-flop, the logic circuit comprises a NOR gate, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate and an XNOR gate, the clock terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are connected, serving as the clock terminal of the Gray code counter, the data input terminal of the first D flip-flop is connected with the output terminal of the XNOR gate and the first input terminal of the NOR gate, the positive output terminal of the first D flip-flop is connected with the second input terminal of the second NAND gate and the first input terminal of the fourth NAND gate, the inverting output terminal of the first D flip-flop is connected with the first input terminal of the third NAND gate, the data input terminal of the second D flip-flop is connected with the output terminal of the first NAND gate and the second input terminal of the NOR gate, the positive output terminal of the second D flip-flop is connected with the first input terminal of the XNOR gate and the second input terminal of the third NAND gate, the data input terminal of the third D flip-flop is connected with the output terminal of the fifth NAND gate and the third input terminal of the NOR gate, the positive output terminal of the third D flip-flop is connected with the second input terminal of the XNOR gate and the second input terminal of the fourth NAND gate, the inverting output terminal of the third D flip-flop is connected with the first input terminal of the second NAND gate, the output terminal of the second NAND gate is connected with the first input terminal of the first NAND gate, the output terminal of the third NAND gate is connected with the first input terminal of the fifth NAND gate, and the output terminal of the fourth NAND gate is connected with the second input terminal of the first NAND gate and the second input terminal of the fifth NAND gate.

[0016] Optionally, the Gray code counter is 4-bit, the Gray code counter comprises four D flip-flops and a logic circuit, the four D flip-flops comprise a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop, the logic circuit comprises an NOR gate, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, an XNOR gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate and an XOR gate, clock terminals of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are connected, as a clock terminal of the Gray code counter, a data input terminal of the first D flip-flop is connected with an output terminal of the XOR gate and a first input terminal of the NOR gate, a positive output terminal of the first D flip-flop is connected with a first input terminal of the second NAND gate, a second input terminal of the fifth NAND gate and a second input terminal of the eighth NAND gate, a negative output terminal of the first D flip-flop is connected with a second input terminal of the first NAND gate, a third input terminal of the sixth NAND gate and a third input terminal of the tenth NAND gate, a data input terminal of the second D flip-flop is connected with an output terminal of the third NAND gate and a second input terminal of the NOR gate, a positive output terminal of the second D flip-flop is connected with a first input terminal of the first NAND gate, a second input terminal of the XOR gate, a second input terminal of the sixth NAND gate and a second input terminal of the ninth NAND gate, a negative output terminal of the second D flip-flop is connected with a second input terminal of the fourth NAND gate and a second input terminal of the tenth NAND gate, a data input terminal of the third D flip-flop is connected with an output terminal of the seventh NAND gate and a third input terminal of the NOR gate, a positive output terminal of the third D flip-flop is connected with a second input terminal of the XNOR gate, a first input terminal of the fourth NAND gate, a first input terminal of the fifth NAND gate and a first input terminal of the tenth NAND gate, a data input terminal of the fourth D flip-flop is connected with an output terminal of the eleventh NAND gate and a fourth input terminal of the NOR gate, a positive output terminal of the fourth D flip-flop is connected with a first input terminal of the XNOR gate, a first input terminal of the eighth NAND gate and a first input terminal of the ninth NAND gate, and a negative output terminal of the fourth D flip-flop is connected with a first input terminal of the sixth NAND gate.

[0017] The application further provides a readout circuit, comprising:

[0018] a comparator; and

[0019] the count circuit, one end of the NAND gate is connected with an output terminal of the comparator, for receiving the count control signal.

[0020] The readout circuit has the beneficial effect of using the count circuit, thereby reducing power consumption.

[0021] The application also provides an image sensor, comprising:

[0022] a pixel cell array for light sensing to generate a voltage signal;

[0023] a ramp signal generating unit for generating a ramp signal; and

[0024] at least one readout circuit connected with the pixel cell array and the ramp signal generating unit.

[0025] The image sensor has the beneficial effect of using the readout circuit, thereby reducing power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 a circuit schematic diagram of a conventional counting circuit in the prior art;

[0027] Figure 2 a timing schematic diagram of a conventional counting circuit in the prior art;

[0028] Figure 3 a circuit schematic diagram of a counting circuit in some embodiments of the application;

[0029] Figure 4 a circuit diagram of a counting circuit in further embodiments of the application;

[0030] Figure 5 a circuit schematic diagram of a 3-bit Gray code counter in some embodiments of the application;

[0031] Figure 6 a circuit diagram of a counting circuit in still further embodiments of the application;

[0032] Figure 7 a circuit schematic diagram of a 4-bit Gray code counter in some embodiments of the application;

[0033] Figure 8 a circuit diagram of a counting circuit in yet further embodiments of the application;

[0034] Figure 9 a circuit schematic diagram of a 2-bit Gray code counter in some embodiments of the application;

[0035] Figure 10 a schematic diagram of an N / m m-bit conversion circuit in some embodiments of the application;

[0036] Figure 11 a schematic diagram of four 3-bit conversion circuits in some embodiments of the application;

[0037] Figure 12 a circuit schematic diagram of an image sensor in some embodiments of the application;

[0038] Figure 13 Circuit diagram of readout circuit in some embodiments of the present application. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings by those skilled in the art. The words such as "comprise" and the like used herein mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, and do not exclude other elements or objects.

[0040] Figure 1 Circuit diagram of prior art counting circuit. Referring to Figure 1 , the prior art counting circuit 100 comprises a NAND gate 101 and a plurality of D flip-flops 102, the NAND gate 101 is used to receive a clock signal and a counting control signal, the plurality of D flip-flops 102 are cascaded, the clock terminal of the first stage D flip-flop 102 is connected with the output terminal of the NAND gate 101, the clock terminal of the next stage D flip-flop 102 is connected with the positive phase output terminal of the previous stage D flip-flop 102, and the inverting output terminal of the D flip-flop 102 is connected with the data input terminal thereof.

[0041] Figure 2 Timing diagram of prior art counting circuit. Referring to Figure 2 and Figure 3 , CLK is a clock signal, CTR_EN is a counting control signal, CLK_ACT is the output signal of the NAND gate, D<0> is the first bit output of the prior art counting circuit, D<1> is the second bit output of the prior art counting circuit, and D<2> is the third bit output of the prior art counting circuit. Wherein, the timing of D<3> and the following is not drawn in sequence.

[0042] Referring to Figure 1 and Figure 2 , according to the coding characteristics of binary, it can be known that the D flip-flop 102 of the prior art counting circuit 100 flips many times in the technical process, especially when counting to a large number code, for example, the 12-bit prior art counting circuit 100 counts to the maximum code 2 12The total number of times of toggling of the D flip-flop 102 is 8178 at -1. Since the counter circuit is a digital circuit, its power consumption is mainly contributed by dynamic power consumption caused by signal toggling. Thus, too many toggling times result in excessive dynamic power consumption of the binary counter circuit, especially when the counting clock frequency is high and the number of bits of the counter circuit is large.

[0043] In view of the problems in the prior art, embodiments of the present application provide a counting circuit. Figure 3 The counting circuit 200 comprises an NAND gate 201, at least one Gray code counter 202 and at least one conversion circuit (not shown in the figure). The NAND gate 201 is configured to receive a clock signal CLK and a counting control signal CTR_EN. The Gray code counters 202 are connected in cascade. The clock terminal of a lower-level Gray code counter 202 is connected to the carry output terminal of an upper-level Gray code counter 202. The clock terminal of the uppermost-level Gray code counter 202 is connected to the output terminal of the NAND gate 201. The conversion circuit is connected to the Gray code output terminal of the Gray code counter 202 in one-to-one correspondence, configured to receive a Gray code and then convert the Gray code into a binary code.

[0044] In some embodiments, the counting circuit is N-bit, the Gray code counter is m-bit, the number of the Gray code counters is N / m, and N, m and N / m are all natural numbers greater than 0.

[0045] Referring to Figure 3 The N-bit counting circuit is implemented by using a segmented encoding mode. Each segment is an m-bit Gray code counter 202, and the entire counting circuit 200 is divided into N / m segments. N / m Gray code counters 202 are connected in cascade, and N / m conversion circuits are connected to the Gray code output terminals of the Gray code counters 202 in one-to-one correspondence. The Gray code counter 202 is a Gray code plus 1 counter.

[0046] Referring to Figure 3 The Gray code output terminal of the first Gray code counter 202 outputs the low m-bit Q <m-1:0>The Gray code output end of the first Gray code counter outputs Q

[0047] With reference to Figure 3 The Gray code output end of the first Gray code counter outputs Q <m-1:0>The Gray code output end of the first Gray code counter outputs Q<2:0>, i.e. 0th to 2nd bits of the N-bit code output by the entire counting circuit; the Gray code output end of the second Gray code counter outputs Q<5:3>, i.e. 3rd to 5th bits of the N-bit code output by the entire counting circuit; the Gray code output end of the third Gray code counter outputs Q<8:6>, i.e. 6th to 8th bits of the N-bit code output by the entire counting circuit; and the Gray code output end of the N / mth Gray code counter outputs Q<N-1:N-m-1>, i.e. N-m-1th to N-1th bits of the N-bit code output by the entire counting circuit.

[0048] In some embodiments, the Gray code counter comprises at least two D flip-flops and a logic circuit, and the D flip-flops are connected to the logic circuit.

[0049] Figure 4 The circuit diagram of the counting circuit in some embodiments of the present application is shown in FIG. 2. Referring to FIG. 2, Figure 4 Taking a 12-bit counting circuit as an example, 4-segment coding is adopted, and each segment is a 3-bit Gray code counter, i.e. four 3-bit Gray code counters 202 are connected in cascade.

[0050] Referring to FIG. 3, Figure 4 The Gray code output end of the first Gray code counter 202 outputs Q<2:0>, i.e. 0th to 2nd bits of the 12-bit output code; the Gray code output end of the second Gray code counter 202 outputs Q<5:3>, i.e. 3rd to 5th bits of the 12-bit output code; the Gray code output end of the third Gray code counter 202 outputs Q<8:6>, i.e. 6th to 8th bits of the 12-bit output code; and the Gray code output end of the fourth Gray code counter 202 outputs Q<11:9>, i.e. 9th to 11th bits of the 12-bit output code.

[0051] Figure 5 The circuit schematic diagram of the 3-bit Gray code counter in some embodiments of the present application is shown in FIG. 4. Referring to FIG. 4, Figure 5 The Gray code counter 202 comprises three D flip-flops and a logic circuit, the three D flip-flops comprising a first D flip-flop 20211, a second D flip-flop 20212 and a third D flip-flop 20213, and the logic circuit comprising an NOR gate 20221, a first NAND gate 20222, a second NAND gate 20223, a third NAND gate 20224, a fourth NAND gate 20225, a fifth NAND gate 20226 and an XNOR gate 20227.

[0052] Referring to FIG. 5, Figure 5 The clock end of the first D flip-flop 20211, the clock end of the second D flip-flop 20212 and the clock end of the third D flip-flop 20213 are connected, as the clock end of the Gray code counter 202, the data input end of the first D flip-flop 20211 is connected with the output end of the XNOR gate 20227 and the first input end of the NAND gate 20221, the positive phase output end of the first D flip-flop 20211 is connected with the second input end of the second NAND gate 20223 and the first input end of the fourth NAND gate 20225, and the inverting output end of the first D flip-flop 20211 is connected with the first input end of the third NAND gate 20224.

[0053] Referring to Figure 5 The data input end of the second D flip-flop 20212 is connected with the output end of the first NAND gate 20222 and the second input end of the NAND gate 20221, the positive phase output end of the second D flip-flop 20212 is connected with the first input end of the XNOR gate 20227 and the second input end of the third NAND gate 20224, and the inverting output end of the second D flip-flop 20212 is left unconnected.

[0054] Referring to Figure 5 The data input end of the third D flip-flop 20213 is connected with the output end of the fifth NAND gate 20226 and the third input end of the NAND gate 20221, the positive phase output end of the third D flip-flop 20213 is connected with the second input end of the XNOR gate 20227 and the second input end of the fourth NAND gate 20225, and the inverting output end of the third D flip-flop 20213 is connected with the first input end of the second NAND gate 20223.

[0055] Referring to Figure 5 The output end of the second NAND gate 20223 is connected with the first input end of the first NAND gate 20222, the output end of the third NAND gate 20224 is connected with the first input end of the fifth NAND gate 20226, and the output end of the fourth NAND gate 20225 is connected with the second input end of the first NAND gate 20222 and the second input end of the fifth NAND gate 20226.

[0056] Figure 6 is a circuit diagram of a counting circuit in another embodiment of the present application. Referring to Figure 4 Taking a 12-bit counting circuit as an example, three 4-bit Gray code counters 202 are connected in cascade mode.

[0057] Referring to Figure 6 The gray code output end of the first gray code counter 202 outputs Q<3:0>, that is, 0th to 3rd bits of the 12-bit output code; the gray code output end of the second gray code counter 202 outputs Q<7:4>, that is, 4th to 7th bits of the 12-bit output code; and the gray code output end of the third gray code counter 202 outputs Q<11:8>, that is, 8th to 11th bits of the 12-bit output code.

[0058] Figure 7 FIG. 1 is a circuit schematic diagram of a 4-bit gray code counter according to an embodiment of the present application. Figure 7 The gray code counter comprises four D flip-flops and a logic circuit, wherein the four D flip-flops comprise a first D flip-flop 20211, a second D flip-flop 20212, a third D flip-flop 20213 and a fourth D flip-flop 20214, and the logic circuit comprises an NOR gate 20221, a first NAND gate 20222, a second NAND gate 20223, a third NAND gate 20224, a fourth NAND gate 20225, a fifth NAND gate 20226, an XNOR gate 20227, a sixth NAND gate 20228, a seventh NAND gate 20229, an eighth NAND gate 202210, a ninth NAND gate 202211, a tenth NAND gate 202212, an eleventh NAND gate 202213 and an XOR gate 202214.

[0059] FIG. 2 is a circuit schematic diagram of a 4-bit gray code counter according to another embodiment of the present application. Figure 7 The clock end of the first D flip-flop 20211, the clock end of the second D flip-flop 20212, the clock end of the third D flip-flop 20213 and the clock end of the fourth D flip-flop are connected, serving as the clock end of the gray code counter.

[0060] FIG. 2 is a circuit schematic diagram of a 4-bit gray code counter according to another embodiment of the present application. Figure 7 The data input end of the first D flip-flop 20211 is connected with the output end of the XOR gate 202214 and the first input end of the NOR gate 20221; the positive output end of the first D flip-flop 20211 is connected with the first input end of the second NAND gate 20223, the second input end of the fifth NAND gate 20226 and the second input end of the eighth NAND gate 202210; and the inverting output end of the first D flip-flop 20211 is connected with the second input end of the first NAND gate 20222, the third input end of the sixth NAND gate 20228 and the third input end of the tenth NAND gate 202212.

[0061] FIG. 2 is a circuit schematic diagram of a 4-bit gray code counter according to another embodiment of the present application. Figure 7 The data input end of the second D flip-flop 20212 is connected with the output end of the third NAND gate 20224 and the second input end of the NOR gate 20221, the positive phase output end of the second D flip-flop 20212 is connected with the first input end of the first NAND gate 20222, the second input end of the XOR gate 202214, the second input end of the sixth NAND gate 20228 and the second input end of the ninth NAND gate 202211, and the inverting output end of the second D flip-flop 20212 is connected with the second input end of the fourth NAND gate 20225 and the second input end of the tenth NAND gate 202212.

[0062] Referring to Figure 7 The data input end of the third D flip-flop 20213 is connected with the output end of the seventh NAND gate 20229 and the third input end of the NOR gate 20221, the positive phase output end of the third D flip-flop 20213 is connected with the second input end of the XNOR gate 20227, the first input end of the fourth NAND gate 20225, the first input end of the fifth NAND gate 20226 and the first input end of the tenth NAND gate 202212, and the inverting output end of the third D flip-flop 20213 is left unconnected.

[0063] Referring to Figure 7 The data input end of the fourth D flip-flop 20214 is connected with the output end of the eleventh NAND gate 202213 and the fourth input end of the NOR gate 20221, the positive phase output end of the fourth D flip-flop 20214 is connected with the first input end of the XNOR gate 20227, the first input end of the eighth NAND gate 202210 and the first input end of the ninth NAND gate 202211, and the inverting output end of the fourth D flip-flop 20214 is connected with the first input end of the sixth NAND gate 20228.

[0064] Figure 8 is a circuit diagram of a counting circuit in some embodiments of the present application. Referring to Figure 8 Taking a 12-bit counting circuit as an example, 6 segments of coding are adopted, and each segment is a 2-bit Gray code counter 202, i.e. 6 2-bit Gray code counters are connected in a cascading manner.

[0065] Referring to Figure 8 The gray code output end of the first gray code counter 202 outputs Q<1:0>, i.e. 0th to 1st bits of the 12-bit output code; the gray code output end of the second gray code counter 202 outputs Q<3:2>, i.e. 2nd to 3rd bits of the 12-bit output code; the gray code output end of the third gray code counter 202 outputs Q<5:4>, i.e. 4th to 5th bits of the 12-bit output code; the gray code output end of the fourth gray code counter 202 outputs Q<7:6>, i.e. 6th to 7th bits of the 12-bit output code; the gray code output end of the fifth gray code counter 202 outputs Q<9:8>, i.e. 8th to 9th bits of the 12-bit output code; and the gray code output end of the sixth gray code counter 202 outputs Q<11:10>, i.e. 10th to 11th bits of the 12-bit output code.

[0066] Figure 9 FIG. 2 is a circuit schematic diagram of a 2-bit gray code counter according to some embodiments of the present application. Figure 9 The gray code counter 202 comprises two D flip-flops and a logic circuit, the two D flip-flops comprising a first D flip-flop 20211 and a second D flip-flop 20212, and the logic circuit comprising an NOR gate 20221, wherein the clock end of the first D flip-flop 20211 and the clock end of the second D flip-flop 20212 are connected, serving as the clock end of the gray code counter 200.

[0067] FIG. 3 is a circuit schematic diagram of an N / m m-bit conversion circuit according to some embodiments of the present application. Figure 9 The non-inverted output end of the first D flip-flop 20211 is connected with the data input end of the second D flip-flop 20212 and the second input end of the NOR gate 20221, the data input end of the first D flip-flop 20211 is connected with the inverted output end of the second D flip-flop 20212 and the first input end of the NOR gate 20221, the inverted output end of the first D flip-flop 20211 is left floating, and the non-inverted output end of the second D flip-flop 20212 is left floating.

[0068] Figure 10 FIG. 3 is a circuit schematic diagram of an N / m m-bit conversion circuit according to some embodiments of the present application. Figure 10 The N / m m-bit conversion circuit 203 corresponds to the N / m m-bit gray code counter.

[0069] FIG. 3 is a circuit schematic diagram of an N / m m-bit conversion circuit according to some embodiments of the present application. Figure 10 The first conversion circuit 203 is connected with the gray code output end of the first gray code counter, for receiving the m-bit gray code G <m-1:0>i.e. 0th to (m-1)th bits of N-bit Golay code outputted by the mth Gray code counter, and then outputting the m-bit Golay code G <m-1:0>conversion into a binary code B of m bits <m-1:0>The first conversion circuit 203 is connected to the first gray code counter for receiving the m-bit gray code G<1:m> outputted by the first gray code counter, i.e. 0-bit to m-1-bit of the N-bit digital code outputted by the first conversion circuit 203; and the second conversion circuit 203 is connected to the second gray code counter for receiving the m-bit gray code G<2m-1:m> outputted by the second gray code counter, i.e. m-bit to 2m-1-bit of the N-bit gray code outputted by the second conversion circuit 203, and then outputting the m-bit gray code G <m-1:0>converts into a binary code B<2m-1:m> of m bits, i.e. m bits to 2m-1 bits of the N-bit digital code output by the N / mth conversion circuit 203; by analogy, the N / mth conversion circuit 203 is connected to the Gray code output end of the N / mth Gray code counter for receiving a Gray code G <n-1:n-m>i.e. N-m bits to N-1 bits of the N-bit Golay code output by the N / m of the Golay code counters, and then the m-bit Golay code G <n-1:n-m>converts the binary code B of m bits into a decimal number <n-1:n-m>N-m bits to N-1 bits of the N-bit digital code outputted by the N / m conversion circuits 203.

[0070] Figure 11 Fig. 4 is a schematic diagram of four 3-bit conversion circuits in some embodiments of the present application. Referring to Fig. 4, Figure 10 The four 3-bit conversion circuits 203 correspond to the four 3-bit Gray code counters.

[0071] Referring to Fig. 4, Figure 11 The Gray code output end of the first conversion circuit 203 connected to the first Gray code counter is used to receive the 3-bit Gray code G<2:0>, i.e. 0 bit to 2 bit of the 12-bit Gray code outputted by the four Gray code counters, and then convert the 12-bit Gray code G<2:0> into the 3-bit binary code B<2-1:0>, i.e. 0 bit to 2 bit of the 12-bit digital code outputted by the four conversion circuits 203.

[0072] Referring to Fig. 4, Figure 11 The Gray code output end of the second conversion circuit 203 connected to the second Gray code counter is used to receive the 3-bit Gray code G<5:3>, i.e. 3 bit to 5 bit of the 12-bit Gray code outputted by the four Gray code counters, and then convert the 12-bit Gray code G<5:3> into the 3-bit binary code B<5:3>, i.e. 3 bit to 5 bit of the 12-bit digital code outputted by the four conversion circuits 203.

[0073] Referring to Fig. 4, Figure 11 The Gray code output end of the third conversion circuit 203 connected to the third Gray code counter is used to receive the 3-bit Gray code G<8:6>, i.e. 6 bit to 8 bit of the 12-bit Gray code outputted by the four Gray code counters, and then convert the 12-bit Gray code G<8:6> into the 3-bit binary code B<8:6>, i.e. 6 bit to 8 bit of the 12-bit digital code outputted by the four conversion circuits 203.

[0074] Referring to Fig. 4, Figure 11 The Gray code output end of the fourth conversion circuit 203 connected to the fourth Gray code counter is used to receive the 3-bit Gray code G<11:9>, i.e. 9 bit to 11 bit of the 12-bit Gray code outputted by the four Gray code counters, and then convert the 12-bit Gray code G<11:9> into the 3-bit binary code B<11:9>, i.e. 9 bit to 11 bit of the 12-bit digital code outputted by the four conversion circuits 203.

[0075] Table 1 is a comparison table of encoding of four kinds of segmenting modes of the counting circuit.

[0076]

[0077]

[0078] In some embodiments, the number of flips of the N-bit binary counter to the maximum digital code is 2 N+1 In some embodiments, the number of flips of the N-bit binary counter to the maximum digital code is 2 m ×(2 N -1) / (2 m -1)-N / m.

[0079] In some embodiments, the number of flips of the 12-bit binary counter to the maximum digital code is 8178; the number of flips of the 3-stage 4-bit Gray code counter to the maximum digital code is 4365; the number of flips of the 4-stage 3-bit Gray code counter to the maximum digital code is 4676; and the number of flips of the 6-stage 2-bit Gray code counter to the maximum digital code is 5454. As can be seen, the number of flips is reduced, greatly reducing power. Refer to Figures 4-9 , the number of devices is increased, and the area occupied is not too large.

[0080] Figure 12 The figure is a circuit schematic diagram of an image sensor in some embodiments of the present application. Refer to Figure 8 , the image sensor 300 includes a pixel unit array 301, a ramp signal generation unit 302, and at least one readout circuit 303, the pixel unit array 301 is used for light sensing to generate a voltage signal VIN, the ramp signal generation unit 302 is used for generating a ramp signal VRAMP, and the readout circuit 303 is connected with the pixel unit array 301 and the ramp signal generation unit 302.

[0081] Refer to Figure 12 , the image sensor 300 further includes a storage and readout unit 304 connected with all the readout circuits 303, for storing and reading out digital signals.

[0082] Figure 13 The figure is a circuit schematic diagram of a readout circuit in some embodiments of the present application. Refer to Figure 13 , the readout circuit 303 includes a comparator 3031 and the counting circuit 200, the counting circuit 200 is connected with the output end of the comparator 3031, and the counting of the double-edge counting circuit is controlled by the output of the comparator 3031.

[0083] Refer to Figure 13 The readout circuit 303 further comprises a first capacitor 3032 and a second capacitor 3033, one end of the first capacitor 3032 is connected with the pixel unit array, for receiving a voltage signal VIN, the other end of the first capacitor 3032 is connected with the positive input end of the comparator 3031, one end of the second capacitor 3033 is connected with the slope signal generating unit, for receiving a slope signal VRAMP, the other end of the second capacitor 3033 is connected with the inverting input end of the comparator 3031.

[0084] While the embodiments of the application have been illustrated and described in detail, it will be apparent that various modifications and changes can be made to the embodiments without departing from the scope and spirit of the application. It should be understood that this application is not limited in its application to the details of construction, the arrangements of components, and the arrangement of steps set forth in the description or illustrated in the drawings. Rather, the application is capable of other embodiments and of being practiced or carried out in various ways.

Claims

1. A counting circuit, characterized in that, include: NAND gates are used to receive clock signals and counting control signals; At least one Gray code counter, wherein the Gray code counters are cascaded, the clock terminal of the next Gray code counter is connected to the carry output terminal of the previous Gray code counter, and the clock terminal of the top Gray code counter is connected to the output terminal of the NAND gate. as well as At least one conversion circuit is connected one-to-one with the Gray code output terminal of the Gray code counter to receive the Gray code and then convert the Gray code into binary code; When the Gray code counter is 2-bit, the Gray code counter includes two D flip-flops and a logic circuit. The two D flip-flops include a first D flip-flop and a second D flip-flop. The logic circuit includes a NOR gate. The clock terminals of the first D flip-flop and the second D flip-flop are connected as the clock terminals of the Gray code counter. The non-inverting output terminal of the first D flip-flop is connected to the data input terminal of the second D flip-flop and the second input terminal of the NOR gate. The data input terminal of the first D flip-flop is connected to the inverting output terminal of the second D flip-flop and the first input terminal of the NOR gate. When the Gray code counter is 3 bits, it includes three D flip-flops and logic circuitry. The three D flip-flops are a first D flip-flop, a second D flip-flop, and a third D flip-flop. The logic circuitry includes a NOR gate, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, and an XOR gate. The clock terminals of the first, second, and third D flip-flops are connected as the clock input of the Gray code counter. The data input of the first D flip-flop is connected to the output of the XOR gate and the first input of the NOR gate. The positive output of the first D flip-flop is connected to the second input of the second NAND gate and the first input of the fourth NAND gate. The inverted output of the first D flip-flop is connected to the first input of the third NAND gate. The data input terminal of the device is connected to the output terminal of the first NAND gate and the second input terminal of the NOR gate. The positive output terminal of the second D flip-flop is connected to the first input terminal of the XOR gate and the second input terminal of the third NAND gate. The data input terminal of the third D flip-flop is connected to the output terminal of the fifth NAND gate and the third input terminal of the NOR gate. The positive output terminal of the third D flip-flop is connected to the second input terminal of the XOR gate and the second input terminal of the fourth NAND gate. The inverted output terminal of the third D flip-flop is connected to the first input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the first input terminal of the first NAND gate. The output terminal of the third NAND gate is connected to the first input terminal of the fifth NAND gate. The output terminal of the fourth NAND gate is connected to the second input terminal of the first NAND gate and the second input terminal of the fifth NAND gate. When the Gray code counter is 4 bits, it includes four D flip-flops and logic circuitry. The four D flip-flops are a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop. The logic circuitry includes NOR gates, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, an XOR gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, and an XOR gate. The clock inputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop... The clock input of the first D flip-flop is connected to the clock input of the fourth D flip-flop, serving as the clock input of the Gray code counter. The data input of the first D flip-flop is connected to the output of the XOR gate and the first input of the NOR gate. The non-inverting output of the first D flip-flop is connected to the first input of the second NAND gate, the second input of the fifth NAND gate, and the second input of the eighth NAND gate. The inverting output of the first D flip-flop is connected to the second input of the first NAND gate, the third input of the sixth NAND gate, and the third input of the tenth NAND gate. The second D flip-flop... The data input terminal of the second D flip-flop is connected to the output terminal of the third NAND gate and the second input terminal of the NOR gate. The positive output terminal of the second D flip-flop is connected to the first input terminal of the first NAND gate, the second input terminal of the XOR gate, the second input terminal of the sixth NAND gate, and the second input terminal of the ninth NAND gate. The inverted output terminal of the second D flip-flop is connected to the second input terminal of the fourth NAND gate and the second input terminal of the tenth NAND gate. The data input terminal of the third D flip-flop is connected to the output terminal of the seventh NAND gate and the third input terminal of the NOR gate. The non-inverting output terminal of the flip-flop is connected to the second input terminal of the XOR gate, the first input terminal of the fourth NAND gate, the first input terminal of the fifth NAND gate, and the first input terminal of the tenth NAND gate. The data input terminal of the fourth D flip-flop is connected to the output terminal of the eleventh NAND gate and the fourth input terminal of the NOR gate. The non-inverting output terminal of the fourth D flip-flop is connected to the first input terminal of the XOR gate, the first input terminal of the eighth NAND gate, and the first input terminal of the ninth NAND gate. The inverting output terminal of the fourth D flip-flop is connected to the first input terminal of the sixth NAND gate.

2. The counting circuit according to claim 1, characterized in that, The counting circuit is N-bit, and the Gray code counter is m-bit, so the number of Gray code counters is N / m, where N, m, and N / m are all natural numbers greater than 0.

3. The counting circuit according to claim 1, characterized in that, The Gray code counter is a Gray code increment counter.

4. The counting circuit according to claim 1, characterized in that, The Gray code counter includes at least two D flip-flops and logic circuitry, with each D flip-flop connected to the logic circuitry.

5. A readout circuit, characterized in that, include: Comparator; as well as In the counting circuit according to any one of claims 1 to 4, one end of the NAND gate is connected to the output of the comparator for receiving the counting control signal.

6. An image sensor, characterized in that, include: A pixel unit array, used for light sensing to generate voltage signals; A ramp signal generation unit is used to generate ramp signals; as well as At least one readout circuit as described in claim 5 is connected to the pixel unit array and the ramp signal generating unit.

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