Pixel circuit and driving method thereof, display substrate, and display device

Abstract

A pixel circuit comprises: a light-emitting module configured to emit light; a driving module configured to drive the light-emitting module to emit light according to a driving voltage in a light-emitting stage; a storage module configured to maintain the driving voltage in the light-emitting stage and provide the driving voltage to the driving module; a first transistor (T1), wherein a first electrode of the first transistor (T1) is connected to a position where the driving module obtains the driving voltage; a second transistor (T2), wherein a first electrode of the second transistor (T2) is connected to a first electrode of the first transistor (T1), and a second electrode of the second transistor (T2) is not directly connected to a signal source; and a voltage-stabilizing capacitor (C1), wherein a first electrode of the voltage-stabilizing capacitor (C1) is connected to a second electrode of the second transistor (T2), and a second electrode of the voltage-stabilizing capacitor (C1) is connected to a constant voltage signal source (VDC).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of pixel circuits, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] In an organic light emitting diode (OLED) display substrate, during the light emission stage, a certain driving voltage is applied to the gate of the driving transistor to make the organic light emitting diode emit a corresponding brightness for display. However, during the display stage, the gate voltage of the driving transistor may change due to the presence of leakage current, thereby causing the brightness of the organic light emitting diode to change, resulting in flickering, which affects the display quality. Summary of the invention

[0003] Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a pixel circuit, comprising:

[0005] A light emitting module configured to emit light;

[0006] A driving module, configured to drive the light-emitting module to emit light according to a driving voltage during a light-emitting phase;

[0007] a storage module, the storage module being configured to maintain the driving voltage during the light emitting stage and provide the driving voltage to the driving module;

[0008] a first transistor, wherein a first electrode of the first transistor is connected to a position where the driving module obtains the driving voltage;

[0009] a second transistor, wherein a first electrode of the second transistor is connected to the first electrode of the first transistor, and a second electrode of the second transistor is not directly connected to the signal source;

[0010] A voltage-stabilizing capacitor, wherein a first electrode of the voltage-stabilizing capacitor is connected to a second electrode of the second transistor, and a second electrode of the voltage-stabilizing capacitor is connected to a constant voltage signal source.

[0011] In some embodiments, the pixel circuit further comprises:

[0012] a third transistor, wherein a first electrode of the third transistor is connected to the second electrode of the first transistor, and a gate of the third transistor is connected to the gate of the first transistor;

[0013] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the second electrode of the second transistor, and a gate of the fourth transistor is connected to the gate of the second transistor;

[0014] The light emitting module comprises a light emitting device;

[0015] The driving module includes a driving transistor, and the driving transistor is configured to drive the light emitting device to emit light according to a voltage of a gate thereof;

[0016] The storage module comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and the storage capacitor is configured to maintain the driving voltage at its first electrode during the light emitting stage and provide the driving voltage to the driving module.

[0017] In some embodiments, the pixel circuit includes a first reset module and a write module;

[0018] The first reset module is configured to reset the voltage of the gate of the driving transistor according to the signals of the initialization signal terminal and the first reset signal terminal; the first reset module includes:

[0019] the first transistor;

[0020] the third transistor, wherein a first electrode of the third transistor is connected to a second electrode of the first transistor, a second electrode of the third transistor is connected to the initialization signal terminal, and a gate of the third transistor is connected to the gate of the first transistor and the first reset signal terminal;

[0021] The writing module is configured to write the driving voltage to the first electrode of the storage capacitor according to the signals of the gate signal terminal and the data signal terminal; the writing module comprises:

[0022] the second transistor;

[0023] the fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the second transistor, a second electrode of the fourth transistor is connected to a second electrode of the driving transistor, and a gate of the fourth transistor is connected to a gate of the second transistor and the gate signal terminal;

[0024] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first electrode of the driving transistor, a second electrode of the fifth transistor is connected to the data signal terminal, and a gate of the fifth transistor is connected to the gate signal terminal;

[0025] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a gate of the sixth transistor is connected to the control signal terminal;

[0026] in,

[0027] The driving transistor and the light emitting device are connected in series between the first power signal terminal and the second power signal terminal;

[0028] The second electrode of the storage capacitor is connected to the first power signal terminal;

[0029] The second electrode of the light emitting device is connected to the second power signal terminal.

[0030] In some embodiments, the constant voltage signal source is any one of the initialization signal terminal, the first power signal terminal, and the second power signal terminal.

[0031] In some embodiments, the pixel circuit further comprises:

[0032] A control module, wherein the control module is configured to control whether the light-emitting device emits light according to the signal at the control signal terminal; the control module comprises: a seventh transistor, wherein a first electrode of the seventh transistor is connected to a second electrode of the driving transistor, a second electrode of the seventh transistor is connected to a first electrode of the light-emitting device, and a gate of the seventh transistor is connected to the control signal terminal;

[0033] A second reset module, the second reset module is configured to reset the voltage of the first electrode of the light-emitting device according to the signals of the second reset signal terminal and the initialization signal terminal; the second reset module includes: an eighth transistor, the first electrode of the eighth transistor is connected to the first electrode of the light-emitting device, the second electrode of the eighth transistor is connected to the initialization signal terminal, and the gate of the eighth transistor is connected to the second reset signal terminal.

[0034] In some embodiments, the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type transistors;

[0035] or,

[0036] The driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

[0037] In a second aspect, an embodiment of the present disclosure provides a method for driving a pixel circuit, wherein the pixel circuit is any one of the above pixel circuits, and the method for driving the pixel circuit includes:

[0038] In the light emitting stage, the storage module is enabled to maintain the driving voltage and provide the driving voltage to the driving module.

[0039] In some embodiments, the driving method of the pixel circuit includes:

[0040] continuously providing an initialization signal to the initialization signal terminal, continuously providing a first power signal to the first power signal terminal, and continuously providing a second power signal to the second power signal terminal;

[0041] In the reset phase, a turn-on signal is provided to the first reset signal terminal, a turn-off signal is provided to the gate signal terminal, and a turn-off signal is provided to the control signal terminal;

[0042] In the writing phase, a shutoff signal is provided to the first reset signal terminal, a turn-on signal is provided to the gate signal terminal, a shutoff signal is provided to the control signal terminal, and a data signal is provided to the data signal terminal;

[0043] In the light emitting stage, a shutoff signal is provided to the first reset signal terminal, a shutoff signal is provided to the gate signal terminal, and a turn-on signal is provided to the control signal terminal.

[0044] In some embodiments, the driving method of the pixel circuit further includes:

[0045] In the reset phase, providing a shutdown signal to the second reset signal terminal;

[0046] In the writing phase, providing a conduction signal to the second reset signal terminal;

[0047] In the light emitting phase, a shutoff signal is provided to the second reset signal terminal.

[0048] In a third aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0049] substrate;

[0050] A plurality of sub-pixels are disposed on the substrate, and at least some of the sub-pixels include any one of the above-mentioned pixel circuits.

[0051] In some embodiments, the first electrode of the voltage-stabilizing capacitor includes: a connecting portion connected between the second electrode of the second transistor and the first electrode of the fourth transistor, and the connecting portion has a plurality of bending structures.

[0052] In some embodiments, the first electrode of the voltage-stabilizing capacitor and the second electrode of the second transistor are arranged in the same layer and are connected as a whole.

[0053] In some embodiments, the first electrode of the voltage-stabilizing capacitor is disposed in the same layer as the active region of the driving transistor, and the first electrode of the voltage-stabilizing capacitor is a conductive semiconductor material;

[0054] The second electrode of the second transistor is arranged in the same layer as the active region of the driving transistor, and the second electrode of the second transistor is a conductive semiconductor material.

[0055] In some embodiments, the second electrode of the voltage-stabilizing capacitor is disposed on the same layer as the initialization signal terminal.

[0056] In some embodiments, in a direction gradually away from the base, the display substrate sequentially includes:

[0057] The active area of ​​the driving transistor and the first electrode of the voltage stabilizing capacitor;

[0058] a gate insulating layer;

[0059] a gate of the driving transistor;

[0060] a first interlayer insulating layer;

[0061] The second electrode of the voltage stabilizing capacitor and the initialization signal terminal.

[0062] In some embodiments, the second electrode of the voltage-stabilizing capacitor is connected to the second electrode of the storage capacitor.

[0063] In some embodiments, the initialization signal terminal includes a first initialization signal terminal and a second initialization signal terminal arranged in the same layer, and the first initialization signal terminal and the second initialization signal terminal are arranged in parallel and spaced apart;

[0064] The second electrode of the eighth transistor is connected to the first initialization signal terminal;

[0065] The second electrode of the third transistor is connected to the second initialization signal terminal.

[0066] In some embodiments, the first reset signal terminal extends along a first direction;

[0067] The first reset signal end of at least part of the pixel circuits is multiplexed as the second reset signal end of the pixel circuits adjacent to the pixel circuit along a second direction; the first direction intersects the second direction.

[0068] In some embodiments, the second electrode of the storage capacitor includes a horizontal connection structure extending along the first direction; at least part of the horizontal connection structures of the pixel circuits adjacent to each other along the first direction are connected to each other;

[0069] The first power signal end extends along a second direction; the first direction intersects with the second direction.

[0070] In some embodiments, the display substrate further comprises:

[0071] An auxiliary conductive structure is arranged to overlap with the first power signal terminal; at least one insulating layer is arranged between the auxiliary conductive structure and the first power signal terminal, and the auxiliary conductive structure is connected to the first power signal terminal through a via in the insulating layer.

[0072] In some embodiments, in a direction gradually away from the base, the display substrate sequentially includes:

[0073] A semiconductor layer, comprising: a first electrode, a second electrode, and an active area of ​​the driving transistor, a first electrode, a second electrode, and an active area of ​​the first transistor, a first electrode, a second electrode, and an active area of ​​the second transistor, a first electrode, a second electrode, and an active area of ​​the third transistor, a first electrode, a second electrode, and an active area of ​​the fourth transistor, a first electrode, a second electrode, and an active area of ​​the fifth transistor, a first electrode, a second electrode, and an active area of ​​the sixth transistor, a first electrode, a second electrode, and an active area of ​​the seventh transistor, a first electrode, a second electrode, and an active area of ​​the eighth transistor, and a first electrode of the voltage-stabilizing capacitor; wherein the first electrode of the voltage-stabilizing capacitor is connected to the second electrode of the second transistor as a whole, and both are conductive semiconductor materials;

[0074] a gate insulating layer;

[0075] A first gate layer, comprising: a gate of the driving transistor, a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, a gate of the sixth transistor, a gate of the seventh transistor, a gate of the eighth transistor, the first reset signal terminal, the second reset signal terminal, the control signal terminal, and a first electrode of the storage capacitor;

[0076] a first interlayer insulating layer;

[0077] The second gate layer includes: the initialization signal terminal, the second electrode of the voltage-stabilizing capacitor, and the second electrode of the storage capacitor;

[0078] a second interlayer insulating layer;

[0079] A first source-drain layer, comprising: the first power signal terminal, the data signal terminal, a first light-emitting access structure, and a voltage-stabilizing connection structure; wherein the first power signal terminal is connected to the second electrode of the storage capacitor through a via hole in the second interlayer insulating layer, and is connected to the first electrode of the sixth transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer; the data signal terminal is connected to the second electrode of the fifth transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the first light-emitting access structure is connected to the second electrode of the seventh transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the voltage-stabilizing connection structure is connected to the second electrode of the storage capacitor through a via hole in the second interlayer insulating layer, and is connected to the second electrode of the voltage-stabilizing capacitor through a via hole in the second interlayer insulating layer;

[0080] a first planarization layer;

[0081] A second source-drain layer, comprising: an auxiliary conductive structure and a second light-emitting access structure; wherein the auxiliary conductive structure overlaps with the first power signal terminal and is connected to the first power signal terminal through a via hole in the first planarization layer; and the second light-emitting access structure is connected to the first light-emitting access structure through a via hole in the first planarization layer;

[0082] a second planarization layer;

[0083] The first electrode of the light emitting device is connected to the second light emitting access structure through a via hole in the second planarization layer.

[0084] In some embodiments, the first source and drain layer further comprises:

[0085] a first connection structure, wherein the first connection structure is connected to the second electrode of the eighth transistor through the via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and is connected to the initialization signal terminal through the via hole in the second interlayer insulating layer;

[0086] a second connection structure, wherein the second connection structure is connected to the second electrode of the third transistor through the gate insulation layer, the first interlayer insulation layer, and the via hole in the second interlayer insulation layer, and is connected to the initialization signal terminal through the via hole in the second interlayer insulation layer;

[0087] A third connection structure, wherein the third connection structure is connected to the gate of the driving transistor through vias in the first interlayer insulating layer and the second interlayer insulating layer, and is connected to the first electrode of the first transistor through vias in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

[0088] In a fourth aspect, an embodiment of the present disclosure provides a display device, comprising:

[0089] Any of the above display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0091] Figure 1 A circuit diagram of a pixel circuit in the related art;

[0092] Figure 2 A simulation result diagram of the change of part of the signal in a pixel circuit over time in the related art;

[0093] Figure 3 A simulation result diagram of the change of light emission brightness over time in a pixel circuit in the related art;

[0094] Figure 4 A circuit diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0095] Figure 5 A driving timing diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0096] Figure 6 A simulation result diagram of the change of part of the signal over time when the capacitance value of the voltage-stabilizing capacitor is different in a pixel circuit provided by an embodiment of the present disclosure;

[0097] Figure 7 A circuit diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0098] Figure 8 A driving timing diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0099] Fig. 9 A simulation result diagram of the change of the Flicker value in a pixel circuit according to the capacitance value of a voltage-stabilizing capacitor provided in an embodiment of the present disclosure;

[0100] Fig.10 A perspective structural diagram of a partial structure of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0101] Fig.11 A schematic diagram of the structure of a POLY layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0102] Fig.12 A schematic structural diagram of a first gate layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0103] Fig.13 A schematic structural diagram of a second gate layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0104] Fig.14 A perspective structural diagram of a structure constituting a voltage-stabilizing capacitor in a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0105] Fig.15 A schematic structural diagram of a first source-drain layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0106] Fig.16 A schematic structural diagram of a second source-drain layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0107] Fig.17 A schematic diagram of the via distribution of a gate insulating layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0108] Fig.18 A schematic diagram of the via distribution of a first interlayer insulating layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0109] Fig.19 A schematic diagram of the via distribution of a second interlayer insulating layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0110] Fig. 20 A schematic diagram of the via distribution of a first planarization layer (also a passivation layer) of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0111] Fig.21 A schematic diagram of the via distribution of a second planarization layer of a pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0112] The meanings of the reference numerals used in the embodiments of the present disclosure are as follows:

[0113] TD, driving transistor; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; OLED, organic light emitting diode;

[0114] Cst, storage capacitor; C1, voltage stabilizing capacitor;

[0115] N1, first node; N2, first node; N3, third node;

[0116] GATE, gate signal terminal; DATA, data signal terminal; RESET1, first reset signal terminal; RESET2, second reset signal terminal; INIT, initialization signal terminal; INIT1, first initialization signal terminal; INIT2, second initialization signal terminal; EM, control signal terminal; VDD, first power signal terminal; VSS, second power signal terminal; VDC, constant voltage signal source;

[0117] 11. Connecting part; 2. Light-emitting device; 31. Auxiliary conductive structure; 32. Horizontal connection structure; 331. First light-emitting access structure; 332. Second light-emitting access structure; 34. Voltage-stabilizing connection structure; 351. First connection structure; 352. Second connection structure; 353. Third connection structure. DETAILED DESCRIPTION

[0118] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the pixel circuit and its driving method, display substrate, and display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0119] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0120] The embodiments of the present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0121] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0122] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0123] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0124] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0125] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0126] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0127] Technical terminology

[0128] In this disclosure, unless otherwise specified, the following technical terms should be understood as follows:

[0129] "Transistor" may specifically be a "Thin Film Transistor (TFT)", which refers to a device comprising at least three terminals: a gate, a drain, and a source, and an active region connected between the source and the drain; wherein, by controlling the voltage relationship between the gate, the source, and the drain, the drain and the source can be insulated so that current cannot flow through (i.e., the transistor is turned off), or current can flow from the source through the active region to the drain (i.e., the transistor is turned on).

[0130] The "drain and source of the transistor" are distinguished by the direction of current flow, so for the transistor device itself, there is no clear source and drain when there is no signal; therefore, in the embodiment of the present disclosure, the first electrode and the second electrode are used to represent the source and drain of the transistor, but there is no necessary corresponding relationship between the first electrode, the second electrode and the source and the drain.

[0131] "Signal terminal" refers to a structure in a pixel circuit that is connected to other external signal sources to provide a corresponding signal. Therefore, a signal terminal is not necessarily a "terminal" or a "connection terminal", but may include all structures connected to the corresponding signal source. For example, the signal terminal may be an integrated structure with the corresponding signal line, or the portion of the signal line in the pixel circuit is the signal terminal. At the same time, the signal terminal and the structure connected thereto may also be integrated. For example, if the signal terminal (such as a gate signal terminal) provides a gate signal for a transistor, the portion of the signal terminal that overlaps with the active area of ​​the transistor may also be the gate of the transistor.

[0132] “Signal source” refers to any “source” that can provide the required signal, which can be the above-mentioned “signal terminal”.

[0133] “Two structures are connected” means that the two structures are directly connected by contact with each other, or they can be indirectly connected through other conductive structures; however, in the embodiments of the present disclosure, structures indirectly connected through devices such as transistors that are not necessarily conductive are not considered to be connected to each other.

[0134] "Node" refers to all structures in a pixel circuit that can be electrically considered as a whole; for example, interconnected electrodes and the connection structure between electrodes are all a "node", but the first and second electrodes of a transistor are different nodes if they are not interconnected.

[0135] A “turn-on signal” refers to a signal that, when loaded to the gate of a transistor, can turn on the transistor; for example, for a P-type transistor, the turn-on signal is a low-level signal, and for an N-type transistor, the turn-on signal is a high-level signal.

[0136] A “shutdown signal” refers to a signal that, when loaded onto the gate of a transistor, can shut down the transistor; for example, for a P-type transistor, the shutdown signal is a high-level signal, and for an N-type transistor, the shutdown signal is a low-level signal.

[0137] Multiple structures "arranged in the same layer" means that the multiple structures are formed by the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that they and other layer structures between the substrate are exactly the same.

[0138] "Patterning process" refers to the steps of forming a structure with a specific pattern, which may be a photolithography process, which includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and photoresist stripping; of course, the patterning process may also be other processes such as an imprinting process and an inkjet printing process.

[0139] Related technologies

[0140] In some related technologies, each sub-pixel of an organic light emitting diode (OLED) display substrate includes a pixel circuit, and the pixel circuit includes an organic light emitting diode for emitting light, that is, the organic light emitting diode emits light required by each sub-pixel.

[0141] A feasible pixel circuit structure can refer to Figure 1, wherein the driving transistor TD controls the current flowing according to the voltage of its own gate, which is the driving current Ioled for the organic light emitting diode OLED to emit light, so the driving transistor TD drives the organic light emitting diode OLED to emit light according to the driving voltage. In the light emitting stage, the storage capacitor Cst keeps the gate of the driving transistor TD at the required driving voltage.

[0142] Reference Figure 1 , the first electrode of the gate of the driving transistor TD is also connected to the second node N2 and the third node N3 through the first transistor T1 and the second transistor T2 respectively. In the light-emitting stage, the voltages of the second node N2 and the third node N3 are usually different. For example, the voltage of the second node N2 may be lower than the voltage of the first node N1, while the voltage of the third node N3 is higher than the voltage of the first node N1. Since the first transistor T1 and the second transistor T2 inevitably have a certain leakage current, the second node N2 will gradually "pull down" the voltage of the first node N1 due to the leakage current of the first transistor T1, and the third node N3 will gradually "pull up" the voltage of the first node N1 due to the leakage current of the second transistor T2. Moreover, the "pull up" of the third node N3 is usually stronger than the "pull down" of the second node N2.

[0143] Therefore, in the pixel circuit of the related art, the simulation results of the changes of some signals over time in the light-emitting stage are referred to Figure 2 It can be seen that in the light emitting stage, the voltage of the first node N1 will gradually increase, that is, the driving voltage will increase suddenly, thereby reducing the driving current Ioled flowing through the organic light emitting diode OLED. Further, the brightness change of the light emitted by the pixel circuit in multiple frames refers to Figure 3 It can be seen that in each frame (in each light-emitting stage), the light-emitting brightness of the organic light-emitting diode OLED decreases.

[0144] Therefore, when the above brightness reduction reaches a level that can be perceived by human eyes, it will cause flickering, affecting the display quality.

[0145] Specific implementation methods of the present disclosure

[0146] First, refer to Figures 4 to 8 , an embodiment of the present disclosure provides a pixel circuit, which includes:

[0147] A light emitting module configured to emit light;

[0148] A driving module, configured to drive the light-emitting module to emit light according to a driving voltage during a light-emitting phase;

[0149] A storage module, the storage module is configured to maintain a driving voltage during a light emitting stage and provide a driving voltage to the driving module;

[0150] A first transistor T1, a first electrode of the first transistor T1 is connected to a position where a driving module obtains a driving voltage;

[0151] a second transistor T2, wherein a first electrode of the second transistor T2 is connected to a first electrode of the first transistor T1, and a second electrode of the second transistor T2 is not directly connected to the signal source;

[0152] A voltage stabilizing capacitor C1, a first electrode of the voltage stabilizing capacitor C1 is connected to a second electrode of the second transistor T2, and a second electrode of the voltage stabilizing capacitor C1 is connected to a constant voltage signal source VDC.

[0153] In the pixel circuit of the embodiment of the present disclosure, the driving module drives the light-emitting module to emit light according to the driving voltage (such as the voltage of the gate of the driving transistor TD) during the light-emitting stage, and the storage module is used to maintain and provide the driving voltage during the light-emitting stage.

[0154] Among them, the first electrodes of the first transistor T1 and the second transistor T2 are both connected to the position where the driving module provides the driving voltage (such as the first node N1, that is, the gate of the driving transistor TD), and their second electrodes are connected to different positions (such as the second node N2 and the third node N3, respectively); thus, the second node N2 will cause the voltage of the first node N1 to change due to the leakage current of the first transistor T1, and the third node N3 will cause the voltage of the first node N1 to change due to the leakage current of the second transistor T2.

[0155] Obviously, the second electrode of the first transistor T1 and the second electrode of the second transistor T2 should be connected to different structures respectively, that is, the first transistor T1 and the second transistor T2 should not be connected in parallel.

[0156] Among them, in the light-emitting stage, the voltage of the second electrode (second node N2) of the first transistor T1 is lower than the voltage of the first electrode (first node N1) of the first transistor T1 (i.e., the driving voltage), and the voltage of the second electrode (third node) of the second transistor T1 is higher than the voltage of the first electrode (first node N1) of the first transistor T1, so the second node N2 and the third node N3 respectively "pull down" and "pull up" the voltage of the first node N1.

[0157] As mentioned above, in some related technologies, the "pull-up" capability of the third node N3 is stronger than the "pull-down" capability of the second node N2, so Figure 2 , Figure 3 In the light emitting stage, the voltage (driving voltage) of the first node N1 will gradually increase, thereby causing a change in display brightness.

[0158] In the disclosed embodiment, the second pole (third node N3) of the second transistor T2 is not directly connected to the signal source, so its voltage is also variable during the light-emitting stage. In the disclosed embodiment, a voltage-stabilizing capacitor C1 is connected to the second pole (third node N3) of the second transistor T2, and the other pole (second pole) of the voltage-stabilizing capacitor C1 is connected to the constant-voltage signal source VDC, that is, connected to any signal source that provides a constant voltage in one frame. Obviously, since the second pole of the voltage-stabilizing capacitor C1 is a constant-voltage signal, it can prevent the voltage of the first pole of the capacitor (that is, the third node N3) from changing, and the larger the capacitance value of the voltage-stabilizing capacitor C1, the stronger the blocking effect.

[0159] Of course, in practice, the structure at the third node N3 itself may also have a certain parasitic capacitance, but the capacitance value of the parasitic capacitance is very small (usually not exceeding 1.5fF), and its other pole is not connected to the constant voltage signal source VDC, so the parasitic capacitance is different from the above-mentioned voltage stabilizing capacitor C1.

[0160] It can be seen that in the embodiment of the present disclosure, by adding a "capacitor (voltage-stabilizing capacitor C1)" to the second electrode (third node N3) of the second transistor T2, the signal stability of the third node N3 can be enhanced, thereby maintaining a "lower" voltage in the light-emitting stage to reduce its ability to "pull up" the voltage of the first node N1, so that the "pull down" and "pull up" effects on the first node N1 tend to be balanced, and then the voltage (driving voltage) of the first node N1 can be better maintained stable in the light-emitting stage, reducing the change in the brightness of the light emitted by the light-emitting device 2, so as to improve or avoid the flicker phenomenon and improve the display quality.

[0161] Therefore, in the pixel circuit of the embodiment of the present disclosure, when the capacitance values ​​of the voltage stabilizing capacitor C1 are 1fF (femtofarad), 1.5fF, 3fF, and 5fF, respectively, the simulation results of the change of some signals over time in the light emitting stage are as follows: Figure 6 .

[0162] The voltage of the third node N3 may "jump" higher due to coupling with other signals (such as the signal of the gate signal terminal GATE), resulting in a higher initial voltage in the light-emitting stage; Figure 6It can be seen that the larger the capacitance value of the voltage-stabilizing capacitor C1 is, the lower the initial voltage of the third node N3 in the light-emitting stage is. This indicates that by increasing the voltage-stabilizing capacitor C1, the ability of the third node N3 to resist the above "jump" can be improved, thereby reducing the initial voltage of the third node N3 in the light-emitting stage, that is, the voltage of the third node N3 can be relatively maintained at a "lower" level in the light-emitting stage, reducing its ability to "pull up" the voltage (driving voltage) of the first node N1, reducing the change in the voltage of the first node N1, and stabilizing the driving current Ioled, that is, stabilizing the luminous brightness of the light-emitting device 2 in the light-emitting stage, so as to improve or avoid the flicker phenomenon and improve the display quality.

[0163] Furthermore, when the capacitance value of the voltage stabilizing capacitor C1 is different, the simulated Flicker value is referenced to Fig. 9 The Flicker value is a dimensionless value calculated based on the brightness-time variation curve in the light-emitting stage, which is used to indicate the degree of flicker of the display. The lower the value, the smaller the flicker, that is, the more stable the brightness and the better the display quality.

[0164] It can be seen that as the capacitance of the voltage stabilizing capacitor C1 increases, the Flicker value can be greatly reduced, that is, the flicker degree can be reduced.

[0165] Reference Figure 4 , Figure 7 , some available specific forms of the pixel circuit of the embodiment of the present disclosure are introduced below.

[0166] In some embodiments, the pixel circuit further comprises:

[0167] The third transistor T3 has a first electrode connected to the second electrode of the first transistor T1 , and a gate of the third transistor T3 connected to the gate of the first transistor T1 .

[0168] In the embodiment of the present disclosure, the above second node N2 can be a node between the first transistor T1 and the third transistor T3, and the gates of the first transistor T1 and the third transistor T3 are connected to each other, so that the two constitute a "dual-gate transistor", that is, the second node N2 can be the middle node of the dual-gate transistor.

[0169] In some embodiments, the pixel circuit further comprises:

[0170] The fourth transistor T4 has a first electrode connected to the second electrode of the second transistor T2 and a gate connected to the gate of the second transistor T2.

[0171] In the embodiment of the present disclosure, the third node N3 may be a node between the second transistor T2 and the fourth transistor T4, and the gates of the second transistor T2 and the fourth transistor T4 are connected to each other, so that the two constitute a "dual-gate transistor", that is, the third node N3 may be the middle node of the dual-gate transistor.

[0172] The middle node of the dual-gate transistor is usually not directly connected to other signal sources, so its ability to maintain its own voltage is relatively weak, and it is more suitable to adopt the voltage-stabilizing capacitor C1 of the embodiment of the present disclosure.

[0173] In some embodiments, the light emitting module includes a light emitting device 2;

[0174] The driving module includes a driving transistor TD, and the driving transistor TD is configured to drive the light emitting device 2 to emit light according to the voltage of its gate;

[0175] The storage module includes a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the gate of the driving transistor TD, and the storage capacitor Cst is configured to maintain a driving voltage at its first electrode during the light emitting stage and provide the driving voltage to the driving module.

[0176] In some embodiments, the light emitting device 2 is an organic light emitting diode OLED.

[0177] As one embodiment of the present disclosure, the above driving module may include a driving transistor TD, the storage module may include a storage capacitor Cst, and the light emitting device 2 may be an organic light emitting diode OLED (OLED).

[0178] In the embodiment of the present disclosure, the light emitting device 2 is an organic light emitting diode OLED for example. Of course, it is also feasible if the light emitting device 2 is in other forms.

[0179] In some embodiments, the pixel circuit includes a first reset module and a write module;

[0180] The first reset module is configured to reset the voltage of the gate of the driving transistor TD according to the signal of the initialization signal terminal INIT and the first reset signal terminal RESET1; the first reset module includes:

[0181] A first transistor T1;

[0182] a third transistor T3, wherein a first electrode of the third transistor T3 is connected to a second electrode of the first transistor T1, a second electrode of the third transistor T3 is connected to an initialization signal terminal INIT, and a gate of the third transistor T3 is connected to a gate of the first transistor T1 and a first reset signal terminal RESET1;

[0183] The writing module is configured to write a driving voltage to the first electrode of the storage capacitor Cst according to the signal of the gate signal terminal GATE and the data signal terminal DATA; the writing module includes:

[0184] A second transistor T2;

[0185] a fourth transistor T4, wherein a first electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2, a second electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor TD, and a gate of the fourth transistor T4 is connected to the gate of the second transistor T2 and the gate signal terminal GATE;

[0186] a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is connected to a first electrode of the driving transistor TD, a second electrode of the fifth transistor T5 is connected to a data signal terminal DATA, and a gate of the fifth transistor T5 is connected to a gate signal terminal GATE;

[0187] a sixth transistor T6, wherein a first electrode of the sixth transistor T6 is connected to the first power signal terminal VDD, a second electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor TD, and a gate of the sixth transistor T6 is connected to the control signal terminal EM;

[0188] in,

[0189] The driving transistor TD and the light emitting device 2 are connected in series between the first power signal terminal VDD and the second power signal terminal VSS;

[0190] The second electrode of the storage capacitor Cst is connected to the first power signal terminal VDD;

[0191] The second electrode of the light emitting device 2 is connected to the second power signal terminal VSS.

[0192] The first power signal terminal VDD and the second power signal terminal VSS are used to provide the light emitting device 2 with an operating voltage for display.

[0193] For example, the first power signal terminal VDD may provide a first power signal Vdd, or a positive voltage signal, and the second power signal terminal VSS may provide a second power signal Vdd, or a negative voltage signal (such as a ground signal). Thus, the first electrode of the light emitting device 2 may be its positive electrode (such as an anode of an organic light emitting diode OLED), and the second electrode of the light emitting device 2 may be its negative electrode (such as a cathode of an organic light emitting diode OLED).

[0194] In some embodiments, the pixel circuit further includes a control module, which is configured to control whether the light-emitting device 2 emits light according to a signal at the control signal terminal EM; the control module includes:

[0195] The seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the second electrode of the driving transistor TD, a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device 2, and a gate of the seventh transistor T7 is connected to the control signal terminal EM.

[0196] In some embodiments, the pixel circuit further includes a second reset module, which is configured to reset the voltage of the first electrode of the light emitting device 2 according to the signal of the second reset signal terminal RESET2 and the initialization signal terminal INIT; the second reset module includes:

[0197] The eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the first electrode of the light emitting device 2, the second electrode of the eighth transistor T8 is connected to the initialization signal terminal INIT, and the gate of the eighth transistor T8 is connected to the second reset signal terminal RESET2.

[0198] As one embodiment of the present disclosure, the pixel circuit may further include other modules such as a control module and a second reset module.

[0199] In some embodiments, the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type transistors;

[0200] or,

[0201] The driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors.

[0202] When the pixel circuit is in the above specific form, for the sake of simplicity, each transistor therein can be an N-type transistor or a P-type transistor.

[0203] In some embodiments, the constant voltage signal source VDC is any one of the initialization signal terminal INIT, the first power signal terminal VDD, and the second power signal terminal VSS.

[0204] When the pixel circuit is in the above specific form, the constant voltage signal source VDC connected to the second electrode of the voltage-stabilizing capacitor C1 can be an existing signal source in the pixel circuit, such as the initialization signal terminal INIT (stable as the initialization signal Vinit), the first power signal terminal VDD (stable as the first power signal Vdd), the second power signal terminal VSS (stable as the second power signal Vss), etc., which will not be described in detail here.

[0205] Among them, the driving method and working principle of the above pixel circuit will be introduced later.

[0206] Second, refer to Figures 4 to 8 The embodiment of the present disclosure provides a driving method of a pixel circuit, the pixel circuit is any one of the above-mentioned pixel circuits, and the driving method of the pixel circuit includes:

[0207] In the light emitting stage, the storage module is maintained at a driving voltage, and a driving voltage is provided to the driving module.

[0208] In the embodiment of the present disclosure, the storage module is made to maintain the driving voltage during the light-emitting stage, and the driving voltage is provided to the driving module to drive the light-emitting device 2 to emit light.

[0209] In the disclosed embodiment, since the voltage-stabilizing capacitor C1 is added to the pixel circuit, the driving voltage in the light-emitting stage has better stability, and the brightness of the light-emitting device 2 varies less, which can improve or avoid flickering and improve display quality.

[0210] During the display process, the driving process (driving method) of the pixel circuit may be performed multiple times, and each driving process includes multiple stages.

[0211] In some embodiments, a driving method of a pixel circuit includes:

[0212] Continuously providing an initialization signal to the initialization signal terminal INIT, continuously providing a first power signal to the first power signal terminal VDD, and continuously providing a second power signal to the second power signal terminal VSS;

[0213] In the reset phase, a turn-on signal is provided to the first reset signal terminal RESET1, a turn-off signal is provided to the gate signal terminal GATE, and a turn-off signal is provided to the control signal terminal EM;

[0214] In the writing phase, a turn-off signal is provided to the first reset signal terminal RESET1, a turn-on signal is provided to the gate signal terminal GATE, a turn-off signal is provided to the control signal terminal EM, and a data signal is provided to the data signal terminal DATA;

[0215] In the light emitting stage, a turn-off signal is provided to the first reset signal terminal RESET1, a turn-off signal is provided to the gate signal terminal GATE, and a turn-on signal is provided to the control signal terminal EM.

[0216] In some embodiments, a driving method of a pixel circuit includes:

[0217] In the reset phase, a shutdown signal is provided to the second reset signal terminal RESET2;

[0218] In the writing phase, a conduction signal is provided to the second reset signal terminal RESET2;

[0219] In the reset phase, a shutdown signal is provided to the second reset signal terminal RESET2.

[0220] In some embodiments, in each stage of the driving process, a corresponding signal may be provided to each signal terminal in the above manner to drive the pixel circuit.

[0221] The signal of the second reset signal terminal RESET2 is always the same as the signal of the gate signal terminal GATE, so the second reset signal terminal RESET2 and the gate signal terminal GATE of the pixel circuit can be connected to the same signal source, such as the same pin on the driver IC.

[0222] Reference Figure 4 , Figure 5 As one method of an embodiment of the present disclosure, the driving method of the pixel circuit of the embodiment of the present disclosure is described below by taking the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 as P-type transistors as an example.

[0223] In each stage of the driving process of the pixel circuit of the embodiment of the present disclosure, the initialization signal Vinit is continuously provided to the initialization signal terminal INIT, the first power signal Vdd is continuously provided to the first power signal terminal VDD, and the second power signal Vss is continuously provided to the second power signal terminal VSS; and the signal conditions provided to other signal terminals in each stage are as follows:

[0224] S101 reset phase: provide a low level signal to the first reset signal terminal RESET1, provide a high level signal to the gate signal terminal GATE, provide a high level signal to the control signal terminal EM, and provide a high level signal to the second reset signal terminal RESET2.

[0225] In this stage, the low level signal of the first reset signal terminal RESET1 turns on the first transistor T1 and the third transistor T3, so that the initialization signal Vinit is written into the first node N1 and the second node N2.

[0226] In the write phase S102 , a high level signal is provided to the first reset signal terminal RESET1 , a low level signal is provided to the gate signal terminal GATE , a high level signal is provided to the control signal terminal EM , a data signal is provided to the data signal terminal DATA , and a low level signal is provided to the second reset signal terminal RESET2 .

[0227] In this stage, the low-level signal of the gate signal terminal GATE turns on the second transistor T2, the fourth transistor T4, and the fifth transistor T5, so that the data signal Vdata of the data signal terminal DATA is written into the first electrode of the driving transistor TD through the fifth transistor T5; and after passing through the driving transistor TD, the voltage of the first node N1 (the first electrode of the storage capacitor Cst) becomes Vdata-Vth, where Vth is the threshold voltage of the driving transistor TD.

[0228] Among them, the above data signals refer to the data signals corresponding to this pixel circuit, and at other times in the driving process, the data signal terminal DATA will actually obtain the data signals corresponding to other pixel circuits (because other pixel circuits may be in the writing stage), but because the fifth transistor T5 is turned off at other times, these data signals will not be written into this pixel circuit.

[0229] At the same time, since the second reset signal terminal RESET2 is a low level signal, the initialization signal Vinit of the initialization signal terminal INIT is written into the first electrode of the light emitting device 2 via the eighth transistor T8 to reset the voltage at this position.

[0230] S103 is a light emitting stage, providing a high level signal to the first reset signal terminal RESET1, providing a high level signal to the gate signal terminal GATE, providing a low level signal to the control signal terminal EM, and providing a high level signal to the second reset signal terminal RESET2.

[0231] In this stage, the control signal terminal EM is a low level signal, so that the sixth transistor T6 and the seventh transistor T7 are both turned on, so the current can flow from the first power signal terminal VDD to the second power signal terminal VSS, and the light-emitting device 2 can continue to emit light until the next reset stage (such as in the next frame) arrives.

[0232] Due to the holding effect of the storage capacitor Cst, the voltage (driving voltage) of the gate (first node N1) of the driving transistor TD in this stage is maintained at Vdata-Vth; and since the voltage of the first electrode of the driving transistor TD is the first power supply signal Vdd, its gate-source voltage Vgs is Vdata-Vth. The driving current Ioled flowing through the driving transistor TD is proportional to the difference between its gate-source voltage Vgs and the threshold voltage Vth, that is, the driving current Ioled is proportional to Vdd-(Vdata-Vth)-Vth=Vdd-Vdata. It can be seen that the driving current Ioled is only related to the data voltage Vdata, and has nothing to do with the threshold voltage Vth of the driving transistor TD, that is, the influence of the threshold voltage drift is eliminated.

[0233] In the embodiment of the present disclosure, during the light-emitting stage, the third node N3 is usually higher than the voltage Vdata-Vth of the first node N1. Therefore, the third node N3 will "pull up" the voltage of the first node N1 due to the leakage current of the second transistor T2, thereby causing the voltage of the first node N1 to gradually increase during the light-emitting stage, and the brightness of the light-emitting device 2 to gradually decrease.

[0234] In the embodiment of the present disclosure, since the voltage-stabilizing capacitor C1 is provided, the voltage of the third node N3 is more stable and can be maintained at a "lower" level, thereby weakening the "pull-up" ability of the first node N1, so that the voltage of the first node N1 is more stable in the light-emitting stage, and the brightness of the light-emitting device 2 is also more stable.

[0235] Specifically, when entering the writing phase, the signal of the gate signal terminal GATE "jumps" from a low-level signal to a high-level signal, so that the second transistor T2 and the fourth transistor T4 are turned off. It can be seen that the gate signal terminal GATE is connected to the gates of the second transistor T2 and the fourth transistor T4, and the third node N3 is the first electrode of the second transistor T2 and the fourth transistor T4, so the distance between the third node N3 and the gate signal terminal GATE is usually very close; therefore, the "jump" of the signal of the gate signal terminal GATE will also increase the voltage of the third node N3 through coupling.

[0236] Since the embodiment of the present disclosure is provided with a voltage-stabilizing capacitor C1, the effect of the "jump" of the signal at the gate signal terminal GATE on the voltage of the third node N3 is weakened. The initial voltage of the third node N3 at the beginning of the light-emitting stage is at a lower level, which can weaken its "pull-up" ability on the voltage of the first node N1, thereby improving the display quality.

[0237] Reference Figure 7 , Figure 8 As another method of the embodiment of the present disclosure, the driving method of the pixel circuit of the embodiment of the present disclosure is described below by taking the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 as N-type transistors as an example.

[0238] In each stage of the driving process of the pixel circuit of the embodiment of the present disclosure, the initialization signal Vinit is continuously provided to the initialization signal terminal INIT, the first power signal Vdd is continuously provided to the first power signal terminal VDD, and the second power signal Vss is continuously provided to the second power signal terminal VSS; and the signal conditions provided to other signal terminals in each stage are as follows:

[0239] S201 reset phase: provide a high level signal to the first reset signal terminal RESET1, provide a low level signal to the gate signal terminal GATE, provide a low level signal to the control signal terminal EM, and provide a low level signal to the second reset signal terminal RESET2.

[0240] In this stage, the high level signal of the first reset signal terminal RESET1 turns on the first transistor T1 and the third transistor T3, so that the initialization signal Vinit is written into the first node N1 and the second node N2.

[0241] In the write phase S202 , a low level signal is provided to the first reset signal terminal RESET1 , a high level signal is provided to the gate signal terminal GATE , a low level signal is provided to the control signal terminal EM , a data signal is provided to the data signal terminal DATA , and a high level signal is provided to the second reset signal terminal RESET2 .

[0242] In this stage, the high-level signal at the gate signal terminal GATE turns on the second transistor T2, the fourth transistor T4, and the fifth transistor T5, so that the data signal Vdata at the data signal terminal DATA is written into the first electrode of the driving transistor TD through the fifth transistor T5; and after passing through the driving transistor TD, the voltage of the first node N1 (the first electrode of the storage capacitor Cst) becomes Vdata-Vth, where Vth is the threshold voltage of the driving transistor TD.

[0243] Among them, the above data signals refer to the data signals corresponding to this pixel circuit, and at other times in the driving process, the data signal terminal DATA will actually obtain the data signals corresponding to other pixel circuits (because other pixel circuits may be in the writing stage), but because the fifth transistor T5 is turned off at other times, these data signals will not be written into this pixel circuit.

[0244] At the same time, since the second reset signal terminal RESET2 is a high level signal, the initialization signal Vinit of the initialization signal terminal INIT is written into the first electrode of the light emitting device 2 via the eighth transistor T8 to reset the voltage at this position.

[0245] S203 is a light emitting stage, providing a low level signal to the first reset signal terminal RESET1, providing a low level signal to the gate signal terminal GATE, providing a high level signal to the control signal terminal EM, and providing a low level signal to the second reset signal terminal RESET2.

[0246] In this stage, the control signal terminal EM is a high level signal, so that the sixth transistor T6 and the seventh transistor T7 are both turned on, so the current can flow from the first power signal terminal VDD to the second power signal terminal VSS, and the light-emitting device 2 can continue to emit light until the next reset stage (such as in the next frame) arrives.

[0247] Due to the holding effect of the storage capacitor Cst, the voltage (driving voltage) of the gate (first node N1) of the driving transistor TD in this stage is maintained at Vdata-Vth; and since the voltage of the first electrode of the driving transistor TD is the first power supply signal Vdd, its gate-source voltage Vgs is Vdata-Vth. The driving current Ioled flowing through the driving transistor TD is proportional to the difference between its gate-source voltage Vgs and the threshold voltage Vth, that is, the driving current Ioled is proportional to Vdd-(Vdata-Vth)-Vth=Vdd-Vdata. It can be seen that the driving current Ioled is only related to the data voltage Vdata, and has nothing to do with the threshold voltage Vth of the driving transistor TD, that is, the influence of the threshold voltage drift is eliminated.

[0248] It can be seen that when the form of the transistor is different, only the levels of the on signal and the off signal are swapped, and the specific driving process and principle of the pixel circuit of the embodiment of the present disclosure do not change, so they will not be described in detail here.

[0249] Thirdly, refer to Figures 4 to 21 , the present disclosure provides a display substrate, which includes:

[0250] substrate;

[0251] A plurality of sub-pixels are disposed on the substrate, and at least some of the sub-pixels include any one of the above-mentioned pixel circuits.

[0252] Among them, the base is the basis for supporting other structures on the display substrate. It is a basically sheet-like structure composed of glass, silicon (such as single crystal silicon), polymer material (such as polyimide) and other materials. It can be rigid or flexible, and its thickness can be in the order of millimeters.

[0253] Among them, sub-pixels refer to the smallest structure that can be used to independently display the required content, that is, the smallest "dot" that can be controlled individually in the display device. Different sub-pixels can have different colors, so that color display can be achieved through the mixing of light from different sub-pixels: for example, a "pixel (or pixel unit)" can be composed of multiple sub-pixels of different colors arranged together, that is, the light emitted by these sub-pixels is mixed together to form a visual "dot", such as three sub-pixels of red, green, and blue colors forming a pixel; or, there may be no clear pixel (or pixel unit), but color display can be achieved through "sharing" between adjacent sub-pixels.

[0254] In the disclosed embodiment, the above devices of the pixel circuit can be arranged on a substrate, and each pixel circuit corresponds to a sub-pixel, that is, the light emitted by the light-emitting device 2 in the pixel circuit serves as the light emitted by the sub-pixel.

[0255] In the pixel circuits corresponding to sub-pixels of different colors, the light emitting device 2 may directly emit light of different colors, or the light emitting device 2 may emit white light which then passes through color filters (CF) of different colors to become light of different colors.

[0256] Since the above pixel circuit is adopted, the display substrate of the embodiment of the present disclosure has stable brightness, no flickering phenomenon and good display quality.

[0257] In some embodiments, sub-pixels may be arranged in an array on a display substrate, and a plurality of signal lines may be used to provide signals to pixel circuits in each sub-pixel to control the sub-pixel to perform display.

[0258] Among them, the signal lines may include multiple gate signal lines extending along a first direction (such as a row direction), multiple first reset signal lines extending along the first direction, multiple second reset signal lines extending along the first direction, multiple control signal lines extending along the first direction, and multiple initialization signal lines extending along the first direction; each gate signal line is connected to the gate signal terminal GATE of the pixel circuit of each sub-pixel in a row, each first reset signal line is connected to the first reset signal terminal RESET1 of the pixel circuit of each sub-pixel in a row, each second reset signal line is connected to the second reset signal terminal RESET2 of the pixel circuit of each sub-pixel in a row (and the second reset signal line can be connected to the same signal source as the gate signal line of the corresponding sub-pixel in the same row), each control signal line is connected to the control signal terminal EM of the pixel circuit of each sub-pixel in a row, and each initialization signal line is connected to the initialization signal terminal INIT of the pixel circuit of each sub-pixel in a row.

[0259] The signal line may further include a plurality of data lines extending along the second direction (eg, the column direction); each data line is connected to a data signal terminal DATA of a pixel circuit of each sub-pixel in a row.

[0260] Among them, the signal line may also include a first power signal line, a second power signal line, an initialization signal line, etc. These signal lines may extend along the row direction or the column direction, or form a grid, and are respectively connected to the first power signal terminal VDD, the second power signal terminal VSS, and the initialization signal terminal INIT of the pixel circuit of each sub-pixel.

[0261] In some embodiments, the capacitance of the voltage stabilizing capacitor C1 is greater than 3 fF (femtofarad).

[0262] Obviously, if the capacitance value of the voltage stabilizing capacitor C1 is too small, it cannot stabilize the voltage of the third node N3. After research, it is found that a better voltage stabilizing effect can be achieved when the capacitance value of the voltage stabilizing capacitor C1 is above 3fF, and further above 5fF.

[0263] In some embodiments, the first electrode of the voltage stabilizing capacitor C1 and the second electrode of the second transistor T2 are disposed in the same layer and connected as a whole.

[0264] Each structure of the pixel circuit disposed on the substrate may be disposed in different layers. Since the first electrode of the voltage stabilizing capacitor C1 needs to be connected to the second electrode of the second transistor T2, Fig.10 , Fig.11 As one embodiment of the present disclosure, the two can be an integrated structure arranged in the same layer to simplify the structure and preparation method of the display substrate.

[0265] When the first electrode of the fourth transistor T4 is also connected to the first electrode of the voltage stabilizing capacitor C1, Fig.10 , Fig.11 The first electrode of the voltage-stabilizing capacitor C1, the second electrode of the second transistor T2, and the first electrode of the fourth transistor T4 may be an integrated structure.

[0266] In some embodiments, the first electrode of the voltage-stabilizing capacitor C1 is disposed in the same layer as the active region of the driving transistor TD, and the first electrode of the voltage-stabilizing capacitor C1 is a conductive semiconductor material;

[0267] The second electrode of the second transistor T2 is disposed in the same layer as the active region of the driving transistor TD, and the second electrode of the second transistor T2 is a conductive semiconductor material.

[0268] Reference Fig.10 , Fig.11 In order to further simplify the structure, the integrated structure composed of the first electrode of the voltage-stabilizing capacitor C1 and the second electrode of the second transistor T2 (and the first electrode of the fourth transistor T4) can also be integrated with the active area of ​​the second transistor T2 (and can also be integrated with the active area of ​​the fourth transistor T4), that is, these structures are all made of semiconductor materials (such as polysilicon materials), but the parts corresponding to the first electrode of the voltage-stabilizing capacitor C1, the second electrode of the second transistor T2, and the first electrode of the fourth transistor T4 need to be conductorized to form conductors.

[0269] Of course, it is also feasible if the first electrode of the second transistor T2, the second electrode of the fourth transistor T4 and other structures are also connected to the above structures as a whole.

[0270] Of course, it is also feasible if the first electrode of the voltage-stabilizing capacitor C1, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, the active area of ​​the second transistor T2, the active area of ​​the fourth transistor T4, etc. are respectively arranged in different layers and connected through structures such as vias in the insulating layer.

[0271] In some embodiments, the first electrode of the voltage-stabilizing capacitor C1 includes a connecting portion 11 connected between the second electrode of the second transistor T2 and the first electrode of the fourth transistor T4 , and the connecting portion 11 has a plurality of bending structures.

[0272] Obviously, the first electrode of the fourth transistor T4 and the second electrode of the second transistor T2 should be connected to form a "double-gate transistor", so that Fig.10 , Fig.11 , the connection structure (connection portion 11) between the first electrode of the fourth transistor T4 and the second electrode of the second transistor T2 is directly used as the first electrode of the voltage-stabilizing capacitor C1, that is, the first electrode of the fourth transistor T4 and the second electrode of the second transistor T2 are connected through the first electrode of the voltage-stabilizing capacitor C1.

[0273] However, refer to Fig.10 , Fig.11 , the distance between the second electrode of the second transistor T2 and the first electrode of the fourth transistor T4 is small, so if the connecting portion 11 directly connects the two, the area of ​​the connecting portion 11 is relatively small, the capacitance value of the corresponding voltage-stabilizing capacitor C1 is relatively small, and the voltage-stabilizing effect is not good enough. For this reason, the above connecting portion 11 (i.e., the first electrode of the voltage-stabilizing capacitor C1) may include a plurality of bending structures, so that within a limited range, the connection between the second electrode of the second transistor T2 and the first electrode of the fourth transistor T4 is realized, and the area of ​​the connecting portion 11 is expanded to increase the capacitance value of the voltage-stabilizing capacitor C1.

[0274] Of course, the above bending structure and the connecting portion 11 are not limitations on the form of the first electrode of the voltage-stabilizing capacitor C1 , and the first electrode of the voltage-stabilizing capacitor C1 may also be in other forms.

[0275] For example, the area of ​​the connection portion 11 may be increased by other forms such as "thickening" or "extending"; or, the first electrode of the voltage-stabilizing capacitor C1 may not be the connection portion 11, but an additional structure connected to the third node N1.

[0276] In some embodiments, the second electrode of the voltage stabilizing capacitor C1 is disposed at the same layer as the initialization signal terminal INIT.

[0277] Obviously, the second pole of the voltage-stabilizing capacitor C1 should be overlapped with and insulated from the first pole of the voltage-stabilizing capacitor C1, that is, the orthographic projections of the first pole of the voltage-stabilizing capacitor C1 and the second pole of the voltage-stabilizing capacitor C1 on the substrate should overlap, and the first pole of the voltage-stabilizing capacitor C1 and the second pole of the voltage-stabilizing capacitor C1 are separated by at least one insulating layer.

[0278] To this end, as a method of the present disclosure, refer to Fig.10 , Fig.13 , Fig.14 , the structure provided at the same layer as the initialization signal terminal INIT can be used as the second electrode of the voltage-stabilizing capacitor C1.

[0279] In some embodiments, in a direction gradually away from the base, the display substrate sequentially includes:

[0280] The active region of the driving transistor TD and the first electrode of the voltage stabilizing capacitor C1;

[0281] Gate insulation layer (GI);

[0282] a gate of a driving transistor TD;

[0283] a first interlayer insulating layer (ILD1);

[0284] The second electrode of the voltage stabilizing capacitor C1 and the initialization signal terminal INIT.

[0285] Among them, the layer where the initialization signal terminal INIT is located (such as the GATE2 layer) is relatively close to the layer where the active area of ​​the transistor is located (POLY) (there are relatively few insulating layers between them), so these two layers are used as the layers where the two poles of the voltage-stabilizing capacitor C1 are located, which can shorten the distance between the two poles of the voltage-stabilizing capacitor C1 and increase the capacitance value of the voltage-stabilizing capacitor C1.

[0286] Of course, it is also feasible to use a structure that is arranged at the same layer as other structures (such as the first power signal terminal VDD, the second power signal terminal VSS, etc.) as the second electrode of the voltage-stabilizing capacitor C1.

[0287] In some embodiments, a second electrode of the voltage-stabilizing capacitor C1 is connected to a second electrode of the storage capacitor Cst.

[0288] As one embodiment of the present disclosure, the second pole of the voltage-stabilizing capacitor C1 can be connected to the second pole of the storage capacitor Cst through other structures. Since the second pole of the storage capacitor Cst must be connected to the first power supply signal terminal VDD, the second pole of the voltage-stabilizing capacitor C1 essentially obtains the first power supply signal Vdd as a constant voltage signal.

[0289] In some embodiments, the initialization signal terminal INIT includes a first initialization signal terminal INIT1 and a second initialization signal terminal INIT2 arranged in the same layer, and the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2 are arranged in parallel and spaced apart;

[0290] The second electrode of the eighth transistor T8 is connected to the first initialization signal terminal INIT1;

[0291] The second electrode of the third transistor T3 is connected to the second initialization signal terminal INIT2.

[0292] Reference Fig.13The initialization signal terminal INIT can be divided into two structures (a first initialization signal terminal INIT1 and a second initialization signal terminal INIT2) arranged in the same layer but independent of each other, which are respectively connected to the second electrode of the third transistor T3 and the second electrode of the eighth transistor T8, so that according to needs, the signals of the second electrode of the third transistor T3 and the second electrode of the eighth transistor T8 can be the same or different to achieve more complex control.

[0293] Of course, it is also feasible if the initialization signal terminal INIT connecting the second electrode of the third transistor T3 and the second electrode of the eighth transistor T8 is an integrated structure (ie, the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2 are not distinguished).

[0294] In some embodiments, the first reset signal terminal RESET1 extends along a first direction;

[0295] The first reset signal terminal RESET1 of at least part of the pixel circuits is multiplexed as the second reset signal terminal RESET2 of the pixel circuits adjacent to the pixel circuits along the second direction; the first direction intersects the second direction.

[0296] Reference Figure 5 , Figure 8 , the signal at the first reset signal terminal RESET1 differs from the signal at the second reset signal terminal RESET2 by one cycle. Fig.12 In the second direction (such as the middle horizontal direction) that crosses (such as perpendicular to) the first direction, Fig.12 In the adjacent pixel circuits in the longitudinal direction (in the middle), the signal of the second reset signal terminal RESET2 of the pixel circuit in the previous row is the same as the signal of the first reset signal terminal RESET1 of the pixel circuit in the current row.

[0297] Therefore, refer to Fig.12 In order to simplify the structure, the first reset signal terminal RESET1 of each pixel circuit can be along the first direction ( Fig.12 The multiplexing direction is extended in the second direction (such as Fig.12 The second reset signal terminal RESET2 of the pixel circuit adjacent to the vertical direction in FIG. Fig.10 The eighth transistor T8 of the previous row of pixel circuits can be located in a rectangular area with other structures of the row of pixel circuits so that the first reset signal terminal RESET1 of the current row of pixel circuits (ie, the second reset signal terminal RESET2 of the previous row of pixel circuits) can be used as its gate.

[0298] In some embodiments, the second electrode of the storage capacitor Cst includes a horizontal connection structure 32 extending along the first direction; at least part of the horizontal connection structures 32 of the pixel circuits adjacent to each other along the first direction are connected to each other;

[0299] The first power signal terminal VDD extends along a second direction; the first direction intersects the second direction.

[0300] Reference Fig.13 , the second electrode of the storage capacitor Cst has a structure that overlaps with the first electrode of the storage capacitor Cst ( Fig.13 In addition to the rectangle with a notch in the middle), there is also a first direction ( Fig.13 A horizontal connection structure 32 extending in the horizontal direction (in the middle), so that multiple storage capacitors Cst in the same row can be connected as a whole through the horizontal connection structure 32.

[0301] At the same time, refer to Fig.15 , the first power signal terminal VDD is along a second direction intersecting the first direction ( Fig.15 The first power signal terminal VDD is necessarily connected to the storage capacitor Cst in each pixel circuit.

[0302] It can be seen that the first power signal terminals VDD of multiple columns are actually electrically connected to the second electrodes of the storage capacitors Cst of the same row, that is, electrically, the structure providing the first power signal Vdd forms a "grid shape", thereby reducing its power supply resistance.

[0303] In some embodiments, the display substrate further comprises:

[0304] An auxiliary conductive structure 31 is arranged overlapping with the first power signal terminal VDD; at least one insulating layer is arranged between the auxiliary conductive structure 31 and the first power signal terminal VDD, and the auxiliary conductive structure 31 is connected to the first power signal terminal VDD through a via in the insulating layer.

[0305] Reference Fig.16 The display substrate may also include an auxiliary conductive structure 31 that overlaps with the first power signal terminal VDD (such as also extending along the second direction), and the auxiliary conductive structure 31 is connected to the first power signal terminal VDD to further reduce the supply resistance of the first power signal Vdd.

[0306] The above pixel circuit is used as an example to exemplify the specific layering of the structure.

[0307] In some embodiments, in a direction gradually away from the base, the display substrate sequentially includes:

[0308] (1) Semiconductor layer (POLY).

[0309] The semiconductor layer is made of a semiconductor material, for example, a polycrystalline silicon material (poly-Si).

[0310] The semiconductor layer includes: a first electrode, a second electrode, and an active area of ​​a driving transistor TD, a first electrode, a second electrode, and an active area of ​​a first transistor T1, a first electrode, a second electrode, and an active area of ​​a second transistor T2, a first electrode, a second electrode, and an active area of ​​a third transistor T3, a first electrode, a second electrode, and an active area of ​​a fourth transistor T4, a first electrode, a second electrode, and an active area of ​​a fifth transistor T5, a first electrode, a second electrode, and an active area of ​​a sixth transistor T6, a first electrode, a second electrode, and an active area of ​​a seventh transistor T7, a first electrode, a second electrode, and an active area of ​​an eighth transistor T8, and a first electrode of a voltage-stabilizing capacitor C1.

[0311] The first electrode of the voltage-stabilizing capacitor C1 and the second electrode of the second transistor T2 are connected as a whole, and both are made of conductive semiconductor materials.

[0312] Reference Fig.11 The active region, the first electrode and the second electrode of each transistor can be located in the semiconductor layer; and the first electrode (connection portion 11) of the voltage-stabilizing capacitor C1 is connected to the second electrode of the second transistor T2 as a whole and is also located in the semiconductor layer.

[0313] Of course, the electrodes of all transistors and the first electrode of the voltage-stabilizing capacitor C1 are made of conductive semiconductor materials.

[0314] (2) Gate insulation layer (GI).

[0315] The gate insulating layer is made of insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the active area of ​​each transistor from the gate.

[0316] Since the active region of each transistor is closer to the substrate than its gate, each transistor is a "bottom-gate transistor".

[0317] Reference Fig.17 The gate insulating layer may include: a via hole for connecting the first power signal terminal VDD and the first electrode of the sixth transistor T1, a via hole for connecting the data signal terminal DATA and the second electrode of the fifth transistor T5, a via hole for connecting the first light-emitting access structure 331 and the second electrode of the seventh transistor T7, a via hole for connecting the first connection structure 351 and the second electrode of the eighth transistor T8, a via hole for connecting the second connection structure 352 and the second electrode of the third transistor T3, and a via hole for connecting the third connection structure 353 and the first electrode of the first transistor T1 (described in detail later).

[0318] (3) First gate layer (GATE1).

[0319] The first gate layer is made of a conductive material, such as a metal material.

[0320] The first gate layer includes: a gate of the driving transistor TD, a gate of the first transistor T1, a gate of the second transistor T2, a gate of the third transistor T3, a gate of the fourth transistor T4, a gate of the fifth transistor T5, a gate of the sixth transistor T6, a gate of the seventh transistor T7, a gate of the eighth transistor T8, a first reset signal terminal RESET1, a second reset signal terminal RESET2, a control signal terminal EM, and a first electrode of the storage capacitor Cst.

[0321] Reference Fig.12 The gates of all transistors and the signal terminals for providing signals to the gates may be located in the first gate layer.

[0322] In addition, the first electrode of the storage capacitor Cst is also located in the first gate layer because it is necessarily the gate of the driving transistor TD (eg, an integrated structure).

[0323] As before, the first reset signal terminal RESET1 of the pixel circuit in this row can also be reused as the second reset signal terminal RESET2 of the pixel circuit in the previous row, that is, in each pixel circuit, there is actually only one reset signal terminal structure.

[0324] (4) First interlayer insulating layer (ILD1).

[0325] The first interlayer insulating layer is made of an insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the structure of the first gate layer from the structure of the subsequent second gate layer.

[0326] Reference Fig.18 The first interlayer insulating layer may include: a via for connecting the first power signal terminal VDD and the first electrode of the sixth transistor T1, a via for connecting the data signal terminal DATA and the second electrode of the fifth transistor T5, a via for connecting the first light-emitting access structure 331 and the second electrode of the seventh transistor T7, a via for connecting the first connection structure 351 and the second electrode of the eighth transistor T8, a via for connecting the second connection structure 352 and the second electrode of the third transistor T3, a via for connecting the third connection structure 353 and the gate of the driving transistor TD, and a via for connecting the third connection structure 353 and the first electrode of the first transistor T1 (described in detail later).

[0327] (5) Second gate layer (GATE2).

[0328] The second gate layer is made of a conductive material, such as a metal material.

[0329] The second gate layer includes: an initialization signal terminal INIT, a second electrode of the voltage-stabilizing capacitor C1, and a second electrode of the storage capacitor Cst.

[0330] Reference Fig.13 The initialization signal terminal INIT, the second electrode of the voltage-stabilizing capacitor C1, and the second electrode of the storage capacitor Cst can be arranged in the second gate layer, and the second electrode of the voltage-stabilizing capacitor C1 can be connected to the second electrode of the storage capacitor Cst through a subsequent voltage-stabilizing connection structure 34 (described in detail later).

[0331] Among them, refer to Fig.13 The initialization signal terminal INIT can also be divided into the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2.

[0332] Among them, refer to Fig.13 The second electrode of the storage capacitor Cst may also include the above-mentioned horizontal connection structure 32.

[0333] Among them, refer to Fig.13 The second electrode of the storage capacitor Cst, except for the cross-connection structure 32, can be a rectangle with a gap, and the gap is for allowing the first electrode of the storage capacitor Cst located thereunder to be connected to the first electrode of the first transistor T1 (described in detail later).

[0334] (6) Second interlayer insulating layer (ILD2).

[0335] The second interlayer insulating layer is made of insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the structure of the second gate layer from the subsequent structure of the first source and drain layer.

[0336] Reference Fig.19 The second interlayer insulating layer may include: a via for connecting the first power signal terminal VDD and the second electrode of the storage capacitor Cst, a via for connecting the first power signal terminal VDD and the first electrode of the sixth transistor T1, a via for connecting the data signal terminal DATA and the second electrode of the fifth transistor T5, a via for connecting the first light-emitting access structure 331 and the second electrode of the seventh transistor T7, a via for connecting the first connection structure 351 and the second electrode of the eighth transistor T8, a via for connecting the first connection structure 351 and the initialization signal terminal INIT, a via for connecting the second connection structure 352 and the second electrode of the third transistor T3, a via for connecting the second connection structure 352 and the initialization signal terminal INIT, a via for connecting the third connection structure 353 and the gate of the driving transistor TD, a via for connecting the third connection structure 353 and the first electrode of the first transistor T1, a via for connecting the voltage-stabilizing connection structure 34 and the second electrode of the storage capacitor Cst, and a via for connecting the voltage-stabilizing connection structure 34 and the second electrode of the voltage-stabilizing capacitor C1 (described in detail later).

[0337] (7) First source and drain layer (SD1).

[0338] The first source-drain layer is made of a conductive material, such as a metal material.

[0339] The first source-drain layer includes: a first power signal terminal VDD, a data signal terminal DATA, a first light-emitting access structure 331 , and a voltage-stabilizing connection structure 34 .

[0340] Among them, the first power signal terminal VDD is connected to the second electrode of the storage capacitor Cst through the via in the second interlayer insulating layer, and is connected to the first electrode of the sixth transistor T1 through the via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer; the data signal terminal DATA is connected to the second electrode of the fifth transistor T5 through the via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the first light-emitting access structure 331 is connected to the second electrode of the seventh transistor T7 through the via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the voltage-stabilizing connection structure 34 is connected to the second electrode of the storage capacitor Cst through the via in the second interlayer insulating layer, and is connected to the second electrode of the voltage-stabilizing capacitor C1 through the via in the second interlayer insulating layer.

[0341] Reference Fig.15 The first power signal terminal VDD and the data signal terminal DATA can be arranged in the first source-drain layer, and the first power signal terminal VDD is connected to the second electrode of the storage capacitor Cst, while the data signal terminal DATA is connected to the second electrode of the fifth transistor T5 to form the above pixel circuit.

[0342] Among them, the second electrode of the seventh transistor T7 needs to be connected to the first electrode of the light emitting device 2, but there are many layers between the two and the distance is large, so refer to Fig.15 The first source-drain layer may also include a first light-emitting access structure 331 connected to the second electrode of the seventh transistor T7, so as to realize the connection of the second electrode of the seventh transistor T7 to the first electrode of the light-emitting device 2 through multiple structures (described in detail later) to avoid disconnection.

[0343] The second electrode of the storage capacitor Cst in the second gate layer and the second electrode of the voltage-stabilizing capacitor C1 can be connected via the voltage-stabilizing connection structure 34 (equivalent to a bridge) in the first source-drain layer.

[0344] In some embodiments, the first source and drain layer further includes:

[0345] A first connection structure 351, the first connection structure 351 is connected to the second electrode of the eighth transistor T8 through the gate insulation layer, the first interlayer insulation layer, and the via hole in the second interlayer insulation layer, and is connected to the initialization signal terminal INIT through the via hole in the second interlayer insulation layer;

[0346] A second connection structure 352, the second connection structure 352 is connected to the second electrode of the third transistor T3 through the gate insulation layer, the first interlayer insulation layer, and the via hole in the second interlayer insulation layer, and is connected to the initialization signal terminal INIT through the via hole in the second interlayer insulation layer;

[0347] The third connection structure 353 is connected to the gate of the driving transistor TD through via holes in the first interlayer insulating layer and the second interlayer insulating layer, and is connected to the first electrode of the first transistor T1 through via holes in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer.

[0348] Reference Fig.10 , Fig.15 In order to realize the electrical connection of structures of some different layers in the pixel circuit, a plurality of corresponding connection structures may be provided in the first source-drain layer.

[0349] Among them, the connection structure may specifically include a first connection structure 351 connecting the second electrode of the eighth transistor T8 to the initialization signal terminal INIT (such as the first initialization signal terminal INIT1); a second connection structure 352 connecting the second electrode of the third transistor T3 to the initialization signal terminal INIT (such as the second initialization signal terminal INIT2); and a third connection structure 353 connecting the driving transistor TD (i.e., the first electrode of the storage capacitor Cst) to the first electrode of the first transistor T1 (such as through the gap in the above storage capacitor Cst), etc.

[0350] Of course, if the above connection structure is provided in other layers, or the form of each electrode of a transistor and a capacitor is changed so that a different connection structure is required, it is also feasible.

[0351] (8) First planarization layer (PLN1).

[0352] The first planarization layer is made of an organic insulating material and is used to eliminate the step difference of the underlying structure.

[0353] Reference Fig. 20 The first planarization layer may include: a via for connecting the first light emitting access structure 331 and the second light emitting access structure 332, and a via for connecting the first power signal terminal VDD and the auxiliary conductive structure 31 (described in detail later).

[0354] (9) Passivation layer (PVX).

[0355] The passivation layer is made of an insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to prevent subsequently formed structures from directly contacting the first planarization layer.

[0356] Among them, the passivation layer and the first planarization layer are two continuous insulating layers (or regarded as two sublayers of an insulating layer), so refer to Fig. 20 , the vias in the passivation layer are exactly the same as the vias in the first planarization layer.

[0357] Therefore, in all descriptions of the embodiments of the present disclosure, the via holes in the first planarization layer may also include the via holes in the passivation layer, which will not be described in detail herein.

[0358] (10) Second source-drain layer (SD2).

[0359] The second source-drain layer is made of a conductive material, such as a metal material.

[0360] The second source-drain layer includes: an auxiliary conductive structure 31 and a second light-emitting access structure 332 .

[0361] Among them, the auxiliary conductive structure 31 is overlapped with the first power signal terminal VDD and connected to the first power signal terminal VDD through a via in the first planarization layer; and the second light-emitting access structure 332 is connected to the first light-emitting access structure 331 through a via in the first planarization layer.

[0362] The auxiliary conductive structure 31 for reducing the supply resistance of the first power signal Vdd may be located in the second source-drain layer and connected to the first power signal terminal VDD.

[0363] The second source-drain layer may further include a second light-emitting access structure 332 connected to the first light-emitting access structure 331 , so that the first electrode of the subsequent light-emitting device 2 is connected to the second electrode of the seventh transistor T7 through the second light-emitting access structure 332 and the first light-emitting access structure 331 .

[0364] (11) Second planarization layer (PLN2).

[0365] The second planarization layer is made of an organic insulating material and is used to eliminate the step difference of the underlying structure.

[0366] Reference Fig.21 The second planarization layer may include: a via hole for connecting the second light emitting access structure 332 and the first electrode of the light emitting device 2 (described in detail later).

[0367] (12) The first electrode of the light emitting device 2.

[0368] The first electrode of the light-emitting device 2 is connected to the second light-emitting access structure 332 through a via hole in the second planarization layer.

[0369] The first electrode of the light emitting device 2 may be disposed on the second planarization layer, and connected to the second electrode of the seventh transistor T7 through the second light emitting access structure 332 and the first light emitting access structure 331 .

[0370] Specifically, the first electrode of the light emitting device 2 may be an anode of an organic light emitting diode (OLED), which may be made of a metal oxide conductive material such as indium tin oxide (ITO).

[0371] In some embodiments, in a direction away from the base, the display substrate may further include the following structures in sequence:

[0372] (13) Pixel definition layer (PDL).

[0373] The pixel defining layer is made of an organic insulating material, and is used to define the range of the light emitting device 2 (such as an organic light emitting diode OLED) through an opening therein.

[0374] (14) The light-emitting layer of the light-emitting device 2.

[0375] The light-emitting layer is a layer actually used for emitting light in the light-emitting device 2 .

[0376] Specifically, the light-emitting layer of the light-emitting device 2 may be a light-emitting layer of an organic light-emitting diode OLED. The light-emitting layer of the organic light-emitting diode OLED is composed of organic materials, which at least includes an organic light-emitting layer (EML), and may also include other stacked auxiliary layers such as an electron injection layer (EIL), an electron transport layer (ETL), a hole injection layer (HIL), and a hole transport layer (HTL).

[0377] The light-emitting layer of the organic light-emitting diode OLED may be a whole-layer structure, which contacts the anode of the organic light-emitting diode OLED at the opening of the pixel defining layer, thereby forming the organic light-emitting diode OLED.

[0378] (15) The second electrode of the light emitting device 2.

[0379] Specifically, the second electrode of the light emitting device 2 may be the cathode of the organic light emitting diode OLED, and the cathode of the organic light emitting diode OLED may be made of a metal conductive material such as aluminum.

[0380] The cathode of the organic light emitting diode OLED may be a whole-layer structure, so it is also the second power signal terminal VSS.

[0381] (16) Encapsulation layer.

[0382] The encapsulation layer may be a stacked structure of alternating organic layers and inorganic layers, and is used to encapsulate other structures therein to prevent other structures (especially the light-emitting layer) from coming into contact with water and oxygen in the environment and aging.

[0383] Among them, the complete film layers in the above-mentioned structures can be formed by solution process, deposition process, etc.; and if the above-mentioned structures have structures with specific shapes, they can be formed by patterning process.

[0384] Of course, the specific layer structure described above is only illustrative and many variations are possible.

[0385] For example, the layers in which each specific structure is located may be different; for another example, the gate of each transistor may also be located in a layer closer to the substrate than its active area, that is, each transistor may not be the above-mentioned "bottom-gate transistor" but a "top-gate transistor", etc.

[0386] In a fourth aspect, an embodiment of the present disclosure provides a display device, comprising:

[0387] Any of the above display substrates.

[0388] The above display substrate can be combined with other components (such as a box cover, a flexible circuit board, a driving chip, a power supply component, etc.) to form a display device with a display function.

[0389] In some embodiments, the display device is an organic light emitting diode (OLED) display device.

[0390] Since the above display substrate is used, the display device of the embodiment of the present disclosure has stable brightness, no flickering phenomenon and good display quality.

[0391] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A pixel circuit, comprising: A light emitting module configured to emit light; A driving module, configured to drive the light-emitting module to emit light according to a driving voltage during a light-emitting phase; a storage module, the storage module being configured to maintain the driving voltage during the light emitting stage and provide the driving voltage to the driving module; a first transistor, wherein a first electrode of the first transistor is connected to a position where the driving module obtains the driving voltage; a second transistor, wherein a first electrode of the second transistor is connected to the first electrode of the first transistor, and a second electrode of the second transistor is not directly connected to the signal source; A voltage-stabilizing capacitor, wherein a first electrode of the voltage-stabilizing capacitor is connected to a second electrode of the second transistor, and a second electrode of the voltage-stabilizing capacitor is connected to a constant voltage signal source; The first electrode of the voltage-stabilizing capacitor comprises: a connecting portion connected between the second electrode of the second transistor and the first electrode of the fourth transistor, the connecting portion having a plurality of bending structures; a third transistor, wherein a first electrode of the third transistor is connected to the second electrode of the first transistor, and a gate of the third transistor is connected to the gate of the first transistor; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the second electrode of the second transistor, and a gate of the fourth transistor is connected to the gate of the second transistor; The light emitting module comprises a light emitting device; The driving module includes a driving transistor, and the driving transistor is configured to drive the light emitting device to emit light according to a voltage of a gate thereof; The storage module comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and the storage capacitor is configured to maintain the driving voltage at its first electrode during the light emitting stage and provide the driving voltage to the driving module; The pixel circuit includes a first resetting module and a writing module; The first reset module is configured to reset the voltage of the gate of the driving transistor according to the signals of the initialization signal terminal and the first reset signal terminal; the first reset module includes: the first transistor; the third transistor, wherein a first electrode of the third transistor is connected to a second electrode of the first transistor, a second electrode of the third transistor is connected to the initialization signal terminal, and a gate of the third transistor is connected to the gate of the first transistor and the first reset signal terminal; The writing module is configured to write the driving voltage to the first electrode of the storage capacitor according to the signals of the gate signal terminal and the data signal terminal; the writing module comprises: the second transistor; the fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the second transistor, a second electrode of the fourth transistor is connected to a second electrode of the driving transistor, and a gate of the fourth transistor is connected to a gate of the second transistor and the gate signal terminal; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first electrode of the driving transistor, a second electrode of the fifth transistor is connected to the data signal terminal, and a gate of the fifth transistor is connected to the gate signal terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a gate of the sixth transistor is connected to the control signal terminal; in, The driving transistor and the light emitting device are connected in series between the first power signal terminal and the second power signal terminal; The second electrode of the storage capacitor is connected to the first power signal terminal; The second electrode of the light emitting device is connected to the second power signal terminal; Wherein, the pixel circuit is arranged on a substrate, and in a direction gradually away from the substrate, sequentially comprises: The active area of ​​the driving transistor and the first electrode of the voltage stabilizing capacitor; a gate insulating layer; a gate of the driving transistor; a first interlayer insulating layer; The second electrode of the voltage stabilizing capacitor and the initialization signal terminal.

2. The pixel circuit according to claim 1, wherein: The constant voltage signal source is any one of the initialization signal terminal, the first power signal terminal, and the second power signal terminal.

3. The pixel circuit according to claim 1, wherein: Also includes: A control module, wherein the control module is configured to control whether the light emitting device emits light according to a signal at the control signal terminal; The control module comprises: a seventh transistor, a first electrode of the seventh transistor is connected to the second electrode of the driving transistor, a second electrode of the seventh transistor is connected to the first electrode of the light emitting device, and a gate of the seventh transistor is connected to the control signal terminal; A second reset module, the second reset module is configured to reset the voltage of the first electrode of the light-emitting device according to the signals of the second reset signal terminal and the initialization signal terminal; the second reset module includes: an eighth transistor, the first electrode of the eighth transistor is connected to the first electrode of the light-emitting device, the second electrode of the eighth transistor is connected to the initialization signal terminal, and the gate of the eighth transistor is connected to the second reset signal terminal.

4. The pixel circuit according to claim 3, wherein: The driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type transistors; or, The driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

5. A method for driving a pixel circuit, wherein: The pixel circuit is the pixel circuit according to any one of claims 1 to 4, and the driving method of the pixel circuit comprises: In the light emitting stage, the storage module is enabled to maintain the driving voltage and provide the driving voltage to the driving module.

6. The driving method of the pixel circuit according to claim 5, wherein: The driving method of the pixel circuit comprises: continuously providing an initialization signal to the initialization signal terminal, continuously providing a first power signal to the first power signal terminal, and continuously providing a second power signal to the second power signal terminal; In the reset phase, a turn-on signal is provided to the first reset signal terminal, a turn-off signal is provided to the gate signal terminal, and a turn-off signal is provided to the control signal terminal; In the writing phase, a shutoff signal is provided to the first reset signal terminal, a turn-on signal is provided to the gate signal terminal, a shutoff signal is provided to the control signal terminal, and a data signal is provided to the data signal terminal; In the light emitting stage, a shutoff signal is provided to the first reset signal terminal, a shutoff signal is provided to the gate signal terminal, and a turn-on signal is provided to the control signal terminal.

7. The driving method of the pixel circuit according to claim 6, wherein: The pixel circuit is the pixel circuit according to claim 3 or 4, and the driving method of the pixel circuit further includes: In the reset phase, providing a shutdown signal to the second reset signal terminal; In the writing phase, providing a conduction signal to the second reset signal terminal; In the light emitting phase, a shutoff signal is provided to the second reset signal terminal.

8. A display substrate, wherein: include: substrate; A plurality of sub-pixels are disposed on the substrate, and at least some of the sub-pixels include the pixel circuit according to any one of claims 1 to 4.

9. The display substrate according to claim 8, wherein: The first electrode of the voltage-stabilizing capacitor and the second electrode of the second transistor are arranged in the same layer and connected as a whole.

10. The display substrate according to claim 9, wherein: The first electrode of the voltage-stabilizing capacitor is arranged in the same layer as the active area of ​​the driving transistor, and the first electrode of the voltage-stabilizing capacitor is a conductive semiconductor material; The second electrode of the second transistor is arranged in the same layer as the active region of the driving transistor, and the second electrode of the second transistor is a conductive semiconductor material.

11. The display substrate according to claim 10, wherein: The second electrode of the voltage stabilizing capacitor is arranged at the same layer as the initialization signal terminal.

12. The display substrate according to claim 11, wherein: The second electrode of the voltage stabilizing capacitor is connected to the second electrode of the storage capacitor.

13. The display substrate according to claim 8, wherein: The pixel circuit is the pixel circuit according to claim 3 or 4; The initialization signal terminal comprises a first initialization signal terminal and a second initialization signal terminal arranged in the same layer, wherein the first initialization signal terminal and the second initialization signal terminal are arranged in parallel and spaced apart; The second electrode of the eighth transistor is connected to the first initialization signal terminal; The second electrode of the third transistor is connected to the second initialization signal terminal.

14. The display substrate according to claim 8, wherein: The pixel circuit is the pixel circuit according to claim 3 or 4; The first reset signal end extends along a first direction; The first reset signal end of at least part of the pixel circuits is multiplexed as the second reset signal end of the pixel circuits adjacent to the pixel circuit along a second direction; the first direction intersects the second direction.

15. The display substrate according to claim 8, wherein: The second electrode of the storage capacitor includes a horizontal connection structure extending along the first direction; at least part of the horizontal connection structures of the pixel circuits adjacent to each other along the first direction are connected to each other; The first power signal end extends along a second direction; the first direction intersects with the second direction.

16. The display substrate according to claim 8, wherein: The display substrate further comprises: An auxiliary conductive structure is arranged to overlap with the first power signal terminal; at least one insulating layer is arranged between the auxiliary conductive structure and the first power signal terminal, and the auxiliary conductive structure is connected to the first power signal terminal through a via in the insulating layer.

17. The display substrate according to claim 8, wherein: The pixel circuit is the pixel circuit according to claim 3 or 4; In a direction gradually away from the base, the display substrate sequentially comprises: A semiconductor layer, comprising: a first electrode, a second electrode, and an active area of ​​the driving transistor, a first electrode, a second electrode, and an active area of ​​the first transistor, a first electrode, a second electrode, and an active area of ​​the second transistor, a first electrode, a second electrode, and an active area of ​​the third transistor, a first electrode, a second electrode, and an active area of ​​the fourth transistor, a first electrode, a second electrode, and an active area of ​​the fifth transistor, a first electrode, a second electrode, and an active area of ​​the sixth transistor, a first electrode, a second electrode, and an active area of ​​the seventh transistor, a first electrode, a second electrode, and an active area of ​​the eighth transistor, and a first electrode of the voltage-stabilizing capacitor; wherein the first electrode of the voltage-stabilizing capacitor is connected to the second electrode of the second transistor as a whole, and both are conductive semiconductor materials; a gate insulating layer; A first gate layer, comprising: a gate of the driving transistor, a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, a gate of the sixth transistor, a gate of the seventh transistor, a gate of the eighth transistor, the first reset signal terminal, the second reset signal terminal, the control signal terminal, and a first electrode of the storage capacitor; a first interlayer insulating layer; The second gate layer includes: the initialization signal terminal, the second electrode of the voltage-stabilizing capacitor, and the second electrode of the storage capacitor; a second interlayer insulating layer; A first source-drain layer, comprising: the first power signal terminal, the data signal terminal, a first light-emitting access structure, and a voltage-stabilizing connection structure; wherein the first power signal terminal is connected to the second electrode of the storage capacitor through a via hole in the second interlayer insulating layer, and is connected to the first electrode of the sixth transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer; the data signal terminal is connected to the second electrode of the fifth transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the first light-emitting access structure is connected to the second electrode of the seventh transistor through a via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the voltage-stabilizing connection structure is connected to the second electrode of the storage capacitor through a via hole in the second interlayer insulating layer, and is connected to the second electrode of the voltage-stabilizing capacitor through a via hole in the second interlayer insulating layer; a first planarization layer; A second source-drain layer, comprising: an auxiliary conductive structure and a second light-emitting access structure; wherein the auxiliary conductive structure overlaps with the first power signal terminal and is connected to the first power signal terminal through a via hole in the first planarization layer; and the second light-emitting access structure is connected to the first light-emitting access structure through a via hole in the first planarization layer; a second planarization layer; The first electrode of the light emitting device is connected to the second light emitting access structure through a via hole in the second planarization layer.

18. The display substrate according to claim 17, wherein: The first source-drain layer further comprises: a first connection structure, wherein the first connection structure is connected to the second electrode of the eighth transistor through the via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and is connected to the initialization signal terminal through the via hole in the second interlayer insulating layer; a second connection structure, wherein the second connection structure is connected to the second electrode of the third transistor through the gate insulation layer, the first interlayer insulation layer, and the via hole in the second interlayer insulation layer, and is connected to the initialization signal terminal through the via hole in the second interlayer insulation layer; A third connection structure, wherein the third connection structure is connected to the gate of the driving transistor through vias in the first interlayer insulating layer and the second interlayer insulating layer, and is connected to the first electrode of the first transistor through vias in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

19. A display device, wherein: include: A display substrate as claimed in any one of claims 8 to 18.

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