Tester device structure unit, parallel tester device structure and wafer

Abstract

The application provides a test device structure unit, a parallel test device structure and a wafer. When a wafer electrical performance test, such as an HCI or NBTI test, is performed using a conventional MOS device test structure, each stage of the MOS device needs to be connected with four SMUs, and the test efficiency is low. In the test process, the gate and the drain of the MOS device to be tested are respectively connected with one SMU, and the source and the base are grounded. By reducing the number of SMUs connected with the MOS device in the test process to two, without increasing the test cost, not only can the mutual interference of multiple devices in the test process be effectively prevented, and the accuracy of the measurement be ensured, but also the excess SMUs can be connected with other MOS devices to be tested, the parallel test of multiple MOS devices can be realized, and the test efficiency can be improved.

Description

Technical Field

[0001] This specification relates to the field of semiconductor testing, specifically to a test device structural unit, a parallel test device structure, and a wafer. Background Technology

[0002] During the wafer manufacturing process, wafers need to undergo a series of stability and electrical performance tests. Source Measurement Units (SMUs, or power management units) are important equipment for testing the electrical performance of wafers.

[0003] Existing testing equipment, due to cost considerations, is typically equipped with four SMUs, which are electrically connected to the source (S), drain (D), gate (G), and base (B) of the MOS transistor in the test structure, respectively. This requires a large test space, takes a long time to complete the test of a wafer, and has low testing efficiency. Summary of the Invention

[0004] In view of this, embodiments of this specification provide a test device structure unit, a parallel test device structure, and a wafer. The test device structure unit connects two SMUs in wafer electrical performance testing, effectively saving test space. Using the same number of test devices, more MOS transistors can be tested simultaneously, improving test efficiency.

[0005] The embodiments in this specification provide the following technical solutions:

[0006] A test device structure unit for wafer testing includes a MOS transistor patterned on the wafer using photolithography. A capacitor patterned using photolithography is disposed between the drain and source of the MOS transistor, and the oxide layer thickness of the capacitor is the same as the oxide layer thickness of the MOS transistor. During wafer testing, the gate and drain of the MOS transistor are electrically connected to a first power supply measurement unit and a second power supply measurement unit, respectively, and the source and base of the MOS transistor are grounded.

[0007] Using the above-described test device structure unit, the test equipment used in the test process is the same as that of traditional test equipment. However, the number of SMUs connected to MOS transistors is reduced to two. This not only reduces the test space but also allows the remaining SMUs in the test equipment to be connected to other MOS transistors, enabling the test equipment to perform parallel tests. This reduces the total wafer test time and improves test efficiency. A capacitor is placed between the drain and source. By utilizing the filtering characteristics of the capacitor, the drain voltage is stabilized, which can effectively prevent voltage fluctuations and mutual interference when multiple MOS transistors are tested simultaneously, ensuring the accuracy of the test.

[0008] This specification also provides an embodiment in which the oxide layer thickness of the capacitor is the same as the oxide layer thickness of the MOS transistor.

[0009] This specification also provides an embodiment in which the MOS transistor includes an N-type MOS transistor or a P-type MOS transistor.

[0010] This specification also provides an embodiment in which the test device structural unit is disposed in the dicing groove of the wafer.

[0011] This specification also provides an embodiment in which the wafer testing includes at least one of hot carrier injection testing and negative bias temperature instability testing.

[0012] This specification also provides a parallel test device structure, which includes at least two test device structure units as described in any of the preceding embodiments.

[0013] This specification also provides an embodiment in which all the MOS transistors described are of the same type.

[0014] This specification also provides an embodiment in which at least one of the MOS transistors is of a different type from the rest of the MOS transistors.

[0015] This specification also provides a wafer comprising a test device structure unit as described in any of the preceding embodiments.

[0016] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0017] The test device structure unit provided by this invention, during wafer testing, such as the drain saturation current (Idsat) degradation experiment in hot carrier injection (HCI) testing, applies voltages to the drain and gate respectively through two power supply measurement units (SMUs), and grounds the source and base through a program. The detection device reads the Idsat reading. A capacitor is placed between the drain and source of each test device structure unit. Utilizing the filtering characteristics of the capacitor, the drain voltage is stabilized, effectively preventing voltage fluctuations and mutual interference when multiple MOS transistors are tested simultaneously, ensuring test accuracy. The test equipment used in the process is the same as traditional test equipment, without increasing the complexity or cost of the test. Since the number of SMUs connecting the MOS transistors in the test device structure unit is reduced to two, not only is the test space reduced, but other SMUs configured in the test equipment can be electrically connected to other test device structure units on the wafer. This allows the test equipment to perform parallel testing of multiple devices, thereby reducing the total wafer testing time and improving test efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the layout of a test device structural unit without capacitors.

[0020] Figure 2 This is an Idsat degradation curve of the HCI parallel test of a test device structure unit without capacitors.

[0021] Figure 3 This is a schematic diagram of the layout of the test device structure unit with capacitors.

[0022] Figure 4 This is an Idsat degradation curve of the HCI parallel test of the test device structure unit with set capacitance. Detailed Implementation

[0023] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] It should be understood that "the connection between component A and component B" means that component A is directly connected to component B, or that component A is indirectly connected to component B through other components. The directional terms such as "upper," "lower," "inner," "outer," and "side" described in the exemplary embodiments of this specification are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this specification.

[0028] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0029] During wafer fabrication, wafers undergo various tests to reject defective dies. Wafer testing includes a series of stability and electrical performance tests, such as measuring drain saturation current (Idsat) in Hot Carrier Injection (HCI) or Negative Bias Temperature Instability (NBTI) tests. Taking HCI testing as an example, existing testing equipment, due to cost considerations, typically includes four Source Measurement Units (SMUs). The wafer testing structure incorporates a MOS transistor, with each of the four SMUs electrically connected to the source, drain, gate, and base of the MOS transistor to measure Idsat. This wafer testing structure requires a large testing space because it uses four SMUs simultaneously on the same MOS transistor, has multiple units to be tested on the same wafer, and results in long testing times and low testing efficiency.

[0030] Through repeated experiments and research, the inventors first proposed a test device structure unit that can reduce the number of SMUs connected to each MOS transistor. For example... Figure 1 As shown, taking HCI testing as an example, the test requires two source transformers (SMUs) to provide voltage to the drain and gate. If the source and base are grounded, for example through program grounding, the two SMUs originally connected to the source and base can be omitted. In this case, the four SMUs in the test equipment can simultaneously connect two MOS transistors, thereby significantly reducing test time and improving test efficiency. In other words, when a MOS transistor device with four terminals (gate, drain, source, and base) is placed on the same test structure, during HCI testing, the SMUs are only used to connect the gate and drain, while the source and base are grounded through program grounding.

[0031] However, the inventors discovered through experiments that the voltage at this grounding terminal was unstable and fluctuated, resulting in unsatisfactory test results. For example... Figure 2 The HCI parallel test Idsat degradation curve shown in the figure indicates that each point with the same gray level represents the same test device. It can be found that there are differences in the test results between different test devices, indicating that the structural units of the test devices need to be improved.

[0032] To address the aforementioned issues, the inventors further propose a test device structure unit. The improvement of this test device structure unit lies in the fact that a capacitor is placed between the drain and source of the MOS transistor. The capacitor stabilizes the drain voltage, thereby preventing voltage fluctuations and mutual interference when multiple MOS transistors are tested simultaneously.

[0033] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0034] This invention provides a test device structure unit for wafer testing, such as... Figure 3 As shown, the test device structure unit is patterned on the wafer using photolithography. Specifically, it includes a MOS transistor and a capacitor patterned on the wafer using photolithography, with the capacitor disposed between the drain and source of the MOS transistor.

[0035] When using the above-described test device structure unit for wafer testing, we will still take HCI testing as an example here, such as... Figure 3 As shown, the gate and drain of the MOS transistor are electrically connected to the first power supply measurement unit SMU1 and the second power supply measurement unit SMU2 of the test device, respectively, and the source and base of the MOS transistor are grounded. It should be noted that the grounding method includes grounding the source and base by controlling the process through a program.

[0036] During wafer testing, the aforementioned test device structure unit allows for the continued use of existing testing equipment and methods. The advantages of this structure unit include reducing the number of SMUs connecting MOS transistors from four to two. The two extra SMUs can be connected to another MOS transistor, enabling parallel testing of both MOS transistors, reducing the total wafer testing time, and improving testing efficiency. Furthermore, the use of only two SMUs per MOS transistor reduces the required testing space. Each test device structure unit also has an independently configured capacitor. Utilizing the filtering characteristics of capacitors, the drain voltage is stabilized, effectively preventing voltage fluctuations and mutual interference when multiple MOS transistors are tested simultaneously, ensuring testing accuracy.

[0037] from Figure 4 The HCI parallel test Idsat degradation curve shows that, after a long period of testing and verification, the differences between the test devices in the figure are small, which is consistent with the single-serial test. It can be regarded as that there is no mutual interference between the samples, proving that the above-mentioned test device structure unit is very effective for parallel testing, which can save test time and ensure the accuracy and validity of test data.

[0038] It should be noted that, Figure 2 and Figure 4 The horizontal axis represents the duration of time, in seconds; the vertical axis represents the degradation rate of Idsat, expressed as a percentage.

[0039] It should also be noted that the above-mentioned test device structure unit can also be used to measure Idsat in negative bias temperature instability (NBTI) testing.

[0040] In some implementations, the oxide thickness of the capacitor in the test device structure unit is the same as the oxide thickness of the MOS transistor therein.

[0041] By controlling the oxide layer thickness of the capacitor, direct breakdown between the drain and source of the MOS transistor due to insufficient oxide layer thickness can be avoided.

[0042] In some implementations, such as Figure 3 As shown, MOS transistors include N-type MOS transistors.

[0043] In some implementations, such as Figure 3 As shown, MOS transistors include P-type MOS transistors.

[0044] It should be noted that the above-mentioned test device structure unit does not limit the type of MOS transistor.

[0045] In some implementations, the test device structure unit is disposed in the dicing groove of the wafer.

[0046] It should be noted that, depending on the design requirements, the test device structural units can also be placed in other locations on the wafer.

[0047] Based on the same inventive concept, embodiments of this specification also provide a parallel test device structure, which includes at least two test device structure units as described in any of the preceding embodiments.

[0048] It should be noted that more even-numbered SMUs can be configured on the test device, with each pair of SMUs electrically connected to one test device structural unit to perform test items. For example, four SMUs can be connected to two test device structural units. Specifically, as shown... Figure 3 As shown, the first MOS transistor (NMOS1) is connected to the first power measurement unit (SMU1) and the second power measurement unit (SMU2); the second MOS transistor (PMOS1) is connected to the third power measurement unit (SMU3) and the fourth power measurement unit (SMU4). Based on the same structural design, 6 SMUs are connected to 3 test device structural units, 8 SMUs are connected to 4 test device structural units, and so on, thereby further improving wafer testing efficiency and shortening the total testing time.

[0049] The technical effects brought about by the parallel test device structure provided in the above embodiments can be referred to the technical effects provided by the various embodiments of the aforementioned test device structure units, and will not be repeated here.

[0050] In some implementations, all MOS transistors in the parallel test device structure are of the same type.

[0051] In some implementations, at least one MOS transistor in the parallel test device structure is of a different type than the other MOS transistors.

[0052] In the above-described approach, the parallel test device structure is not limited by the type of MOS transistor and can be applied to P-type or N-type MOS transistors, as well as test environments that have both P-type and N-type MOS transistors.

[0053] Based on the same inventive concept, embodiments of this specification also provide a wafer, the wafer including test device structure units as described in any of the preceding embodiments.

[0054] The technical effects that the wafers provided in the above embodiments can bring can be referred to the technical effects provided in the various embodiments of the aforementioned test device structure units, and will not be repeated here.

[0055] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments described later are relatively simple in description because they correspond to the system; relevant parts can be referred to the descriptions in the system embodiments.

[0056] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A test device structure unit for wafer testing, characterized by, The test device structure unit comprises a MOS transistor patterned on a wafer by photolithography, a capacitor patterned by photolithography is arranged between the drain and the source of the MOS transistor, when wafer testing is performed, the gate and the drain of the MOS transistor are electrically connected to a first power supply measurement unit and a second power supply measurement unit respectively, and the source and the base of the MOS transistor are grounded. The test device structure unit is arranged in a scribe groove of the wafer.

2. The test device structure unit according to claim 1, characterized in that The oxide layer thickness of the capacitor is the same as the oxide layer thickness of the MOS transistor.

3. The test device structure unit of claim 1, wherein, The MOS transistor comprises an N-type MOS transistor or a P-type MOS transistor.

4. The test device structure unit of claim 1, wherein, The wafer testing comprises at least one of hot carrier injection testing and negative bias temperature instability testing.

5. A parallel test device structure, characterized by The parallel test device structure comprises at least two test device structure units as claimed in any one of claims 1 to 4.

6. The parallel test device structure of claim 5, wherein, All the MOS transistors are of the same type.

7. The parallel test device structure of claim 5, wherein, At least one of the MOS transistors is of a different type from the rest of the MOS transistors.

8. A wafer, characterized by, The wafer comprises test device structure units as claimed in any one of claims 1 to 4.

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