InfiniBand network data cache processing system and method

Abstract

The present disclosure provides an InfiniBand network data cache processing system and method, belonging to the field of network communication technology. The solution uses FPGAs to implement data processing and caching, significantly reducing the overhead associated with hardware equipment. Furthermore, due to features such as field programmability, the data processing mechanism can be flexibly modified. Compared to software implementations, hardware implementations offer faster processing speeds. Furthermore, the solution utilizes a parallel structure design of multiple random access memories for cross-clock domain data processing, and multiple large-capacity storage buffers for parallel storage, storing different parts of the same data packet in different large-capacity storage buffers. These designs accelerate the write and read speeds of the cache system, increase throughput, and speed up the transmission speed of the FPGA data cache processing system, preventing the FPGA data cache processing system from losing data due to congestion.

Description

Technical Field

[0001] The present disclosure belongs to the field of network communication technology, and in particular relates to an InfiniBand network data cache processing system and method. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

[0003] InfiniBand (IB) is a computer network communication standard for high-performance computing. It offers extremely high throughput and low latency for interconnecting data between computers. InfiniBand is also used as a direct or switched interconnect between servers and storage systems, as well as for interconnecting storage systems.

[0004] FPGAs are a type of semi-custom circuit within application-specific integrated circuits (ASICs) and are programmable logic arrays. The basic structure of an FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, routing resources, embedded dedicated hard cores, underlying embedded functional units, and various hardware resources. FPGAs are infinitely reprogrammable and designed using Verilog HDL, enabling flexible data packet capture, processing, and modification. They also have large-capacity buffer memory (i.e., various synchronous dynamic random access memory resources on the FPGA board) for caching and forwarding data.

[0005] The inventors discovered that many existing scientific research and engineering industries require the capture, processing or modification of IB data packets, as well as data caching. While these can be achieved by designing a hardware and software system using an FPGA, the IB network often has a relatively high transmission speed. For cost reasons, the read and write speeds of the large-capacity buffer memory in the FPGA are often lower than those of the IB network. This can lead to data loss due to congestion at the receiving end of the FPGA hardware and software system. Summary of the Invention

[0006] To address the aforementioned issues, the present disclosure provides an InfiniBand network data caching processing system and method. This solution effectively addresses the issue of data loss at the receiving end due to congestion when the IB network transmission speed exceeds the transmission speed of the storage device in the FPGA hardware and software system. Furthermore, the solution utilizes FPGAs to implement data processing and caching, significantly reducing the hardware equipment overhead. Furthermore, due to its field programmability and other features, the data processing mechanism can be flexibly modified. Compared to software implementations, hardware implementations offer significantly faster processing speeds.

[0007] According to a first aspect of an embodiment of the present disclosure, an InfiniBand network data cache processing system is provided, which is designed based on an FPGA device and includes:

[0008] A data receiving module, which is used to receive data from the IB network;

[0009] The data processing module is used to parse the received data, extract data information, and perform corresponding processing based on preset rules;

[0010] A first cross-clock domain processing module, which is used to perform cross-clock domain processing on the processed data to balance the output rate and the input rate;

[0011] A data writing and path selection module is used to read data after cross-clock domain processing and write data packet data and control information into the large-capacity storage buffer by polling the idle status of each large-capacity storage buffer;

[0012] A storage module comprising a plurality of large-capacity storage buffers, wherein the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0013] A data reading and path selection module, which is used to read the control information of the data packet and read the data of each part of the data packet from each large-capacity storage buffer in sequence according to the control information;

[0014] The second cross-clock domain processing module is used to perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0015] The data sending module is used to send the data after cross-clock preprocessing to the IB server.

[0016] Furthermore, the receiving of data from the IB network is specifically as follows:

[0017] Step 1: Capture data packet header control symbols, and perform data capture based on the data packet header control symbols;

[0018] Step 2: Capture the remaining internal data of the packet;

[0019] Step 3: Capture the control symbol at the end of the data packet and capture the complete data packet;

[0020] Step 4: Return to step 1 and recapture the next data packet.

[0021] Furthermore, the received data is parsed and data information is extracted, and corresponding processing is performed based on preset rules, specifically:

[0022] Separate the packet header and tail, and parse the internal data information according to the packet type;

[0023] Extract information, perform CRC verification, and process internal information based on preset rules;

[0024] Re-add the packet header and tail to assemble the data packet.

[0025] Furthermore, the processed data is processed across clock domains to balance the output rate and the input rate, specifically by placing multiple random access memories in parallel, writing to each random access memory in turn from top to bottom at the input end, and reading from all random access memories at the output end at the same time.

[0026] Furthermore, the read data is processed across clock domains to convert its clock domain into the same clock as the IB server, specifically by connecting multiple random access memories in parallel, reading from each random access memory in turn from top to bottom at the output end, and writing to all random access memories at the input end at the same time.

[0027] Furthermore, the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers, specifically:

[0028] Step 1: Prepare storage space for the first data packet header data and record the storage buffer number and write address control information to which the storage space belongs;

[0029] Step 2: Read the data packet header data from the first cross-clock domain processing module and temporarily store it;

[0030] Step 3: Read the next portion of data in the current data packet from the first cross-clock domain processing module;

[0031] Step 4: Write the data into each prepared large-capacity storage buffer and record the storage buffer number and write address control information;

[0032] Step 5: If the data portion is the end of the data packet, the data packet is determined to be finished, and then step 6 is executed; otherwise, jump to step 3;

[0033] Step 6: Prepare storage space for the next data packet header data, combine the data packet header data, the previously recorded data packet control information, and the number and write address control information of the storage buffer to which the storage space prepared for the next data packet header belongs, and write them into the storage space prepared for the data packet header data, and then jump to step 2.

[0034] Furthermore, the control information of the data packet is read, and each part of the data packet is read from each large-capacity storage buffer in sequence according to the control information, specifically:

[0035] Step 1: Obtain the write storage buffer number and write address control information of the first data packet header data;

[0036] Step 2: Read the storage space where the data packet header is stored, obtain the data packet header data, data control information of each part of the data packet, the storage buffer number of the next data packet header data and the write address control information;

[0037] Step 3: Sending a data packet header to the first cross-clock domain processing module;

[0038] Step 4: Determine the memory number and address of each portion of the data in the data packet according to the data packet header address control information of each portion of the data packet, thereby reading the data from each large-capacity buffer memory;

[0039] Step 5: Send data to the cross-clock domain processing data unit;

[0040] Step 6: When the data is the end of the data packet, determine that the data packet ends, read the next data packet according to the storage buffer number and write address control information of the next data packet header data in the data packet header address, and jump to step 2; otherwise, jump to step 4.

[0041] According to a second aspect of an embodiment of the present disclosure, a method for processing InfiniBand network data cache is provided. The method is based on the above-mentioned InfiniBand network data cache system and includes:

[0042] Receive data from the IB Network;

[0043] Parse the received data, extract data information, and process it accordingly based on preset rules;

[0044] Perform cross-clock domain processing on the processed data to balance the output rate and input rate;

[0045] Reading data after cross-clock domain processing, and writing data packet data and control information into a storage module including a plurality of large-capacity storage buffers by polling the idle status of each large-capacity storage buffer; the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0046] Reading control information of the data packet, and sequentially reading each part of the data packet from each large-capacity storage buffer according to the control information;

[0047] Perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0048] Send the cross-clock preprocessed data to the IB server.

[0049] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored and running on the memory, wherein the processor executes the above-mentioned InfiniBand network data cache processing method.

[0050] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored. The program is executed by a processor to implement the above-mentioned InfiniBand network data cache processing method.

[0051] Compared with the prior art, the present invention has the following advantages:

[0052] (1) The present disclosure provides an InfiniBand network data caching system and method. This solution can prevent congestion and data loss at the receiving end when the IB network transmission speed exceeds the transmission speed of the storage device of the FPGA hardware and software system. Furthermore, the solution utilizes FPGAs to implement data processing and caching, significantly reducing the hardware equipment overhead. Furthermore, due to its field programmability, the data processing mechanism can be flexibly modified. Compared to software implementations, hardware implementations offer significantly faster processing speeds.

[0053] (2) The cross-clock domain data processing scheme described in this disclosure utilizes a parallel architecture design of multiple random access memories and multiple large-capacity storage buffers for parallel storage, storing different parts of the same data packet in different large-capacity storage buffers. These designs accelerate the write and read speeds of the cache system, increase throughput, and speed up the transmission speed of the FPGA data cache processing system, preventing the FPGA data cache processing system from losing data due to congestion.

[0054] Advantages of additional aspects of the present disclosure will be given in part in the following description and in part will become apparent from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings, which constitute a part of the present disclosure, are used to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure.

[0056] Figure 1 Schematic diagram of the receiving end structure of the FPGA-based InfiniBand network described in the embodiment of the present disclosure;

[0057] Figure 2 This is a schematic diagram of the structure of an InfiniBand network data cache processing system described in an embodiment of the present disclosure;

[0058] Figure 3 is a flow chart of the IB data capture method described in an embodiment of the present disclosure;

[0059] Figure 4 is a flowchart of IB data processing described in an embodiment of the present disclosure;

[0060] Figure 5 This is a processing flow chart of the first cross-clock domain processing module described in an embodiment of the present disclosure;

[0061] Figure 6 This is a processing flow chart of the second cross-clock domain processing module described in an embodiment of the present disclosure;

[0062] Figure 7 This is a flowchart of data writing and path selection described in an embodiment of the present disclosure;

[0063] Figure 8 This is a flowchart of data reading and path selection described in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0065] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs.

[0066] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0067] In the absence of conflict, the embodiments of the present disclosure and the features thereof may be combined with each other.

[0068] Example 1:

[0069] The purpose of this embodiment is to provide an InfiniBand network data cache processing system.

[0070] An InfiniBand network data cache processing system is designed based on an FPGA device and includes:

[0071] A data receiving module, which is used to receive data from the IB network;

[0072] The data processing module is used to parse the received data, extract data information, and perform corresponding processing based on preset rules;

[0073] A first cross-clock domain processing module, which is used to perform cross-clock domain processing on the processed data to balance the output rate and the input rate;

[0074] A data writing and path selection module is used to read data after cross-clock domain processing and write data packet data and control information into the large-capacity storage buffer by polling the idle status of each large-capacity storage buffer;

[0075] A storage module comprising a plurality of large-capacity storage buffers, wherein the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0076] A data reading and path selection module, which is used to read the control information of the data packet and read the data of each part of the data packet from each large-capacity storage buffer in sequence according to the control information;

[0077] The second cross-clock domain processing module is used to perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0078] The data sending module is used to send the data after cross-clock preprocessing to the IB server.

[0079] Furthermore, the receiving of data from the IB network is specifically as follows:

[0080] Step 1: Capture data packet header control symbols, and perform data capture based on the data packet header control symbols;

[0081] Step 2: Capture the remaining internal data of the packet;

[0082] Step 3: Capture the control symbol at the end of the data packet and capture the complete data packet;

[0083] Step 4: Return to step 1 and recapture the next data packet.

[0084] Furthermore, the received data is parsed and data information is extracted, and corresponding processing is performed based on preset rules, specifically:

[0085] Separate the packet header and tail, and parse the internal data information according to the packet type;

[0086] Extract information, perform CRC verification, and process internal information based on preset rules;

[0087] Re-add the packet header and tail to assemble the data packet.

[0088] Furthermore, the processed data is processed across clock domains to balance the output rate and the input rate, specifically by placing multiple random access memories in parallel, writing to each random access memory in turn from top to bottom at the input end, and reading from all random access memories at the output end at the same time.

[0089] Furthermore, the read data is processed across clock domains to convert its clock domain into the same clock as the IB server, specifically by connecting multiple random access memories in parallel, reading from each random access memory in turn from top to bottom at the output end, and writing to all random access memories at the input end at the same time.

[0090] Furthermore, the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers, specifically:

[0091] Step 1: Prepare storage space for the first data packet header data and record the storage buffer number and write address control information to which the storage space belongs;

[0092] Step 2: Read the data packet header data from the first cross-clock domain processing module and temporarily store it;

[0093] Step 3: Read the next portion of data in the current data packet from the first cross-clock domain processing module;

[0094] Step 4: Write the data into each prepared large-capacity storage buffer and record the storage buffer number and write address control information;

[0095] Step 5: If the data portion is the end of the data packet, the data packet is determined to be finished, and then step 6 is executed; otherwise, jump to step 3;

[0096] Step 6: Prepare storage space for the next data packet header data, combine the data packet header data, the previously recorded data packet control information, and the number and write address control information of the storage buffer to which the storage space prepared for the next data packet header belongs, and write them into the storage space prepared for the data packet header data, and then jump to step 2.

[0097] Furthermore, the control information of the data packet is read, and each part of the data packet is read from each large-capacity storage buffer in sequence according to the control information, specifically:

[0098] Step 1: Obtain the write storage buffer number and write address control information of the first data packet header data;

[0099] Step 2: Read the storage space where the data packet header is stored, obtain the data packet header data, data control information of each part of the data packet, the storage buffer number of the next data packet header data and the write address control information;

[0100] Step 3: Sending a data packet header to the first cross-clock domain processing module;

[0101] Step 4: Determine the memory number and address of each portion of the data in the data packet according to the data packet header address control information of each portion of the data packet, thereby reading the data from each large-capacity buffer memory;

[0102] Step 5: Send data to the cross-clock domain processing data unit;

[0103] Step 6: When the data is the end of the data packet, determine that the data packet ends, read the next data packet according to the storage buffer number and write address control information of the next data packet header data in the data packet header address, and jump to step 2; otherwise, jump to step 4.

[0104] Specifically, for ease of understanding, the solution disclosed herein is described in detail below with reference to the accompanying drawings:

[0105] In order to explain the solution of this embodiment in detail, the following Figure 1 Take this as an example for description.

[0106] Figure 1 The receiving end of an FPGA-based InfiniBand network. The IB network transmits InfiniBand data from the other end of the network. The FPGA hardware and software system receives this data, captures it according to the InfiniBand protocol, modifies it (such as modifying InfiniBand flow control data to control data exchange between the IB network and the IB server), caches it, and then sends it to the IB server.

[0107] FPGAs are a type of semi-custom circuit within application-specific integrated circuits (ASICs). They are programmable logic arrays designed using Verilog HDL. This embodiment describes designing a data cache processing system within the FPGA device to capture, process or modify, cache, and retransmit data from the IB network to the IB server.

[0108] like Figure 2 As shown, the InfiniBand network data cache processing system described in this embodiment (based on FPGA device design) includes: a data receiving module, a data processing module, a first cross-clock domain processing module, a data writing and path selection module, a storage module, a data reading and path selection module, a second cross-clock domain processing module and a data sending module.

[0109] The following is an introduction to the functions of each module.

[0110] Data receiving module: Receives data from the IB network and captures it according to the format specified by the InfiniBand network protocol. A detailed description is provided below.

[0111] Data Processing Module: This module parses and extracts information from the data captured by the Data Receiver, and processes and modifies it as needed. A detailed description is provided below.

[0112] The first and second cross-clock domain processing modules use a random access memory (RAM), typically used as a temporary data storage medium. RAM can write (store) or read (retrieve) information from any specified address at any time, and different write and read clocks can be specified to process data across clock domains. This balances the output and input rates. A detailed description is provided below.

[0113] The Data Write and Path Selection Module polls each bulk storage buffer, writes each portion of the data packet to each bulk storage buffer based on idle feedback, records control information such as the write address, and writes the data to the bulk storage buffer. A detailed description is provided below.

[0114] The memory module includes several large-capacity memory buffers, including DDR, QDR and other SRAM (Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that the data stored in this type of memory can be constantly retained as long as the power is maintained.). The control maintains multiple FIFO structures in the memory.

[0115] Data Reading and Path Selection Module: Reads data packet control information and, based on this information, reads the various data components of the data packet located in each large-capacity storage buffer. A detailed description is provided below.

[0116] Send data module: sends data to the IB server.

[0117] The overall process of the solution described in this embodiment is as follows:

[0118] The data receiving module receives data from the IB network and captures it according to the format specified by the InfiniBand network protocol. A detailed description is provided below.

[0119] The data processing module parses and extracts information from the captured data, processing and modifying it as needed. A detailed description is provided below.

[0120] The first clock domain processing module processes data across clock domains, converting its clock domain to the same clock as the bulk storage buffer. By using a single input and multiple outputs, it balances the output rate with the high-speed input rate. A detailed description is provided below.

[0121] The data writing and routing module reads data from the cross-clock domain data processing unit, polls each large-capacity storage buffer, and writes the packet data and control information to the large-capacity storage buffer. Detailed description is provided below.

[0122] Multiple large-capacity storage buffers perform FIFO storage in parallel, and various parts of the same data packet are stored in different large-capacity storage buffers.

[0123] The data reading and path selection module reads the control information of the data packet and reads the data of the data packet from each large-capacity storage buffer in sequence according to the control information. Detailed description is given below.

[0124] The second clock domain processing module processes data across clock domains, converting its clock domain to the same clock as the IB server. By using multiple inputs and a single output, it balances the input rate with the high-speed output rate. A detailed description is provided below.

[0125] The data sending module reads data from the cross-clock domain data processing unit and sends the data to the IB server.

[0126] The following is a detailed description of the above process:

[0127] (1) IB data capture

[0128] According to the InfiniBand network protocol, each type of data packet has control symbols and data packet formats, and each type of data packet needs to be captured separately. Figure 3 As shown, it is divided into three steps. The first step is to capture the control symbols of the headers of various data packets, classify them and start capturing; the second step is to continue capturing the remaining internal data of the data packet; the third step is to capture the control symbols at the end of the data packet, capture the complete data packet, return to the first step, and start processing the next data packet again.

[0129] (2) IB data processing and modification

[0130] Process and modify data according to InfiniBand network protocol regulations and development and design needs. Figure 4 As shown, it is divided into three steps. The first step is to separate the packet header and tail, and parse the internal data information according to the packet type; the second step is to extract the information, perform CRC check and other processing, and modify the internal information; the third step is to re-add the packet header and tail, combine the data packet, and start the first step again.

[0131] (3) Cross-clock domain data processing

[0132] Using random access memory such as BRAM, the write and read clocks can have different characteristics, and the read clock is set to the clock of the large-capacity storage buffer, thereby converting the data clock domain to the clock domain of the large-capacity storage buffer.

[0133] exist Figure 2 In the clock domain processing storage unit A (i.e., the first clock domain processing module), its input speed is equal to that of the IB network, which is often greater than the write speed of a single large-capacity storage buffer. In order to balance the output rate and the high-speed input rate and avoid data congestion, as shown in the following example: Figure 5 As shown, by connecting multiple random access memories in parallel, data is written to each random access memory in turn from top to bottom at the input end, and all random access memories are read at the output end at the same time.

[0134] exist Figure 2 In the clock domain processing storage unit B (i.e., the second clock domain processing module), its output speed is equal to that of the IB server, which is often greater than the reading speed of a single large-capacity storage buffer. In order to balance the input rate and high-speed output rate, as shown in the following example: Figure 6 As shown, by connecting multiple random access memories in parallel, reading from each random access memory is performed in turn from top to bottom at the output end, while writing to all random access memories at the input end at the same time.

[0135] (4) Data writing and path selection

[0136] like Figure 7Writing data into the storage buffer is divided into five steps. The first step is to prepare storage space for the first data packet header data and record the storage buffer number, address, and other control information to which the storage space belongs. The second step is to read the data packet header data from the cross-clock domain data processing unit and temporarily store it. The third step is to read the next portion of data in the data packet from the cross-clock domain data processing unit. The fourth step is to query each large-capacity storage buffer in turn to see if they are ready and find the storage buffer ready for writing data. The fifth step is to write the portion of data into each prepared large-capacity storage buffer and record the storage buffer number, write address, and other control information. The sixth step is to determine that the data packet ends and continue to the seventh step if the portion of data is the end of the data packet. Otherwise, repeat the third step. The seventh step is to prepare storage space for the next data packet header data and write the data packet header data, the previously recorded control information for each portion of the data packet, and the control information such as the number and address of the storage buffer to which the storage space prepared for the next data packet header belongs into the storage space prepared for the data packet header data, and then start again from the second step.

[0137] (5) Reading data and path selection

[0138] like Figure 8 As shown, reading data from the storage buffer is divided into six steps. The first step is to obtain the write storage buffer number, address and other control information of the first data packet header data; the second step is to read the storage space where the data packet header is stored, and obtain the data packet header data, control information of each data portion of the data packet, the storage buffer number and address of the next data packet header data and other control information; the third step is to send the data packet header to the cross-clock domain data processing unit; the fourth step is to determine the memory number and address of each data portion of the data packet based on the control information of each data portion of the data packet in the data packet header address, and read the data from each large-capacity buffer memory; the fifth step is to send the data to the cross-clock domain data processing unit; the sixth step is to determine the end of the data packet if the data is the end of the data packet, and read the next data packet based on the storage buffer number and address and other control information of the next data packet header data in the data packet header address, and repeat the second step; otherwise, repeat the fourth step.

[0139] Example 2:

[0140] The purpose of this embodiment is to provide an InfiniBand network data cache processing method.

[0141] An InfiniBand network data cache processing method, based on the above-mentioned InfiniBand network data cache processing system, comprises:

[0142] Receive data from the IB Network;

[0143] Parse the received data, extract data information, and process it accordingly based on preset rules;

[0144] Perform cross-clock domain processing on the processed data to balance the output rate and input rate;

[0145] Reading data after cross-clock domain processing, and writing data packet data and control information into a storage module including a plurality of large-capacity storage buffers by polling the idle status of each large-capacity storage buffer; the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0146] Reading control information of the data packet, and sequentially reading each part of the data packet from each large-capacity storage buffer according to the control information;

[0147] Perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0148] Send the cross-clock preprocessed data to the IB server.

[0149] Furthermore, the specific details of the method described in this embodiment have been described in detail in Example 1 and will not be repeated here.

[0150] Example 3:

[0151] The purpose of this embodiment is to provide an electronic device.

[0152] An electronic device includes a memory, a processor, and a computer program stored and running on the memory, wherein the processor implements the following steps when executing the program:

[0153] Receive data from the IB Network;

[0154] Parse the received data, extract data information, and process it accordingly based on preset rules;

[0155] Perform cross-clock domain processing on the processed data to balance the output rate and input rate;

[0156] Reading data after cross-clock domain processing, and writing data packet data and control information into a storage module including a plurality of large-capacity storage buffers by polling the idle status of each large-capacity storage buffer; the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0157] Reading control information of the data packet, and sequentially reading each part of the data packet from each large-capacity storage buffer according to the control information;

[0158] Perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0159] Send the cross-clock preprocessed data to the IB server.

[0160] Example 4:

[0161] The purpose of this embodiment is to provide a non-transitory computer-readable storage medium.

[0162] A non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0163] Receive data from the IB Network;

[0164] Parse the received data, extract data information, and process it accordingly based on preset rules;

[0165] Perform cross-clock domain processing on the processed data to balance the output rate and input rate;

[0166] Reading data after cross-clock domain processing, and writing data packet data and control information into a storage module including a plurality of large-capacity storage buffers by polling the idle status of each large-capacity storage buffer; the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers;

[0167] Reading control information of the data packet, and sequentially reading each part of the data packet from each large-capacity storage buffer according to the control information;

[0168] Perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server;

[0169] Send the cross-clock preprocessed data to the IB server.

[0170] Those skilled in the art will appreciate that the units, i.e., algorithm steps, of the various examples described in this embodiment can be implemented using electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0171] The InfiniBand network data cache processing system and method provided by the above embodiment can be implemented and has broad application prospects.

[0172] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. An InfiniBand network data cache processing system, characterized in that: It is designed based on FPGA devices and includes: A data receiving module, which is used to receive data from the IB network; The data processing module is used to parse the received data, extract data information, and perform corresponding processing based on preset rules; A first cross-clock domain processing module, which is used to perform cross-clock domain processing on the processed data to balance the output rate and the input rate; The processed data is processed across clock domains to balance the output rate and the input rate, specifically by: writing to each random access memory in turn from top to bottom at the input end at the same time, and reading from all random access memories at the output end at the same time; A data writing and path selection module is used to read data after cross-clock domain processing and write data packet data and control information into the large-capacity storage buffer by polling the idle status of each large-capacity storage buffer; A storage module comprising a plurality of large-capacity storage buffers, wherein the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers; A data reading and path selection module, which is used to read the control information of the data packet and read the data of each part of the data packet from each large-capacity storage buffer in sequence according to the control information; The second cross-clock domain processing module is used to perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server; The read data is processed across clock domains to convert its clock domain to the same clock as the IB server, specifically by placing multiple random access memories in parallel, reading from each random access memory in turn from top to bottom at the output end, and writing to all random access memories at the input end at the same time; The data sending module is used to send the data after cross-clock preprocessing to the IB server.

2. The InfiniBand network data cache processing system according to claim 1, wherein: The data received from the IB network is specifically: Step 1: Capture the control symbol of the data packet header, and perform data capture based on the control symbol of the data packet header; Step 2: Capture the remaining internal data of the data packet; Step 3: Capture the control symbol at the end of the data packet and capture the complete data packet; Step 4: Return to step 1 and recapture the next data packet.

3. The InfiniBand network data cache processing system according to claim 1, wherein: The received data is parsed and data information is extracted, and corresponding processing is performed based on preset rules, specifically: Separate the packet header and tail, and parse the internal data information according to the packet type; Extract information, perform CRC verification, and process internal information based on preset rules; Re-add the packet header and tail to assemble the data packet.

4. The InfiniBand network data cache processing system according to claim 1, wherein: The data after cross-clock domain processing is read, and the data packet data and control information are written into the large-capacity storage buffer by polling the idle status of each large-capacity storage buffer, specifically: Step 1: Prepare storage space for the first data packet header data and record the storage buffer number and write address control information to which the storage space belongs; Step 2: Read the data packet header data from the first cross-clock domain processing module and temporarily store it; Step 3: Read the next portion of data in the current data packet from the first cross-clock domain processing module; Step 4: Write the data into each prepared large-capacity storage buffer and record the storage buffer number and write address control information; Step 5: If the data portion is the end of the data packet, the data packet is determined to be finished, and then step 6 is executed; otherwise, jump to step 3; Step 6: Prepare storage space for the next data packet header data, combine the data packet header data, the previously recorded data packet control information, and the number and write address control information of the storage buffer to which the storage space prepared for the next data packet header belongs, and write them into the storage space prepared for the data packet header data, and then jump to step 2.

5. The InfiniBand network data cache processing system according to claim 1, wherein: The control information of the data packet is read, and each part of the data packet is read from each large-capacity storage buffer in sequence according to the control information, specifically: Step 1: Obtain the write storage buffer number and write address control information of the first data packet header data; Step 2: Read the storage space where the data packet header is stored, obtain the data packet header data, data control information of each part of the data packet, the storage buffer number of the next data packet header data and the write address control information; Step 3: Sending the data packet header to the second cross-clock domain processing module; Step 4: Determine the memory number and address of each portion of the data in the data packet according to the data packet header address control information of each portion of the data packet, thereby reading the data from each large-capacity buffer memory; Step 5: Send data to the second cross-clock domain processing module; Step 6: When the data is the end of the data packet, determine that the data packet ends, read the next data packet according to the storage buffer number and write address control information of the next data packet header data in the data packet header address, and jump to step 2; otherwise, jump to step 4.

6. An InfiniBand network data cache processing method, based on an InfiniBand network data cache processing system according to any one of claims 1 to 5, comprising: Receive data from the IB Network; Parse the received data, extract data information, and process it accordingly based on preset rules; Perform cross-clock domain processing on the processed data to balance the output rate and input rate; Reading data after cross-clock domain processing, and writing data packet data and control information into a storage module including a plurality of large-capacity storage buffers by polling the idle status of each large-capacity storage buffer; the plurality of large-capacity storage buffers adopt parallel FIFO storage to store different parts of the same data packet in different large-capacity storage buffers; Reading control information of the data packet, and sequentially reading each part of the data packet from each large-capacity storage buffer according to the control information; Perform cross-clock domain processing on the read data and convert its clock domain to the same clock as the IB server; Send the cross-clock preprocessed data to the IB server.

7. An electronic device comprising a memory, a processor, and a computer program stored and running on the memory, wherein the processor executes the InfiniBand network data cache processing method according to claim 6.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the InfiniBand network data cache processing method according to claim 6.

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