Coordinate rotation digital computer and method thereof, signal processing circuit and chip

Abstract

The embodiment of the present application relates to a coordinate rotation digital computer circuit and a method thereof, a signal processing circuit and a chip, the coordinate rotation digital computer circuit comprising: an iterative operation module, the iterative operation module comprising: a horizontal coordinate operation unit, configured to obtain a (k+1)th horizontal coordinate x (k+1) according to a (k-1)th iteration operation obtained (k-1)th horizontal coordinate x (k) and (k-1)th vertical coordinate y (k) when k < n; obtain the (k+1)th horizontal coordinate x (k+1) according to the (k)th horizontal coordinate x (k) when k >= n; a vertical coordinate operation unit connected with the horizontal coordinate operation unit, configured to obtain a (k+1)th vertical coordinate y (k+1) according to the (k)th horizontal coordinate x (k) and the (k)th vertical coordinate y (k); a phase operation unit connected with the vertical coordinate operation unit, configured to obtain a (k+1)th phase phase (k+1) according to the (k-1)th iteration operation obtained (k-1)th phase phase (k) and the (k)th vertical coordinate y (k); and an output module connected with the iterative operation module, configured to output the (k+1)th phase phase (k+1) as a target phase of to-be-measured data when k = m.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and particularly relate to a coordinate rotation digital computer circuit and method thereof, a signal processing circuit and a chip. BACKGROUND

[0002] The coordinate rotation digital computer (CORDIC) is a way of converting trigonometric functions, inverse trigonometric functions and the like into simple operations such as addition, subtraction and shifting. Since the hardware circuit does not have the function of trigonometric functions and the like, the coordinate rotation digital computer is widely used in the field of hardware circuit to overcome the above-mentioned functional defects in the hardware circuit. However, the operation amount of the coordinate rotation digital computer in the prior art is too large, which leads to an operation speed that cannot meet the use demand of users. SUMMARY

[0003] Therefore, it is necessary to provide a coordinate rotation digital computer circuit and method thereof, a signal processing circuit and a chip with fast operation speed to solve the above technical problems.

[0004] In a first aspect, the present application provides a coordinate rotation digital computer circuit, comprising:

[0005] an iterative operation module configured to perform multiple iterative operations according to a to-be-measured data and a preset initial phase, the iterative operation module comprising:

[0006] a horizontal coordinate operation unit configured to, when k < n, obtain a (k+1)th horizontal coordinate according to a kth horizontal coordinate obtained by a (k-1)th iterative operation and the kth vertical coordinate, and when k ≥ n, obtain the (k+1)th horizontal coordinate according to the kth horizontal coordinate, wherein k is a current iteration number, n is a first number threshold, m is a second number threshold, k, m and n are all positive integers, and n < m;

[0007] a vertical coordinate operation unit connected with the horizontal coordinate operation unit and configured to obtain a (k+1)th vertical coordinate according to the kth horizontal coordinate and the kth vertical coordinate;

[0008] a phase operation unit connected with the vertical coordinate operation unit and configured to obtain a (k+1)th phase according to a kth phase obtained by a (k-1)th iterative operation and the kth vertical coordinate;

[0009] an output module connected with the iterative operation module and configured to, when k = m, output the kth phase as a target phase of the to-be-measured data.

[0010] In a second aspect, the present application provides a signal processing circuit, comprising:

[0011] The coordinate rotation digital computer as described above is used to obtain a target amplitude and a target phase of a signal to be measured.

[0012] The peak clipping circuit is connected with the coordinate rotation digital computer and is used to obtain a peak clipping signal with the preset amplitude threshold and the target phase when the target amplitude is greater than the preset amplitude threshold.

[0013] In a third aspect, the present application provides a chip comprising the coordinate rotation digital computer as described above or the signal processing circuit as described above.

[0014] In a fourth aspect, the present application provides a coordinate rotation digital computer method, comprising:

[0015] Performing multiple iteration operations according to the data to be measured and a preset initial phase;

[0016] When k = m, outputting the kth phase as a target phase of the data to be measured, k being a current iteration number;

[0017] The iteration operation comprises:

[0018] When k < n, obtaining a k+1th abscissa according to a k-1th abscissa obtained by the k-1th iteration operation and the kth ordinate; when k ≥ n, obtaining the k+1th abscissa according to the kth abscissa, n being a first number threshold; obtaining a k+1th ordinate according to the kth abscissa and the kth ordinate; obtaining a k+1th phase according to a k-1th phase obtained by the k-1th iteration operation and the kth ordinate, m being a second number threshold, k, m and n being positive integers, and n < m;

[0019] In the coordinate rotation digital computer, when obtaining the k+1th abscissa x(k+1), compared with a common operation mode of two parameters x(k) and y(k), when k ≥ n, the k+1th abscissa x(k+1) is obtained only according to one parameter x(k), which on the one hand requires less data to be obtained and on the other hand requires a simpler operation process. Therefore, the present embodiment splits the abscissa obtaining mode according to the iteration number k, and since the abscissa operation process is simplified, in the multiple iteration operations, only the first n times need to adopt the operation mode in the related art, and the remaining times can adopt a simpler operation mode, thereby improving the operation speed of the coordinate rotation digital computer. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0021] Figure 1 Structure diagram of a coordinate rotation digital computer circuit of an embodiment;

[0022] Figure 2 Structure diagram of a circuit corresponding to one iteration operation in an iteration operation module of an embodiment;

[0023] Figure 3 Structure diagram of a coordinate rotation digital computer circuit of an embodiment;

[0024] Figure 4 Structure diagram of a coordinate rotation digital computer circuit of an embodiment;

[0025] Figure 5 Flow chart of a coordinate rotation digital computer circuit method of an embodiment;

[0026] Figure 6 Subflow chart of step 502 of an embodiment. DETAILED DESCRIPTION

[0027] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0028] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise explicitly and specifically limited.

[0029] Figure 1 Structure diagram of a coordinate rotation digital computer circuit of an embodiment, refer to Figure 1 The coordinate rotation digital computer circuit includes an iteration operation module 100 and an output module 200.

[0030] The iteration operation module 100 is configured to perform multiple iteration operations according to the to-be-tested data and the preset initial phase. The output module 200 is connected with the iteration operation module 100, and the output module 200 is configured to output the kth phase as a target phase of the to-be-tested data when k = m. Wherein, k and m are positive integers, k is a current iteration number, the iteration number k is incremented by 1 after each iteration operation, and m is a second number threshold. That is, when the iteration number k is less than the second number threshold m, the iteration operation module 100 continues to perform the next iteration operation. When the iteration number k is equal to the second number threshold m, the iteration operation module 100 stops the iteration operation, and the output module 200 outputs the phase obtained by the iteration operation module 100 in the last iteration operation, that is, the output module 200 outputs the mth phase.

[0031] Specifically, the content represented by the to-be-tested data corresponds to a use scenario of the coordinate rotation digital computer. For example, the use scenario of the coordinate rotation digital computer is a radio frequency communication scenario, and the content represented by the to-be-tested data can be the characteristics of a radio frequency signal at a certain moment. The to-be-tested data is configured with a first abscissa and a first ordinate, and the preset initial phase can also be referred to as a first phase. The iteration operation module 100 can obtain an updated abscissa, ordinate and phase after each iteration operation. For example, according to the initial preset phase and the first abscissa and the first ordinate of the to-be-tested data, the first iteration operation can be performed to obtain a second abscissa, a second ordinate and a second phase. Further, according to the first abscissa, the first ordinate and the first phase obtained by the first iteration operation, the second iteration operation can be performed to obtain a second abscissa, a second ordinate and a second phase, and so on. It should be noted that in each iteration process, the abscissa, the ordinate and the phase can be obtained at the same time, or the abscissa, the ordinate and the phase can be obtained in sequence. The application embodiments do not limit the above-mentioned order of acquisition.

[0032] The second number threshold m can be 8, 12, 16, etc., and the embodiment is not limited. An exemplary simulation can be performed on the coordinate rotation digital computer by using data cases to determine the second number threshold m of the coordinate rotation digital computer. Specifically, each data case is configured with a preset first horizontal coordinate, a first vertical coordinate, and a known preset phase. During the simulation, the first horizontal coordinate and the first vertical coordinate of the data case can be input into the coordinate rotation digital computer, and the difference between the simulation phase after each iteration and the preset phase is compared. When the difference between the simulation phase and the preset phase is less than a certain value, it is determined that the current iteration number can meet the accuracy requirement. Further, a plurality of data cases can be simulated, and the iteration number corresponding to each test case that can meet the accuracy requirement is obtained, thereby comprehensively determining the second number threshold m. For example, the maximum value of the plurality of iteration numbers that can meet the accuracy requirement can be selected to determine the second number threshold m.

[0033] In the embodiment, the iteration operation module 100 includes a horizontal coordinate operation unit 110, a vertical coordinate operation unit 120, and a phase operation unit 130, and the vertical coordinate operation unit 120 is connected to the horizontal coordinate operation unit 110 and the phase operation unit 130.

[0034] The horizontal coordinate operation unit 110 is configured to perform the kth iteration operation according to the kth horizontal coordinate x(k) and the kth vertical coordinate y(k) obtained by the (k-1)th iteration operation when k < n, thereby obtaining the (k+1)th horizontal coordinate x(k+1). When k ≥ n, the (k+1)th horizontal coordinate x(k+1) is obtained according to the kth horizontal coordinate x(k). Wherein, n is the first number threshold, n is also a positive integer, and n < m. The vertical coordinate operation unit 120 is configured to obtain the (k+1)th vertical coordinate y(k+1) according to the kth horizontal coordinate x(k) and the kth vertical coordinate y(k). The phase operation unit 130 is configured to obtain the (k+1)th phase phase(k+1) according to the kth phase phase(k) obtained by the (k-1)th iteration operation and the kth vertical coordinate y(k).

[0035] It can be understood that, when the k+1th abscissa x(k+1) is obtained, compared with the way of operating jointly according to two parameters x(k) and y(k), when k≥n, x(k+1) is obtained only according to one parameter x(k), on the one hand, the amount of data to be obtained is less, and on the other hand, the operation process to be performed is also simpler. Therefore, the embodiment splits the abscissa obtaining manner according to the iteration number k, can obtain the required operation accuracy through the first n times of iteration operation, and then improves the operation speed through the last m-n times of iteration operation. The inventor finds that, in the related art, for the abscissa, the same operation manner is usually adopted for each iteration operation. Therefore, three operations are required for each iteration to obtain the abscissa, the ordinate and the phase, respectively. Taking the second number threshold m as an example, the coordinate rotation digital operation circuit in the related art needs to perform 3*m operations. However, in the embodiment, since the operation process of the abscissa is simplified, only the first n times need to adopt the operation manner in the related art, and the remaining times can adopt a relatively simple operation manner, so that the operation speed of the coordinate rotation digital operation circuit is improved.

[0036] In one embodiment, the kth abscissa x(k) can be directly taken as the k+1th abscissa x(k+1), that is, x(k+1)=x(k). Based on the above manner, when k≥n, the k+1th abscissa x(k+1) can be obtained without any operation, so that the operation amount of obtaining the abscissa when k≥n is minimized. That is, only the first n times of iteration needs to be operated, and the remaining times do not need to be operated. Therefore, the coordinate rotation digital operation circuit of the embodiment only needs to perform 2*m+n operations, so that the operation speed of the coordinate rotation digital operation circuit is further improved.

[0037] The coordinate rotation digital computer can adopt any one of a serial structure, a parallel structure, and a parallel pipeline structure, and the circuit structure corresponding to one iteration operation of the iteration operation module 100 can be set according to actual needs, and the embodiment is not limited in this regard. The serial structure time-multiplexes the iteration operation module 100, and continuously transmits the data output by the output end of the iteration operation module 100 to the input end of the iteration operation module 100, so that the space occupied by the coordinate rotation digital computer is minimized, but the control timing is relatively complex. The parallel structure is an extension of the serial structure, and each iteration operation is assigned an independent operation circuit. For example, the horizontal coordinate operation unit 110 includes a plurality of independent operation circuits. Each operation circuit in the parallel structure thus does not need to be connected to a control circuit, and only needs to perform a shift, addition, or subtraction operation determined by the circuit connection relationship. Compared with the serial structure, the parallel structure can have a better operation speed. The parallel pipeline structure adds a pipeline register to the parallel structure, so that the length of the critical path changes from N operation circuits in the parallel structure to one operation circuit. Therefore, the parallel pipeline structure has the fastest processing speed, but at the cost of consuming more resources. When the parallel structure or the parallel pipeline structure is adopted, the circuit structure corresponding to one iteration operation of the iteration operation module 100 of the embodiment does not need to be provided with the operation circuit of the horizontal coordinate from the nth time to the mth time, so that the number of operation circuits that need to be set can be reduced, and the area and power consumption of the coordinate rotation digital computer can be reduced.

[0038] In one embodiment, the operation of obtaining the (k+1)th horizontal coordinate x(k+1) according to the kth horizontal coordinate x(k) and the kth vertical coordinate y(k), the operation of obtaining the (k+1)th vertical coordinate y(k+1) according to the kth horizontal coordinate x(k) and the kth vertical coordinate y(k), and the operation of obtaining the (k+1)th phase phase(k+1) according to the kth phase phase(k) and the kth vertical coordinate y(k) can be implemented in a manner in the related art.

[0039] Specifically, the circuit structure corresponding to one iteration operation includes a horizontal coordinate operation circuit, a vertical coordinate operation circuit, and a phase operation circuit. The horizontal coordinate operation unit 110 includes a plurality of horizontal coordinate operation circuits, the vertical coordinate operation unit 120 includes a plurality of vertical coordinate operation circuits, and the phase operation unit 130 includes a plurality of phase operation circuits. Figure 2 The circuit structure corresponding to one iteration operation of the iteration operation module 100 of one embodiment is shown in FIG. 2. Figure 2, the horizontal coordinate operation circuit includes a first shift register, a first addition-subtraction operation circuit and a most significant bit (MSB) acquisition circuit. The first shift register is configured to perform shift processing on the kth vertical coordinate y(k), and the first addition-subtraction operation circuit is configured to perform one of addition and subtraction operation on the kth horizontal coordinate x(k) and the kth vertical coordinate y(k) after the shift processing. The MSB acquisition circuit is configured to acquire the MSB of the kth vertical coordinate y(k), so as to determine the approximation direction in the iterative operation, i.e., to determine whether the first addition-subtraction operation circuit performs addition operation or subtraction operation. Specifically, when the MSB of the kth vertical coordinate y(k) is positive, y(k)>0, the first addition-subtraction operation circuit performs addition operation, x(k+1)=x(k)+y(k)>>k; when the MSB of the kth vertical coordinate y(k) is negative, y(k)<0, the first addition-subtraction operation circuit performs subtraction operation, x(k+1)=x(k)-y(k)>>k. The vertical coordinate operation circuit includes a second shift register, a second addition-subtraction operation circuit, a MSB acquisition circuit and an inverter. The second shift register is configured to perform shift processing on the kth horizontal coordinate x(k), and the second addition-subtraction operation circuit is configured to perform one of addition and subtraction operation on the kth vertical coordinate y(k) and the kth horizontal coordinate x(k) after the shift processing. The MSB acquisition circuit is configured to acquire the MSB of the kth vertical coordinate y(k), so as to determine the approximation direction in the iterative operation, i.e., to determine whether the second addition-subtraction operation circuit performs addition operation or subtraction operation. Specifically, when the MSB of the kth vertical coordinate y(k) is positive, y(k)>0, the second addition-subtraction operation circuit performs subtraction operation, y(k+1)=y(k)-x(k)>>k; when the MSB of the kth vertical coordinate y(k) is negative, y(k)<0, the second addition-subtraction operation circuit performs addition operation, y(k+1)=y(k)+x(k)>>k. The phase operation circuit includes a third addition-subtraction operation circuit and a MSB acquisition circuit. The third addition-subtraction operation circuit is configured to perform one of addition and subtraction operation on the kth phase phase(k) and a preset phase iterative increment θk. The MSB acquisition circuit is configured to acquire the MSB of the kth vertical coordinate y(k), so as to determine the approximation direction in the iterative operation, i.e., to determine whether the third addition-subtraction operation circuit performs addition operation or subtraction operation. Specifically, when the MSB of the kth vertical coordinate y(k) is positive, y(k)>0, the third addition-subtraction operation circuit performs addition operation, phase(k+1)=phase(k)+θk; when the MSB of the kth vertical coordinate y(k) is negative, y(k)<0, the third addition-subtraction operation circuit performs subtraction operation, phase(k+1)=phase(k)-θk. The preset phase iterative increment θk is determined according to the following formula: θk=2π / (2k+1) .

[0040] In one of the embodiments, the output module 200 is further configured to output the target amplitude of the to-be-tested data when k = m, the target amplitude being determined according to the k-th coordinate x(k) obtained in the (k-1)-th iteration operation and a compensation factor, the compensation factor having a preset mapping relationship with the first number threshold n. Specifically, the target phase is equal to the product of the (k+1)-th coordinate x(k+1) and the compensation factor C. It can be understood that, since the value of the coordinate does not change after the n-th iteration operation, the compensation factor corresponding to the first number threshold n is needed to be compensated to obtain the accurate target amplitude. Wherein, The compensation factor can be pre-stored in the storage circuit in the form of a lookup table and obtained directly when needed.

[0041] In one of the embodiments, the coordinate rotation digital computer further comprises an initialization module. The initialization module is configured to obtain and output a first horizontal coordinate and a first vertical coordinate according to a to-be-tested signal, and output the preset initial phase. Wherein, the to-be-tested signal is expressed in a complex number form as the to-be-tested data, the first horizontal coordinate is a real part of the to-be-tested data, and the first vertical coordinate is an imaginary part of the to-be-tested data. Specifically, let the to-be-tested data be , is an imaginary unit, , When , the initial phase is When , the and are taken inversely, and the initial phase is set as .

[0042] Figure 3 is a structure diagram of the coordinate rotation digital computer of one of the embodiments, for reference Figure 3 In one of the embodiments, the iteration operation module 100 further comprises an amplitude comparison unit 140. Wherein, the amplitude comparison unit 140 is connected with the horizontal coordinate operation unit 110, the vertical coordinate operation unit 120 and the phase operation unit 130 respectively. The amplitude comparison unit 140 is configured to judge whether the k-th coordinate x(k) satisfies a preset horizontal coordinate condition when k = n. When the preset horizontal coordinate condition is satisfied, the horizontal coordinate operation unit 110, the vertical coordinate operation unit 120 and the phase operation unit 130 are controlled to perform the k-th iteration operation.

[0043] It can be understood that in some application scenarios, it is only meaningful to obtain the target phase and the target amplitude by the coordinate rotation digital computer only when the amplitude of the data to be measured is greater than a certain preset amplitude threshold. For example, in the scenario of crest factor reduction (CFR), only when the target amplitude of the signal is greater than the preset amplitude threshold, the preset peak clipping window function needs to be weighted according to the sine value and the cosine value of the target phase, so as to realize the peak clipping function. In other words, when the target amplitude of the signal is less than or equal to the preset amplitude threshold, there is no need to perform peak clipping, and accordingly there is no need to obtain the target phase. Therefore, in this case of less than or equal to the preset amplitude threshold, there is no need to perform the subsequent iterative operation, thereby the power consumption of the coordinate rotation digital computer in the operation process can be greatly reduced.

[0044] For example, the preset abscissa condition can be that the nth abscissa is greater than a preset abscissa threshold. The preset abscissa threshold can be determined according to the preset amplitude threshold and the compensation factor, so as to indirectly determine whether the target amplitude of the data to be measured is greater than the preset amplitude threshold. For another example, the preset abscissa condition can be that the current amplitude is greater than the preset amplitude threshold, and then the current amplitude can be obtained according to the nth abscissa and the compensation factor, and the current amplitude and the preset amplitude threshold are compared, so as to directly determine whether the target amplitude of the data to be measured is greater than the preset amplitude threshold. In this embodiment, by the above manner, it can be determined in time whether the iterative operation needs to be continued, thereby improving the operation efficiency and reducing the power consumption. It can be understood that since the target amplitude is equal to the value of the current amplitude obtained according to the nth abscissa, if the preset abscissa condition is determined by the amplitude, the output module 200 does not need to obtain the target amplitude again before outputting, but can directly output the current amplitude, thereby reducing the operation amount.

[0045] In one embodiment, the amplitude comparison unit 140 is further connected with the output module 200, and the amplitude comparison unit 140 is further configured to control the abscissa operation unit 110, the ordinate operation unit 120 and the phase operation unit 130 to stop the iterative operation, and control the output module 200 to output the target amplitude when the preset abscissa condition is not met. In this embodiment, by stopping the iterative operation in time and outputting the target amplitude, the subsequent iterative operation can be avoided, thereby reducing the operation amount. Moreover, by outputting the target amplitude, the actual situation of the data to be measured can be informed to the user, thereby facilitating other processing and analysis.

[0046] Figure 4 For a structure diagram of the coordinate rotation digital computer of one embodiment, refer to FIG. 3. Figure 4In one of the embodiments, the iteration operation module 100 further comprises a sine operation unit 150 and a cosine operation unit 160. The sine operation unit 150 is connected with the longitudinal coordinate operation unit 120, and is configured to obtain a (k+1)th sine value according to a kth sine value, a kth cosine value and a kth longitudinal coordinate y(k) obtained by the k-1th iteration operation. The cosine operation unit 160 is connected with the longitudinal coordinate operation unit 120 and the sine operation unit 150 respectively, and is configured to obtain a (k+1)th cosine value according to the kth sine value, the kth cosine value and the kth longitudinal coordinate y(k). The output module 200 is further connected with the sine operation unit 150 and the cosine operation unit 160 respectively, and is configured to output a target sine value and / or a target cosine value of the to-be-measured data when k=m, the target sine value being the kth sine value, and the target cosine value being the kth cosine value. It can be understood that in some application scenarios, subsequent processing needs to be performed according to the target sine value and / or the target cosine value of the to-be-measured data. For example, a pre-set peak clipping window function can be weighted according to the target sine value and the target cosine value. In this embodiment, the target sine value and the target cosine value of the to-be-measured data can be obtained at the same time when the horizontal coordinate, the longitudinal coordinate and the phase are obtained, and compared with the mode of obtaining the target sine value and the target cosine value according to the target phase after the target phase is obtained, the mode of this embodiment can further improve the operation speed.

[0047] The embodiment of the present application further provides a signal processing circuit, comprising a peak clipping circuit and a coordinate rotation digital operation circuit as described above. The coordinate rotation digital operation circuit is configured to obtain a target amplitude and a target phase of a to-be-measured signal. The peak clipping circuit is connected with the coordinate rotation digital operation circuit, and is configured to obtain a peak clipping signal with a preset amplitude threshold and the target phase when the target amplitude is greater than the preset amplitude threshold.

[0048] Specifically, Orthogonal Frequency Division Multiplexing (OFDM) is a waveform commonly used in 4G LTE and 5G NR uplink and downlink, offering advantages such as high spectrum utilization, strong anti-fading capability, and strong anti-inter-symbol interference capability. However, a drawback of OFDM technology is its excessively high Peak-to-Average Power Ratio (PAPR) in the time domain, meaning the peak power is much greater than the average power. Signals with high PAPR easily cause the RF power amplifier to operate in the nonlinear region, reducing its efficiency and introducing nonlinear out-of-band power leakage, a critical problem that mobile communication system transmitters need to address. Therefore, this embodiment employs a peak factor reduction method. For sampled values ​​in the time-domain complex signal whose amplitude exceeds a certain threshold, the peak factor is reduced to below the threshold according to the original phase, and corresponding time-domain smoothing is performed. For example, for the signal... ,if Preset amplitude threshold The signal will then be reduced to During the reduction process, the target amplitude and target phase of the signal under test can be obtained through the coordinate rotation digital operation circuit of the above embodiment, thereby improving the operation speed of the signal processing circuit and reducing the size of the signal processing circuit.

[0049] This application also provides a chip, including the coordinate rotation digital arithmetic circuit as described above or the signal processing circuit as described above. Based on the coordinate rotation digital arithmetic circuit of the above embodiments, the chip of this embodiment can have a smaller size and a faster processing speed. Wherein, when a signal processing circuit is included, the chip can have a faster signal processing speed.

[0050] This application also provides a coordinate rotation digital arithmetic circuit method. Figure 5 A flowchart of a coordinate rotation digital computation circuit method according to an embodiment is provided. Figure 5 The coordinate rotation digital operation circuit method includes steps 502 to 504. Here, k is the current iteration number, n is the first iteration threshold, and m is the second iteration threshold. k, m, and n are all positive integers, and n... <m。

[0051] Step 502: Perform multiple iterative calculations based on the data to be tested and the preset initial phase.

[0052] Step 504: When k=m, output the k-th phase phase(k) as the target phase of the data to be measured.

[0053] in, Figure 6 Here is a sub-flowchart of step 502 in one embodiment, refer toFigure 6 The iteration operation in step 502 includes steps 5022 to 5028.

[0054] In step 5022, when k < n, the k+1th abscissa x(k+1) is obtained according to the kth abscissa x(k) and the kth ordinate y(k) obtained in the k-1th iteration operation.

[0055] In step 5024, when k ≥ n, the k+1th abscissa x(k+1) is obtained according to the kth abscissa x(k).

[0056] In step 5026, the k+1th ordinate y(k+1) is obtained according to the kth abscissa x(k) and the kth ordinate y(k).

[0057] In step 5028, the k+1th phase phase(k+1) is obtained according to the kth phase phase(k) and the kth ordinate y(k).

[0058] In the embodiment, when the k+1th abscissa x(k+1) is obtained, compared with the operation mode of obtaining the abscissa and the ordinate according to two parameters x(k) and y(k), the abscissa x(k+1) is obtained according to one parameter x(k) when k ≥ n, which reduces the amount of data to be obtained and simplifies the operation process. Therefore, in the embodiment, the operation process of the abscissa is simplified, and only the first n times of iteration operation needs to be performed according to the operation mode in the related art, and the remaining times of iteration operation can be performed according to a simple operation mode, thereby improving the operation speed of the coordinate rotation digital computer.

[0059] In one embodiment, before the multiple iteration operations are performed according to the to-be-tested data and the preset initial phase, the method further includes the following steps: obtaining a target operation precision; performing multiple iteration operations according to the preset correction data and the preset initial phase, and respectively calculating the amplitudes and phases corresponding to the abscissas, the ordinates and the phases obtained in each iteration operation; determining the iteration number corresponding to the amplitude with the target operation precision as the n, and determining the iteration number corresponding to the phase with the target operation precision as the m.

[0060] Specifically, based on the operation circuit provided in the foregoing embodiments, with the increase of the iteration number k, the iteration variable abscissa x is monotonously increasing. However, the iteration variable abscissa y is constantly fluctuating in the positive and negative range. Therefore, with the increase of the iteration number k and the decrease of y, the iteration increment of the abscissa x is decreasing at a double speed. This means that, on the one hand, the output accuracy of the amplitude is much higher than that of the phase at the same iteration number. On the other hand, if the same output accuracy is required, the iteration number required by the amplitude is about half of that required by the phase. At the same time, the value of the second number threshold m depends on the output accuracy required by the algorithm. The higher the accuracy requirement, the greater the value of the second number threshold m. Therefore, in the embodiment, by comparing the first iteration increment and the second iteration increment, the appropriate iteration number k can be determined after the second number threshold m is determined according to the output accuracy, so that the amplitude and the phase have similar output accuracy.

[0061] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.

[0062] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A coordinate rotation digital arithmetic circuit, characterized in that, Comprising: An iterative operation module for obtaining a target operation accuracy; Performing multiple iterative operations based on preset calibration data and a preset initial phase, and respectively calculating the amplitudes and phases corresponding to the abscissas, ordinates, and phases obtained from each iterative operation; Determining that the number of iterations corresponding to the amplitude with the target operation accuracy is n, and determining that the number of iterations corresponding to the phase with the target operation accuracy is m; Performing multiple iterative operations based on the data to be measured and the preset initial phase, and the iterative operation module includes: An abscissa operation unit for obtaining the (k + 1)-th abscissa based on the k-th abscissa and the k-th ordinate obtained from the (k - 1)-th iterative operation when k < n; and obtaining the (k + 1)-th abscissa based on the k-th abscissa when k ≥ n, where k is the current number of iterations, n is the first number threshold, m is the second number threshold, k, m, and n are all positive integers, and n < m; An ordinate operation unit connected to the abscissa operation unit for obtaining the (k + 1)-th ordinate based on the k-th abscissa and the k-th ordinate; A phase operation unit connected to the ordinate operation unit for obtaining the (k + 1)-th phase based on the k-th phase obtained from the (k - 1)-th iterative operation and the k-th ordinate; An output module connected to the iterative operation module for outputting the k-th phase as the target phase of the data to be measured when k = m.

2. The coordinate rotation digital operation circuit according to claim 1, characterized in that, The output module is further configured to output the target amplitude of the data to be measured when k = m, and the target amplitude is determined based on the k-th abscissa obtained from the (k - 1)-th iterative operation and a compensation factor, and the compensation factor has a preset mapping relationship with the first number threshold n.

3. The coordinate rotation digital operation circuit according to claim 2, characterized in that, The iterative operation module further includes: An amplitude comparison unit connected to the abscissa operation unit, the ordinate operation unit, and the phase operation unit respectively. The amplitude comparison unit is configured to determine whether the k-th abscissa satisfies a preset abscissa condition when k = n, and when the preset abscissa condition is satisfied, controlling the abscissa operation unit, the ordinate operation unit, and the phase operation unit to perform the k-th iterative operation.

4. The coordinate rotation digital operation circuit according to claim 3, characterized in that, The amplitude comparison unit is further connected to the output module, and the amplitude comparison unit is further configured to control the abscissa operation unit, the ordinate operation unit, and the phase operation unit to stop the iterative operation and control the output module to output the target amplitude when the preset abscissa condition is not satisfied.

5. The coordinate rotation digital operation circuit according to claim 1, characterized in that, The iterative operation module further includes: A sine operation unit connected to the ordinate operation unit for obtaining the (k + 1)-th sine value based on the k-th sine value, the k-th cosine value, and the k-th ordinate obtained from the (k - 1)-th iterative operation; A cosine operation unit connected to the ordinate operation unit and the sine operation unit respectively for obtaining the (k + 1)-th cosine value based on the k-th sine value, the k-th cosine value, and the k-th ordinate; Wherein, the output module is also respectively connected to the sine operation unit and the cosine operation unit, and is used to output the target sine value and / or the target cosine value of the measured data when k = m, the target sine value is the k-th sine value, and the target cosine value is the k-th cosine value.

6. The coordinate rotation digital operation circuit according to claim 1, characterized in that, It further includes: An initialization module, configured to respectively obtain and output a first abscissa and a first ordinate according to the measured signal; And output the preset initial phase; Wherein, the measured signal is expressed in a complex number form as the measured data, the first abscissa is the real part of the measured data, and the first ordinate is the imaginary part of the measured data.

7. A signal processing circuit, characterized in that, It includes: The coordinate rotation digital operation circuit according to any one of claims 2 to 6, configured to obtain the target amplitude and the target phase of the measured signal; A clipping circuit, connected to the coordinate rotation digital operation circuit, configured to obtain a clipped signal having the preset amplitude threshold and the target phase when the target amplitude is greater than the preset amplitude threshold.

8. A chip, characterized in that, It includes the coordinate rotation digital operation circuit according to any one of claims 1 to 6 or the signal processing circuit according to claim 7.

9. A coordinate rotation digital arithmetic circuit method, characterized in that, It includes: Obtain the target operation accuracy; Perform multiple iterative operations according to the preset correction data and the preset initial phase, and respectively calculate the amplitudes and phases corresponding to the abscissa, ordinate and phase obtained by each iterative operation; Determine that the number of iterations corresponding to the amplitude having the target operation accuracy is n, and determine that the number of iterations corresponding to the phase having the target operation accuracy is m; Perform multiple iterative operations according to the measured data and the preset initial phase; When k = m, output the k-th phase as the target phase of the measured data, where k is the current number of iterations; Wherein, one iterative operation includes: When k < n, obtain the (k + 1)-th abscissa according to the k-th abscissa and the k-th ordinate obtained by the (k - 1)-th iterative operation; when k ≥ n, obtain the (k + 1)-th abscissa according to the k-th abscissa, where n is the first number threshold; obtain the (k + 1)-th ordinate according to the k-th abscissa and the k-th ordinate; obtain the (k + 1)-th phase according to the k-th phase obtained by the (k - 1)-th iterative operation and the k-th ordinate, where k, m, and n are all positive integers, and n < m.

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