System on chip module verification apparatus and system on chip system verification method

Abstract

This invention proposes a system-on-a-chip (SoC) module verification device and a system-on-a-chip (SoC) system verification method. The device includes: a multi-protocol universal interface configured to connect to SoC modules under test with different data buses; and a module verification chip configured to generate stimulus signals and send them to the SoC module under test via the multi-protocol universal interface, and to receive response signals from the SoC module under test and monitor the stimulus signals and response signals via the multi-protocol universal interface. The SoC module verification device of this invention enables simultaneous verification of module functional coverage and interface communication functions at the module level, and allows the verification environment to be easily reused in system-level SoC verification, thereby improving the efficiency of system-level SoC verification.

Description

Technical Field

[0001] This invention relates to the field of system-on-chip (SoC) verification technology, and in particular to a system-on-chip module verification device and a system-on-chip system verification method. Background Technology

[0002] For the verification of a complex system-on-a-chip (SoC), verification engineers typically conduct the verification work from the bottom up, in layers, from the module level to the subsystem level and then to the system level. Module-level verification mainly focuses on whether the module's own functions are fully covered, while functions involving cross-unit interaction, such as module interface communication functions, need to be verified at the higher system level.

[0003] However, for system-level verification, the verification of module communication function is only one of its many functional verifications. In addition, it also needs to perform various verifications such as functional coupling verification and system performance verification. Furthermore, due to the large scale of the system, running a verification cycle takes a long time, and the paths that need to be traced will also increase exponentially, making it difficult to locate the problem. The above problems make system-on-chip verification extremely time-consuming and inefficient.

[0004] Therefore, improving the verification efficiency of system-on-a-chip systems is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] To address the aforementioned technical problems, in a first aspect of the present invention, a system-on-a-chip (SoC) module verification device is proposed, comprising: a multi-protocol universal interface configured to connect to SoC modules under test with different data buses; and a module verification chip configured to generate an excitation signal and send it to the SoC module under test through the multi-protocol universal interface, and to receive a response signal from the SoC module under test and monitor the excitation signal and the response signal through the multi-protocol universal interface.

[0006] In one or more embodiments, the module verification chip includes a reference model having the same logical function as the system-on-a-chip module under test, a monitoring module, a comparator, and multiple module verification ports. The multiple module verification ports are respectively connected to the multi-protocol universal interface. The multiple module verification ports include: a first module verification port configured to generate an excitation signal; a second module verification port configured to monitor the slave interface of the system-on-a-chip module under test; a third module verification port configured to generate a feedback signal to the response signal; and a fourth module verification port configured to monitor the master interface of the system-on-a-chip module under test. The multiple module verification ports are provided by the monitoring module.

[0007] In one or more embodiments, the reference model is configured to obtain the excitation signal sequentially through the multi-protocol general interface and the second module verification port, and generate a corresponding first response signal to send to the comparator.

[0008] In one or more embodiments, the comparator is configured to obtain a second response signal from the system-on-a-chip module under test to the stimulus through the fourth module verification port, and compare it with the first response signal to verify the logic function and interface communication function of the system-on-a-chip module under test.

[0009] In one or more embodiments, the multi-protocol universal interface includes: a first master interface configured to connect the first module verification port and the slave interface of the system-on-a-chip (SoC) under test; a first slave interface configured to connect the third module verification port and the master interface of the SoC under test; a second slave interface, a first connector, and a first slave bind interface connected in sequence, wherein the first slave interface is configured to connect to the second module verification port, and the first slave bind interface is configured to bind to the slave interface of the SoC module under test; and a second master interface, a second connector, and a second slave bind interface connected in sequence, wherein the second slave interface is configured to connect to the fourth module verification port, and the second slave bind interface is configured to bind to the master interface of the SoC module under test.

[0010] In one or more embodiments, the first connector and the second connector are configured to control the connection or disconnection of the passage in which they reside.

[0011] In one or more embodiments, the system-on-a-chip module verification device further includes an interface configuration file configured to control the connection objects of the multi-protocol general interface through macro definitions.

[0012] In one or more embodiments, the connection object includes: a system-on-a-chip module under test, a system-on-a-chip subsystem, or a system-on-a-chip system.

[0013] In one or more embodiments, the interface configuration file further includes preset connection relationships between system-on-a-chip subsystems in the system-on-a-chip system and connection relationships between system-on-a-chip modules within each subsystem.

[0014] In a second aspect of the invention, a system-on-a-chip (SoC) system verification method is proposed. The method includes the following steps implemented using the SoC module verification devices described in the above embodiments: verifying each SoC module of the SoC system using multiple preset SoC module verification devices to obtain multiple reference models and multiple comparators corresponding to each SoC module; during the SoC system verification stage, binding the bind interface of the multi-protocol universal interface with the corresponding interface of each SoC module to verify the logical functions and interface communication functions of each SoC module; and responding to a fault in the SoC system, having the corresponding SoC module verification device report an error and locate the fault.

[0015] The beneficial effects of this invention include: the system-on-a-chip module verification device of this invention enables simultaneous verification of the module's functional coverage (i.e., logical functions) and interface communication functions during the module-level system-on-a-chip verification process; furthermore, the system-on-a-chip module verification device of this invention can be reused in the system-level system-on-a-chip verification process, thereby avoiding the repeated construction of the verification environment during the system-level system-on-a-chip verification process, and can also be used to locate faults when system-on-a-chip system failures occur, thereby improving the convergence speed of system-on-a-chip system verification. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the system-on-a-chip module verification device of the present invention;

[0018] Figure 2 This is a schematic diagram of the system-on-a-chip module verification device according to a specific embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the connection relationship when the system-on-a-chip module verification device of the present invention is applied to system-on-a-chip verification at the system level;

[0020] Figure 4 This is a flowchart of the system-on-a-chip system verification method of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0022] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0023] Figure 1 This is a schematic diagram of the system-on-a-chip module verification device of the present invention. Figure 1 As shown, the system-on-a-chip module verification device of the present invention includes: a multi-protocol universal interface 100 configured to connect to a system-on-a-chip module 300 under test with different data buses; and a module verification chip 200 configured to generate an excitation signal and send it to the system-on-a-chip module 300 under test through the multi-protocol universal interface 100, and receive a response signal from the system-on-a-chip module 300 under test and monitor the excitation signal and response signal through the multi-protocol universal interface 100.

[0024] In this embodiment, the present invention designs a system-on-a-chip (SoC) module verification device. This device can connect to various SoC modules with different data buses and can verify the logic function of the SoC module under test by sending stimuli to the SoC module under test and receiving responses. In addition, during this process, it can also verify the interface communication function of the SoC module under test by monitoring the stimuli and response signals on the corresponding interfaces of the SoC module under test. This greatly reduces the occurrence of faults in the subsequent SoC verification process and helps to improve the convergence speed and efficiency of SoC verification.

[0025] In a further embodiment, the module verification chip 200 includes a reference model 210 having the same logical function as the system-on-a-chip module under test (SoC), a monitoring module 220, a comparator 230, and multiple module verification ports 221-224. These multiple module verification ports are respectively connected to the multi-protocol universal interface 100. The multiple module verification ports 221-224 include: a first module verification port 221 configured to generate an excitation signal; a second module verification port 222 configured to monitor the slave interface of the SoC 300 under test; a third module verification port 223 configured to generate a feedback signal to the response signal; and a fourth module verification port 224 configured to monitor the master interface of the SoC 300 under test. The multiple module verification ports are provided by the monitoring module 220.

[0026] Specifically, the aforementioned monitoring module 220 is a monitoring program written in System Verilog. Different module monitoring ports (i.e., ...) provided by the monitoring module... Figure 1 The VIP port (hereinafter referred to as VIP port for ease of description) corresponds to different monitoring subroutines. VIP port is an abbreviation for Authentication IP, and each IP corresponds to a device under test, such as the system-on-a-chip module under test (i.e., the VIP port). Figure 1 (The DUT in the diagram). The VIP port has two operating modes: passive and active. In passive mode, the VIP port monitors the master and slave interfaces of the system-on-a-chip (SoC) under test. In active mode, the VIP port acts as a command sender, generating stimulus signals or feedback signals to the SoC module's response signals, i.e., responding to the SoC module 300 under test. The aforementioned multi-protocol general-purpose interface 100 is an integrated interface composed of multiple interfaces capable of communicating with each other.

[0027] The reference model 210 in the aforementioned monitoring chip 200 is configured to obtain excitation signals sequentially through the multi-protocol general interface 100 and the second module verification port 222, and generate a corresponding first response signal to send to the comparator 230. The comparator 230 is configured to obtain a second response signal from the system-on-a-chip module 300 under test in response to the excitation through the fourth module verification port 224, and compare it with the first response signal to verify the logic function and interface communication function of the system-on-a-chip module under test. An error is reported when the first response signal and the second response signal are different.

[0028] In the above verification process, the existing technology passed... Figure 1 The path indicated by "×" obtains the excitation or response signal. However, during subsystem / system-level verification, these active VIP ports are replaced by the actual RTL module, and the connection between the DUT and the active VIP ports no longer exists. This makes it difficult to reuse the reference model 210 and comparator 230 at higher levels. Therefore, in this invention, the input and output data of the reference model 210 and comparator 230 are no longer obtained from the monitor of the active VIP port, but from the monitor of the passive VIP port. This allows all components in the monitoring module, such as the reference model and comparator, to be directly reused at higher levels, assisting in quickly locating faults in high-level system-on-a-chip verification and accelerating the verification speed of the entire system-on-a-chip system.

[0029] Figure 2 This is a schematic diagram of the system-on-a-chip module verification device according to a specific embodiment of the present invention. Figure 2 The present invention provides a more detailed description of the composition of the multi-protocol universal interface 100. For example... Figure 2 As shown, MST represents the master interface and SLV represents the slave interface. The multi-protocol universal interface 100 includes: a first master interface configured to connect the first module verification port and the slave interface of the system-on-a-chip (SoC) under test; a first slave interface configured to connect the third module verification port and the master interface of the SoC under test; a second slave interface, a first connector, and a first slave bind interface connected in sequence, wherein the first slave interface is configured to connect to the second module verification port, and the first slave bind interface is configured to bind to the slave interface of the SoC module under test; a second master interface, a second connector, and a second slave bind interface connected in sequence, wherein the second slave interface is configured to connect to the fourth module verification port, and the second slave bind interface is configured to bind to the master interface of the SoC module under test. In this embodiment, the present invention uses the bind method to connect the passive VIP port and the corresponding active VIP port to the master / slave interface of the same SoC module under test, thereby realizing simultaneous communication and communication monitoring. The first connector and the second connector are configured to control the conduction or disconnection of their respective paths to control whether to monitor the interface of the SoC module under test.

[0030] In a further embodiment, the system-on-a-chip (DUT) module verification device further includes an interface configuration file. This configuration file configures connection objects for controlling a multi-protocol general interface via macro definitions. The connection objects include: the DUT module under test, a DUT subsystem, or a DUT system. In this embodiment, macros are used as switches to change the DUT path, enabling the DUT to be quickly applied at both the module and system levels via include statements.

[0031] In a further embodiment, the interface configuration file also pre-defines the connection relationships between various system-on-a-chip (SoC) subsystems within the SoC system, as well as the connection relationships between various SoC modules within each subsystem. During SoC system testing, the top-level connection primarily connects the corresponding port signals in the DUT to the interface signals of the active VIP port or passive VIP port for data interaction between the VIP subroutine and the DUT. However, when there is a real RTL interface connected to the DUT at the system level, the connection relationships in the top-level file cannot be fully reused. Therefore, in this invention, the subsystem reused connection portion of the top-level file is written separately in the hdl_connect interface configuration file, thereby ensuring the application of the SoC module verification device of this invention in the subsystem-level / system-level SoC verification process.

[0032] Figure 3 This is a schematic diagram illustrating the connection relationships when the system-on-a-chip module verification device of the present invention is applied to system-level chip verification. For example... Figure 3 As shown, devices 0-3 are the system-level chip module verification devices of the present invention; devices 0-2 each implement module-level system-level chip verification; devices 0-2 together implement subsystem-level system-level chip verification; devices 0-3 together implement system-level system-level chip verification. For device 0-3, the objects it connects to can be controlled by configuring the macro definitions in the corresponding interface configuration file.

[0033] Based on the above embodiments, the present invention also proposes a system-on-a-chip system verification method. Figure 4 This is a flowchart illustrating the system-on-a-chip verification method of the present invention. Figure 4 As shown, the workflow of the system-on-a-chip (SoC) system verification method of the present invention utilizes the following steps implemented by the SoC module verification devices in the above embodiments: Step S1: Verify each SoC module of the SoC system using multiple preset SoC module verification devices to obtain multiple reference models and multiple comparators corresponding to each SoC module; Step S2: In the SoC system verification stage, bind the bind interface of the multi-protocol general interface to the corresponding interface of each SoC module to verify the logical functions and interface communication functions of each SoC module; Step S3: In response to a fault in the SoC system, the corresponding SoC module verification device reports the error and locates the fault.

[0034] In the system-on-a-chip (SoC) system verification method of the present invention, the verification devices for each SoC module can be configured by the personnel responsible for developing the SoC module and used for testing. After the module-level verification is completed, the verification personnel maintaining the subsystem / system-level environment no longer need to configure VIP ports separately for each SoC module, but can directly reuse the module verification device. Thus, by reusing the SoC verification environment, the time for setting up the verification environment during SoC verification is shortened, and it has wide applicability.

[0035] When the verification device of this invention is integrated into the subsystem environment, if a fault such as a data comparison error occurs during subsystem or system-level verification, the error message it provides will provide location information, thereby saving verification engineers a lot of time, accelerating the verification convergence of the entire system-on-a-chip system, and improving verification efficiency.

[0036] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0037] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0038] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0039] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A system-on-chip module verification apparatus, comprising: The system comprises: a multi-protocol universal interface configured to connect a system-on-chip module under test having different data buses; a module verification chip configured to generate stimulus signals and send them to the system-on-chip module under test through the multi-protocol universal interface, receive response signals from the system-on-chip module under test through the multi-protocol universal interface, and monitor the stimulus signals and the response signals; the module verification chip comprises a reference model having the same logical function as the system-on-chip module under test, a monitoring module, a comparator, and a plurality of module verification ports connected to the multi-protocol universal interface, wherein the plurality of module verification ports comprise a first module verification port configured to generate stimulus signals, a second module verification port configured to monitor a slave interface of the system-on-chip module under test, a third module verification port configured to generate feedback signals for the response signals, and a fourth module verification port configured to monitor a master interface of the system-on-chip module under test; the monitoring module is a monitoring program based on System Verilog language, and is configured to operate the first module verification port and the third module verification port in an active mode and operate the second module verification port and the fourth module verification port in a passive mode; the reference model is configured to obtain the stimulus signals through the multi-protocol universal interface and the second module verification port in sequence, and generate corresponding first response signals to send to the comparator; the comparator is configured to obtain second response signals from the system-on-chip module under test for the stimulus signals through the fourth module verification port, and compare the second response signals with the first response signals to verify the logical function and interface communication function of the system-on-chip module under test; the multi-protocol universal interface comprises a first master interface configured to connect the first module verification port and a slave interface of the system-on-chip under test, a first slave interface configured to connect the third module verification port and a master interface of the system-on-chip under test, a second slave interface, a first connector, and a first slave bind interface connected in sequence, wherein the first slave interface is configured to connect the second module verification port, and the first slave bind interface is configured to bind with a slave interface of the system-on-chip module under test; a second master interface, a second connector, and a second slave bind interface connected in sequence, wherein the second slave interface is configured to connect the fourth module verification port, and the second slave bind interface is configured to bind with a master interface of the system-on-chip module under test. The first connector and the second connector are configured to control the conduction or disconnection of the paths in which they are located.

2. The system-on-chip module validation apparatus of claim 1, wherein The system-on-chip module verification device further comprises an interface configuration file configured to control the connection objects of the multi-protocol universal interface through macro definition.

3. The system-on-chip module validation apparatus of claim 1, wherein ​ 4. The system-on-chip module verification apparatus of claim 3, wherein The connection object includes a system-level chip module, a system-level chip subsystem or a system-level chip system to be tested.

5. The system-on-chip module verification apparatus of claim 4, wherein The interface configuration file further presets connection relationships between system-level chip subsystems in the system-level chip system and connection relationships between system-level chip modules inside the subsystems.

6. A system-on-chip system verification method, comprising: The method includes the following steps implemented by the system-level chip module verification device of any one of claims 1-5: Each system-level chip module of the system-level chip system is verified by a plurality of preset system-level chip module verification devices to obtain a plurality of reference models corresponding to the system-level chip modules and a plurality of comparators; In a system-level chip system verification stage, the bind interface of the multi-protocol universal interface is bound to the corresponding interface of each system-level chip module to verify the logic function and interface communication function of each system-level chip module; In response to a failure of the system-level chip system, an error is reported and the failure is located by the corresponding system-level chip module verification device.

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