A controller and chip

Abstract

The present disclosure provides a kind of controller and chip, it is related to integrated circuit technical field, more particularly to chip technology and voice technology.The specific implementation scheme is: a kind of controller, configuration is in chip, the controller includes multiple storage and interconnection interface and configuration interface;Wherein, the configuration interface is configured to the working mode of the multiple storage and interconnection interface, wherein the working mode includes storage interface mode and interconnection interface mode;Each storage and interconnection interface is configured based on the configuration of the configuration interface, and it is externally connected memory in the storage interface mode, or it is externally connected other chip in the interconnection interface mode.The present disclosure can realize multi-port storage and multi-chip interconnection in the same interface in the controller of chip by configuration, on the premise of controllable cost, not only can expand the required storage capacity, but also can improve overall computing power through inter-chip interconnection, meet different product requirements.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, in particular to chip technology and voice technology, and specifically to a controller and a chip. BACKGROUND

[0002] With the gradual maturity and continuous promotion of AI technology, intelligent voice technology has also developed rapidly. At present, there are various intelligent voice chips applied in intelligent sound boxes and intelligent vehicles and other terminals on the market.

[0003] According to different application requirements of the market, the existing intelligent voice related chips can be simply divided into two kinds of low-cost chips and high-cost chips. Among them, the low-cost intelligent voice chip has a wide application market and can be applied to low-cost screenless sound boxes, intelligent vehicles with high popularization rate, intelligent home appliances and IOT (Internet of Things) and other market fields. SUMMARY

[0004] The present disclosure provides a controller and a chip.

[0005] According to an aspect of the present disclosure, a controller configured in a chip is provided, and the controller comprises a plurality of storage and interconnection interfaces and a configuration interface; wherein,

[0006] The configuration interface is configured to configure the working mode of the plurality of storage and interconnection interfaces, wherein the working mode comprises a storage interface mode and an interconnection interface mode.

[0007] Each of the storage and interconnection interfaces is configured to externally connect a memory in the storage interface mode or externally connect another chip in the interconnection interface mode based on the configuration of the configuration interface.

[0008] Optionally, the chip further comprises a bus, and the controller further comprises:

[0009] The bus slave interface is configured to complete data transmission between the bus and the externally connected memory.

[0010] The bus master interface is configured to complete data transmission between the externally connected interconnection chip and the bus.

[0011] Optionally, the controller further comprises:

[0012] The multi-channel data management module is connected with the plurality of storage and interconnection interfaces, the bus slave interface and the bus master interface respectively, and is configured to convert and route data between the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface.

[0013] Optionally, the configuration interface is further configured to configure address mapping relationships between the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface.

[0014] Correspondingly, the multi-channel data management module is specifically configured to: according to the address mapping relationships, perform conversion and routing of data between the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface.

[0015] Optionally, the storage interface mode is a master mode of the storage and interconnection interface, and the interconnection interface mode is a slave mode of the storage and interconnection interface.

[0016] Optionally, the number of storage and interconnection interfaces configured in the interconnection interface mode is 0, 1 or more than one.

[0017] Optionally, the number of storage and interconnection interfaces configured in the storage interface mode is at least 1.

[0018] Optionally, the memory is a pseudo-static random memory.

[0019] Optionally, the chip is a voice chip.

[0020] According to another aspect of the present disclosure, a chip is provided, comprising a controller, the controller comprising a plurality of storage and interconnection interfaces and a configuration interface; wherein,

[0021] The configuration interface is configured to configure working modes of the plurality of storage and interconnection interfaces, wherein the working modes include a storage interface mode and an interconnection interface mode.

[0022] Each of the storage and interconnection interfaces is configured to, based on the configuration of the configuration interface, externally connect a memory in the storage interface mode or externally connect other chips in the interconnection interface mode.

[0023] Optionally, the chip further comprises a bus, and the controller further comprises:

[0024] A bus slave interface is configured to complete data transmission between the bus and the externally connected memory.

[0025] A bus master interface is configured to complete data transmission between the externally connected interconnection chip and the bus.

[0026] Optionally, the controller further comprises:

[0027] A multi-channel data management module is connected with the plurality of storage and interconnection interfaces, the bus slave interface and the bus master interface respectively, and is configured to perform conversion and routing of data between the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface.

[0028] Optionally, the chip is a voice chip, and the chip further comprises an embedded neural network processor, a central processing unit, a digital signal processor, a peripheral module, a storage module and a voice input and output module, which are connected to the bus respectively.

[0029] Optionally, the plurality of storage and interconnection interfaces of the controller of the chip are configured as storage interface modes.

[0030] Optionally, the plurality of storage and interconnection interfaces of the controller of the chip are configured as storage interface modes, and any target storage and interconnection interface is connected to a storage and interconnection interface configured as an interconnection interface mode in a controller of a first external interconnection chip, and the remaining storage and interconnection interfaces in the controller of the first external interconnection chip are configured as storage interface modes.

[0031] Optionally, the plurality of storage and interconnection interfaces of the controller of the chip are configured as storage interface modes, and each storage and interconnection interface is connected to a storage and interconnection interface configured as an interconnection interface mode in a controller of a second external interconnection chip, and the remaining storage and interconnection interfaces in the controller of the second external interconnection chip are configured as storage interface modes.

[0032] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are used to better understand the present scheme and do not limit the present disclosure. Among them:

[0034] Figure 1 is a schematic diagram of a controller according to an embodiment of the present disclosure;

[0035] Figure 2 is a schematic diagram of another controller according to an embodiment of the present disclosure;

[0036] Figure 3 is a schematic diagram of another controller according to an embodiment of the present disclosure;

[0037] Figure 4 is a schematic diagram of a chip according to an embodiment of the present disclosure;

[0038] Figure 5 is a schematic diagram of a voice chip according to an embodiment of the present disclosure;

[0039] Figure 6 is a structural diagram of multi-port storage of a chip according to an embodiment of the present disclosure;

[0040] Figure 7is a structure diagram of an interconnected chip according to an embodiment of the present disclosure;

[0041] Figure 8 is another structure diagram of an interconnected chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are included to provide a thorough understanding of embodiments of the present disclosure by a person of ordinary skill in the art, and should not be construed as limiting the present disclosure to particular embodiments. Thus, it will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0043] Figure 1 is a schematic diagram of a controller according to an embodiment of the present disclosure, the controller of the present embodiment is configured in a chip, such as a voice chip, etc. The controller can be connected to other modules (not shown in the figure) in the chip through a bus. As shown in the figure, the controller includes a plurality of storage and interconnection interfaces 101 and a configuration interface 102, wherein, Figure 1

[0044] The plurality of storage and interconnection interfaces 101, i.e. storage and interconnection interfaces 0-n, n is a natural number, the number of storage and interconnection interfaces can be configured as needed, and the present embodiment does not make any limitation on the number of storage and interconnection interfaces.

[0045] The configuration interface is used to configure the working mode of the plurality of storage and interconnection interfaces, wherein the working mode includes a storage interface mode and an interconnection interface mode.

[0046] Each storage and interconnection interface is used to externally connect a memory in the storage interface mode or externally connect other chips in the interconnection interface mode based on the configuration of the configuration interface. The number of storage and interconnection interfaces configured as the storage interface mode and the interconnection interface mode can be selected according to the size of the storage capacity that needs to be expanded and the required computing power. For example, at least one storage and interconnection interface is configured as the storage interface mode, but only one of the storage and interconnection interfaces is configured as the interconnection interface mode to externally connect other chips. In addition, two or more storage and interconnection interfaces can also be configured to externally connect other chips. The externally connected other chips are the same as the current chip and also have a controller, so the externally connected other chips can also continue to externally connect memories or other chips, thereby achieving the purpose of further expanding the storage capacity and improving the overall computing power of the chip.

[0047] ​The storage and interconnection interface may be, for example, an SRAM (Static Random-Access Memory), a PSRAM (Pseudo Static Random Access Memory), a DDR2 (Double Data Rate 2) interface, or the like, and is configured according to the required memory. For the same storage and interconnection interface, different configurations of the working mode of the interface through a configuration interface can realize an external memory or an external other chip. The configuration interface may be, for example, an APB (Advanced Peripheral Bus) bus interface, or a register interface that can be configured, and the register configuration of a plurality of storage and interconnection interfaces through the configuration interface can realize the configuration of different working modes thereof.

[0048] It should be noted that the current intelligent voice terminal product, such as the widely used intelligent sound box, as a low-cost terminal product, has limited performance and function, and has storage capacity and computing power constraints on algorithms. If the current chip cannot meet the capacity and computing power requirements of the algorithm model on the hardware, under the premise of controllable cost, the existing technology usually adjusts the function support or re-modifies the algorithm, that is, uses the algorithm to adapt to the chip to solve the problem. However, the workload consumed by the algorithm is not only very large, but also very long, and the overall effect is not very good, which will directly affect the function implementation and user experience of the terminal product. If a high-end memory or a chip with better computing power is directly used to update and replace, it does not meet the current demand for low-cost terminal products, and in the middle and low-end application scenarios, there is no obvious advantage in power consumption and cost.

[0049] The technical scheme of the embodiment of the present disclosure, under the premise of controllable cost, continues to use the original low-cost memory, only increases the controller in the chip, and configures the working mode of the plurality of storage and interconnection interfaces through the configuration interface in the controller, so that the memory or other chips can be externally connected as needed, so as to achieve the purpose of expanding the storage capacity and optimizing the computing power. Moreover, in the implementation, since a plurality of storage and interconnection interfaces are reserved in the controller, according to different needs of different terminal products, the same hardware can be used, and only the configuration interface needs to be configured, so that a proper number of storage and interconnection interfaces can be selected to externally connect the memory, which is more flexible to use, has wider applicability, and can reduce development cost and improve development efficiency.

[0050] Figure 2 is another schematic diagram of a controller according to an embodiment of the present disclosure. The embodiment is further optimized on the basis of the above-mentioned embodiment. As shown in Figure 2As shown, the controller includes a plurality of storage and interconnection interfaces 201, a configuration interface 202, a bus slave interface 203, and a bus master interface 204. Among them, the controller is connected to other modules in the chip through the bus in the chip, and the interfaces connected to the bus include the bus slave interface 203 and the bus master interface 204. The bus slave interface is used to complete the data transmission between the bus and the external memory; and the bus master interface is used to complete the data transmission between the external interconnection chip and the bus.

[0051] Specifically, the storage and interconnection interface is in the master mode of the interface in the storage interface mode, and is in the slave mode of the interface in the interconnection interface mode, that is, the storage interface and the interconnection interface are master-slave interfaces of the same standard, so that the master-slave mode of the storage and interconnection interface can be configured to be in the storage interface mode or the interconnection interface mode, and the storage and interconnection interface can be externally connected to the memory or the chip. Among them, whether in the master mode or in the slave mode of the interface, the data transmission is bidirectional, but the control is unidirectional, that is, in the master mode of the interface, the controller is the control party, and in the slave mode of the interface, the external memory or the chip is the control party, and the control party will actively perform the read and write operations of the data. It should be noted that how the interface performs the read and write operations of the data in the master-slave mode can be determined according to the type of the interface and the corresponding interface protocol, which will not be described here.

[0052] In the embodiment of the present disclosure, when the external memory is connected, the bus slave interface and the storage and interconnection interface configured in the storage interface mode form a storage channel to complete the data transmission between the bus and the external memory. For example, the bus slave interface receives a data packet from the bus and converts it, and then transmits it to the corresponding memory through the storage and interconnection interface configured in the storage interface mode. When the other chip is connected externally, the bus master interface and the storage and interconnection interface configured in the interconnection interface mode form an interconnection channel to complete the data transmission between the external interconnection chip and the bus. For example, the data packet from the other chip is transmitted to the bus through the bus master interface after being converted by the bus master interface.

[0053] Therefore, the technical scheme of the embodiment of the present disclosure, in the case of controllable cost, uses the original low-cost memory, only increases the controller in the chip, and configures the working mode of the plurality of storage and interconnection interfaces through the configuration interface in the controller, and then uses the bus slave interface and the bus master interface as the storage channel and the interconnection channel of the externally connected memory and the externally connected chip respectively, to complete the transmission of the data packet between the bus and the externally connected memory, and between the externally connected interconnection chip and the bus, so as to achieve the purpose of expanding the storage capacity and optimizing the computing power.

[0054] Figure 3 is another schematic diagram of a controller according to the embodiment of the present disclosure, which is further optimized on the basis of the above-mentioned embodiment. As shown inFigure 3 As shown, the controller includes a plurality of storage and interconnection interfaces 301, a configuration interface 302, a bus slave interface 303, a bus master interface 304, and a multi-channel data management module 305. Among them, the functions of the plurality of storage and interconnection interfaces 301, the configuration interface 302, the bus slave interface 303, and the bus master interface 304 are the same as described in the above embodiments, and will not be repeated here. The multi-channel data management module 305 is connected with the plurality of storage and interconnection interfaces 301, the bus slave interface 303, and the bus master interface 304 respectively, and is used to convert and route data between the plurality of storage and interconnection interfaces 301 and the bus slave interface 303 and the bus master interface 304.

[0055] Specifically, the configuration interface is not only used to configure the working mode of the plurality of storage and interconnection interfaces, but also used to configure the address mapping relationship between each of the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface. Of course, the configuration interface is also used to configure the address space of the bus slave interface and the bus master interface. Correspondingly, the multi-channel data management module is specifically used to convert and route data between the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface according to the address mapping relationship.

[0056] Since the controller includes a plurality of storage and interconnection interfaces, and each storage and interconnection interface can be configured as a storage interface mode to interface with a storage or as an interconnection interface mode to interface with other chips, there are multiple data channels. In the embodiment of the present disclosure, through the multi-channel data management module, according to the configuration of the working mode and the address space of each channel by the configuration interface, after analyzing the address space of the data packet, according to the address mapping relationship between each of the plurality of storage and interconnection interfaces and the bus slave interface and the bus master interface, the data transmission in different channels can be completed, ensuring the correctness and accuracy of the data transmission of multiple interfaces and multiple channels, and also ensuring the correctness of the data transmission in the case of expanding the storage capacity and the computing power.

[0057] Specifically, when external storage is connected, the bus slave interface and the storage and interconnection interface configured in the storage interface mode constitute a storage channel to complete data transmission between the bus and the external storage. For example, the bus slave interface receives a data packet from the bus, sends the data packet to the multi-channel data management module after conversion, the multi-channel data management module parses the data packet, obtains the address space of the interface, routes according to the address space, selects the target storage and interconnection interface, and finally reaches the storage of the storage and interconnection interface. When other chips are connected, the bus master interface and the storage and interconnection interface configured in the interconnection interface mode constitute an interconnection channel to complete data transmission between the external interconnection chip and the bus. For example, the multi-channel data management module obtains a data packet from the storage and interconnection interface configured in the interconnection interface mode, sends the data packet to the bus master interface according to the preconfigured address mapping relationship, and the data packet comes from the storage of the interconnection chip connected to the storage and interconnection interface, and then the bus master interface sends the data packet to the bus after conversion.

[0058] Figure 4 is a schematic diagram of a chip according to an embodiment of the present disclosure. As shown in Figure 4 the controller 40 of the chip of the present embodiment further includes a plurality of storage and interconnection interfaces 401 and a configuration interface 402. The chip of the present embodiment can realize multi-port storage and interconnection through the controller. That is, the working modes of the plurality of storage and interconnection interfaces are configured through the configuration interface, wherein the working modes include a storage interface mode and an interconnection interface mode. Each storage and interconnection interface is used to externally connect a storage in the storage interface mode or externally connect other chips in the interconnection interface mode based on the configuration of the configuration interface.

[0059] Thus, under the condition of controllable cost, the original low-cost storage is used, only the controller is added in the chip, and the working modes of the plurality of storage and interconnection interfaces are configured through the configuration interface in the controller, so that the storage or other chips can be externally connected as needed, so as to achieve the purposes of expanding the storage capacity and optimizing the computing power. Moreover, in implementation, since a plurality of storage and interconnection interfaces are reserved in the controller, according to different needs of different terminal products, the same hardware is used, and only the configuration interface is configured, so that a proper number of storage and interconnection interfaces can be selected to externally connect the storage, which is more flexible to use, has wider applicability, can reduce development cost, and improves development efficiency. At the same time, when the layout of the product circuit board is designed, it is not limited by the interface wiring, and whether the storage or the chip is externally connected, the layout does not need to be redesigned, but only needs to be connected to the plurality of storage and interconnection interfaces reserved in the controller, and each storage and interconnection interface is the same in function, so that the optimal position of the storage and interconnection interface can be selected for configuration and use according to different layout arrangements, and thus the use is more flexible.

[0060] Figure 5 is a schematic diagram of a voice chip according to an embodiment of the present disclosure, which is further optimized based on the above-mentioned embodiment. As shown in Figure 5 , the voice chip is connected by a bus to perform data transmission. Specifically, it includes an embedded neural network processor, a controller, a central processing unit / digital signal processor, a peripheral module, a storage module, and a voice input / output module. The voice input / output module receives external voice data through a voice input / output interface and plays the output voice after recognition and processing.

[0061] Specifically, the embedded neural network processor NPU (Natural Processing Unit) is used for neural network voice algorithm implementation; the controller is used for data storage and implementation of data transmission and storage sharing between chips; the central processing unit (CPU) / digital signal processor (DSP) is the system control center of the chip. If DSP is selected, the chip also has the function of processing voice signal algorithm, and can support software operating systems such as FreeRTOS (real-time operating system kernel) / Linux, etc.; the peripheral module includes communication interfaces such as SPI (Serial Peripheral Interface), high-speed UART (universal asynchronous receiver / transmitter), SDIO (Secure Digital Input and Output), etc. The high-speed UART can be used for Bluetooth BT (BitTorrent) connection, and the SDIO can be used for WIFI module connection to realize wireless communication expansion function; the storage module can be ROM (Read-Only Memory) or Flash (flash memory), and can be used as the storage of the CPU / DSP startup program; the voice input / output module supports I2S (Inter-IC Sound), PDM (Pulse Density Modulation), TDM (Time Division Multiplexing), etc. audio format devices.

[0062] Figure 6 is a structural diagram of chip multi-port storage according to an embodiment of the present disclosure, which gives an example of single-chip external multi-port storage based on the above-mentioned embodiment. As shown in Figure 6As shown, the number of the plurality of storage and interconnection interfaces (not shown in the figure) of the controller in the chip is 4, which are all configured as storage interface mode, i.e. the master mode of the interface, and each is externally connected with a PSRAM memory.

[0063] Specifically, in the embodiment, the plurality of ports of the single-chip storage and interconnection interface all work as a single storage interface mode, and directly access 4 PSRAM memories to realize storage capacity expansion. For example, the single-chip capacity of the external memory PSRAM is 8-32M, and 4 ports store simultaneously. Assuming that the capacity of the PSRAM is 32MB, the maximum capacity can reach 32MB x 4 = 128MB, which can meet the storage requirements of the neural network model of the current more intelligent voice algorithm.

[0064] In implementation, the working mode of the 4 storage and interconnection interfaces is configured through the configuration interface in the chip controller in advance, i.e. configured as the master mode of the interface, and the address mapping relationship between the 4 storage and interconnection interfaces and the bus slave interface and the bus master interface is also configured. When receiving the data packet from the bus through the bus slave interface, the multi-channel data management module in the controller analyzes it to obtain the address space of the interface, and selects the current corresponding storage and interconnection interface from the 4 storage and interconnection interfaces according to the address mapping relationship, and then sends the data packet to the externally connected PSRAM through the selected storage and interconnection interface for storage. Similarly, based on the read request, the required data can also be read from the externally connected PSRAM and converted by the multi-channel data management module and sent to the bus through the bus slave interface. Thus, the data transmission between the bus and the externally connected memory can be completed.

[0065] In addition, for the existing chip packaging technology, the PSRAM can be used as an external storage grain of the chip, or can be packaged into a complete new voice chip by being combined with the chip, with higher integration.

[0066] Figure 7 is a structure diagram of an interconnection chip according to an embodiment of the present disclosure. The embodiment is based on the above-mentioned embodiment, and gives an example of two-chip interconnection and external multi-port storage. As shown in the figure, Figure 7 As shown, the number of the plurality of storage and interconnection interfaces (not shown in the figure) of the controller in the chip A and the chip B is 4. Among them, the plurality of storage and interconnection interfaces of the chip A are all configured as storage interface mode, and any storage and interconnection interface is connected to the storage and interconnection interface configured as interconnection interface mode in the controller of the chip B. In the controller of the chip A and the chip B, except for the interconnection storage and interconnection interface, the rest of the storage and interconnection interfaces are all configured as storage interface mode, and each is externally connected with a PSRAM.

[0067] In this embodiment, chip A and chip B are interconnected. Chip A and chip B can be the same voice chip and both have four-way storage and interconnection interfaces. Each chip supports three-way external storage PSRAM to expand the storage capacity, one of which is mainly used for interface interconnection. The interface connected between chip A and chip B is configured as a storage interface mode, and the interface connected between chip B and chip A is configured as an interconnection interface mode, so as to realize data interaction between chip A and chip B.

[0068] Specifically, when the interface connected between chip A and chip B is configured as a storage interface mode, and the interface connected between chip B and chip A is configured as an interconnection interface mode, it indicates that chip A is the master and chip B is the slave. Conversely, when the interface connected between chip A and chip B is configured as an interconnection interface mode, and the interface connected between chip B and chip A is configured as a storage interface mode, it indicates that chip B is the master and chip A is the slave. As for which one of the two interconnected chips is the master chip and which one is the slave chip, the embodiments of the present disclosure do not limit it, and the corresponding configuration can be made based on product functions and algorithm implementation. In addition, in the multi-chip interconnection scenario, how to realize the algorithmic power allocation of multiple chips can also be realized according to the product function and through the algorithm, and the embodiments of the present disclosure do not make any limitation on this.

[0069] Taking chip A as the master and chip B as the slave as an example, for chip A, chip B and its three externally connected PSRAMs can be regarded as the storage device externally connected to chip A, not only a part of the algorithmic power can be allocated to chip B for processing through the algorithm, but also storage sharing can be realized with chip B, and the data obtained through chip B processing can be directly stored in the PSRAM externally connected to chip B, without returning to the externally connected PSRAM of chip A. When it is necessary to read this part of data, based on the data reading request, the multi-channel data management module in the controller of chip B selects the corresponding storage and interconnection interface according to the address carried in the request, and obtains the data from the PSRAM externally connected to the interface, and then transmits the data to chip A through the interface channel between chip B and chip A, and finally converts and routes the data through the multi-channel data management module of chip A, and transmits the data to the bus through the bus master interface, so as to complete a data reading.

[0070] In this embodiment, it is assumed that the PSRAM capacity is 32MB, so the total storage capacity is 2x 3x 32MB = 192MB, which is 64MB more than the single-chip solution. At the same time, since two chips work together, the overall algorithmic power is also doubled. Compared with the single-chip voice chip solution, it can further meet the main demand of storage and algorithmic power of the current intelligent voice algorithm neural network model.

[0071] Figure 8is another structure diagram of an interconnected chip according to an embodiment of the present disclosure, and the embodiment gives an example of five-chip interconnection and external multi-port storage based on the above embodiment. As shown in Figure 8 The number of the plurality of storages and interconnection interfaces (not shown in the figure) of the controller in the chips A-E is 4, the plurality of storages and interconnection interfaces of the controller of the chip A are all configured as storage interface mode, and each of the plurality of storages and interconnection interfaces is connected to the storage and interconnection interface configured as interconnection interface mode in the controller of the chip B-E, and the remaining storages and interconnection interfaces in the controller of the chip B-E are all configured as storage interface mode and are respectively externally connected to one PSRAM.

[0072] The embodiment supports multi-port storage and inter-chip interconnection, and realizes five-chip interconnection. Among them, the chips A-E can be completely identical voice chips, and all have controllers. Except that the four storages and interconnection interfaces in the chip A are configured as storage interface mode to interconnect the four chips outside, each of the other chips supports three-way storage and interconnection interface to externally connect PSRAM to expand the storage capacity, and the other storage and interconnection interface is configured as interconnection interface mode, which is mainly used for interface interconnection. Assuming that the capacity of the PSRAM is 32MB, the overall storage capacity that can be expanded in the embodiment is 4x 3x 32MB = 384MB. Since the five chips are task-divided, the overall computing power is increased to 5 times compared with a single chip. This configuration almost completely meets the main demand of storage and computing power of the current intelligent voice algorithm neural network model and the future expansion demand.

[0073] In the embodiment, the chip A is the master chip, and controls the data read and write of the chips B-E. In other multi-chip interconnection embodiments, any one of the chips can also be the master. For the interconnection channel of any two interconnected chips, one storage and interconnection interface is configured as storage interface mode, and the other storage and interconnection interface is configured as interconnection interface mode, so as to complete data interaction. Therefore, the master-slave configuration relationship of the interconnected chips and the configuration mode of the interfaces in the corresponding interconnection channel can be configured according to product functions and algorithm implementation, and the embodiments of the present disclosure do not make any limitation on this.

[0074] It can be known from the above embodiments that the chip provided by the embodiments of the present disclosure provides a configurable multi-port storage and interconnection controller, the controller includes a plurality of storage and interconnection interfaces, and through configuration, multi-port storage and multi-chip interconnection can be realized under the same interface. When multi-chip interconnection is realized, shared storage can also be realized. The main chip can store or read data from the storage device connected to other chips. Under the premise of controllable cost, the embodiments of the present disclosure not only can expand the required storage capacity, but also can realize the improvement of the overall computing power through inter-chip interconnection, meet different product requirements, and have obvious cost advantages. In the development stage of different products, the use is also very flexible. According to the product requirements and in a configurable manner, multi-port storage and inter-chip interconnection can be realized, the application range is wide, and the development efficiency is high.

[0075] In the technical solutions of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0076] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A controller configured on a chip, the controller including a plurality of storage and interconnect interfaces and a configuration interface; wherein, The configuration interface is used to configure the working modes of the plurality of storage and interconnect interfaces, wherein the working modes include storage interface mode and interconnect interface mode; Each of the storage and interconnect interfaces is configured to connect an external memory in the storage interface mode or to connect other chips in the interconnect interface mode, based on the configuration of the configuration interface; wherein the storage interface mode is the master mode of the storage and interconnect interface; and the interconnect interface mode is the slave mode of the storage and interconnect interface.

2. The controller according to claim 1, wherein, The chip also includes a bus, and the controller also includes: The bus slave interface is used to complete data transmission between the bus and the external memory; The bus master interface is used to complete data transmission between the external interconnect chip and the bus.

3. The controller according to claim 2, further comprising: The multi-channel data management module is connected to the multiple storage and interconnect interfaces, bus slave interfaces, and bus master interfaces respectively, and is used to perform data conversion and routing between the multiple storage and interconnect interfaces and the bus slave interfaces and bus master interfaces.

4. The controller according to claim 3, wherein, The configuration interface is also used to configure the address mapping relationship between each of the plurality of storage and interconnect interfaces and the bus slave interface and the bus master interface; Accordingly, the multi-channel data management module is specifically used to: perform data conversion and routing between the multiple storage and interconnect interfaces and the bus slave interface and bus master interface according to the address mapping relationship.

5. The controller according to claim 1, wherein, The number of storage and interconnect interfaces configured in interconnect interface mode is 0 or more.

6. The controller according to claim 1, wherein, The number of storage and interconnect interfaces configured in storage interface mode is at least one.

7. The controller according to claim 1, wherein, The memory is a pseudo-static random access memory.

8. The controller according to claim 1, wherein, The chip in question is a voice chip.

9. A chip, comprising a controller, the controller including a plurality of storage and interconnect interfaces and a configuration interface; wherein, The configuration interface is used to configure the working modes of the plurality of storage and interconnect interfaces, wherein the working modes include storage interface mode and interconnect interface mode; Each of the storage and interconnect interfaces is configured to connect an external memory in the storage interface mode or to connect other chips in the interconnect interface mode, based on the configuration of the configuration interface; wherein the storage interface mode is the master mode of the storage and interconnect interface; and the interconnect interface mode is the slave mode of the storage and interconnect interface.

10. The chip according to claim 9, further comprising a bus, wherein, The controller also includes: The bus slave interface is used to complete data transmission between the bus and the external memory; The bus master interface is used to complete data transmission between the external interconnect chip and the bus.

11. The chip according to claim 10, wherein, The controller also includes: The multi-channel data management module is connected to the multiple storage and interconnect interfaces, bus slave interfaces, and bus master interfaces respectively, and is used to perform data conversion and routing between the multiple storage and interconnect interfaces and the bus slave interfaces and bus master interfaces.

12. The chip according to claim 10, wherein, The chip is a voice chip, and the chip also includes: an embedded neural network processor, a central processing unit, a digital signal processor, a peripheral module, a storage module, and a voice input / output module, which are respectively connected to the bus.

13. The chip according to claim 9, wherein, The controller of the chip is configured with multiple storage and interconnect interfaces in storage interface mode.

14. The chip according to claim 9, wherein, The controller of the chip has multiple storage and interconnect interfaces configured in storage interface mode, and any one of the storage and interconnect interfaces is connected to the storage and interconnect interface configured in interconnect interface mode in the controller of the first external interconnect chip. The remaining storage and interconnect interfaces in the controller of the first external interconnect chip are all configured in storage interface mode.

15. The chip according to claim 9, wherein, The controller of the chip has multiple storage and interconnect interfaces configured in storage interface mode, and each storage and interconnect interface is connected to the storage and interconnect interface configured in interconnect interface mode in the controller of the second external interconnect chip. The remaining storage and interconnect interfaces in the controller of the second external interconnect chip are all configured in storage interface mode.

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