An APB bus bridge across clock domains and its method

Abstract

A cross-clock-domain APB bus bridge is provided. The APB bus bridge includes: a source clock domain port, a destination clock domain port, a FIFO, an APB bus protocol generation circuit, and a source clock domain handshake signal generation circuit. In this application, the FIFO is used to cache write data, and according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO, it is determined whether to raise the source clock domain handshake signal, that is, to decide whether to return the source clock domain handshake signal in advance to indicate to the APB host that the current write transmission has been completed, so as to achieve the acceleration of the write transmission when the write cache is enabled. In addition, this application also provides a method for cross-clock-domain access executed by the APB bus bridge.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of chip design, and more particularly to an APB bus bridge across clock domains and a method thereof. Background Art

[0002] This section introduces various aspects that can facilitate a better understanding of the present disclosure. Therefore, the statements in this section should be read from this perspective and should not be construed as admitting what is prior art and what is not prior art.

[0003] With the change of requirements and the development of process dimensions, the system-on-chip (SoC) has been more and more widely applied to the field of integrated circuits due to its advantages such as small area, low power consumption and powerful functions. The IP core reuse technology can greatly accelerate the design process of the SoC and improve the reliability, which is one of the key technologies for the development of the SoC. The IP core reuse requires a unified bus interface. Different design units in the system follow the unified bus protocol when interfacing with other modules, and only need to be connected to communicate without complex interface conversion.

[0004] Currently, the AMBA (Advanced Microcontroller Bus Architecture) protocol is a set of bus protocols widely used in SoC design. Among them, the APB (Advanced Peripheral Bus) protocol is an interface protocol widely used for register access, which has advantages such as low overhead and simple implementation. However, different functional modules in the system often work at different clock frequencies. When the central processing unit (CPU) wants to access the registers in these different clock domains through the bus, cross-clock domain processing is required. Performing cross-clock domain processing at the APB bus interface has advantages such as simple design and clear interface, which can greatly accelerate subsequent clock domain crossing (CDC) checks.

[0005] Currently, the existing APB cross-clock domain processing solutions mainly adopt handshaking, FIFO or edge alignment cross-clock processing using a clock enable signal. These solutions can all perform cross-clock domain processing of the APB bus. However, whether it is a read operation or a write operation, it needs to wait until the handshaking signal (pready) at the destination end is synchronized back before execution, so the speed is relatively slow.

[0006] In the prior art, the patent application with the publication number CN101377691A discloses a method for cross - clock - domain processing by means of control - signal handshaking. Among them, the clock synchronization circuit synchronizes the chip - select signal (psel) and the enable signal (penable) in the APB clock domain to the clock domain of the accessed end, outputs them as control signals (msel) to the control register, and then synchronizes the control signals (msel) back to the APB clock domain and sends them back to the APB bridge as handshaking signals (pready). However, there are problems with this solution. Especially for a write transfer, it always needs to wait until the handshaking signal from the destination end is synchronized back before it can be completed. Therefore, the speed of the write transfer is slow.

[0007] In another PCT international patent application WO2016192217A1, an APB bus bridge is disclosed. The technical solution of this patent only processes cross - clock - domain of synchronous clocks with clock edges aligned and a frequency ratio of positive integer N, and requires an additional clock enable signal. Similarly, this solution has a similar problem, that is, it cannot accelerate the write operation, and still needs to wait until the handshaking signal from the destination end is synchronized back to complete a write transfer.

[0008] Therefore, the prior art cannot dynamically accelerate the APB write transfer when implementing a cross - clock - domain APB bus. Summary of the Invention

[0009] It is desired to implement a cross - clock - domain APB bus bridge that can dynamically accelerate write transfers. To solve at least some of the above problems in the prior art, in the present disclosure, circuits, methods, and devices for an APB bus bridge are provided. It can be understood that the embodiments of the present disclosure are not limited to being on a system - on - a - chip (SoC), but can be more widely applied to any application scenario with similar problems.

[0010] The present invention caches write data by using a FIFO (First In First Out buffer). Once the write data is received in the FIFO, it can be selected whether to return pready in advance according to the control signal of the write cache switch. When the write cache operation is enabled, the write transfer can be completed quickly, which can release the CPU (Central Processing Unit) and the bus so that they can process other tasks, increasing the system efficiency;

[0011] Various embodiments of the present disclosure are mainly intended to provide circuits, methods, and devices for implementing a cross - clock - domain APB bus bridge. When reading the following description of specific embodiments in conjunction with the accompanying drawings, other features and advantages of the embodiments of the present disclosure will also be understood, where the drawings illustrate the principles of the embodiments of the present disclosure by way of example.

[0012] Generally, embodiments of the present disclosure provide a solution for a cross-clock-domain APB bus bridge for dynamically accelerating write input operations. The present disclosure uses a FIFO to cache write data and determines whether to raise the source clock domain handshake signal according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO, that is, determines whether to return the source clock domain handshake signal in advance to indicate to the APB host that the current write transmission has been completed, so as to achieve the acceleration of the write transmission when the write cache is enabled. In a first aspect, a cross-clock-domain APB bus bridge is provided. The APB bus bridge includes: a source clock domain port, a destination clock domain port, a FIFO, an APB bus protocol generation circuit, and a source clock domain handshake signal generation circuit. Among them, the source clock domain port is configured to be connected to a master device operating in the source clock domain; the destination clock domain port is configured to be connected to one or more APB slave devices operating in the destination clock domain; a transmission start detection circuit is configured to generate a transmission start flag (trans_start) when a transmission request occurs; the FIFO is configured to cache write data and control information, where the FIFO has a non-full signal (~fifo_full), and the non-full signal indicates whether the cache of the FIFO is full; the APB bus protocol generation circuit is configured to read and parse the information cached in the FIFO and generate a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit is further configured to obtain the destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain; the source clock domain handshake signal generation circuit is configured to determine whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; wherein, if the current transmission is a write transmission with write cache enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal; wherein when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; if the current transmission is a read transmission or a write transmission with write cache not enabled, wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

[0013] Further preferably, the cache information includes write data, and the write data includes the direction signal (pwrite), the write data signal (pwdata), the write strobe signal (pstrb), and the address signal (paddr) of the APB port in the source clock domain; wherein, if the direction signal (pwrite) is equal to 1, the current transmission is a write input; if the direction signal (pwrite) is equal to 0, the current transmission is a read input.

[0014] Further preferably, the APB bus bridge includes a write buffer enable synchronization circuit, which is configured to synchronize a write buffer enable signal (wbuf_en) triggered by a transmission start flag to obtain a write buffer enable synchronization signal (wbuf_en_sync), wherein the synchronization causes the write buffer enable synchronization signal to remain unchanged during the current transmission.

[0015] Still further preferably, the write buffer enable synchronization circuit performing the synchronization of the write buffer enable signal (wbuf_en) includes: when the value of the transmission start flag is 1, the write buffer enable synchronization signal is assigned the write buffer enable signal, and the registered write buffer enable signal (wbuf_en_reg) is updated to the write buffer enable signal; when the value of the transmission start flag is 0, the write buffer enable synchronization signal is assigned the registered write buffer enable signal (wbuf_en_reg).

[0016] In one embodiment, if the clocks of the source clock domain and the destination clock domain are synchronous clocks, the FIFO uses a synchronous FIFO with two clock ports; if the clocks of the source clock domain and the destination clock domain are asynchronous clocks, the FIFO uses an asynchronous FIFO.

[0017] In one embodiment, the APB bus bridge is applied to an SoC platform based on the AMBA protocol.

[0018] In one embodiment, the APB bus bridge is directly connected to an APB master. Wherein, the APB master is a master of the APB protocol.

[0019] In one embodiment, the APB bus bridge is connected to an AXI protocol bus or an AHB protocol bus through a protocol conversion bus bridge.

[0020] In a second aspect, a method for cross-clock domain access performed by an APB bus bridge is provided. The APB bus bridge includes: a source clock domain port for connecting a master device operating in the source clock domain; a destination clock domain port for connecting one or more APB slave devices operating in the destination clock domain; a transmission start detection circuit; a write buffer enable synchronization circuit; a FIFO for caching write data and control information, wherein the FIFO has a not-full signal (~fifo_full), and the not-full signal indicates whether the cache of the FIFO is full; an APB bus protocol generation circuit; and a source clock domain handshake signal generation circuit, which is configured to select the source of generating the source clock domain handshake signal according to whether the current transmission is a write transmission with write buffer enable and the cache status of the FIFO; the method includes, when a transmission request occurs, performing the following steps:

[0021] S1: The transmission start detection circuit generates a transmission start flag;

[0022] S2: Trigger the write buffer enable synchronization circuit by the transmission start flag to perform the synchronization of the write buffer enable signal, so as to obtain a write buffer enable synchronization signal, where the synchronization makes the write buffer enable synchronization signal remain unchanged during the current transmission;

[0023] S3: The source clock domain handshake signal generation circuit selects the source for generating the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write buffer enabled and the cache status of the FIFO; where, if the current transmission is a write transmission with write buffer enabled, wait until the cache information required for the current transmission is written into the FIFO, and then pull up the source clock domain handshake signal. When the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is not full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; if the current transmission is a read transmission or a write transmission with write buffer not enabled, wait until the destination clock domain handshake signal is generated, and then pull up the source clock domain handshake signal.

[0024] In one embodiment, the method further includes performing the following steps: The APB bus protocol generation circuit reads and parses the information cached in the FIFO, and generates a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit also obtains the destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain.

[0025] In one embodiment, the method further includes performing the following steps: When the source clock domain handshake signal is generated, and the transmission start detection circuit generates a FIFO write signal, and the FIFO non-full signal of the FIFO is 1, trigger the writing of the cache information required for the current transmission into the FIFO.

[0026] In one embodiment, the cache information includes write data, and the write data includes the direction signal (pwrite), write data signal (pwdata), write strobe signal (pstrb), and address signal (paddr) of the source clock domain APB port; where, if the direction signal (pwrite) is equal to 1, the current transmission is a write input; if the direction signal (pwrite) is equal to 0, the current transmission is a read input.

[0027] In one embodiment, the write buffer enable synchronization circuit performing the synchronization of the write buffer enable signal includes: when the value of the transmission start flag is 1, the write buffer enable synchronization signal is assigned the write buffer enable signal, and the registered write buffer enable signal (wbuf_en_reg) is updated to the write buffer enable signal; when the value of the transmission start flag is 0, the write buffer enable synchronization signal is assigned the registered write buffer enable signal (wbuf_en_reg).

[0028] In a third aspect, a cross-clock domain APB bus bridge is provided. The APB bus bridge includes: a source clock domain port, a destination clock domain port, a transmission start detection module, a FIFO, an APB bus protocol generation module, and a source clock domain handshake signal (pready_s) generation module; The transmission start detection module is configured to generate a transmission start flag (trans_start) when a transmission request occurs; The FIFO is configured to cache write data and control information, where the FIFO has a non-full signal (~fifo_full), and the non-full signal indicates whether the cache of the FIFO is full; The APB bus protocol generation module is configured to read and parse the information cached in the FIFO and generate a destination clock domain control signal and a destination clock domain write data signal in the destination clock domain, where the destination clock domain control signal includes a destination clock domain handshake signal (pready_d); The source clock domain handshake signal generation module is configured to determine whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; Wherein, if the current transmission is a write transmission with write cache enabled, after waiting for the cache information required for the current transmission to be written into the FIFO, raise the source clock domain handshake signal; Wherein when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; If the current transmission is a read transmission or a write transmission with write cache not enabled, wait for the destination clock domain handshake signal to be generated and then raise the source clock domain handshake signal.

[0029] In one embodiment, the APB bus bridge includes a write cache enable synchronization module. The write cache enable synchronization module is configured to synchronize the write cache enable signal (wbuf_en) triggered by the transmission start flag to obtain a write cache enable synchronization signal (wbuf_en_sync), where the synchronization causes the write cache enable synchronization signal to remain unchanged during the current transmission.

[0030] In one embodiment, the APB bus bridge is directly connected to an APB host. Wherein, the APB host is a host of the APB protocol.

[0031] In one embodiment, the APB bus bridge is connected to an AXI protocol bus or an AHB protocol bus through a protocol conversion bus bridge.

[0032] According to various embodiments of the present disclosure, by using a first-in-first-out buffer (FIFO) to cache write data, once the write data is written into the FIFO, it can be determined whether to return the source clock domain handshake signal (pready_s) in advance. Thus, when the write cache operation is in the enabled state, the write transfer can be completed quickly, thereby releasing the central processing unit (CPU) and the protocol bus to handle other tasks and increasing system efficiency. Therefore, a cross-clock domain APB bus bridge with dynamic write acceleration can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] As an example, according to the following detailed description with reference to the accompanying drawings, the above and other aspects, features, and advantages of various embodiments of the present disclosure will become more fully apparent. In the drawings, like reference numerals or letters are used to refer to like or equivalent elements. The drawings are shown for better understanding of the embodiments of the present disclosure, and the drawings are not necessarily drawn to scale. In the drawings:

[0034] Figure 1 shows a block diagram of an SoC bus interconnection structure based on the AMBA protocol;

[0035] Figure 2 shows a block diagram of a cross-clock domain APB bus bridge according to an embodiment of the present disclosure;

[0036] Figure 3 shows a block diagram of a cross-clock domain APB bus bridge according to an embodiment of the present disclosure;

[0037] Figure 4 shows a schematic diagram of a write cache enable synchronization circuit according to an example of the present disclosure;

[0038] Figure 5 shows a waveform schematic diagram of the generation of the source clock domain handshake signal (pready_s) according to an embodiment of the present disclosure;

[0039] Figure 6 shows a waveform schematic diagram of two consecutive write cache write operations according to an example of the present disclosure (assuming the cache state of the FIFO is not full);

[0040] Figure 7 shows a waveform schematic diagram of a write input with write cache enabled followed by a write input without write cache enabled according to an example of the present disclosure (assuming the cache state of the FIFO is not full);

[0041] Figure 8 shows a waveform schematic diagram of two write inputs without write cache enabled according to an example of the present disclosure (assuming the cache state of the FIFO is not full);

[0042] Figure 9It is a waveform schematic diagram showing a write input operation with one - stroke write cache enabled according to an example of the present disclosure, followed by a one - stroke read operation (assuming that the cache state of the FIFO is not full);

[0043] Figure 10 It is a structural block diagram showing a specific example of an APB bus bridge across clock domains according to an embodiment of the present disclosure;

[0044] Figure 11 It is a flowchart showing a method of cross - clock - domain access executed by an APB bus bridge according to an embodiment of the present disclosure;

[0045] Figure 12 It is a schematic block diagram showing an APB bus bridge across clock domains according to a specific example of the present disclosure. Detailed implementation manners

[0046] Now, the present disclosure will be discussed with reference to several example embodiments. It should be understood that these embodiments are discussed only for the purpose of enabling those skilled in the art to better understand the present disclosure and thus implement the present disclosure, rather than implying any limitation on the scope of the present disclosure.

[0047] References in the specification to "an embodiment", "embodiment", "example embodiment", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it should be considered within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments (whether explicitly described or not).

[0048] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish the elements from each other. For example, without departing from the scope of the example embodiments, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0049] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when used herein, the terms "comprises", "comprising", "has", "having", "contains", "containing" and / or "incorporating" specify the presence of the stated features, elements and / or components, etc., but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof.

[0050] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Some exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0051] Figure 1 FIG. 100 is a block diagram showing a typical SoC bus interconnect structure based on the AMBA bus, specifically including: a central processing unit (CPU) 102, a direct memory access unit (DMA) 104, and some other bus masters 106; a bus interconnect module 108; a memory 110 and other bus slaves 112; a protocol conversion 114 and a cross-clock domain bus bridge 116 that implements an APB-to-APB bridge. It should be understood that the following is described only for illustrative purposes Figure 1 and does not imply any limitation on the scope of the present disclosure.

[0052] In an Figure 1 AMBA bus-based SoC system as shown, when performing high-speed data exchange, bus interconnect based on the AXI or AHB protocol is mainly adopted, while when performing low-speed operations such as configuration registers, the APB protocol is usually adopted because such low-speed operations have low speed requirements, and the APB protocol is relatively simple, so it is easy to implement and has relatively small overhead.

[0053] The configuration of the registers is mainly processed by the CPU. The protocol and cross-clock domain conversion from the bus interface of the CPU to the APB interface of the registers need to be performed through a bus bridge. Usually, the registers of various peripherals have different frequencies, so the method of first converting the protocol and then converting the frequency can be adopted to reduce the overhead. At this time, an APB-to-APB cross-clock domain bus bridge is required. The advantages of this approach are: on the one hand, implementing cross-clock domain at the APB protocol port has less overhead than implementing it at AXI or AHB; on the other hand, splitting one path of the APB protocol into multiple paths is simpler than the AXI protocol or the AHB protocol. Therefore, this method does not require the use of multiple AXI or AHB-to-APB protocol conversion bus bridges.

[0054] Embodiment 1

[0055] In Embodiment 1, an APB bus bridge across clock domains is provided.

[0056] Figure 2 FIG. 7 is a structural block diagram of an APB bus bridge 200 across clock domains according to an embodiment of the present disclosure. The APB bus bridge 200 according to this embodiment includes the following parts: a source clock domain port, a destination clock domain port, a transmission start detection circuit, a FIFO, an APB bus protocol generation circuit, and a source clock domain handshake signal generation circuit. Among them:

[0057] The source clock domain port is configured to be connected to a master device operating in the source clock domain;

[0058] The destination clock domain port is configured to be connected to one or more APB slave devices operating in the destination clock domain; by way of example and not limitation, the APB slave device may be a peripheral register. By way of example and not limitation, the APB bus bridge performs address decoding through an address decoder to determine which APB slave device communicates with the master device according to the address and control signals.

[0059] The transmission start detection circuit is configured to generate a transmission start flag (trans_start) when a transmission request occurs;

[0060] The FIFO is configured to cache write data and control information, where the FIFO has a non-full signal (~fifo_full), and the non-full signal indicates whether the cache of the FIFO is full;

[0061] The APB bus protocol generation circuit is configured to read and parse the information cached in the FIFO from the FIFO, and generate a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit is also configured to obtain a destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain;

[0062] The source clock domain handshake signal generation circuit is configured to determine whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; where,

[0063] If the current transmission is a write transmission with write cache enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal; where when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO;

[0064] If the current transfer is a read transfer or a write transfer with write caching disabled, wait for the destination clock domain handshake signal to be generated, and then raise the source clock domain handshake signal.

[0065] More specifically, the cached information of the write input includes write data, which includes the direction signal (pwrite), write data signal (pwdata), write strobe signal (pstrb), and address signal (paddr) of the APB port in the source clock domain. Among them, if the direction signal (pwrite) is equal to 1, the current transfer is a write input; if the direction signal (pwrite) is equal to 0, the current transfer is a read input.

[0066] As Figure 2 shown in the APB bus bridge 200, it also includes input / output interface signals: the source clock domain clock clk_s, the source clock domain reset signal rstn_s, the destination clock domain clock clk_d, the destination clock domain reset signal rstn_d, the remaining APB bus interface signals at the source clock domain end (with the signal name suffix marked as _s), and the remaining APB bus interface signals at the destination clock domain end (with the signal name suffix as _d).

[0067] More specifically, the input signals of the transfer start detection circuit include the source clock domain select signal (psel_s), the source clock domain enable signal (penable_s), and the status information of the FIFO. The transfer start detection circuit generates a transfer start flag according to the transfer request. This flag is only valid in the first clock cycle of the transfer start, and this signal is used for the synchronization of the write cache enable register. The transfer start detection circuit can generate a FIFO write signal (push) according to the judgment logic. Specifically, when the transfer start flag is 1 and the cache status of the FIFO is not full, a FIFO write signal is generated, and this FIFO write signal triggers the writing of the cached information required for the current transfer into the FIFO. This FIFO write signal needs to ensure that each transfer has a corresponding correct and valid piece of information written into the FIFO.

[0068] Embodiment 2

[0069] In Embodiment 2, a cross-clock domain APB bus bridge is provided.

[0070] Figure 3 FIG. shows a structural block diagram of a cross-clock domain APB bus bridge 300 according to an embodiment of the present disclosure. The APB bus bridge 300 according to this embodiment includes the following parts: a source clock domain port, a destination clock domain port, a transfer start detection circuit, a write cache enable synchronization circuit, a FIFO, an APB bus protocol generation circuit, and a source clock domain handshake signal generation circuit. Among them:

[0071] The source clock domain port is configured to be used to connect to the master device operating in the source clock domain;

[0072] The destination clock domain port is configured to connect to one or more APB slaves operating in the destination clock domain; by way of example and not limitation, the APB slave can be a peripheral register; by way of example and not limitation, the APB bus bridge performs address decoding through an address decoder to determine, based on the address and control signals, which APB slave communicates with the master device.

[0073] The transmission start detection circuit is configured to generate a transmission start flag (trans_start) when a transmission request occurs;

[0074] The write cache enable synchronization circuit is configured to synchronize the write cache enable signal (wbuf_en) triggered by the transmission start flag to obtain a write cache enable synchronization signal (wbuf_en_sync), wherein the synchronization causes the write cache enable synchronization signal to remain unchanged during the current transmission;

[0075] The FIFO is configured to cache write data and control information, where the FIFO has a not-full signal (~fifo_full), and the not-full signal indicates whether the cache of the FIFO is full;

[0076] The APB bus protocol generation circuit is configured to read and parse the information cached in the FIFO and generate a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit is also configured to obtain the destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain;

[0077] The source clock domain handshake signal generation circuit is configured to determine whether to raise the source clock domain handshake signal (pready_s) based on whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; wherein,

[0078] If the current transmission is a write transmission with write cache enabled, then after waiting for the cache information required for the current transmission to be written into the FIFO, raise the source clock domain handshake signal; wherein when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is not full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO;

[0079] If the current transmission is a read transmission or a write transmission with write cache not enabled, then after waiting for the destination clock domain handshake signal to be generated, raise the source clock domain handshake signal.

[0080] More specifically, in the source clock domain handshake signal generation circuit, the default state of the source clock domain handshake signal (pready_s) is set to 0, and it becomes 1 when the source clock domain handshake signal is raised.

[0081] If the current transfer is a read transfer or a write transfer with the write cache disabled, wait for the handshake signal in the destination clock domain to be generated, and then raise the handshake signal in the source clock domain. As an example, if the current transfer is a read transfer or a write transfer with the write cache disabled, a pulse signal is generated based on the destination clock domain handshake signal (pready_d), destination clock domain enable signal (penable_d), and destination clock domain select signal (psel_d) in the destination clock domain, and this pulse signal is synchronized back to the source clock domain to generate the handshake signal in the source clock domain, which is used as the output of the handshake signal generation circuit in the source clock domain. The destination clock domain handshake signal is generated after waiting for all write transfers with the write cache enabled in the destination clock domain to complete.

[0082] More specifically, the write cache enable signal (wbuf_en_d) synchronized to the destination clock domain is used to mask the handshake signal for write cache enabled transfers in the destination clock domain. Because when the transfer is a write cache enabled transfer, the handshake signal in the source clock domain has already been generated by the handshake signal generation circuit in the source clock domain and does not need to be generated again. Therefore, this signal is used to mask the useless destination clock domain handshake signal to prevent it from being mis-transmitted to the source clock domain and causing transfer errors.

[0083] More specifically, the FIFO write timing is set as follows: if the cache status of the FIFO is not full, a FIFO write signal is generated by the transfer start detection circuit in the first clock cycle of each transfer; if the cache status of the FIFO is full, the write timing is the first clock cycle when the FIFO becomes not full and there is a transfer request. The FIFO read timing is set as follows: the FIFO is read when its cache status is not empty.

[0084] More specifically, the cache information of the write input includes write data, and the write data includes the direction signal (pwrite), write data signal (pwdata), write strobe signal (pstrb), and address signal (paddr) of the APB port in the source clock domain; among them, if the direction signal (pwrite) is equal to 1, the current transfer is a write input; if the direction signal (pwrite) is equal to 0, the current transfer is a read input.

[0085] More specifically, the write cache enable synchronization circuit performs the synchronization of the write cache enable signal (wbuf_en) as follows:

[0086] When the value of the transfer start flag is 1, the write cache enable synchronization signal is assigned the write cache enable signal, and the registered write cache enable signal (wbuf_en_reg) is updated to the write cache enable signal;

[0087] When the value of the transmission start flag is 0, the write buffer enable synchronization signal is assigned the register write buffer enable signal (wbuf_en_reg).

[0088] Since the input write buffer enable signal (wbuf_en) may change at any time, the write buffer enable synchronization circuit can synchronize the value of the write buffer enable signal in the first clock cycle at the beginning of a transfer to obtain the write buffer enable synchronization signal, which is used as a flag to indicate whether the write buffer is enabled for this transfer.

[0089] Figure 4 The schematic diagram of a write buffer enable synchronization circuit is shown as an example. Among them, the inputs of the write buffer enable synchronization circuit include the transmission start flag (trans_start) and the write buffer enable signal (wbuf_en). As an example, the write buffer enable synchronization circuit uses a D flip-flop and a selector. After synchronizing the write buffer enable signal using the transmission start flag, it outputs the write buffer enable synchronization signal (wbuf_en_sync) that remains unchanged during the transfer in the source clock domain port. It should be noted that the circuit structure of the above write buffer enable synchronization circuit is only an example of the present disclosure, but the present disclosure is not limited thereto. For example, other circuit structures can be adopted according to actual situations.

[0090] Specifically, according to Figure 4 the shown write buffer enable circuit, its specific working principle is: when the transmission start flag (trans_start) is 1, the write buffer enable synchronization signal (wbuf_en_sync) is assigned the write buffer enable signal (wbuf_en), and the register write buffer enable signal (wbuf_en_reg) is updated to the write buffer enable signal (wbuf_en), and the register write buffer enable signal (wbuf_en_reg) remains unchanged at other times; when the transmission start flag (trans_start) is 0, the write buffer enable synchronization signal (wbuf_en_sync) is assigned the register write buffer enable signal (wbuf_en_reg).

[0091] As an example rather than a limitation, if the clocks of the source clock domain and the destination clock domain are synchronous clocks, the FIFO uses a synchronous FIFO with two clock ports; if the clocks of the source clock domain and the destination clock domain are asynchronous clocks, the FIFO uses an asynchronous FIFO.

[0092] As an example rather than a limitation, the APB bus bridge is applied to an SoC platform based on the AMBA protocol.

[0093] As an example rather than a limitation, the APB bus bridge is directly connected to the APB host. Among them, the APB host is the host of the APB protocol.

[0094] As an example and not a limitation, the APB bus bridge is connected to the AXI protocol bus or the AHB protocol bus through a protocol conversion bus bridge.

[0095] More specifically, the APB bus protocol generation circuit is further configured to generate control signals and data signals conforming to the APB bus protocol according to the destination clock domain handshake signal (pready_d) of the APB bus input in the destination clock domain.

[0096] Example 1: Write transfers with two consecutive write buffer enables (assuming the cache states of the FIFO are not full and full respectively)

[0097] Such as Figure 5 illustrates the overall working process in which each part of the APB bus bridge combines to generate the source clock domain handshake signal, which is specifically described as follows:

[0098] When a transfer request starts, first, the write buffer enable synchronization circuit synchronizes the write buffer enable signal (wbuf_en) to obtain the write buffer enable synchronization signal (wbuf_en_sync), which remains unchanged during the transfer process at the source clock domain port.

[0099] Such as Figure 5 shown in, the source clock domain select signal (psel_s) is 1 and the source clock domain enable signal (penable_s) is 0, indicating that the first write transfer request with write buffer enable is generated. Therefore, the transfer start flag (trans_start) becomes 1 (as shown by the first dotted circle from left to right in Figure 5 ). At this time, the corresponding FIFO not full signal (fifo_full) is 0, which means that the cache state of the FIFO is not full. Therefore, at the end of the current cycle of the transfer start flag (trans_start), the transfer start detection circuit generates the FIFO write signal corresponding to the first transfer request (as shown by the first arrow from left to right in Figure 5 ). According to the generated FIFO write signal, the information to be cached for the current write transfer request is stored in the FIFO. And, the source clock domain handshake signal generation circuit raises the source clock domain handshake signal (pready_s) (as shown by the first solid circle from left to right in Figure 5 ), that is, returns the source clock domain handshake signal to indicate to the APB host that the current write transfer has been completed. Among them, the APB host is the host of the APB protocol.

[0100] When the source clock domain select signal (psel_s) is 1 and the source clock domain enable signal (penable_s) changes from 1 to 0 again, it indicates that the second write transfer request with write buffer enable is generated. Therefore, the transfer start flag (trans_start) becomes 1 again (asFigure 5 as shown by the second dashed circle in []. At this time, the corresponding FIFO not full signal (fifo_full) is 1, indicating that the buffer status of the FIFO is full. Therefore, the source clock domain handshake signal generation circuit needs to wait until the buffer status of the FIFO becomes not full before the source clock domain handshake signal generation circuit raises the source clock domain handshake signal (pready_s) (as shown by the second solid circle from left to right in []) Figure 5 as shown by the second solid circle from left to right in []. And the transmission start detection circuit generates a FIFO write signal corresponding to the first transfer request (as shown by the second arrow from left to right in []) Figure 5 as shown by the second arrow from left to right in []. According to the generated FIFO write signal, the information to be buffered for the current write transfer request is stored in the FIFO. Specifically, the source clock domain handshake signal can be set to the inverse value when the FIFO not full signal (fifo_full) becomes 0.

[0101] It should be understood that if the current transfer request is a read transfer or a write transfer with write buffering disabled, the source clock domain handshake signal is raised after waiting for the destination clock domain transfer to complete.

[0102] In addition, the APB bus protocol generation circuit is configured to determine whether to read the buffered information from the FIFO according to the buffer status of the read end of the FIFO. When the buffer status of the read end of the FIFO is not empty, the APB bus protocol generation circuit reads the buffered information in the FIFO and parses it, and generates control and write data signals conforming to the APB protocol in the destination clock domain.

[0103] Further optimized, the destination clock domain APB port generates a destination clock domain handshake signal (pready_d), and determines whether to synchronize the destination clock domain handshake signal (pready_d) to the source clock domain according to the write buffer enable signal (wbuf_en_d) synchronized to the destination clock domain and the destination clock domain direction signal (pwrite_d). Specifically:

[0104] If the write buffer enable signal (wbuf_en_d) and the destination clock domain direction signal (pwrite_d) are both 1 at the same time, it means that the current transfer in the destination clock domain is a write transfer with write buffering enabled. Since the source clock domain handshake signal generation circuit has already returned the handshake signal in advance, there is no need to synchronize the destination clock domain handshake signal (pready_d) to the source clock domain at this time;

[0105] Otherwise, the destination clock domain handshake signal (pready_d) is synchronized to the source clock domain and assigned to the source clock domain handshake signal (pready_s).

[0106] In addition, the destination clock domain data signal (prdata_d) is also assigned to the source clock domain data signal (prdata_s), and the destination clock domain error response signal (pslverr_d) is assigned to the source clock domain error response signal (pslverr_s).

[0107] Example 2: Two consecutive write cache enabled write operations (assuming the cache status of the FIFO is not full)

[0108] As Figure 6 shows the overall working process of each part of the APB bus bridge combined to generate the source clock domain handshake signal, which is specifically described as follows:

[0109] In this example, it is assumed that the cache status of the FIFO always remains non-full (i.e., the signal is 0), as Figure 6 the waveform diagram of the FIFO non-full signal (fifo_full) is not shown. As Figure 6 shown, both write transfer requests are write transfer operations with write cache enabled. As marked in the figure, after receiving the write transfer request in the source clock domain, since the cache status of the FIFO is not full, the cache information will be written into the FIFO, and the source clock domain handshake signal will be pulled high (as marked by the first and second circles and arrows from left to right in the figure), without waiting for the handshake signal (pready_d) returned by the destination clock domain. These two write cache enabled transfers only require 4 source clock cycles to complete at the source clock domain end and return the source clock domain handshake signal respectively. While at the destination clock domain end, it takes some time to actually write the data to the destination (as marked by the third and fourth circles and arrows from left to right in the figure).

[0110] Therefore, through the technical solution of this application, by returning the source clock domain handshake signal in advance, the write input operation with write cache enabled can be accelerated, and the CPU can be released in advance for other operations.

[0111] Example 3: A write input with write cache enabled followed by a write input without write cache enabled (assuming the cache status of the FIFO is not full)

[0112] As Figure 7 shows the overall working process of each part of the APB bus bridge combined to generate the source clock domain handshake signal, which is specifically described as follows:

[0113] In this example, it is assumed that the cache status of the FIFO always remains non-full (i.e., the signal is 0), as Figure 7 the waveform diagram of the FIFO non-full signal (fifo_full) is not shown. As Figure 7 shown, a write input with write cache enabled, and then a write input without write cache enabled follows. As Figure 7As identified, for the first write input operation with write cache enabled, after receiving the write transfer request in the source clock domain, since the cache status of the FIFO is not full, the cache information will be written into the FIFO, and the handshake signal in the source clock domain will be pulled high (as identified by the first circle and arrow from left to right in the figure), without waiting for the handshake signal (pready_d) returned from the destination clock domain. The second write input request is a write input operation without write cache enabled (as identified by the second circle and arrow from left to right in the figure). Therefore, this write input operation needs to return the destination domain handshake signal (pready_d) corresponding to the second write operation without write cache enabled after all cache write operations before the destination clock domain is completed (as identified by the fourth circle and arrow in the figure), for generating the handshake signal (pready_s) in the source clock domain (as identified by the fifth circle and arrow from left to right in the figure).

[0114] Example 4: Two write inputs without write cache enabled (assuming the cache status of the FIFO is not full)

[0115] As Figure 8 shows the overall working process of each part of the APB bus bridge combined to generate the handshake signal in the source clock domain, which is described in detail as follows:

[0116] In this example, it is assumed that the cache status of the FIFO always remains non-full (i.e., the signal is 0), as Figure 8 the waveform diagram of the FIFO non-full signal (fifo_full) is not shown. As Figure 8 shown, two write inputs without write cache enabled. As Figure 8 As identified, for the first write input operation without write cache enabled, after receiving the write transfer request in the source clock domain, since it is a write input without write cache enabled, it needs to wait until all cache write operations before the destination clock domain are completed (as identified by the second circle and arrow from left to right in the figure), and return the destination domain handshake signal (pready_d) corresponding to the first write operation without write cache enabled, for generating the handshake signal (pready_s) in the source clock domain (as identified by the third arrow from left to right in the figure). Similarly, for the second write input operation without write cache enabled, after receiving the write transfer request in the source clock domain, since it is a write input without write cache enabled, it needs to wait until all cache write operations before the destination clock domain are completed (as identified by the fourth circle and arrow from left to right in the figure), and return the destination domain handshake signal (pready_d) corresponding to the second write operation without write cache enabled, for generating the handshake signal (pready_s) in the source clock domain (as identified by the sixth arrow from left to right in the figure).

[0117] Example 5: A write input operation with write cache enabled is followed by a read operation (assuming that the cache status of the FIFO is not full).

[0118] As Figure 9 shown, the various parts of the APB bus bridge are combined to generate the overall working process of the source clock domain handshake signal, which is specifically described as follows:

[0119] In this example, it is assumed that the cache status of the FIFO always remains non-full (i.e., the signal is 0). As Figure 9 shown in, the waveform diagram of the FIFO non-full signal (fifo_full) is not shown. As Figure 9 shown, after a write input operation with write cache enabled, a read operation follows. As Figure 9 As identified in, for the first write input operation with write cache enabled, after receiving the write transfer request in the source clock domain, since the cache status of the FIFO is not full, the cache information will be written into the FIFO, and the source clock domain handshake signal will be pulled high (as identified by the first circle and arrow from left to right in the figure), without waiting for the handshake signal (pready_d) returned from the destination clock domain. The second request is a read operation (as identified by the second circle and arrow from left to right in the figure). Therefore, after all the previous cache write operations in the destination clock domain are completed, the data (prdata_d) of the read transfer and the error response signal (pslverr_d) of the read transfer need to be returned to the source clock domain, and at the same time, the destination domain handshake signal (pready_d) corresponding to the second read operation is returned (as identified by the fourth circle and arrow in the figure) to be used to generate the source clock domain handshake signal (pready_s) (as identified by the fifth circle and arrow from left to right in the figure).

[0120] Embodiment 3

[0121] In Embodiment 3, a specific example of an APB bus bridge across clock domains is provided. Figure 10 is a structural block diagram showing an APB bus bridge 1000 across clock domains according to an embodiment of the present disclosure. The APB bus bridge 1000 according to this embodiment includes the following parts: a source clock domain port, a destination clock domain port, a transmission start detection circuit, a write cache enable synchronization circuit, a FIFO, an APB bus protocol generation circuit, and a source clock domain handshake signal generation circuit. Among them: the source clock domain handshake signal generation circuit includes a handshake signal synchronization module (pready synchronization module), a selector, and an AND gate.

[0122] Among them, the source clock domain port is configured to connect to a master device operating in the source clock domain; the destination clock domain port is configured to connect to one or more APB slave devices operating in the destination clock domain, where the APB slave device can be a peripheral register; the transmission start detection circuit is configured to generate a transmission start flag (trans_start) when a transmission request occurs; the write buffer enable synchronization circuit is configured to synchronize the write buffer enable signal (wbuf_en) triggered by the transmission start flag to obtain a write buffer enable synchronization signal (wbuf_en_sync), where the synchronization causes the write buffer enable synchronization signal to remain unchanged during the current transmission; the FIFO is configured to cache write data and control information, where the FIFO has a not-full signal (~fifo_full), and the not-full signal indicates whether the cache of the FIFO is full; the APB bus protocol generation circuit is configured to read and parse the information cached in the FIFO from the FIFO and generate a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit is also configured to obtain a destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain; the source clock domain handshake signal generation circuit is configured to determine whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write buffer enabled and the cache status of the FIFO; among them,

[0123] If the current transmission is a write transmission with write buffer enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal; when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is not full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO;

[0124] If the current transmission is a read transmission or a write transmission with write buffer not enabled, wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

[0125] More specifically, in the source clock domain handshake signal generation circuit, the default state of the source clock domain handshake signal (pready_s) is set to 0, and it becomes 1 when the source clock domain handshake signal is raised.

[0126] The technical solution of this application can support the dynamic switching of the write buffer enable signal (wbuf_en). The rewritten write buffer enable signal (wbuf_en) can come from a register or the bufferable information in the awcache signal in the AXI protocol.

[0127] When the present invention needs to configure a large number of registers at one time and there are multiple write transfer operations, it can significantly accelerate the system speed. If it is necessary to ensure that the written data is truly written to the destination, an additional read operation or a non-cached write operation can be added after the write operation.

[0128] Embodiment 4

[0129] In Embodiment 4, a method for cross-clock domain access executed by an APB bus bridge is provided. Figure 11 FIG. is a flowchart showing a method for cross-clock domain access executed by an APB bus bridge according to an embodiment of the present disclosure. The APB bus bridge according to the present embodiment includes the following parts: a source clock domain port for connecting a master device operating in a source clock domain; a destination clock domain port for connecting one or more APB slave devices operating in a destination clock domain; a transmission start detection circuit; a write cache enable synchronization circuit; a FIFO for caching write data and control information, where the FIFO has a non-full signal (~fifo_full), and the non-full signal indicates whether the cache of the FIFO is full; an APB bus protocol generation circuit; and a source clock domain handshake signal generation circuit configured to select the source for generating the source clock domain handshake signal according to whether the current transmission is a write transmission with write cache enabled and the cache state of the FIFO. Among them, by way of example and not limitation, the APB slave device may be a peripheral register.

[0130] A method for cross-clock domain access executed by an APB bus bridge includes, when a transmission request occurs, performing the following steps:

[0131] Step 1: The transmission start detection circuit generates a transmission start flag;

[0132] Step 2: The write cache enable synchronization circuit is triggered by the transmission start flag to perform synchronization of the write cache enable signal to obtain a write cache enable synchronization signal, where the synchronization causes the write cache enable synchronization signal to remain unchanged during the current transmission;

[0133] Step 3: The source clock domain handshake signal generation circuit determines whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write cache enabled and the cache state of the FIFO; where, if the current transmission is a write transmission with write cache enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal. When the transmission start detection circuit generates a transmission start flag and the cache state of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; if the current transmission is a read transmission or a write transmission with write cache not enabled, wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

[0134] Preferably, the method may further include:

[0135] Step 4: The APB bus protocol generation circuit reads and parses the information cached in the FIFO, generates a destination clock domain write data signal in the destination clock domain, and the APB bus protocol generation circuit also acquires the destination clock domain handshake signal (pready_d) input by the APB bus in the destination clock domain.

[0136] Specific example

[0137] In Embodiment 5, a cross-clock domain APB bus bridge is provided. Figure 12 FIG. is a schematic block diagram of a cross-clock domain APB bus bridge showing a specific example according to the present disclosure. The APB bus bridge includes: a source clock domain port, a destination clock domain port, a FIFO, an APB bus protocol generation module, and a source clock domain handshake signal (pready_s) generation module;

[0138] A transmission start detection module configured to generate a transmission start flag (trans_start) when a transmission request occurs;

[0139] A FIFO configured to cache write data and control information, where the FIFO has a non-full signal (~fifo_full), and the non-full signal indicates whether the cache of the FIFO is full;

[0140] An APB bus protocol generation module configured to read and parse the information cached in the FIFO and generate a destination clock domain control signal and a destination clock domain write data signal in the destination clock domain, where the destination clock domain control signal includes a destination clock domain handshake signal (pready_d);

[0141] A source clock domain handshake signal generation module, which is configured to determine whether to raise the source clock domain handshake signal (pready_s) according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; wherein, by way of example and not limitation, the source clock domain handshake signal generation module includes an edge synchronization module, and a read or non-cache write completion signal generation module. In the specific implementation process, first, the read or non-cache write completion signal generation module generates a completion signal (done_d), and the completion signal (done_d) is a single-cycle pulse signal; then the edge synchronization module synchronizes the single-cycle pulse signal to the source clock domain using the edge synchronization method to generate the source clock domain (pready_s) signal. Among them, when the destination domain chip select signal (psel_d), the destination domain enable signal (penable_d), and the destination clock domain handshake signal (pready_d) are all 1, and at this time the operation of the destination domain is a read operation or a non-cache write operation, the completion signal (done_d) is set to 1. In addition, the data (prdata_s) of the read transmission and the read transmission error response signal (pslverr_s) in the source clock domain need to be updated to the data (prdata_d) of the read transmission and the read transmission error response signal (pslverr_d) in the destination clock domain when the completion signal (done_d) is 1. Through this caching operation, it can be ensured that after the destination clock domain transmission is completed, even if the data (prdata_d) of the read transmission and the read transmission error response signal (pslverr_d) in the destination clock domain have changed, and at this time the source clock domain transmission is still not completed, there will be no error in the data (prdata_s) of the read transmission and the read transmission error response signal (pslverr_s) obtained by the source clock domain.

[0142] If the current transmission is a write transmission with write cache enabled, then wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal; wherein when the transmission start detection circuit generates a transmission start flag and the cache status of the FIFO is not full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO;

[0143] If the current transmission is a read transmission or a write transmission with write cache not enabled, then wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

[0144] Further optimized, the APB bus bridge includes a write buffer enable synchronization module. The write buffer enable synchronization module is configured to synchronize the write buffer enable signal (wbuf_en) triggered by the transfer start flag to obtain a write buffer enable synchronization signal (wbuf_en_sync). Among them, the synchronization makes the write buffer enable synchronization signal remain unchanged during the current transfer. The technical solution of this application creatively designs an APB bus bridge across clock domains. Through the connection method and interactive working mode of each unit in the system, a FIFO is used to achieve access across clock domains, and the write buffer enable synchronization circuit is triggered by the transfer start flag (trans_start) to synchronize the write buffer enable signal (wbuf_en). Furthermore, through the source clock domain handshake signal generation circuit, the source clock domain handshake signal can be returned in advance for the write input operation with write buffer enable without waiting for the corresponding write input operation at the destination end to complete. Therefore, the switching between the write operation with write buffer enable and the write operation without write buffer enable can be dynamically performed.

[0145] The present invention uses a FIFO to cache write data and control information, and determines whether to return the source clock domain handshake signal (pready_s) in advance according to the control signal to complete the write transfer in advance, realizing the write transfer acceleration when the write buffer option is enabled, enabling the CPU (Central Processing Unit) and the bus in the system to complete the register configuration operation in advance and process other transactions, greatly improving the efficiency of the system.

[0146] In addition, the present invention supports both synchronous and asynchronous clock domain crossings. If it is a synchronous clock domain crossing, a synchronous FIFO is used for the FIFO; otherwise, an asynchronous FIFO is used. If the clocks of the source clock domain and the destination clock domain are asynchronous clocks, an asynchronous FIFO is used for the FIFO.

[0147] The present invention adopts a method of dynamically enabling the write buffer function. Therefore, the write buffer enable switches for each write transfer can be the same or different, which is compatible with the traditional APB clock domain crossing method while adding an option for write acceleration.

[0148] The technical solution of the present invention has been applied to the MCU (Microcontroller Unit) chip, and the simulation results and FPGA tests have both proved the feasibility of the above technical solution.

[0149] Generally, the various embodiments of the present disclosure can be implemented using hardware or special-purpose circuits, software, logic, or any combination thereof. Some aspects can be implemented using hardware, while other aspects can be implemented using firmware or software that can be executed by a controller, microprocessor, or other computing device. Although the various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flowcharts, or using some other graphical representation, it will be appreciated that the blocks, apparatus, systems, techniques, or methods described herein can be implemented (by way of non-limiting example) using hardware, software, firmware, special-purpose circuits or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0150] As an example, embodiments of the present disclosure can be described in the general context of machine-executable instructions (e.g., instructions included in program modules) that are executed in a device on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of program modules can be combined or split as needed among program modules. The machine-executable instructions of program modules can be executed within a local or distributed device. In a distributed device, program modules can be located in both local and remote storage media.

[0151] Moreover, although the operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these details should not be construed as limiting the scope of the present disclosure, but rather as descriptions of features that may be specific to particular embodiments. The specific features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0152] Although the present disclosure has been described in language specific to structural features and / or method acts, it should be understood that the present disclosure as defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An APB bus bridge across clock domains, characterized in that, The APB bus bridge includes: A source clock domain port configured to connect to a master device operating in the source clock domain; A destination clock domain port configured to connect to one or more APB slave devices operating in the destination clock domain; A transmission start detection circuit configured to generate a transmission start flag when a transmission request occurs; A FIFO configured to cache write data and control information, where the FIFO has a non-full signal indicating whether the cache of the FIFO is full; An APB bus protocol generation circuit configured to read and parse the information cached in the FIFO and generate a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit is also configured to obtain a destination clock domain handshake signal input by the APB bus in the destination clock domain; A source clock domain handshake signal generation circuit configured to determine whether to raise the source clock domain handshake signal based on whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO. Among them, If the current transmission is a write transmission with write cache enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal. When the transmission start detection circuit generates the transmission start flag and the cache status of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; If the current transmission is a read transmission or a write transmission with write cache not enabled, wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

2. The APB bus bridge according to claim 1, characterized in that, The cache information includes write data, and the write data includes a direction signal, a write data signal, a write strobe signal, and an address signal of the APB port in the source clock domain. Among them, if the direction signal is equal to 1, the current transmission is a write input; if the direction signal is equal to 0, the current transmission is a read input.

3. The APB bus bridge according to claim 2, characterized in that, The APB bus bridge includes a write cache enable synchronization circuit configured to synchronize the write cache enable signal triggered by the transmission start flag to obtain a write cache enable synchronization signal. Among them, the synchronization makes the write cache enable synchronization signal remain unchanged during the current transmission.

4. The APB bus bridge according to claim 3, characterized in that, The write cache enable synchronization circuit performs the synchronization of the write cache enable signal including: When the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned the write cache enable signal, and the registered write cache enable signal is updated to the write cache enable signal; When the value of the transmission start flag is 0, the write cache enable synchronization signal is assigned the registered write cache enable signal.

5. The APB bus bridge according to claim 1, characterized in that, If the clocks of the source clock domain and the destination clock domain are synchronous clocks, the FIFO uses a synchronous FIFO with two clock ports; if the clocks of the source clock domain and the destination clock domain are asynchronous clocks, the FIFO uses an asynchronous FIFO.

6. The APB bus bridge according to any one of claims 1-5, characterized in that The APB bus bridge is applied to an SoC platform based on the AMBA protocol.

7. The APB bus bridge according to any one of claims 1-5, characterized in that, The APB bus bridge is directly connected to the APB host.

8. The APB bus bridge according to claim 7, characterized in that, The APB bus bridge is connected to the AXI protocol bus or the AHB protocol bus through a protocol conversion bus bridge.

9. A method for cross-clock domain access performed by an APB bus bridge, characterized in that the APB bus bridge includes: a source clock domain port for connecting a master device operating in the source clock domain; a destination clock domain port for connecting one or more APB slave devices operating in the destination clock domain; a transmission start detection circuit; a write cache enable synchronization circuit; a FIFO for caching write data and control information, where the FIFO has a non-full signal, and the non-full signal indicates whether the cache of the FIFO is full; an APB bus protocol generation circuit; and a source clock domain handshake signal generation circuit configured to select the source for generating the source clock domain handshake signal according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO. The method includes, when a transmission request occurs, performing the following steps: The transmission start detection circuit generates a transmission start flag. The write cache enable synchronization circuit is triggered by the transmission start flag to perform synchronization of the write cache enable signal to obtain a write cache enable synchronization signal, where the synchronization causes the write cache enable synchronization signal to remain unchanged during the current transmission. The source clock domain handshake signal generation circuit determines whether to raise the source clock domain handshake signal according to whether the current transmission is a write transmission with write cache enabled and the cache status of the FIFO; where, if the current transmission is a write transmission with write cache enabled, wait until the cache information required for the current transmission is written into the FIFO, and then raise the source clock domain handshake signal, where when the transmission start detection circuit generates the transmission start flag and the cache status of the FIFO is non-full, a FIFO write signal is generated, and the FIFO write signal triggers the writing of the cache information required for the current transmission into the FIFO; if the current transmission is a read transmission or a write transmission with write cache not enabled, wait until the destination clock domain handshake signal is generated, and then raise the source clock domain handshake signal.

10. The method according to claim 9, wherein The method further includes performing the following steps: The APB bus protocol generation circuit reads and parses the information cached in the FIFO, and generates a destination clock domain write data signal in the destination clock domain. The APB bus protocol generation circuit also obtains the destination clock domain handshake signal input by the APB bus in the destination clock domain.

11. The method according to claim 10, characterized in that, The cached information includes write data, and the write data includes a direction signal, a write data signal, a write strobe signal, and an address signal of the source clock domain APB port; where, if the direction signal is equal to 1, the current transmission is a write input; if the direction signal is equal to 0, the current transmission is a read input.

12. The method according to claim 11, wherein The write cache enable synchronization circuit performing the synchronization of the write cache enable signal includes: When the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned the write cache enable signal, and the registered write cache enable signal is updated to the write cache enable signal. When the value of the transmission start flag is 0, the write cache enable synchronization signal is assigned the registered write cache enable signal.

Images