A low-voltage district three-level topology generation method and device

Abstract

The application belongs to the field of power supply system, and provides a low-voltage transformer area three-level topology structure generation method and device, which comprises the following steps: obtaining current values of all circuit breakers at a current time node; sorting the obtained current values of the circuit breakers in descending order; taking the circuit breaker with the largest current value as a root node, calculating all possible combinations when the sum of current values of other remaining circuit breakers is equal to the current value of the root node circuit breaker, and recording each possible combination as a sub-node set; screening out a sub-node set with the least nodes from all sub-node sets to form a least sub-node set, taking one of the least sub-node sets as a sub-node, and calculating all topology relationships; until all sets in the least sub-node set are calculated, the final all topology relationships and the occurrence probability of the corresponding topology relationships are obtained; the possible relationship of the root node is calculated preferentially for the three-level topology structure, and the calculation amount is reduced to improve the calculation efficiency by using the set for relevant calculation.

Description

Technical Field

[0001] This invention belongs to the field of power supply system technology, specifically relating to a method and apparatus for generating a three-level topology structure for low-voltage distribution areas. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] With the rapid development of the power grid, higher demands are being placed on the intelligence and precision of distribution transformer areas. This is also a trend in power grid development, and distribution transformer areas have an increasingly urgent need for topology. With technological advancements, new equipment already possesses topology identification capabilities, but there is still a need for topology calculation for older equipment.

[0004] Most of the field has a three-level topology. The common method of calculating the topology based on the current requires calculating all the possibilities of the data nodes. The time complexity of calculating each possibility is Cn1 + Cn2 + ... Cnn (combinations). According to the calculation of sets, all possible relationships need to be calculated, which is computationally intensive and time-consuming. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a method and apparatus for generating a three-level topology structure for low-voltage distribution areas. This invention targets three-level topology distribution areas and significantly reduces the amount of data that needs to be calculated by operating on the data set.

[0006] According to some embodiments, the first aspect of the present invention provides a method for generating a three-level topology structure for a low-voltage distribution area, employing the following technical solution:

[0007] A method for generating a three-level topology structure for a low-voltage distribution area includes:

[0008] Get the current values ​​of all circuit breakers at the current time point;

[0009] The obtained circuit breaker current values ​​are sorted from largest to smallest;

[0010] Taking the circuit breaker with the largest current value as the root node, calculate all possible combinations when the sum of the current values ​​of the other remaining circuit breakers equals the current value of the root node circuit breaker. Each possibility is recorded as a set of child nodes.

[0011] Select the set of child nodes with the fewest nodes from the entire set of child nodes to form the set of the fewest child nodes;

[0012] Calculate all topological relationships using one of the sets with the fewest child nodes as child nodes;

[0013] The process continues until all sets in the minimum child node set have been calculated, yielding the final complete topological relationships and the probability of their occurrence.

[0014] Furthermore, the method also includes:

[0015] Obtain the current values ​​of all circuit breakers at the next time node, repeat the above process, and use the topology relationship with the highest probability as the three-level topology relationship of the low-voltage distribution area to generate the three-level topology structure of the low-voltage distribution area.

[0016] Furthermore, the step of calculating all topological relationships using one of the sets with the fewest child nodes as child nodes specifically involves:

[0017] The set of child nodes with the most nodes is selected from the entire set of child nodes to obtain the set of child nodes with the most nodes.

[0018] By subtracting each set in the minimum child node set from the maximum child node set, we obtain the minimum difference node set and the maximum difference node set.

[0019] Taking each node in one of the sets with the fewest child nodes as a child node, calculate the set of all leaf nodes where the sum of the circuit breaker currents in the set with the largest difference equals the current value of the child node.

[0020] When all nodes in one of the sets of minimum child nodes have been calculated, the complete topological relationships are obtained.

[0021] Furthermore, the step of calculating the set of all leaf nodes for which the sum of the circuit breaker currents in the set of nodes with the least child nodes is equal to the current value of the circuit breaker in the child node, specifically by taking each node in one of the sets of nodes with the least child nodes as a child node, is as follows:

[0022] Taking a node from one of the sets of minimum child nodes as a child node, calculate all possible combinations when the sum of the circuit breaker currents of 1, 2...n nodes in the set of maximum difference nodes equals the circuit breaker current value of that child node. Record each possibility as a leaf node set.

[0023] Take another node from one of the sets with the fewest child nodes as a child node, and repeat the above process until all nodes in one of the sets with the fewest child nodes have been calculated, thus obtaining the complete set of leaf nodes.

[0024] Furthermore, the step of subtracting each set in the minimum child node set from the maximum child node set to obtain the minimum difference node set and the maximum difference node set specifically involves:

[0025] Subtract the set of the most child nodes from each set in the set of the fewest child nodes to obtain the set of the fewest difference nodes;

[0026] Subtract each set in the set of least child nodes from the set of most child nodes to obtain the set of nodes with the largest difference.

[0027] Furthermore, the minimum set of child nodes is a set of child nodes that contains multiple nodes with the same number of nodes and the minimum number of nodes.

[0028] Furthermore, the set of child nodes with the most child nodes is the set of child nodes with the largest number of unique nodes.

[0029] According to some embodiments, the second aspect of the present invention provides a three-level topology generation device for low-voltage distribution areas, which adopts the following technical solution:

[0030] A three-level topology generation device for low-voltage distribution areas includes:

[0031] The current acquisition module is configured to acquire the current values ​​of all circuit breakers at the current time point;

[0032] The current sorting module is configured to sort the acquired circuit breaker current values ​​from largest to smallest.

[0033] The child node generation module is configured to take the circuit breaker with the largest current value as the root node, calculate all possible combinations when the sum of the current values ​​of the other remaining circuit breakers equals the current value of the root node circuit breaker, and record each possibility as a set of child nodes.

[0034] The topology generation module is configured to select the set of child nodes with the fewest nodes from the entire set of child nodes to form the set of the fewest child nodes.

[0035] Calculate all topological relationships using one of the sets with the fewest child nodes as child nodes;

[0036] The process continues until all sets in the minimum child node set have been calculated, yielding the final complete topological relationships and the probability of their occurrence.

[0037] According to some embodiments, a third aspect of the present invention provides a computer-readable storage medium.

[0038] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in a method for generating a three-level topology of a low-voltage distribution area as described in the first aspect above.

[0039] According to some embodiments, a fourth aspect of the present invention provides a computer device.

[0040] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in the method for generating a three-level topology of a low-voltage distribution area as described in the first aspect above.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] 1. This invention targets three-level topology transformer areas, first calculating the possible relationships of the root node, then using sets to perform related calculations, eliminating unnecessary computational load, and finally performing calculations on all possibilities of the processed data. This significantly reduces the amount of data that needs to be calculated, lowers the computational time complexity, and thus improves computational efficiency.

[0043] 2. In this invention, the set of child nodes with the fewest nodes and the set of child nodes with the most nodes are taken from the set of child nodes. The difference between the two is used to remove the common part of the two. The relevant calculations are performed through the sets, thereby reducing unnecessary calculations and improving calculation efficiency. Attached Figure Description

[0044] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0045] Figure 1 This is a flowchart of a method for generating a three-level topology structure for a low-voltage distribution area, as described in an embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0047] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0048] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0049] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0050] Example 1

[0051] like Figure 1 As shown, this embodiment provides a method for generating a three-level topology structure for a low-voltage distribution area. This embodiment uses the application of this method to a server as an example for illustration. It is understood that this method can also be applied to terminals, and can also be applied to systems including terminals, servers, and other components, and can be implemented through interaction between the terminal and the server. The server can be an independent physical server, a server cluster composed of multiple physical servers, or a distributed system. It can also be a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network servers, cloud communication, middleware services, domain name services, CDN security services, and big data and artificial intelligence platforms. The terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, etc., but is not limited to these. The terminal and server can be directly or indirectly connected via wired or wireless communication, which is not limited herein. In this embodiment, the method includes the following steps:

[0052] Get the current values ​​of all circuit breakers at the current time point;

[0053] The obtained circuit breaker current values ​​are sorted from largest to smallest;

[0054] Taking the circuit breaker with the largest current value as the root node, calculate all possible combinations when the sum of the current values ​​of the other remaining circuit breakers equals the current value of the root node circuit breaker. Each possibility is recorded as a set of child nodes.

[0055] Select the set of child nodes with the fewest nodes from the entire set of child nodes to form the set of the fewest child nodes.

[0056] Calculate all topological relationships using one of the sets with the fewest child nodes as child nodes;

[0057] The process continues until all sets in the minimum child node set have been calculated, yielding the final complete topological relationships and the probability of their occurrence.

[0058] Specifically, the method described in this embodiment includes the following processes:

[0059] S1: Collect all circuit breaker current values ​​at this moment;

[0060] S2: Sort all the current values ​​of the circuit breakers collected from largest to smallest;

[0061] S3: The circuit breaker with the largest current value is the root node;

[0062] S4: From the remaining circuit breakers, calculate the possibilities that the sum of one, two...n currents equals the sum of the currents of the previous level. Each possibility is recorded as a set of child nodes, denoted as S1, S2, S3...Sn.

[0063] S5: Select the set of child nodes with the fewest nodes from the entire set of child nodes to form the set of the fewest child nodes, denoted as Sv(Sv1,Sv2,...Svs, where 1≤s<n). The set of the fewest child nodes Sv contains multiple sets of child nodes with the same number of nodes and the fewest number of nodes.

[0064] S6: Select the set of child nodes with the most nodes from the entire set of child nodes. The set of child nodes with the most nodes is called Sm. The set of child nodes with the most nodes is the only set of child nodes with the most nodes.

[0065] For example, if the current values ​​of all circuit breakers are 10, 5, 4, 3, 2, 1, with 10 as the root node, the possible root node sets are S1(5,4,1), S2(5,3,2), and S3(4,3,2,1). Then, the minimum set of child nodes is Sv(Sv1,Sv2), where Sv1 is S1 and Sv2 is S2. The maximum set of child nodes Sm is S3.

[0066] S7: Take the difference between a set Svx in the set of the fewest child nodes Sv and the set of the most child nodes to obtain the set of the fewest difference nodes Svc and the set of the fewest difference nodes Smc;

[0067] Let Svc = Svx - Sm, and Smc = Sm - Svx; where x represents the x-th set in the minimum child node set Sv.

[0068] S8: Taking each node in the minimum difference node set Svc as a child node, calculate the set of all leaf nodes where the sum of the circuit breaker currents in the maximum difference node set Smc equals the current value of the child node. Specifically:

[0069] Taking a node in the minimum difference node set Svc as a child node, calculate all possible combinations when the sum of the circuit breaker currents of 1, 2, ..., n nodes in the maximum difference node set Smc equals the circuit breaker current value of that child node. Each possibility is recorded as a leaf node set, denoted as Sln (Sl1, Sl2...Sln).

[0070] If Sln is taken as a leaf node, then the topological relationship is calculated. Record the topological relationship, go to S7, and select another set in the set with the fewest child nodes Sv to perform a loop operation.

[0071] S9: Until all nodes in the minimum difference node set Svc have been calculated, the final complete topological relationships and the probability of occurrence of the corresponding topological relationships are obtained.

[0072] S10: Obtain the current values ​​of all circuit breakers at the next time node, repeat the above steps S1-S9, and generate the three-level topology structure of the low-voltage distribution area by taking the topology relationship with the highest probability as the three-level topology relationship of the low-voltage distribution area.

[0073] The calculation of the superior topological relationship based on the current may result in multiple possible relationships, all of which include the actual topological relationship. For example, if the actual topological relationship is 1, at this moment there may be three relationships: 1, 2, and 3. At the next moment, it may be 1, 4, etc. In this way, as time goes by, the probability of the actual topological relationship appearing increases.

[0074] Example 2

[0075] This embodiment provides a three-level topology generation device for low-voltage distribution areas, including:

[0076] The current acquisition module is configured to acquire the current values ​​of all circuit breakers at the current time point;

[0077] The current sorting module is configured to sort the acquired circuit breaker current values ​​from largest to smallest.

[0078] The child node generation module is configured to take the circuit breaker with the largest current value as the root node, calculate all possible combinations when the sum of the current values ​​of the other remaining circuit breakers equals the current value of the root node circuit breaker, and record each possibility as a set of child nodes.

[0079] The topology generation module is configured to select the set of child nodes with the fewest nodes from the entire set of child nodes to form the set of the fewest child nodes.

[0080] Calculate all topological relationships using one of the sets with the fewest child nodes as child nodes;

[0081] The process continues until all sets in the minimum child node set have been calculated, yielding the final complete topological relationships and the probability of their occurrence.

[0082] The examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in Embodiment 1 above. It should be noted that the above modules, as part of the system, can be executed in a computer system such as a set of computer-executable instructions.

[0083] The descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] The proposed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and the division of modules described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed.

[0085] Example 3

[0086] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the method for generating a three-level topology of a low-voltage distribution area as described in Embodiment 1 above.

[0087] Example 4

[0088] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the method for generating a three-level topology of a low-voltage distribution area as described in Embodiment 1 above.

[0089] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0090] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0093] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0094] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A low-voltage district three-level topology generation method, characterized in that, The method comprises the following steps: obtaining current values of all circuit breakers at a current time node; sorting the obtained current values of the circuit breakers in descending order; taking the circuit breaker with the largest current value as a root node, and calculating all possible combinations when the sum of current values of the remaining circuit breakers is equal to the current value of the root node circuit breaker, and each possible combination is recorded as a sub-node set; filtering out a sub-node set with the least nodes from all sub-node sets to form a least-node sub-node set; taking one of the least-node sub-node sets as a sub-node, and calculating all topology relations, specifically as follows: filtering out a sub-node set with the most nodes from all sub-node sets to obtain a most-node sub-node set; performing difference operations between all sets in the least-node sub-node set and the most-node sub-node set to obtain a minimum-difference node set and a maximum-difference node set, specifically as follows: subtracting the most-node sub-node set from all sets in the least-node sub-node set to obtain the minimum-difference node set, wherein the least-node sub-node set is a sub-node set with the same number of nodes and the least number of nodes; subtracting each set in the least-node sub-node set from the most-node sub-node set to obtain the maximum-difference node set; respectively taking each node in the minimum-difference node set as a sub-node, and calculating all leaf node sets when the sum of current values of the nodes in the maximum-difference node set is equal to the current value of the sub-node; obtaining all topology relations when the calculation of the nodes in the minimum-difference node set is completed; repeating the above process until the calculation of all sets in the least-node sub-node set is completed, and obtaining the final all topology relations and the occurrence probability of the topology relations.

2. The low-voltage area three-level topology generation method of claim 1, wherein, The method further comprises the following steps: obtaining current values of all circuit breakers at a next time node, and repeating the above process to obtain a low-voltage transformer substation three-level topology structure by taking the topology relation with the largest probability as the low-voltage transformer substation three-level topology relation.

3. The low-voltage area three-level topology generation method of claim 1, wherein, The step of respectively taking each node in the minimum-difference node set as a sub-node, and calculating all leaf node sets when the sum of current values of the nodes in the maximum-difference node set is equal to the current value of the sub-node, specifically comprises the following steps: respectively calculating all possible combinations when the sum of current values of 1, 2,..., n nodes in the maximum-difference node set is equal to the current value of the sub-node, and taking one node in the minimum-difference node set as a sub-node, and recording each possible combination as a leaf node set; respectively taking the other node in the minimum-difference node set as a sub-node, and repeating the above process until the calculation of all nodes in the minimum-difference node set is completed to obtain all leaf node sets.

4. The low-voltage area three-level topology generation method of claim 1, wherein, The most-node sub-node set is the only sub-node set with the most nodes.

5. A low-voltage district three-level topology generation device, characterized by, The method comprises the following steps: a current collection module configured to obtain current values of all circuit breakers at a current time node; a current sorting module configured to sort the obtained current values of the circuit breakers in descending order; a sub-node generation module configured to take the circuit breaker with the largest current value as a root node, and calculate all possible combinations when the sum of current values of the remaining circuit breakers is equal to the current value of the root node circuit breaker, and record each possible combination as a sub-node set; a topology structure generation module configured to filter out a sub-node set with the least nodes from all sub-node sets to form a least-node sub-node set; Take one of the least child node sets as a child node, calculate all the topology relations, specifically: Filter the child node set with the most nodes from all child node sets to obtain the most child node set; Subtract each set in the least child node set from the most child node set to obtain the minimum difference node set and the maximum difference node set, specifically: Subtract each set in the least child node set from the most child node set to obtain the minimum difference node set, wherein the least child node set is a child node set with the same number of nodes and the least number of nodes; Subtract each set in the least child node set from the most child node set to obtain the maximum difference node set; Take each node in the minimum difference node set as a child node, calculate all the leaf node sets when the sum of the node circuit breakers in the maximum difference node set is equal to the current value of the child node; When all the nodes in the minimum difference node set are calculated, all the topology relations are obtained; Until all the sets in the least child node set are calculated, the final topology relations and the corresponding topology relation probabilities are obtained.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the steps in the low-voltage district three-level topology structure generation method of any one of claims 1-4.

7. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the steps in the low-voltage district three-level topology structure generation method of any one of claims 1-4.

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