A memory translation method, system, device, and storage medium
By mapping the memory to BSRAM in the FPGA design based on factors such as the number of read/write ports and data width, the resource occupation and power consumption problems caused by improper memory mapping are solved, and the memory footprint is optimized and power consumption is reduced.
Patent Information
- Application Number
- CN202210763626.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-30
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2042-06-30
AI Technical Summary
In FPGA design, slight differences in the BSRAM memory models of FPGA chips from different manufacturers or models can lead to improper memory mapping, resulting in the consumption of excessive memory and logic resources, and affecting chip area and power consumption.
By acquiring the initial netlist, traversing and identifying the memories that can be mapped to BSRAM, and mapping them to the corresponding type and number of BSRAMs based on the number of read/write ports, data width, and address width, or mapping memories that cannot be mapped to BSRAM to SRAM or registers, the use of memory is optimized.
This effectively reduces the area occupied by memory in the chip, improves the efficiency of layout and routing, and reduces power consumption.
Smart Images
Figure CN115169270B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design, and more specifically to a memory conversion method, system, device, and storage medium. Background Technology
[0002] With the development of modern EDA technology, programmable logic devices (FPGAs) have been widely used in digital signal processing, network communication, industrial control, and computer-related products. FPGA technology has seen increasingly widespread application in electronic design in recent years. The programmability of FPGA hardware logic, large capacity, high speed, and embedded memory arrays make it particularly suitable for applications such as high-speed data acquisition, complex control logic, and precise timing logic. Memory is an indispensable module in digital application systems.
[0003] Because the BSRAM memory models of FPGA chips from different manufacturers or of different models are slightly different, users use logic languages to describe the memory in FPGA design to adapt to different FPGA models, and map it to different memories during the synthesis process.
[0004] When memory is present in the design, the memory IP core is directly used to map the memory after synthesis. If the mapping is improper, or if the address width or data width of the memory exceeds the input width of the memory IP core, the synthesis process will consume more memory resources or generate more logic resources and routing resources, affecting subsequent placement and routing.
[0005] When inappropriate memory or logic resources are used to represent memory, the circuit becomes more complex, the chip occupies a larger area, affecting layout and routing, and power consumption also increases. Summary of the Invention
[0006] In view of this, in order to overcome at least one aspect of the above problems, embodiments of the present invention propose a memory conversion method, comprising the following steps:
[0007] Obtain the initial netlist;
[0008] Traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM;
[0009] Obtain the number and address size of the read / write ports for each first memory and each second memory;
[0010] Map each of the first memory to the corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each first memory, or map each of the second memory to the corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each second memory.
[0011] In some embodiments, traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM further includes:
[0012] In response to the fact that the attribute constraint of the memory in the initial netlist is BSRAM, the memory is determined to be the first memory that can be mapped to BSRAM;
[0013] If a memory in the initial netlist has no attribute constraints and its data width or address width is greater than a preset value, then the memory is determined to be a second memory that can be mapped to BSRAM.
[0014] In some embodiments, it also includes:
[0015] Obtain the attribute constraints of other memories in the initial netlist that cannot be mapped to BSRAM;
[0016] In response to the property constraint of the other memory being SRAM, it is mapped to SRAM;
[0017] In response to the attribute constraint of the other memory being a register, it is mapped to a register.
[0018] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0019] Since the first memory has only one read port, it is mapped as a ROM;
[0020] Since the second memory has only one read port, it is mapped as a ROM.
[0021] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0022] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP;
[0023] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP.
[0024] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0025] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP;
[0026] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP.
[0027] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0028] In response to the first memory having one read port and two write ports and the address of the read port being the same as that of one of the write ports, or the first memory having two read ports and one write port and the address of the write port being the same as that of one of the read ports, or the first memory having two read ports and two write ports and the address of each of the two write ports being the same as that of one of the read ports, it is mapped to DP;
[0029] In response to the second memory having one read port and two write ports and the read port having the same address as one of the write ports, or the second memory having two read ports and one write port and the write port having the same address as one of the read ports, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports respectively, it is mapped to DP.
[0030] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0031] In response to the fact that the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the first memory, the first memory is directly mapped to BSRAM;
[0032] Since the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the second memory, the second memory is directly mapped to BSRAM.
[0033] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0034] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the first memory and the data width is less than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the first memory.
[0035] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the second memory and the data width is less than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the second memory.
[0036] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0037] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is larger than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0038] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is larger than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0039] In some embodiments, multiple BSRAMs are enabled via a number of preset address bits to determine the BSRAMs used, and the output of data is selected via the number of preset address bits, further including:
[0040] The logic circuit is used to perform operations on the several preset address bits to determine the BSRAM to be used;
[0041] The output of data is selected using a multi-level MUX, wherein the preset address bits are respectively used as the turn-on signal of each MUX in the multi-level MUX.
[0042] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0043] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is smaller than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the first memory.
[0044] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is smaller than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the second memory.
[0045] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a memory conversion system, comprising:
[0046] The first acquisition module is configured to acquire the initial netlist;
[0047] The traversal module is configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM;
[0048] The second acquisition module is configured to acquire the number and address size of the read / write ports of each first memory and each second memory;
[0049] The mapping module is configured to map each of the first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each first memory, or to map each of the second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each second memory.
[0050] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer device, comprising:
[0051] At least one processor; and
[0052] A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of any of the memory switching methods described above.
[0053] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of any of the memory conversion methods described above.
[0054] The present invention has one of the following beneficial technical effects: the solution proposed in the present invention can be applied in chip design or FPGA design. When the design includes memory for logical representation, the memory can be replaced by one or more BSRAMs, which can effectively reduce the chip area occupied by the memory. Attached Figure Description
[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0056] Figure 1 A schematic flowchart of a memory conversion method provided for an embodiment of the present invention;
[0057] Figure 2 A schematic diagram of the mapping process provided for an embodiment of the present invention when d0 <= d1 and a0 <= a1;
[0058] Figure 3 A schematic diagram of the mapping process provided for an embodiment of the present invention when d0>d1 and a0<=a1;
[0059] Figure 4A schematic diagram of the mapping process provided for an embodiment of the present invention when d0 <= d1 and a0 > a1;
[0060] Figure 5 A schematic diagram of the memory conversion system provided for an embodiment of the present invention;
[0061] Figure 6 A schematic diagram of the structure of a computer device provided for an embodiment of the present invention;
[0062] Figure 7 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.
[0064] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.
[0065] In embodiments of the present invention, RAM stands for Random Access Memory; BSRAM stands for Block SRAM; ROM stands for Read Only Memory; SP stands for Single Port RAM; SDP stands for Simple Dual Port RAM; and DP stands for Dual Port RAM.
[0066] According to one aspect of the present invention, embodiments of the present invention provide a memory switching method, such as... Figure 1 As shown, it may include the following steps:
[0067] S1, Obtain the initial netlist;
[0068] S2, Traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM;
[0069] S3, obtain the number and address size of the read / write ports of each first memory and each second memory;
[0070] S4, map each of the first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each first memory, or map each of the second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each second memory.
[0071] The solution proposed in this invention can be applied in chip design or FPGA design. When the design includes memory for logical representation, the memory can be replaced by one or more BSRAMs, which can effectively reduce the chip area occupied by the memory.
[0072] In some embodiments, traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM further includes:
[0073] In response to the fact that the attribute constraint of the memory in the initial netlist is BSRAM, the memory is determined to be the first memory that can be mapped to BSRAM;
[0074] If a memory in the initial netlist has no attribute constraints and its data width or address width is greater than a preset value, then the memory is determined to be a second memory that can be mapped to BSRAM.
[0075] In some embodiments, it also includes:
[0076] Obtain the attribute constraints of other memories in the initial netlist that cannot be mapped to BSRAM;
[0077] In response to the property constraint of the other memory being SRAM, it is mapped to SRAM;
[0078] In response to the attribute constraint of the other memory being a register, it is mapped to a register.
[0079] Specifically, BSRAM is divided into Read-Only Memory (ROM), Single-Port RAM (SP), Pseudo-Dual-Port RAM (SDP), and Dual-Port RAM (DP), etc. During the mapping process, the memory is mapped based on the relationship between the number of read / write ports, address width, and data width. For example, if there are attribute constraints during the mapping process, when the attribute constraint is register, the memory is directly split into register representations; when the attribute constraint is SRAM, the memory is mapped as SRAM; and when the attribute constraint is BSRAM, or the memory size exceeds a certain size and there are no attribute constraints, the memory is mapped as BSRAM.
[0080] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0081] Since the first memory has only one read port, it is mapped as a ROM;
[0082] Since the second memory has only one read port, it is mapped as a ROM.
[0083] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0084] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP;
[0085] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP.
[0086] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0087] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP;
[0088] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP.
[0089] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes:
[0090] In response to the first memory having one read port and two write ports and the address of the read port being the same as that of one of the write ports, or the first memory having two read ports and one write port and the address of the write port being the same as that of one of the read ports, or the first memory having two read ports and two write ports and the address of each of the two write ports being the same as that of one of the read ports, it is mapped to DP;
[0091] In response to the second memory having one read port and two write ports and the read port having the same address as one of the write ports, or the second memory having two read ports and one write port and the write port having the same address as one of the read ports, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports respectively, it is mapped to DP.
[0092] Specifically, when the first or second memory has only one read port, it is mapped as ROM. When the first or second memory has one read port and one write port, and the addresses of the read and write ports are the same, it is mapped as SP. When the first or second memory has one read port and one write port, and the addresses of the read and write ports are different, it is mapped as SDP. When the first or second memory has one read port and two write ports, and the address of the read port is the same as the address of one of the write ports, it is mapped as DP. When the first or second memory has two read ports and one write port, and the address of the write port is the same as the address of one of the read ports, it is mapped as DP. When the first or second memory has two read ports and two write ports, and the addresses of the two write ports are the same as the addresses of the read ports respectively, it is mapped as DP.
[0093] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0094] In response to the fact that the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the first memory, the first memory is directly mapped to BSRAM;
[0095] Since the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the second memory, the second memory is directly mapped to BSRAM.
[0096] Specifically, assuming the data width of the first or second memory is d0 and the address width is a0, the data width of the BSRAM to be mapped is d1 and the address width is a1.
[0097] like Figure 2 As shown, when d0 <= d1 and a0 <= a1, that is, the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the first memory or the second memory, the BSRAM element is directly used for replacement.
[0098] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0099] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the first memory and the data width is less than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the first memory.
[0100] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the second memory and the data width is less than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the second memory.
[0101] Specifically, similarly, assume the data width of the first or second memory is d0 and the address width is a0, and the data width of the BSRAM to be mapped is d1 and the address width is a1. When d0 > d1 and a0 <= a1, that is, the address width of the BSRAM to be mapped is greater than the address width of the first or second memory and the data width is less than the data width of the first or second memory, multiple BSRAMs are used for mapping, and the sum of the data widths of the multiple BSRAMs is greater than the data width of the first or second memory.
[0102] For example, such as Figure 3 As shown, when d0 > d1 and d0 <= 2d1, two BSRAMs can be used for data expansion. BSRAM0 can output data from d0-1 to d, while BSRAM1 can output data from d1-1 to 0.
[0103] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0104] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is larger than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0105] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is larger than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0106] In some embodiments, multiple BSRAMs are enabled via a number of preset address bits to determine the BSRAMs used, and the output of data is selected via the number of preset address bits, further including:
[0107] The logic circuit is used to perform operations on the several preset address bits to determine the BSRAM to be used;
[0108] The output of data is selected using a multi-level MUX, wherein the preset address bits are respectively used as the turn-on signal of each MUX in the multi-level MUX.
[0109] Specifically, similarly, assume the data width of the first or second memory is d0 and the address width is a0, and the data width of the BSRAM to be mapped is d1 and the address width is a1. When d0 <= d1 and a0 > a1, that is, the address width of the BSRAM to be mapped is less than the address width of the first or second memory, and the data width is greater than the data width of the first or second memory, multiple BSRAMs are used for mapping. Simultaneously, several preset address bits can be used to enable and determine the BSRAM to be used, and several preset address bits can also be used to select the data output.
[0110] For example, such as Figure 4As shown, when a0 = 3 and a1 = 2 (a0 = a1 + 1), the number of multiple BSRAMs is 2. The address bits of the BSRAM to be mapped are bit 0 and bit 1, respectively, while the address bits of the first memory or the second memory are bit 0, bit 1, and bit 2, respectively. Therefore, the address bits of the first memory or the second memory are one more than the address bits of the BSRAM to be mapped, and the value (0 or 1) of this address bit (bit 2, i.e., bit a1 or bit a0-1) determines which BSRAM is enabled. The MUX is also turned on through this address bit.
[0111] Similarly, when a0 = 3 and a1 = 1 (a0 = a1 + 2), the number of BSRAMs is 4. The address bits of the BSRAM to be mapped are bit 0, while the address bits of the first or second memory are bit 0, bit 1, and bit 2, respectively. Therefore, the address bits of the first or second memory are two more than the address bits of the BSRAM to be mapped, and the value (00, 01, 10, 11) of these two address bits (bit 2, bit 1, i.e., bit a0-1 and bit a0-2) determines which BSRAM is enabled. The enable signal of each MUX in the two-stage MUX (four-to-one) is also determined by the value (00, 01, 10, 11) of these two address bits (bit 2, bit 1, i.e., bit a0-1 and bit a0-2).
[0112] Therefore, when the address width of the BSRAM to be mapped is less than the address width of the first memory or the second memory, the number of multiple BSRAMs is 2. a0-a1 The preset address bits are (bit a0-1, bit a0-2, ..., bit a1).
[0113] In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes:
[0114] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is smaller than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the first memory.
[0115] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is smaller than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the second memory.
[0116] Specifically, when the address width of the BSRAM to be mapped is smaller than the address width of the first memory or the second memory, and the data width is smaller than the data width of the first memory or the second memory, the first memory or the second memory can be mapped into multiple BSRAMs first, and then each of the multiple BSRAMs can be mapped into multiple BSRAMs again. Figure 4 Each BSRAM in the middle is again based on Figure 3 The rules shown are mapped to multiple BSRAMs.
[0117] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a memory conversion system 400, such as... Figure 5 As shown, it includes:
[0118] The first acquisition module 401 is configured to acquire the initial netlist;
[0119] Traversal module 402 is configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM;
[0120] The second acquisition module 403 is configured to acquire the number and address size of the read / write ports of each first memory and each second memory;
[0121] The mapping module 404 is configured to map each of the first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each first memory, or to map each of the second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each second memory.
[0122] In some embodiments, the traversal module 402 is further configured to:
[0123] In response to the fact that the attribute constraint of the memory in the initial netlist is BSRAM, the memory is determined to be the first memory that can be mapped to BSRAM;
[0124] If a memory in the initial netlist has no attribute constraints and its size is greater than a preset value, then the memory is determined to be a second memory that can be mapped to BSRAM.
[0125] In some embodiments, a third acquisition module is also included, configured as follows:
[0126] Obtain the attribute constraints of other memories in the initial netlist that cannot be mapped to BSRAM;
[0127] In response to the property constraint of the other memory being SRAM, it is mapped to SRAM;
[0128] In response to the attribute constraint of the other memory being a register, it is mapped to a register.
[0129] In some embodiments, the mapping module 404 is further configured to:
[0130] Since the first memory has only one read port, it is mapped as a ROM;
[0131] Since the second memory has only one read port, it is mapped as a ROM.
[0132] In some embodiments, the mapping module 404 is further configured to:
[0133] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP;
[0134] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP.
[0135] In some embodiments, the mapping module 404 is further configured to:
[0136] In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP;
[0137] In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP.
[0138] In some embodiments, the mapping module 404 is further configured to:
[0139] In response to the first memory having one read port and two write ports and the address of the read port being the same as that of one of the write ports, or the first memory having two read ports and one write port and the address of the write port being the same as that of one of the read ports, or the first memory having two read ports and two write ports and the address of each of the two write ports being the same as that of one of the read ports, it is mapped to DP;
[0140] In response to the second memory having one read port and two write ports and the read port having the same address as one of the write ports, or the second memory having two read ports and one write port and the write port having the same address as one of the read ports, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports respectively, it is mapped to DP.
[0141] In some embodiments, the mapping module 404 is further configured to:
[0142] In response to the fact that the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the first memory, the first memory is directly mapped to BSRAM;
[0143] Since the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the second memory, the second memory is directly mapped to BSRAM.
[0144] In some embodiments, mapping each of the first memory or the second memory to a corresponding number of BSRAMs based on the data width and address width of each first memory or each second memory further includes:
[0145] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the first memory and the data width is less than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the first memory.
[0146] In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the second memory and the data width is less than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the second memory.
[0147] In some embodiments, the mapping module 404 is further configured to:
[0148] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is larger than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0149] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is larger than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
[0150] In some embodiments, the mapping module 404 is further configured to:
[0151] The logic circuit is used to perform operations on the several preset address bits to determine the BSRAM to be used;
[0152] The output of data is selected using a multi-level MUX, wherein the preset address bits are respectively used as the turn-on signal of each MUX in the multi-level MUX.
[0153] In some embodiments, the mapping module 404 is further configured to:
[0154] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is smaller than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the first memory.
[0155] In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is smaller than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the second memory.
[0156] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 6 As shown, embodiments of the present invention also provide a computer device 501, comprising:
[0157] At least one processor 520; and
[0158] The memory 510 stores a computer program 511 that can be run on the processor. When the processor 520 executes the program, it performs the steps of any of the memory switching methods described above.
[0159] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 7 As shown, embodiments of the present invention also provide a computer-readable storage medium 601, which stores a computer program 610. When the computer program 610 is executed by a processor, it performs the steps of any of the memory conversion methods described above.
[0160] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods.
[0161] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.
[0162] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.
[0163] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.
[0164] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.
[0165] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0166] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0167] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.
Claims
1. A memory conversion method, characterized in that, Includes the following steps: Obtain the initial netlist; Traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM; Obtain the number and address size of the read / write ports for each first memory and each second memory; Map each of the first memory to the corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width; or map each of the second memory to the corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width. Mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes: In response to the first memory having one read port and two write ports and the address of the read port being the same as that of one of the write ports, or the first memory having two read ports and one write port and the address of the write port being the same as that of one of the read ports, or the first memory having two read ports and two write ports and the address of each of the two write ports being the same as that of one of the read ports, it is mapped to DP; In response to the second memory having one read port and two write ports and the read port having the same address as one of the write ports, or the second memory having two read ports and one write port and the write port having the same address as one of the read ports, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports respectively, it is mapped to DP.
2. The method as described in claim 1, characterized in that, Traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM, further includes: In response to the fact that the attribute constraint of the memory in the initial netlist is BSRAM, the memory is determined to be the first memory that can be mapped to BSRAM; If a memory in the initial netlist has no attribute constraints and its data width or address width is greater than a preset value, then the memory is determined to be a second memory that can be mapped to BSRAM.
3. The method as described in claim 1, characterized in that, Also includes: Obtain the attribute constraints of other memories in the initial netlist that cannot be mapped to BSRAM; In response to the property constraint of the other memory being SRAM, it is mapped to SRAM; In response to the attribute constraint of the other memory being a register, it is mapped to a register.
4. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes: Since the first memory has only one read port, it is mapped as a ROM; Since the second memory has only one read port, it is mapped as a ROM.
5. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes: In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP; In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are the same, it is mapped to SP.
6. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, further includes: In response to the fact that the first memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP; In response to the fact that the second memory has a read port and a write port and the addresses of the read port and the write port are different, it is mapped to an SDP.
7. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes: In response to the fact that the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the first memory, the first memory is directly mapped to BSRAM; Since the address width and data width of the BSRAM to be mapped are both greater than the address width and data width of the second memory, the second memory is directly mapped to BSRAM.
8. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes: In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the first memory and the data width is less than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the first memory. In response to the fact that the address width of the BSRAM to be mapped is greater than the address width of the second memory and the data width is less than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the sum of the data widths of the multiple BSRAMs is greater than the data width of the second memory.
9. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes: In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is larger than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits. In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is larger than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and the output of data is selected by a number of preset address bits.
10. The method as described in claim 9, characterized in that, Multiple BSRAMs are enabled via several preset address bits to determine the BSRAM being used, and the data output is selected via several preset address bits, further including: The logic circuit is used to perform operations on the several preset address bits to determine the BSRAM to be used; The output of data is selected using a multi-level MUX, wherein the preset address bits are respectively used as the turn-on signal of each MUX in the multi-level MUX.
11. The method as described in claim 1, characterized in that, Mapping each first memory to a corresponding type and number of BSRAMs based on its data width and address width, or mapping each second memory to a corresponding type and number of BSRAMs based on its data width and address width, further includes: In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the first memory and the data width is smaller than the data width of the first memory, the first memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the first memory. In response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory and the data width is smaller than the data width of the second memory, the second memory is mapped into multiple BSRAMs, wherein the multiple BSRAMs are enabled by several preset address bits to determine the BSRAM to be used, and the output of data is selected by several preset address bits. Each of the mapped BSRAMs is then mapped into multiple BSRAMs again, wherein the sum of the data widths of the multiple BSRAMs obtained by remapping each BSRAM is greater than the data width of the second memory.
12. A memory conversion system, characterized in that, include: The first acquisition module is configured to acquire the initial netlist; The traversal module is configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM; The second acquisition module is configured to acquire the number and address size of the read / write ports of each first memory and each second memory; The mapping module is configured to map each of the first memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each first memory, or to map each of the second memory to a corresponding type and number of BSRAMs based on the number of read / write ports, data width, and address width of each second memory. The mapping module is also configured as follows: In response to the first memory having one read port and two write ports and the address of the read port being the same as that of one of the write ports, or the first memory having two read ports and one write port and the address of the write port being the same as that of one of the read ports, or the first memory having two read ports and two write ports and the address of each of the two write ports being the same as that of one of the read ports, it is mapped to DP; In response to the second memory having one read port and two write ports and the read port having the same address as one of the write ports, or the second memory having two read ports and one write port and the write port having the same address as one of the read ports, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports respectively, it is mapped to DP.
13. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program and performs the steps of the method as described in any one of claims 1-11.
14. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-11.
Citation Information
Patent Citations
Multi-thread comprehensive method and device
CN112580286A
Multiplier conversion method, system, equipment and medium
CN114115804A