Data processing system based on multiple working modes and low resource utilization

Abstract

This data processing system, based on a multi-mode, low-resource-occupancy approach, relates to the field of CMOS detector application technology. It addresses the problem of excessive logic resource consumption and high resource occupancy in existing linear CMOS detectors during high line frequency operation. The system uses only one write enable and write address for all full-spectral image data; a separate write enable and write address is used for multispectral bands; corresponding multiplication operations are implemented using multiplier resources; and the cached data address regions are arranged in a continuously increasing manner instead of leaving gaps, significantly reducing logic resource usage. Furthermore, the starting address of each line's write operation is implemented using an integrated multiplier instead of logic resources, further reducing resource occupancy.

Description

TECHNICAL FIELD

[0001] The application relates to a multi-working-mode low-resource-occupancy data processing system, in particular to a multi-working-mode low-resource-occupancy data processing system based on aerospace application. BACKGROUND

[0002] In order to realize high line frequency operation, a linear array CMOS detector can split image data into multiple channels and output in parallel. Directly using a single RAM for time-sharing writing and reading of multi-channel image data, the clock frequency of writing and reading is several times or even several tens or hundreds of times of the pixel clock of the detector, which may exceed the maximum frequency allowed by the device.

[0003] At present, a relatively easy method is to write data of each channel into a RAM in parallel, and output in time according to the transmission sequence of data during reading. If independent write enable and write address are used for each RAM, more logic resources will be occupied, and the problem of excessively high resource occupancy rate may occur. SUMMARY

[0004] The application provides a multi-working-mode low-resource-occupancy data processing system to solve the problems of occupying more logic resources and causing excessively high resource occupancy rate during the realization of high line frequency operation of the existing linear array CMOS detector.

[0005] The multi-working-mode low-resource-occupancy data processing system comprises a detector, a timing driver and a timing driving module. The timing driving module outputs a driving control timing signal, which is sent to the detector after passing through the timing driver. The system further comprises a data training module, a panchromatic data selection module, a multispectral data selection module, a panchromatic buffer RAM and four multispectral buffer RAMs.

[0006] The timing driving module simultaneously outputs a panchromatic data valid signal qs_lval and a multispectral data valid signal mul_lval, which are transmitted to the panchromatic data selection module and the multispectral data selection module respectively.

[0007] The detector outputs serial image data, which is simultaneously output as parallel panchromatic image data and multispectral image data by the data training module, and is sent to the panchromatic data selection module and the multispectral data selection module respectively.

[0008] The panchromatic data selection module generates new panchromatic data qs_data and a write enable signal qs_ram_wen according to the input panchromatic data valid signal qs_lval and the panchromatic image data, and writes the data into the panchromatic buffer RAM.

[0009] The multispectral data selection module generates new write enable signals and multispectral RAM data according to the input multispectral data valid signal mul_lval and multispectral image data, and writes the data into four multispectral buffer RAMs; data is read out from the panchromatic buffer RAM, the multispectral B1 buffer RAM, the multispectral B2 buffer RAM, the multispectral B3 buffer RAM and the multispectral B4 buffer RAM in time and transmitted to the data transmission 2711 interface;

[0010] The detector has a super-resolution mode and a push-broom mode, and the ratio of the line period length of the multispectral to the line period length of the panchromatic in the super-resolution mode is equal to the number of multispectral bands; and the ratio of the line period length of the multispectral to the line period length of the panchromatic in the push-broom mode is equal to half of the number of multispectral bands.

[0011] The present application has the following advantages:

[0012] The processing system has the following advantages: all the write enable signals of the panchromatic channels are the same, which are the delay of the panchromatic synchronization signal and the length is the number m of the output valid data of each line; all the panchromatic channels use the same write address; and the logical resource occupation is close to one-tenth.

[0013] The processing system has the following advantages: all the write enable signals of the multispectral channels are the same, which are the delay of the multispectral synchronization signal and the length is the number n of the output valid data of each line; all the multispectral channels use the same write address; and the logical resource occupation is close to one-tenth.

[0014] The processing system has the following advantages: for the first address of the write operation of each line, an integrated multiplier is used instead of logical resources, further reducing the resource occupation rate. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The present application discloses a principle diagram of the data processing system based on the low resource occupation rate of multiple working modes. DETAILED DESCRIPTION

[0016] Combination Figure 1 The data processing system based on the low resource occupation rate of multiple working modes includes a data transmission 2711 interface, a detector, a timing driver, a timing driving module, a data training module, a panchromatic data selection module, a multispectral data selection module, a panchromatic buffer RAM, a multispectral B1 buffer RAM, a multispectral B2 buffer RAM, a multispectral B3 buffer RAM and a multispectral B4 buffer RAM. The timing driving module outputs a driving control timing signal, which is output to the detector after passing through the timing driver.

[0017] The timing drive module simultaneously outputs the panchromatic data valid signal qs_lval and the multispectral data valid signal mul_lval, which are respectively sent to the panchromatic data selection module and the multispectral data selection module. The serial image data output by the detector is simultaneously output as parallel panchromatic image data and multispectral image data by the data training module, which are respectively sent to the panchromatic data selection module and the multispectral data selection module.

[0018] The panchromatic data selection module generates new data qs_data and write enable signal qs_ram_wen based on the input data valid signal qs_lval and image data data_parallel_out(41to 0), and writes them into the panchromatic buffer RAM;

[0019] The multispectral data selection module generates four new multispectral RAM data mul_data_b1, mul_data_b2, mul_data_b3, and mul_data_b4 and a write enable signal mul_ram_wen based on the input data valid signal mul_lval and image data data_parallel_out(53 to 42), and writes them into the four multispectral buffer RAMs. The full-color buffer RAM, multi-spectral B1 buffer RAM, multi-spectral B2 buffer RAM, multi-spectral B3 buffer RAM and multi-spectral B4 buffer RAM are time-division controlled by the read enable signals ram_ren_top_5m, ram_ren_bot_5m(0), ram_ren_bot_5m(1), ram_ren_bot_5m(2), ram_ren_bot_5m(3) and the read address signals ram_raddr_top_5m, ram_raddr_bot_5m, read out data ram_rdata_top_5m, ram_rdata_bot_5mb1, ram_rdata_bot_5mb2, ram_rdata_bot_5mb3 and ram_rdata_bot_5mb4 and send them to the data transmission 2711 interface.

[0020] The detector has two operating modes: super-resolution and pushbroom. In super-resolution mode, the ratio of the line period length of the multispectral spectrum to the line period length of the panchromatic spectrum is equal to the number of multispectral bands; in pushbroom mode, the ratio of the line period length of the multispectral spectrum to the line period length of the panchromatic spectrum is equal to half the number of multispectral bands.

[0021]

[0022] In the formula, mul_lenth tuisao mul_lenth is the row period length of the multispectral spectrum in pushbroom mode. chaofenqs_lenth is the line period length of the multispectral spectrum in super-resolution mode, qs_lenth is the line period length of the panchromatic spectrum, and p is the number of multispectral bands.

[0023] In this implementation, the write enable signal for all panchromatic channels is the same, which is the delay of the panchromatic synchronization signal, and its length is the number of valid data (m) per line. All panchromatic channels use the same write address, and the number of loop rows for the write address is twice the ratio of the multispectral and panchromatic line periods. The first write address corresponding to the rising edge of the write enable for each line is the product of the number of loop rows and the number of pixels per line, incremented by 1 at the rising edge of each pixel clock, and stops incrementing after the write enable goes low. That is, in super-resolution mode, the number of loop write operations is 2p rows, and the write operation address range is 0 to (2pm-1); in pushbroom mode, the number of loop write operations is p rows, and the write operation address range is 0 to (pm-1).

[0024] In this implementation, the write enable signal for all multispectral channels is the same, which is the delay of the multispectral synchronization signal, and its length is n, the number of valid data outputs per line. All multispectral channels use the same write address, and the write address loop has 2 rows. The first write address corresponding to the rising edge of the write enable for each row is the product of the loop number and the number of pixels per row. This increments by 1 at the rising edge of each pixel clock cycle and stops after the write enable goes low. The write operation address range is 0 to (2^n - 1).

[0025] In this embodiment, the number β of panchromatic buffer RAMs is the same as the number β of panchromatic channels. The bit width of the write operation of the buffer RAM is the same as the bit width of the data. The ratio of the depth of the panchromatic data to the number of image data per row is twice the number of spectral bands, which is 2pm; the depth of the multispectral data is twice the number of image data per row, which is 2n.

[0026] In this embodiment, the read data bit width of the full color is twice the write data bit width r; in push-sweep mode, the write grayscale values ​​of two adjacent pixels are added together and then divided by 2; in super-resolution mode, the high and low bits are extracted and output in a time-division manner.

[0027]

[0028] In the formula dn o DN is the output value; r is the bit width of the write operation, equal to the number of valid data entries per channel; dn i This is the parallel data read with a bit width of 2r; dn 2i and dn 2i+1 For writing parallel data with a bit width of r; dn 2i ((r-1)downto 1) represents parallel data dn with a bit width of r. 2i The high (r-1) bits, dn i((2r-1)downto r) represents parallel data dn with a bit width of 2r. i The high rbit in

[0029] In this embodiment, the variation pattern of the full-color read address is as follows:

[0030] For a 2η detector, the numbering is from 1 to 2η, where the numbering is 1, 3, 5, ... 2η-1 for odd-numbered detectors and the numbering is 2, 4, 6, ... 2η for even-numbered detectors.

[0031] In super-resolution mode, the read address only begins to change after the falling edge of the valid signal for p rows of input data is detected. After the read address begins to change, the number of rows that are cyclically changed is 2p rows.

[0032] In push-broom mode, the read address only begins to change after the falling edge of the valid signal for line p / 2 of the input data is detected. After the read address begins to change, the number of lines that are cycled through is p.

[0033] In even-slice super-resolution mode: the address changes once every two data transmission clock cycles (panchromatic and multispectral buffer RAM); the address of channel 1 is... The addresses of the panchromatic channels 2 to (β-1) of the odd-numbered slice detector increment from 0 until... The address of the last channel β of the odd-numbered pixel detector is 0-(λ-1). The number of valid data read per line is 4λ+(β-2)×m, where λ is the number of pixels transmitted by channel 1.

[0034] In odd-slice super-resolution mode: the address changes once every two data transmission clock cycles; the address of full-color channel 1 is... The addresses of the even-numbered plate detectors' panchromatic channels 2 to (β-1) are from... The value decreases gradually until it reaches 0; the address of the last channel β of the panchromatic detector for even-numbered plates is (λ-1)-0. The number of valid data read from each line is 4λ+(β-2)×m.

[0035] In even-number chip pushbroom mode: the address changes once for each data transmission clock cycle; the address of channel 1 is... The addresses of the panchromatic channels 2 to (β-1) of the odd-numbered slice detector increment from 0 until... The address of the last channel β of the odd-numbered plate detector is 0-(λ-1). The number of valid data read per line is...

[0036] In odd-chip pushbroom mode: the address changes once for each data transmission clock cycle; the address of full-color channel 1 is... The addresses of the even-numbered plate detectors' panchromatic channels 2 to (β-1) are from... The value begins to decrease and continues until it reaches 0; the address of the last channel β of the panchromatic detector for even-numbered plates is (λ-1)-0. The number of valid data read from each line is...

[0037] In this embodiment, the multispectral read address changes as follows: the read address only begins to change after the falling edge of a valid signal for a line of input data is detected.

[0038] The even-numbered chips change their address every four data transmission clock cycles; the read address of channel 1 of the odd-numbered chip detector multispectral system is (α-λ / 2+1)~α; the read addresses of channels 2~(δ-1) of the odd-numbered chip detector multispectral system increase from 0 to (m-1); the read address of the last channel of the odd-numbered chip detector multispectral system, channel δ, is 0-(λ / 2-1).

[0039] The address of odd-numbered chips changes every four data transmission clock cycles; the read address of channel 1 of the multispectral detector of odd-numbered chips is α~(α-λ / 2+1); the read address of channels 2~(δ-1) of the multispectral detector of even-numbered chips decreases from (m-1) to 0; the read address of the last channel of the multispectral detector of even-numbered chips, i.e., channel δ, is (λ / 2-1)-0.

[0040] In the formula, α represents the position of the last valid data in the first output row; the number of valid data read per row is...

[0041] In this embodiment, the read data bit width of the multispectral data is the same as the write data bit width, and the data read directly from the buffer RAM is used.

[0042] The starting address of each write operation is implemented using an integrated multiplier instead of logical resources.

[0043] The timing driver module, data training module, panchromatic data selection module, multispectral data selection module, panchromatic buffer RAM, multispectral B1 buffer RAM, multispectral B2 buffer RAM, multispectral B3 buffer RAM, and multispectral B4 buffer RAM described in this embodiment use Xilinx's XC6VLX240T-2FFG1156C device; the data transmission 2711 interface uses TI's TLK2711; the CMOS detector uses Chenxin's TDI CMOS detector; and the timing driver uses the JSR164245 chip.

Claims

1. A data processing system based on multi-working mode and low resource occupation, the processing system comprising a detector, a time sequence driver and a time sequence driving module; the time sequence driving module outputs a driving control time sequence signal through the time sequence driver, and then outputs a driving control signal into the detector; characterized in that: The data training module, the panchromatic data selection module, the multispectral data selection module, the panchromatic buffer RAM and the four multispectral buffer RAMs are also included. ​ The timing driving module simultaneously outputs the panchromatic data valid signal qs_lval and the multispectral data valid signal mul_lval, which are transmitted to the panchromatic data selection module and the multispectral data selection module respectively. The detector outputs serial image data, which are simultaneously outputted by the data training module as parallel panchromatic image data and multispectral image data, and are transmitted to the panchromatic data selection module and the multispectral data selection module respectively. The panchromatic data selection module generates new panchromatic data qs_data and a write enable signal qs_ram_wen according to the inputted panchromatic data valid signal qs_lval and the panchromatic image data, and writes them into the panchromatic buffer RAM. The multispectral data selection module generates new write enable signals and data in the four multispectral buffer RAMs according to the inputted multispectral data valid signal mul_lval and the multispectral image data, and writes them into the four multispectral buffer RAMs correspondingly. Data are read from the panchromatic buffer RAM, the multispectral B1 buffer RAM, the multispectral B2 buffer RAM, the multispectral B3 buffer RAM and the multispectral B4 buffer RAM in time division, and are transmitted to the data transmission 2711 interface. The write enable signals of all panchromatic channels are the same, which are the delay of the panchromatic synchronization signal. The write addresses of all panchromatic channels are the same, and the cycle line number of the write address is twice the ratio of the multispectral line period to the panchromatic line period. The first write address of each line write address corresponding to the rising edge of the write enable signal is the product of the cycle line number and the pixel number of each line. The write enable signals of all multispectral channels are the same, which are the delay of the multispectral synchronization signal. The same write address is used in all multispectral channels, and the first write address of each line write address corresponding to the rising edge of the write enable signal is the product of the cycle line number and the pixel number of each line. The detector has a super-resolution mode and a push-broom mode, and the ratio of the multispectral line period length to the panchromatic line period length in the super-resolution mode is equal to the multispectral spectral band number. The ratio of the multispectral line period length to the panchromatic line period length in the push-broom mode is equal to half of the multispectral spectral band number. Full color read data bit width is twice of write data bit width ; in push scan mode, the write gray value of adjacent two pixels is added and divided by 2; in super resolution mode, high bit and low bit are output respectively in time division The integrated multiplier is used for the first address of the write operation of each line.

2. The multi-work mode based low resource occupancy data processing system according to claim 1, wherein: The number of the full-color buffer RAMs The bit width of the write operation of the full-color buffer RAM is the same as the bit width of each row of data, and the ratio of the depth of the full-color data to the number of each row of image data is 2 times the number of spectral bands. The depth of the multi-spectral data is 2 times the number of each row of image data.

3. The multi-work mode based low resource occupancy data processing system of claim 2, wherein: The change rule of the panchromatic read address is: detecting After the falling edge of the row input data valid signal, the read address starts to change. After the read address starts to change, the number of rows of the cyclic change is rows.

4. The multi-work mode based low resource occupancy data processing system of claim 3, wherein: The change rule of the panchromatic read address is: The address of the full-color channel 1 of the detector is - The address of the channel 2 ~ increases from 0 to ; the address of the last full-color channel is 0- ; m is the number of effective data outputted by each row of the full-color channel; is the number of pixels transmitted by the channel 1.

5. The multi-work mode based low resource occupancy data processing system of claim 1, wherein: The read data bit width of the multispectral is the same as the write data bit width, and the data read from the buffer RAM is directly used.

6. The multi-work mode based low resource occupancy data processing system according to claim 1, wherein: The change rule of the multispectral read address is: The read address of the 1 channel of the multi-spectrum of the detector is ; the read address of the 2nd channel is increased from 0 to the end of ; the read address of the last channel, i.e. the 3rd channel, is 0- ; in the formula, the position of the last valid data output in the first row is ; the number of valid data read in each row is ; ; ; the position of the last valid data output in the first row is​ m is the number of valid data output per row of the full color channel; the number of pixels transmitted for channel 1.

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