A method for detecting channel mobility and photolithography variation of MOS devices

Abstract

The present disclosure provides a method for detecting channel mobility and photolithography variation of a MOS device, comprising: preparing a first MOS device and a second MOS device; obtaining a difference ΔR1 between the on-resistance R1 of a linear region of the first MOS device and the on-resistance R2 of a linear region of the second MOS device; obtaining M1 based on the number and unit length of first gate trenches and the width of the first gate trenches; and plotting a curve of ΔR1 and M1 to determine the slope K2 and intercept r of the curve. s M2 is obtained based on the capacitance per unit area of ​​the gate electrode contact, the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / second MOS device with the N-drift layer as the channel. The accumulation channel mobility of the MOS device is obtained using K2 and M2. This disclosure effectively avoids the influence of processes such as photolithography and etching on the accuracy of the extracted channel mobility, enriching the detection methods for the channel mobility of MOS devices.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a method for detecting channel mobility and photolithography variation of a MOS device. Background Art

[0002] Silicon carbide (SiC) is currently the fastest-growing wide-bandgap power semiconductor device. Its physical and electrical properties surpass those of traditional silicon, making it a crucial component in clean energy power electronics. Silicon carbide's vertical trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET), with its non-polar channel surface, offers higher mobility and greater cell integration. This makes SiC trench MOSFETs a research hotspot for next-generation low-power electronic devices, promising applications in new energy vehicles, locomotive traction, photovoltaics, and smart grids.

[0003] However, the channel carrier mobility of silicon carbide trench MOSFETs remains difficult to characterize during the actual fabrication process. In traditional planar MOSFET structures, the channel is located on the wafer surface, so the channel mobility can be obtained by designing lateral MOSFET devices with different gate lengths and using data fitting. This becomes very difficult in silicon carbide trench structures, especially since the current silicon carbide MOSFET channel length is submicron (usually around 0.5μm). By increasing the number of photolithography times and etching structures of different depths, or adding ion implantation process technology to design specific structures, the channel mobility of silicon carbide trench MOS devices is evaluated. This method becomes more complicated and is greatly affected by indirect parameter fluctuations. At the same time, the channel mobility of silicon carbide MOS devices gradually decreases with increasing gate voltage, so the mobility obtained by converting using simple mathematical and physical formulas lacks sufficient credibility.

[0004] Therefore, it is very necessary to find a suitable method for detecting the channel mobility of silicon carbide trench structure MOS. Summary of the Invention

[0005] In response to the above-mentioned defects in the prior art, the present disclosure provides a method for detecting the channel mobility and lithography variation of MOS devices. By designing trench MOS unit structures with different numbers and different trench widths, inversion channel devices and accumulation channel devices with different width-to-length ratios are sequentially formed. The channel mobility of the inversion layer and accumulation layer of the silicon carbide trench MOS is evaluated using mathematical analysis, effectively avoiding the influence of line width deviation caused by processes such as lithography and etching on the accuracy of the extracted channel mobility, and effectively evaluating the dual channel mobility of the trench MOS device under different gate voltage conditions, thereby enriching the channel mobility detection methods of silicon carbide MOS devices.

[0006] The present disclosure provides a method for detecting channel mobility and photolithography variation of a MOS device, comprising: preparing a first MOS device and a second MOS device using a MOS device preparation process, wherein n first gate trenches are equidistantly provided on the first MOS device, and the widths W of the n first gate trenches are the same; n second gate trenches are equidistantly provided on the second MOS device, and the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx, ..., W+(n-1)Δx in sequence; obtaining a difference ΔR1 between the on-resistance R1 of a linear region of the first MOS device and the on-resistance R2 of a linear region of the second MOS device; obtaining a difference ΔR1 between the two based on the number, unit length, and width of the first gate trenches / the second gate trenches. n represents the number of first gate trenches / second gate trenches, Δx represents the unit length, and W represents the width of the first gate trench; plot ΔR1 versus M1 to determine the slope K2 and intercept r of the curve. s M2 is obtained according to the capacitance per unit area of ​​the gate electrode contact, the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / second MOS device with the N drift layer as the channel, M2 = C OX (V G -V T2 );C OX represents the capacitance per unit area of ​​the gate electrode contact, V G Represents the voltage applied at the gate electrode contact point, V T2 represents the threshold voltage of the first MOS device / second MOS device with the N drift layer as the channel; through K2 and M2, the accumulation channel mobility of the MOS device is obtained

[0007] Optionally, the value range of W is 1-100 μm, and the value range of the distance between two adjacent first gate trenches is 1-100 μm.

[0008] Optionally, the value range of Δx is 2-50 μm.

[0009] Optionally, the value range of n is 20-100.

[0010] The present disclosure also provides a method for detecting inversion channel mobility of a MOS device, comprising: preparing a first MOS device and a second MOS device using a MOS device preparation process, wherein n first gate trenches are equidistantly provided on the first MOS device, and the n first gate trenches have the same width W; n second gate trenches are equidistantly provided on the second MOS device, and the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx, ..., W+(n-1)Δx, in sequence; obtaining a difference ΔR1 between the on-resistance R1 of a linear region of the first MOS device and the on-resistance R2 of a linear region of the second MOS device; obtaining M1 based on the number of first gate trenches / second gate trenches, a unit length, and the width of the first gate trenches; plotting a curve graph of ΔR1 and M1 to determine a slope K2 of the curve; obtaining M3 based on the number of first gate trenches / second gate trenches and the width of the first gate trenches; n represents the number of the first gate trench / second gate trench, W represents the width of the first gate trench; draw a curve graph of R1 and M3, and determine the slope K of the curve; obtain K1 based on K and K2, L SUM =2D1+W;L SUM represents the total channel length involved in the accumulation channel; D1 represents the depth of the first gate trench / second gate trench beyond the P-type base layer, W represents the width of the first gate trench per unit area, and L represents the length of the first gate trench / second gate trench; M4 is obtained based on the unit area capacitance of the gate electrode contact, the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / second MOS device with the P-type base layer as the channel, M4=C OX (V G -V T1 );C OX represents the capacitance per unit area of ​​the gate electrode contact, V G Represents the voltage applied at the gate electrode contact point, V T1 represents the threshold voltage of the first MOS device / the second MOS device with the P-type base layer as the channel; according to K1 and M4, the inversion channel mobility μ of the MOS device is obtained CH ,

[0011] Optionally, the value range of W is 1-100 μm.

[0012] Optionally, the value range of Δx is 2-50 μm.

[0013] Optionally, the value range of n is 20-100.

[0014] Optionally, the distance between two adjacent first gate trenches ranges from 1 μm to 100 μm.

[0015] The present disclosure also provides a method for detecting lithographic variation of a MOS device, comprising: preparing a first MOS device and a second MOS device using a MOS device preparation process, wherein n first gate trenches are equidistantly formed on the first MOS device, and the n first gate trenches have the same width W; n second gate trenches are equidistantly formed on the second MOS device, and the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx, ..., W+(n-1)Δx, in sequence; obtaining a difference ΔR1 between the on-resistance R1 of a linear region of the first MOS device and the on-resistance R2 of a linear region of the second MOS device; obtaining M1 based on the number and unit length of the first gate trenches / the second gate trenches, and the width of the first gate trench; n represents the number of first gate trenches / second gate trenches, Δx represents the unit length, and W represents the width of the first gate trench; plot ΔR1 versus M1 to determine the slope K2 and intercept r of the curve. s ; M3 is obtained according to the number of the first gate trench / the second gate trench and the width of the first gate trench, n represents the number of first gate trenches / second gate trenches, and W represents the width of the first gate trench; plot R1 and M3 to determine the intercept Y; plot Y and K2 to determine the slope K3; based on K3 and M3, the MOS device lithography variation ΔL is obtained.

[0016] The method for detecting the channel mobility and lithography variation of MOS devices disclosed herein designs trench MOS unit structures with different numbers and different trench widths to sequentially form inversion channel devices and accumulation channel devices with different width-to-length ratios. Mathematical analytical detection is then used to evaluate the channel mobility of the inversion layer and accumulation layer of the silicon carbide trench MOS. This effectively avoids the influence of line width deviation caused by processes such as lithography and etching on the accuracy of the extracted channel mobility, effectively evaluates the dual channel mobility of the trench MOS device under different gate voltage conditions, and enriches the channel mobility detection methods of silicon carbide MOS devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The flowchart of the method for detecting the accumulation channel mobility of a MOS device according to an embodiment of the present disclosure is schematically shown;

[0018] Figure 2 Schematically shows a structural diagram of a MOS device according to an embodiment of the present disclosure;

[0019] Figure 3 Schematically shows a structural diagram of a first MOS device according to an embodiment of the present disclosure;

[0020] Figure 4 Schematically shows a structural diagram of a second MOS device according to an embodiment of the present disclosure;

[0021] Figure 5 The flowchart of the method for detecting the inversion channel mobility of a MOS device according to an embodiment of the present disclosure is schematically shown;

[0022] Figure 6 The flowchart of the method for detecting the photolithography variation of a MOS device according to an embodiment of the present disclosure is schematically shown.

[0023] Description of reference numerals:

[0024] n++ type silicon carbide substrate substrate-10; n+ type buffer layer-20; n drift layer-30; p type base layer-40; n+ type source layer-50; p+ type base layer-60; gate dielectric-70; gate electrode contact-80; passivation layer-90; source electrode contact-100. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0026] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] Figure 1 The flowchart of the method for detecting accumulation-type channel mobility of a MOS device according to an embodiment of the present disclosure is schematically shown.

[0028] like Figure 1 As shown, an embodiment of the present disclosure provides a method for detecting accumulation-type channel mobility of a MOS device, including operations S110 to S160.

[0029] In operation S110 , a first MOS device and a second MOS device are manufactured using a MOS device manufacturing process.

[0030] The first MOS device is provided with n first gate trenches at equal intervals, and the widths W of the n first gate trenches are the same.

[0031] The second MOS device is provided with n second gate trenches at equal intervals, wherein the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx, . . . W+(n-1)Δx in sequence.

[0032] In operation S120 , a difference ΔR1 between the on-resistance R1 of the first MOS device linear region and the on-resistance R2 of the second MOS device linear region is obtained.

[0033] In operation S130, M1 is obtained according to the number of the first gate trenches / the second gate trenches, the unit length, and the width of the first gate trenches. Wherein, n represents the number of first gate trenches / second gate trenches, Δx represents the unit length, and W represents the width of the first gate trench.

[0034] In operation S140 , a graph of ΔR1 and M1 is plotted to determine the slope K2 and intercept r of the curve. s .

[0035] In operation S150, M2 is obtained according to the unit area capacitance of the gate electrode contact, the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / the second MOS device with the N drift layer as the channel, M2=C OX (V G -V T2 );C OX represents the capacitance per unit area of ​​the gate electrode contact, V G Represents the voltage applied at the gate electrode contact point, V T2 Indicates the threshold voltage of the first MOS device / the second MOS device with the N-drift layer as the channel.

[0036] In operation S160, the accumulation channel mobility of the MOS device is obtained by K2 and M2. in,

[0037] In this embodiment, the manufacturing process of the MOS device includes operations S111 to S119.

[0038] In operation S111 , a silicon carbide epitaxial wafer substrate is prepared, and an n+ type buffer layer 20 , an n drift layer 30 , a p type base layer 40 and a p+ type base layer 60 are epitaxially grown in sequence from bottom to top on an n++ type silicon carbide substrate 10 .

[0039] In operation S112 , an n + type source layer 50 is formed in the p + type base layer 60 by using a doping method such as ion implantation.

[0040] In operation S113, a certain thickness of silicon dioxide or polysilicon or a metal dielectric is deposited on the n+ type source layer 50 to form a barrier layer, which is patterned by photolithography and dry-etched. The barrier layer is then used to dry-etch the silicon carbide substrate by physical or chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), to prepare a first trench in the upper portion of the n drift layer 30, the p-type base layer 40, and the n+ type source layer 50.

[0041] In operation S114 , a gate dielectric 70 is uniformly deposited to a certain thickness on the inner wall and bottom of the first trench.

[0042] In operation S115 , the first trench after the gate dielectric 70 is deposited is filled using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The filling material completely covers the interior of the first trench and the upper portion of the n+ type source layer 50 and has a planarized surface.

[0043] In operation S116, the filling material is dry-etched by physical or chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), to eventually form a gate electrode contact 80 in the first trench whose upper edge is flush with the upper edge of the n+ type source layer 50.

[0044] In operation S117 , a source electrode contact 100 is formed over the n + -type source region layer 50 , the p + -type base region layer 60 , and the gate electrode contact 80 .

[0045] In operation S118 , a second trench is etched on the source electrode contact 100 above the gate electrode contact 80 and a portion of the n + -type source region layer 50 .

[0046] In operation S119 , the second trench is filled and a passivation layer 90 is formed.

[0047] Figure 2 The schematic diagram shows the structure of a MOS device according to an embodiment of the present disclosure.

[0048] like Figure 2 As shown, the silicon carbide trench MOS device prepared according to the preparation process of the MOS device includes an n++ type silicon carbide substrate substrate 10, an n+ type buffer layer 20, an n drift layer 30, a p-type base layer 40, a p+ type base layer 60 and a source electrode contact 100 arranged in sequence from bottom to top.

[0049] In this embodiment, a first trench is opened on the n-drift layer 30 , the p-type base layer 40 and the p+-type base layer 60 . A gate electrode contact 80 is provided in the first trench, and a gate dielectric 70 is provided between the gate electrode contact 80 and the first trench.

[0050] In this embodiment, an n + type source layer 50 is disposed between the gate dielectric 70 and the p + type base layer 60 .

[0051] In this embodiment, a second trench is opened in the source electrode contact 100 above the gate electrode contact 80 , and a passivation layer 90 is disposed in the second trench.

[0052] In this embodiment, the thickness of the p-type base layer 40 is 0.2-1 μm.

[0053] In this embodiment, since the cell size and channel length of the manufactured MOS device are small, the integration of traditional detection methods in the device tape-out process is slightly insufficient. Therefore, it is necessary to use the MOS device detection method in this application to extract the inversion channel resistance R ch and the accumulation channel resistance R Ach The channel mobility involved, where all p-regions in the MOS device are formed as inversion channels, all n-regions are formed as accumulation channels, the channel length is the distance between the two source and drain doped regions, and the channel width is the effective source and drain region size perpendicular to the channel length.

[0054] Figure 3 The schematic diagram shows the structure of a first MOS device according to an embodiment of the present disclosure.

[0055] like Figure 3 As shown, the first MOS devices are arranged in the x-direction with the first gate trench as a unit. Each first trench of the first MOS device has the same width, W, and forms a source electrode contact point V at the left and right ends in the x-direction. S and the drain electrode contact point V D , all gate electrode contacts 80 in the first MOS device converge to form a gate electrode contact point V G .

[0056] Figure 4 The figure schematically shows a structural diagram of a second MOS device according to an embodiment of the present disclosure.

[0057] like Figure 4 As shown, the second MOS device has n second gate trenches equidistantly spaced in the x-direction corresponding to the n first gate trenches of the first MOS device. The widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx, ... W+(n-1)Δx, respectively. The second MOS device forms source electrode contacts V at its left and right ends in the x-direction. S and the drain electrode contact point V D , all gate electrode contacts 80 in the second MOS device converge to form a gate electrode contact point V G .

[0058] The spacing between the n first gate trenches of the first MOS device is the same as the spacing between the n second gate trenches of the second MOS device.

[0059] Optionally, the value range of W is 1-100 μm, and the value range of the distance between two adjacent first gate trenches is 1-100 μm.

[0060] Optionally, the value range of Δx is 2-50 μm.

[0061] Optionally, the value range of n is 20-100.

[0062] Figure 5 The flowchart of the method for detecting the inversion channel mobility of a MOS device according to an embodiment of the present disclosure is schematically shown.

[0063] like Figure 5 As shown, the present disclosure further provides a method for detecting inversion channel mobility of a MOS device, including operations S510 to S590.

[0064] In operation S510 , a first MOS device and a second MOS device are manufactured using a MOS device manufacturing process.

[0065] Wherein, n first gate trenches are equidistantly formed on the first MOS device, and the widths W of the n first gate trenches are the same.

[0066] N second gate trenches are equidistantly formed on the second MOS device, and the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx . . . W+(n-1)Δx in sequence.

[0067] In operation S520 , a difference ΔR1 between the on-resistance R1 of the first MOS device linear region and the on-resistance R2 of the second MOS device linear region is obtained.

[0068] In operation S530 , M1 is obtained according to the number of first gate trenches / second gate trenches, a unit length, and a width of the first gate trench.

[0069] In operation S540 , a graph of ΔR1 and M1 is plotted to determine a slope K2 of the curve.

[0070] In operation S550, M3 is obtained according to the number of the first gate trenches / the second gate trenches and the width of the first gate trenches. n represents the number of first gate trenches / second gate trenches, and W represents the width of the first gate trenches.

[0071] In operation S560 , a graph of R1 and M3 is plotted to determine a slope K of the graph.

[0072] In operation S570, K1 is obtained according to K and K2. L SUM =2D1+W;L SUM represents the total channel length involved in the accumulation channel; D1 represents the depth of the first gate trench / second gate trench exceeding the P-type base layer, W represents the width of the unit first gate trench, and L represents the length of the first gate trench / second gate trench.

[0073] In operation S580, M4 is obtained according to the unit area capacitance of the gate electrode contact, the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / the second MOS device with the P-type base layer as the channel, M4=C OX (V G →V T1 );C OX represents the capacitance per unit area of ​​the gate electrode contact, V G Represents the voltage applied at the gate electrode contact point, V T1 Indicates the threshold voltage of the first MOS device / the second MOS device with the P-type base layer as the channel.

[0074] In operation S590, the inversion channel mobility μ of the MOS device is obtained according to K1 and M4. CH ,

[0075] Optionally, the value range of W is 1-100 μm.

[0076] Optionally, the value range of Δx is 2-50 μm.

[0077] Optionally, the value range of n is 20-100.

[0078] Optionally, the distance between two adjacent first gate trenches ranges from 1 μm to 100 μm.

[0079] Figure 6 The flowchart of the method for detecting the photolithography variation of a MOS device according to an embodiment of the present disclosure is schematically shown.

[0080] like Figure 6 As shown, the present disclosure further provides a method for detecting photolithography variation of a MOS device, including operations S610 to S670.

[0081] In operation S610 , a first MOS device and a second MOS device are manufactured using a MOS device manufacturing process.

[0082] Wherein, n first gate trenches are equidistantly formed on the first MOS device, and the widths W of the n first gate trenches are the same.

[0083] N second gate trenches are equidistantly formed on the second MOS device, and the widths of the n second gate trenches are W, W+Δx, W+2Δx, W+3Δx . . . W+(n-1)Δx in sequence.

[0084] In operation S620 , a difference ΔR1 between the on-resistance R1 of the first MOS device linear region and the on-resistance R2 of the second MOS device linear region is obtained.

[0085] In operation S630, M1 is obtained according to the number of the first gate trenches / the second gate trenches, the unit length, and the width of the first gate trenches. n represents the number of first gate trenches / second gate trenches, Δx represents the unit length, and W represents the width of the first gate trench; plot ΔR1 versus M1 to determine the slope K2 and intercept r of the curve. s .

[0086] In operation S640, M3 is obtained according to the number of the first gate trenches / the second gate trenches and the width of the first gate trenches. n represents the number of first gate trenches / second gate trenches, and W represents the width of the first gate trenches.

[0087] In operation S650 , a graph of R1 and M3 is plotted, and an intercept Y is determined.

[0088] In operation S660 , a graph of Y and K2 is plotted to determine a slope K3 of the graph.

[0089] In operation S670, the MOS device photolithography variation ΔL is obtained according to K3 and M3.

[0090] In this embodiment, the principle of formula derivation is as follows, including steps A to H.

[0091] Step A: Testing the transfer characteristics of the first MOS device I D -V G During the test, the drain electrode voltage is much smaller than the gate electrode voltage. According to different device structure designs, the threshold voltage V with the p-type base layer 40 as the channel is determined. T1 , and the threshold voltage V with the n-drift layer 30 as the channel T2 .

[0092] Step B: Testing the given high gate voltage V of the first MOS device and the second MOS device G Output characteristics I D -V D , thereby determining the on-resistance R1 of the first MOS device and the on-resistance R2 of the second MOS device.

[0093] Step C: Formula (1) and formula (2) shown below are well known in the industry.

[0094]

[0095]

[0096] Subtracting formula (1) from formula (2) yields the formula for the differential resistance ΔR1 as shown in the following formula (3).

[0097]

[0098] In formulas (1), (2) and (3), μ CH is the inversion channel mobility, μ ACH is the accumulation channel mobility, L is the channel length, W is the channel width in the z direction, L SUM is the total channel length involved in the accumulation channel, L SUM The depth of the gate trench extending beyond the p-type base layer 40 is multiplied by 2 and added to the unit width of the gate trench, V G is the applied gate voltage, V T1 and V T2 The threshold voltage determined in step A, C OX is the capacitance per unit area of ​​the gate dielectric, n is the number of repeated gate trenches in structures 1 and 2, Δx is the unit increment width designed by the photoresist, and r s is the device series resistance, r s The corresponding resistance reference value can be approximately obtained by designing thin n+ source region layers 50 with the same length.

[0099] Step D: By designing different n values ​​or Δx values, the equation (3) is obtained. A series of data points of the curve are fitted using the least squares method to determine the slope of the curve. The intercept is r s .

[0100] Step E: Based on the slope determined in the previous step And the known C OX 、V G and V T2 , thereby extracting the SiC trench accumulation channel mobility μ ACH .

[0101] Step F: Assume that the preset L is caused by the actual photolithography, etching and other processes SUM The change in is ΔL. Substituting the slope K2 determined in the above steps into formula (1) yields formulas (4) and (5).

[0102]

[0103]

[0104] Here, By designing different n values ​​in the layout, we can obtain the equation (4) for A series of data points of the curve are fitted using the least squares method to determine that the slope of the curve is K = K1·L + K2·L SUM , the intercept is Y.

[0105] Step G: According to the slope K, K2, L, L SUM , And the known C OX 、V G and V T1 , and thus extract the SiC trench inversion channel mobility μ CH .

[0106] Step H: Fixed n value, varying gate voltage V G Repeat the process from step B to step G to obtain a series of data points on the Y-K2 curve determined in equation (5), and then use the least squares method to fit the slope of the curve to determine The intercept is r s . Thus determine the preset L caused by actual lithography, etching and other processes SUM The change in ΔL value.

[0107] In the specific embodiments described above, the substrate material used is not limited to silicon carbide and should include power electronic semiconductor materials such as silicon, gallium nitride, gallium oxide, and diamond. When other semiconductor materials are used as substrates, the detection method of the embodiment can also be used to extract the channel mobility in a trench MOS structure.

[0108] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for detecting accumulation channel mobility of a MOS device, characterized in that: include: A first MOS device and a second MOS device are prepared using the MOS device preparation process, wherein n first gate trenches (110) are equidistantly provided on the first MOS device, and the widths W of the n first gate trenches (110) are the same; n second gate trenches (120) are equidistantly provided on the second MOS device, and the widths of the n second gate trenches (120) are W, W+Δx, W+2Δx, W+3Δx...W+(n-1)Δx in sequence; According to the on-resistance R1 of the linear region of the first MOS device and the on-resistance R2 of the linear region of the second MOS device, a difference ΔR1 between the two is obtained; M1 is obtained according to the number of the first gate trenches (110) / the second gate trenches (120), the unit length and the width of the first gate trenches (110), n represents the number of the first gate trenches (110) / the second gate trenches (120), Δx represents the unit length, and W represents the width of the first gate trenches (110); Draw a graph of ΔR1 and M1 to determine the slope K2 and intercept r of the curve s ; M2 is obtained based on the unit area capacitance of the gate electrode contact (80), the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / second MOS device with the N drift layer (30) as the channel, M2=C OX (V G -V T2 );C OX represents the capacitance per unit area of ​​the gate electrode contact (80), V G represents the voltage applied at the gate electrode contact point, V T2 Indicates the threshold voltage of the first MOS device / the second MOS device with the N drift layer (30) as the channel; The accumulation channel mobility of the MOS device is obtained by K2 and M2.

2. The method for detecting accumulation channel mobility of a MOS device according to claim 1, wherein: The value range of W is 1-100 μm, and the value range of the distance between two adjacent first gate trenches (110) is 1-100 μm.

3. The method for detecting accumulation channel mobility of a MOS device according to claim 1, wherein: The value range of Δx is 2-50 μm.

4. The method for detecting accumulation channel mobility of a MOS device according to claim 1, wherein: The value range of n is 20-100.

5. A method for detecting inversion channel mobility of a MOS device, characterized in that: include: A first MOS device and a second MOS device are prepared using the MOS device preparation process, wherein n first gate trenches (110) are equidistantly provided on the first MOS device, and the widths W of the n first gate trenches (110) are the same; n second gate trenches (120) are equidistantly provided on the second MOS device, and the widths of the n second gate trenches (120) are W, W+Δx, W+2Δx, W+3Δx...W+(nl)Δx, in sequence; According to the on-resistance R1 of the linear region of the first MOS device and the on-resistance R2 of the linear region of the second MOS device, a difference ΔR1 between the two is obtained; Obtaining M1 according to the number and unit length of the first gate trenches (110) / the second gate trenches (120) and the width of the first gate trenches (110); n represents the number of the first gate trenches (110) / the second gate trenches (120), Δx represents the unit length, and W represents the width of the first gate trenches (110); Draw a curve graph of ΔR1 and M1 to determine the slope K2 of the curve; M3 is obtained according to the number of the first gate trenches (110) / the second gate trenches (120) and the width of the first gate trenches (110), n represents the number of the first gate trenches (110) / second gate trenches (120), and W represents the width of the first gate trenches (110); Draw a curve graph of the R1 and the M3, and determine the slope K of the curve; According to the K and the K2, K1 is obtained. L SUM =2D1+W;L SUM represents the total channel length involved in the accumulation-type channel; D1 represents the depth of the first gate trench (110) / the second gate trench (120) exceeding the P-type base layer (40); W represents the width of the first gate trench (110) per unit; and L represents the length of the first gate trench (110) / the second gate trench (120); M4 is obtained based on the unit area capacitance of the gate electrode contact (80), the voltage applied at the gate electrode contact point, and the threshold voltage of the first MOS device / second MOS device with the P-type base layer (40) as the channel, M4=C OX (V G →V T1 );C OX represents the capacitance per unit area of ​​the gate electrode contact (80), V G represents the voltage applied at the gate electrode contact point, V T1 Indicates the threshold voltage of the first MOS device / the second MOS device with the P-type base layer (40) as the channel; According to K1 and M4, the inversion channel mobility μ of the MOS device is obtained. CH , 6. The method for detecting inversion channel mobility of a MOS device according to claim 5, wherein: The value range of W is 1-100 μm.

7. The method for detecting inversion channel mobility of a MOS device according to claim 5, wherein: The value range of Δx is 2-50 μm.

8. The method for detecting inversion channel mobility of a MOS device according to claim 5, wherein: The value range of n is 20-100.

9. The method for detecting inversion channel mobility of a MOS device according to claim 8, wherein: The distance between two adjacent first gate trenches (110) ranges from 1 to 100 μm.

10. A method for detecting lithography variation of a MOS device, characterized in that: include: A first MOS device and a second MOS device are prepared using the MOS device preparation process, wherein n first gate trenches (110) are equidistantly provided on the first MOS device, and the widths W of the n first gate trenches (110) are the same; n second gate trenches (120) are equidistantly provided on the second MOS device, and the widths of the n second gate trenches (120) are W, W+Δx, W+2Δx, W+3Δx...W+(n-1)Δx in sequence; According to the on-resistance R1 of the linear region of the first MOS device and the on-resistance R2 of the linear region of the second MOS device, a difference ΔR1 between the two is obtained; M1 is obtained according to the number of the first gate trenches (110) / the second gate trenches (120), the unit length and the width of the first gate trenches (110), n represents the number of the first gate trenches (110) / the second gate trenches (120), Δx represents the unit length, and W represents the width of the first gate trenches (110); Draw a graph of ΔR1 and M1 to determine the slope K2 and intercept r of the curve s ; M3 is obtained according to the number of the first gate trenches (110) / the second gate trenches (120) and the width of the first gate trenches (110), n represents the number of the first gate trenches (110) / second gate trenches (120), and W represents the width of the first gate trenches (110); Draw a graph of R1 and M3 to determine the intercept Y; Draw a curve graph of Y and K2 to determine the slope K3 of the curve; According to K3 and M3, the MOS device lithography variation ΔL is obtained.

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