Method for forming semiconductor structure and method for manufacturing semiconductor device

Abstract

The application provides a semiconductor structure forming method and a semiconductor device manufacturing method, and the forming method comprises the following steps: providing a substrate, wherein the substrate has a first region and a second region, a first fin is arranged on the first region, a second fin is arranged on the second region, and the conductive types of the first fin and the second fin are opposite; sequentially forming a hard mask material layer and a sidewall material layer, and combining the sidewall material layers between adjacent first fins and second fins to form a boundary sidewall; and forming a first epitaxial structure on the first region and a second epitaxial structure on the second region by using the hard mask material layer and taking the boundary sidewall as a spacer layer of the first region and the second region. In the application, the sidewall material layer is combined between the first fin and the second fin to form the boundary sidewall, and the boundary sidewall is used as a spacer layer of the first epitaxial structure and the second epitaxial structure, so that the short circuit problem of the first epitaxial structure and the second epitaxial structure is prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor structure forming method and a semiconductor device manufacturing method. BACKGROUND

[0002] In the field of semiconductor technology, static random access memory (SRAM) devices, as a typical semiconductor device, are widely used in electronic devices such as computers, mobile phones, digital cameras, etc. In the prior art, some designs use fin-type field effect transistors (FinFET) as transistor devices of SRAM cells to improve the density and performance of SRAM.

[0003] Taking FinFET as an example of the transistor of the SRAM device, N-type FinFET and P-type FinFET are provided in the storage area of the SRAM device, and the N-type FinFET (nFET) and the P-type FinFET (pFET) are relatively close, which causes the embedded epitaxial structure (as a source-drain structure, for example, SiP) of the N-type FinFET and the embedded epitaxial structure (as a source-drain structure, for example, SiGe) of the P-type FinFET to be easily short-circuited due to the side protruding topography of the two. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor structure forming method and a semiconductor device manufacturing method to solve the short circuit problem caused by the close distance between the embedded epitaxial structures of the N-type FinFET and the P-type FinFET.

[0005] To solve the above technical problems, the semiconductor structure forming method provided by the present application comprises: providing a substrate, the substrate having a first region and a second region, the first region being provided with a plurality of first fins, the second region being provided with a plurality of second fins, the conductive type of the first fins being opposite to that of the second fins, and the distance between adjacent first fins and the distance between adjacent second fins being greater than the distance between adjacent first fins and second fins; sequentially forming a hard mask material layer and a sidewall material layer, the hard mask material layer conformally covering the surface of the substrate, the outer wall of the first fin and the outer wall of the second fin, the sidewall material layer covering the hard mask material layer and merging the sidewall material layers between adjacent first fins and second fins to form a boundary sidewall; using the boundary sidewall as a spacer layer of the first region and the second region, forming a first epitaxial structure in the first region and a second epitaxial structure in the second region, and isolating adjacent first epitaxial structures and second epitaxial structures by the boundary sidewall.

[0006] Optionally, the substrate is covered with an isolation medium layer, which fills part of the height of the first fin and the second fin.

[0007] Optionally, before forming the hard mask material layer, a plurality of virtual gates are formed on the isolation medium layer, the virtual gates being arranged at intervals and spanning the first fin and the second fin.

[0008] Optionally, the hard mask material layer and the sidewall material layer are formed by an ALD process, the hard mask material layer conformally covering the isolation medium layer, the first fin, the second fin and the virtual gates.

[0009] Optionally, the step of forming the first epitaxial structure in the first region comprises: forming a first patterned mask layer, which covers the second region and at least part of the boundary sidewall and exposes the first region; using the first patterned mask layer, removing the sidewall material layer, the hard mask material layer and at least part of the height of the first fin in the first region; removing the first patterned mask layer and epitaxially forming the first epitaxial structure on the remaining first fin, the first epitaxial structure being in contact with one side of the boundary sidewall.

[0010] Optionally, after forming the first epitaxial structure, an oxidation layer is formed on the outer wall of the first epitaxial structure by an ISSG process.

[0011] Optionally, the step of forming the second epitaxial structure in the second region comprises: forming a second patterned mask layer, which covers the first region and at least part of the boundary sidewall and exposes the second region; using the second patterned mask layer, removing the sidewall material layer, the hard mask material layer and at least part of the height of the second fin in the second region; removing the second patterned mask layer and epitaxially forming the second epitaxial structure on the remaining second fin, the second epitaxial structure being in contact with one side of the boundary sidewall.

[0012] Optionally, the material of the hard mask material layer comprises silicon nitride and the material of the sidewall material layer comprises silicon oxide.

[0013] Optionally, the first region is a P-type region, the material of the first epitaxial structure comprises SiGe, the second region is an N-type region and the material of the second epitaxial layer comprises SiP.

[0014] Based on another aspect of the present application, a semiconductor device manufacturing method is also provided, which comprises the semiconductor structure forming method as described above.

[0015] In summary, the application forms a boundary side wall between the first fin and the second fin by using the hard mask material layer to cover the first region and the second region as a hard mask when forming the hard mask material layer and the side wall material layer, and using the side wall material layer to cover the hard mask material layer, and using the side wall material layer to merge and form the boundary side wall between the first fin and the second fin, the boundary side wall is located between the first fin and the second fin, and can be used as a spacing layer of the first epitaxial structure formed on the first fin and the second epitaxial structure formed on the second fin, thereby preventing the short connection problem of the first epitaxial structure and the second epitaxial structure, simplifying the forming process of the first epitaxial structure and the second epitaxial structure, and improving the yield. BRIEF DESCRIPTION OF DRAWINGS

[0016] Those skilled in the art will understand that the drawings provided are for a better understanding of the present application, and do not constitute any limitation on the scope of the present application.

[0017] Figure 1 is a flowchart of the forming method of the semiconductor structure provided by the embodiment;

[0018] Figures 2 to 11 The corresponding structure schematic diagram of the corresponding steps of the forming method of the semiconductor structure provided by the embodiment.

[0019] In the drawings:

[0020] 10-substrate; 11-isolation medium layer; AA-first region; BB-second region; 12-first fin; 13-second fin; D1-first direction; D2-second direction;

[0021] 21-hard mask material layer; 22-side wall material layer; 23-boundary side wall; 31-first patterned mask layer; 32-first epitaxial structure;

[0022] 33-oxide layer; 41-second patterned mask layer; 42-second epitaxial structure. DETAILED DESCRIPTION

[0023] In order to make the purpose, advantages and characteristics of the present application clearer, the following will further describe the present application in combination with the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different scales are sometimes used in different emphasis of the drawings.

[0024] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. The term "plurality" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. The term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only to describe a particular object and do not imply or suggest relative importance or imply a specific number of the technical features indicated. Thus, features qualified with "first," "second," "third," etc. can expressly or implicitly include one or at least two of the features unless the context clearly dictates otherwise.

[0025] Embodiment One

[0026] Figure 1 is a flowchart of the method for forming a semiconductor structure provided by Embodiment One.

[0027] As shown in Figure 1 , the method for forming a semiconductor structure provided by the present embodiment includes the following steps:

[0028] S01: providing a substrate, the substrate having a first region and a second region, the first region being provided with a plurality of first fins, the second region being provided with a plurality of second fins, the first fins and the second fins being of opposite conductivity types, and the spacing between adjacent first fins and the spacing between adjacent second fins both being greater than the spacing between adjacent first fins and second fins;

[0029] S02: sequentially forming a hard mask material layer and a sidewall material layer, the hard mask material layer conformally covering the surface of the substrate, the outer walls of the first fins, and the outer walls of the second fins, and the sidewall material layer covering the hard mask material layer and merging the sidewall material layers between adjacent first fins and second fins to form a boundary sidewall;

[0030] S03: using the boundary sidewall as a spacer layer for the first region and the second region, forming a first epitaxial structure in the first region and a second epitaxial structure in the second region, and isolating adjacent first epitaxial structures and second epitaxial structures by the boundary sidewall.

[0031] Figures 2 to 11 The corresponding structure schematic diagram corresponding to the respective steps of the method for forming a semiconductor structure provided by the present embodiment will be described in detail below. Figures 2 to 11 The method for forming a semiconductor structure will be described in detail.

[0032] First, please refer to Figure 2In step S01, a substrate 10 is provided, which has a first region AA and a second region BB. The first region AA has first fins 12 formed thereon, and the second region BB has second fins 13 formed thereon. The first fins 12 and the second fins 13 have opposite conductivity types. The spacing between adjacent first fins 12 and the spacing between adjacent second fins 13 are both greater than the spacing between adjacent first fins 12 and second fins 13.

[0033] The substrate 10 can be any suitable substrate material known to those skilled in the art, such as at least one of silicon, silicon-on-insulator (SOI), silicon-on-silicon (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. In this embodiment, the substrate 10 is taken as an example of silicon (silicon substrate).

[0034] Specifically, the silicon substrate can be etched by double patterning or multiple patterning to form a plurality of fins (including the first fins 12 and the second fins 13) arranged at intervals on the substrate 10. The plurality of fins can be arranged along a first direction D1 and each fin extends along a second direction D2. The first direction D1 and the second direction D2 are orthogonal to the surface of the substrate 10. The plurality of fins can have the same or as close as possible height. The substrate 10 is covered with an isolation dielectric layer 11, which fills part of the height of the fins and exposes the remaining part of the height of the fins. The fins exposed on the isolation dielectric layer 11 are used to form active regions in subsequent processes. The formed substrate 10 has a first region AA and a second region BB. The fins in the first region AA can be the first fins 12, and the fins in the second region BB can be the second fins 13. The first fins 12 and the second fins 13 have opposite conductivity types by at least two ion implantation processes of different conductivity types. In particular, the spacing between the first fins 12 in the first region AA can be a first spacing, the spacing between the second fins 13 in the second region BB can be a second spacing, and the spacing between adjacent first fins 12 and second fins 13 is less than the first spacing and the second spacing. The first spacing can be the same as or different from the second spacing, and the width of the first fins 12 and the width of the second fins 13 can also be the same or different. It is not difficult to understand that, since the spacing between adjacent first fins 12 and second fins 13 is small, the risk of shorting of the epitaxial structure formed in subsequent processes is greater than the risk of shorting of the epitaxial structure between the first fins 12 or between the second fins 13.

[0035] In the embodiment, the first region AA can be a P-type region, and the second region BB can be an N-type region, i.e., a P-type FinFET is formed by the first fin 12, and an N-type FinFET is formed by the second fin 13. Of course, in practice, due to the etching process, the angle between the sidewall of the formed fin and the surface of the substrate 10 can be 85°-90°, i.e., the cross-sectional shape of the fin along the first direction D1 is trapezoidal (narrow on top and wide on bottom).

[0036] In a specific embodiment, taking the first region AA as a P-type region and the second region BB as an N-type region as an example, the first interval can be 52 nm, the second interval can be 69 nm, and the interval between adjacent first fins 12 and second fins 13 can be 48.5 nm.

[0037] Next, a plurality of spaced-apart dummy gates (not shown) are formed on the isolation medium layer 11, the plurality of dummy gates span the first fin 12 and the second fin 13 along the first direction D1 (each dummy gate extends along the first direction D1 and the plurality of dummy gates are arranged along the second direction D2), the area covered by the dummy gate on the first fin 12 and the second fin 13 is taken as a gate region, a gate structure (such as a metal gate structure) is formed in the subsequent step, and the area on both sides of the first fin 12 and the second fin 13 exposed by the dummy gate is taken as a source-drain region, for forming a source-drain structure (source end and drain end). Moreover, a side wall structure can also be formed on the sidewall of the dummy gate for protecting the dummy gate. It should be noted that the drawings in the embodiment are cross-sectional views of the source-drain region along the first direction D1, and the dummy gate and the side wall structure are not shown.

[0038] Next, referring to Figure 3 , step S02 is performed to form a hard mask material layer 21 that conformally covers the isolation medium layer 11, the outer wall of the first fin 12, the outer wall of the second fin 13, and the outer wall of the dummy gate.

[0039] Specifically, the hard mask material layer 21 can be a hard material such as silicon nitride or silicon carbon nitride with better isolation effect, and ALD (atomic layer deposition) process is preferably used to form the hard mask material layer 21 to improve the step coverage and film quality. The thickness of the hard mask material layer 21 is relatively thin, for example, it can be 10-50 angstroms, to reduce the stress. Of course, the hard mask material layer 21 will also extend to cover the dummy gate and the side wall structure, which are not shown in the figure.

[0040] Next, referring to Figure 4 , a side wall material layer 22 is formed to cover the outer wall of the hard mask material layer 21 until the side wall material layer 22 between adjacent first fins 12 and second fins 13 merges to form a boundary side wall 23.

[0041] The material of the sidewall material layer 22 is different from that of the hard mask material layer 21, and both are easier to achieve a larger etching selectivity. For example, the material of the hard mask material layer 21 is silicon nitride, and the material of the sidewall material layer 22 is silicon oxide, which is formed by ALD process to improve the step coverage and film quality. Moreover, the ALD process is easier to control the thickness of the film, and the thickness of the sidewall material layer 22 is preferably controlled to make the sidewall material layer 22 between the adjacent first fins 12 and the second fins 13 merge to form the boundary sidewall 23, and the boundary sidewall 23 is located between the first region AA and the second region BB. However, the sidewall material layer 22 between the first fins 12 or the second fins 13 does not merge due to the relatively large spacing between the first fins 12 or the second fins 13.

[0042] Then, step S03 is performed to form the first epitaxial structure 32 in the first region AA and the second epitaxial structure 42 in the second region BB by using the boundary sidewall 23 as a spacer layer, and the adjacent first epitaxial structure 32 and the second epitaxial structure 42 are isolated by the boundary sidewall 23.

[0043] The step of forming the first epitaxial structure 32 in the first region AA may, for example, include:

[0044] Referring to Figure 5 , a first patterned mask layer 31 is formed to cover the second region BB and at least part of the boundary sidewall 23, and expose the first region AA. The first patterned mask layer 31 can be a patterned photoresist layer, which covers the sidewall material layer 22 and the boundary sidewall 23 in the second region BB, and the width of the boundary sidewall 23 covered by the first patterned mask layer 31 can be determined according to the width of the first epitaxial structure 32 adjacent to the boundary sidewall 23 (the width of the side adjacent to the boundary sidewall 23). That is, the wider the width of the first epitaxial structure 32 adjacent to the boundary sidewall 23, the narrower the width of the boundary sidewall 23 covered by the first patterned mask layer 31. In practice, the first patterned mask layer 31 covers at least half of the width of the boundary sidewall 23 to prevent the boundary sidewall 23 from being deformed (inclined or bent) due to excessive etching and adversely affecting the function of the boundary sidewall 23 as a spacer layer.

[0045] Referring to Figure 6 , the exposed sidewall material layer 22, the hard mask material layer 21, and at least part of the first fins 12 with a height are sequentially removed by using the first patterned mask layer 31. Specifically, the dry etching process can be used to remove the sidewall material layer 22 on the first region AA and the exposed boundary sidewall 23, and then remove the hard mask material layer 21 on the first region AA and the outer wall of the first fins 12. Subsequently, at least part of the first fins 12 with a height on the isolation medium layer 11 are removed.

[0046] Preferably, a remaining portion of the first fin 12 and the hard mask material layer 21 of the sidewall of the first fin 12 can be reserved (remaining) according to the size (height and width) of the subsequent first epitaxial structure 32, wherein the height of the remaining hard mask material layer 21 is higher than the height of the remaining first fin 12 (the height on the isolation medium layer 11), and the remaining hard mask material layer 21 can preferably constrain the morphology and size of the subsequent first epitaxial structure growth. It should be understood that, in the case of ensuring that the top surface of the subsequently formed first epitaxial structure is substantially the same as the height of the first fin 12, the higher the height of the remaining first fin 12, the smaller the size of the first epitaxial structure grown on the remaining first fin 12.

[0047] Referring to Figure 7 , the first patterned mask layer 31 is removed, and the first epitaxial structure 32 is formed on the remaining first fin 12 by epitaxial process. The first epitaxial structure 32 can be in contact with one side of the boundary side wall 23. Taking the first region AA as a P-type region as an example, the first epitaxial structure 32 can be formed on the remaining first fin 12 by epitaxial process, and the material of the first epitaxial structure 32 can include SiGe. The first epitaxial structure 32 on both sides of the dummy gate can cause the first fin 12 (conductive channel) under the dummy gate to be under compressive stress, so as to improve the mobility of hole carriers. The first epitaxial structure 32 grows upward along the remaining first fin 12, and the cross-sectional shape of the first epitaxial structure 32 along the first direction D1 is diamond-shaped (rhombus), and the two sides thereof protrude outward to occupy the space (gap) on both sides thereof.

[0048] In particular, since the boundary side wall 23 is arranged between the first fin 12 and the second fin 13, one side of the first epitaxial structure 32 close to the second fin 13 is limited by the boundary side wall 23, that is, one side of the first epitaxial structure 32 grown on the first fin 12 is in contact with the boundary side wall 23, thereby facilitating the isolation between the first fin 12 and the second fin 13. Of course, the first epitaxial structure 32 grown on the other first fin 12 away from the second fin 13 is not affected.

[0049] Referring to Figure 8 , an oxide layer 33 is formed to cover the outer wall of the first epitaxial structure 32.

[0050] Specifically, the ISSG (in-situ steam generation) process can be used to form the oxide layer 33 on the outer wall of the first epitaxial structure 32 for protecting the first epitaxial structure 32, so as to take into account the formation rate and film quality of the oxide layer 33. Taking the material of the first epitaxial structure 32 including SiGe as an example, the material of the oxide layer 33 can be silicon oxide.

[0051] Then, the step of forming the second epitaxial structure in the second region BB may, for example, comprise:

[0052] Referring to Figure 9 , a second patterned mask layer 41 is formed to cover the first region AA and at least part of the border sidewall 23, and to expose the second region BB.

[0053] The second patterned mask layer 41 may be a patterned photoresist layer covering the isolation medium layer 11, the oxide layer 33 of the first epitaxial structure 32, and at least part of the border sidewall 23 in the first region AA. The width of the border sidewall 23 covered by the second patterned mask layer 41 may be determined according to the width of the second epitaxial structure to be formed near the border sidewall 23. That is, the wider the width of the second epitaxial structure (to be formed later) near the border sidewall 23, the narrower the width of the border sidewall 23 covered by the second patterned mask layer 41. In practice, the second patterned mask layer 41 may cover at least half of the spacing between the adjacent first fin 12 and the second fin 13 to prevent the border sidewall 23 from being excessively etched and thus deformed (tilted or bent).

[0054] Referring to Figure 10 , the exposed sidewall material layer 22, the hard mask material layer 21, and at least part of the second fin 13 are sequentially removed using the second patterned mask layer 41, and the border sidewall 23 (or the remaining border sidewall 23) is located between the first region AA and the second region BB. The method for removing the sidewall material layer 22, the hard mask material layer 21, and at least part of the second fin 13 in the second region BB may refer to the method for removing the sidewall material layer, the hard mask material layer, and the second fin in the first region AA using the first patterned mask layer, which will not be described herein.

[0055] Referring to Figure 11 , the second patterned mask layer 41 is removed, and a second epitaxial structure 42 is formed on the remaining second fin 13 by epitaxial growth. The second epitaxial structure 42 is in contact with one side of the border sidewall 23.

[0056] Taking the second region BB as an N-type region as an example, the second epitaxial structure 42 may be formed on the remaining second fin 13 by epitaxial growth. The material of the second epitaxial structure 42 may include SiP. The second epitaxial structure 42 on both sides of the dummy gate causes the second fin 13 (conductive channel) under the dummy gate to be under tensile stress, thereby improving the mobility of electron carriers. The second epitaxial structure 42 grows upward along the remaining second fin 13, and the cross-sectional shape of the second epitaxial structure 42 along the first direction D1 is diamond-shaped (rhombus-shaped), with two sides protruding outward to occupy the space on both sides.

[0057] In particular, due to the boundary side wall 23 provided between the first fin 12 and the second fin 13, the side of the second epitaxial structure 42 close to the first fin 12 is limited by the boundary side wall 23, i.e. the side of the second epitaxial structure 42 can be in contact with the boundary side wall 23, and the first epitaxial structure 32 and the second epitaxial structure 42 are isolated by the boundary side wall 23 to prevent shorting (short circuit) of the adjacent first epitaxial structure 32 and the second epitaxial structure 42. Of course, the first epitaxial structure 32 grown on the other second fin 13 away from the first fin 12 is not affected.

[0058] Embodiment Two

[0059] Embodiment Two also provides a method for manufacturing a semiconductor device, which includes the semiconductor structure as described above. In an embodiment, the semiconductor device can be, for example, an SRAM device. Specifically, the SRAM device includes a storage region and a logic region, the storage region has storage cells formed thereon, and the logic region has logic cells formed thereon, and the storage cells and the logic cells both use FinFETs as transistor devices. The storage cells and the logic cells both include P-type FinFETs and N-type FinFETs, wherein the storage cells have adjacent (parallel) pull-up transistors (e.g. P-type FinFETs) and pull-down transistors (e.g. N-type FinFETs), and the pull-up transistors and the pull-down transistors have a close distance (e.g. less than the distance between other P-type FinFETs or other N-type FinFETs), i.e. the storage region (storage cells) of the SRAM device can be formed by the method for forming the semiconductor structure as described above to prevent shorting of the epitaxial structures of the adjacent pull-up transistors and pull-down transistors. The distance between the P-type FinFETs and the N-type FinFETs in the logic region can be normally set (the same as or greater than the distance between other P-type FinFETs or other N-type FinFETs), so that the semiconductor structure as described above can be formed in the logic region synchronously with the storage region without additional masks and corresponding processes. However, it is worth mentioning that when the side wall material layers of the storage region are combined to form the boundary side wall, the side wall material layers of the logic region are not combined to form the boundary side wall, but this does not affect the formation of the semiconductor structure as described above in the logic region, and the process also has the effect of preventing shorting of the epitaxial structures. Of course, it is also feasible that no boundary side wall is formed between the P-type FinFETs and the N-type FinFETs in the logic region.

[0060] In other words, the method for manufacturing a semiconductor device provided by the embodiment can include the method for forming the semiconductor structure as described above.

[0061] In summary, the application forms a hard mask material layer and a sidewall material layer, uses the hard mask material layer to cover the first area and the second area as a hard mask, and uses the sidewall material layer to cover the hard mask material layer, and uses the sidewall material layer to form a boundary sidewall between the first fin and the second fin, the boundary sidewall is located between the first fin and the second fin, and can be used as a spacing layer of a first epitaxial structure formed on the first fin and a second epitaxial structure formed on the second fin, thereby preventing the short connection problem of the first epitaxial structure and the second epitaxial structure, simplifying the forming process of the first epitaxial structure and the second epitaxial structure, and improving the yield.

[0062] The above description is only a description of the preferred embodiments of the application, and is not any limitation on the scope of the application, and any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first region and a second region, the first region having a plurality of first fins, the second region having a plurality of second fins, the first fins and the second fins having opposite conductivity types, and the spacing between adjacent first fins and the spacing between adjacent second fins being greater than the spacing between adjacent first fins and second fins. A hard mask material layer and a sidewall material layer are formed sequentially. The hard mask material layer conformally covers the surface of the substrate, the outer wall of the first fin, and the outer wall of the second fin. The sidewall material layer covers the hard mask material layer and merges the sidewall material layers between adjacent first fins and second fins to form a boundary sidewall. Using the boundary sidewall as a spacer between the first region and the second region, a first extensional structure is formed in the first region and a second extensional structure is formed in the second region, so that the boundary sidewall isolates the adjacent first extensional structure and the second extensional structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, An isolation dielectric layer is covered on the substrate, and the isolation dielectric layer fills to a portion of the height of the first fin and the second fin.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, Before forming the hard mask material layer, a plurality of spaced virtual gates are formed on the isolation dielectric layer, the virtual gates spanning the first fin and the second fin.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The hard mask material layer and the sidewall material layer are formed using an ALD process. The hard mask material layer conformally covers the isolation dielectric layer, the first fin, the second fin, and the dummy gate.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the first epitaxial structure in the first region includes: A first patterned mask layer is formed, covering the second region and at least a portion of the boundary sidewalls, and exposing the first region; Using the first patterned mask layer, the sidewall material layer, the hard mask material layer, and at least a portion of the height of the first fin in the first region are removed; Remove the first patterned mask layer and epitaxially form the first epitaxial structure on the remaining first fin, the first epitaxial structure being in contact with one side of the boundary sidewall.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, After the first epitaxial structure is formed, an oxide layer is formed on the outer wall of the first epitaxial structure using the ISSG process.

7. The method for forming a semiconductor structure according to claim 5 or 6, characterized in that, The step of forming the second epitaxial structure in the second region includes: A second patterned mask layer is formed, covering the first area and at least part of the boundary sidewalls, and exposing the second area; Using the second patterned mask layer, the sidewall material layer, hard mask material layer, and at least a portion of the height of the second fin in the second region are removed; Remove the second patterned mask layer and epitaxially form the second epitaxial structure on the remaining second fin, the second epitaxial structure being in contact with one side of the boundary sidewall.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The hard mask material layer is made of silicon nitride, and the sidewall material layer is made of silicon oxide.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The first region is a P-type region, and the material of the first epitaxial structure includes SiGe. The second region is an N-type region, and the material of the second epitaxial layer includes SiP.

10. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes the method for forming a semiconductor structure as described in any one of claims 1 to 9.

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