Electrostatic protection device structure

Abstract

The application relates to the technical field of semiconductor integrated circuits, in particular to a static protection device structure. The static protection device structure comprises a first conductive type substrate, an upper layer of the first conductive type substrate forms a first conductive type well region; in the first conductive type well region, source regions and drain regions are arranged in a transverse interval, the source regions and the drain regions are both of a second conductive type; all the drain regions are connected to lead out a static input end of the static protection device structure, and each source region is connected to lead out a static output end of the static protection device structure; a first conductive type diffusion region is inserted into the drain region, and the first conductive type diffusion region is not provided with a leading-out end; and a polysilicon gate is located on an interval region between the interval adjacent source region and drain region. The static protection device structure can solve the problems of high turn-on voltage and low static protection capability of the static protection device structure in the related art.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and specifically to an electrostatic discharge (ESD) protection device structure. Background Technology

[0002] Currently popular process technologies use CMOS (Complementary Metal-Oxide-Semiconductor Transistor) as electrostatic discharge (ESD) protection devices.

[0003] The electrostatic discharge (ESD) protection device in related technologies includes spaced-apart source and drain regions. When static electricity occurs, the adjacent source and drain regions become conductive, forming a discharge channel through which the static charge is discharged. However, the formation of this discharge channel requires a high turn-on voltage, which is detrimental to the ESD protection capability of the ESD protection device. Summary of the Invention

[0004] This application provides a structure for an electrostatic discharge (ESD) protection device that can solve the problems of high turn-on voltage and low ESD protection capability in related technologies.

[0005] To address the technical problems described in the background art, this application provides an electrostatic discharge (ESD) protection device structure, the ESD protection device structure comprising:

[0006] A first conductivity type substrate, wherein a first conductivity type well region is formed on the upper layer of the first conductivity type substrate;

[0007] In the first conductivity type well region, source regions and drain regions are arranged laterally at intervals, and both source regions and drain regions are of the second conductivity type; all the drain regions are connected to lead out the electrostatic input terminal of the electrostatic protection device structure, and each of the source regions leads out the electrostatic output terminal of the electrostatic protection device structure.

[0008] Insert a first conductivity type diffusion region into the drain region, wherein the first conductivity type diffusion region has no lead-out terminals;

[0009] A polysilicon gate, the polysilicon gate being located on a spacer region between adjacent source and drain regions.

[0010] Optionally, the outermost part of the electrostatic protection device structure is the source region.

[0011] Optionally, a plurality of first conductivity type diffusion regions are formed in one of the drain regions, and the plurality of first conductivity type diffusion regions are spaced apart.

[0012] Optionally, a contact hole is formed on the drain region to lead out the drain region.

[0013] Optionally, no contact holes are formed on the diffusion region of the first conductivity type.

[0014] Optionally, the adjacent drain and source regions, and the first conductivity type well region located between the adjacent drain and source regions, together form a parasitic transistor.

[0015] Optionally, when electrostatic charge enters the electrostatic protection device structure from the drain region, the PN junction between the drain region and the first conductivity type diffusion region is broken down first.

[0016] Optionally, the electrostatic output terminal is grounded.

[0017] The technical solution of this application includes at least the following advantages: when electrostatic charge enters the structure of the electrostatic protection device from the drain, the parasitic transistor in the structure creates a conductive channel between the adjacent drain and source regions 230. Because a P-type diffusion region is inserted in the drain region, the breakdown location of the parasitic transistor is not initially in the N-junction between the drain and P-type well regions near the conductive channel, but rather in the PN junction between the drain and P-type diffusion regions. Since the breakdown voltage of the junction between the drain and P-type diffusion regions is lower, even after breakdown, the electrostatic charge will still flow to the source region through the aforementioned conductive channel and exit from the source region, thus triggering the parasitic transistor to turn on and discharge current. Therefore, this application can effectively reduce the turn-on voltage of electrostatic protection without changing the area occupied by the electrostatic protection device structure, while also improving its electrostatic protection capability, and can also be used in normal current output circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A cross-sectional view of an embodiment of the electrostatic protection device provided in this application is shown.

[0020] Figure 2 The diagram shows a top view of an embodiment of the electrostatic protection device provided in this application. Detailed Implementation

[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0025] The semiconductor conductivity type in this application includes an opposite first conductivity type and a second conductivity type, that is, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0026] N-type and P-type semiconductors are produced by doping semiconductors with different types of impurities. Doping a semiconductor with an element from Group V of the periodic table, such as arsenic or antimony, as a donor impurity, yields an N-type semiconductor. Doping a semiconductor with an element from Group III of the periodic table, such as boron or indium, as an acceptor impurity, yields a P-type semiconductor.

[0027] The conductivity of N-type semiconductors and P-type semiconductors is different.

[0028] Figure 1This illustration shows a cross-sectional view of an electrostatic discharge (ESD) protection device structure according to an embodiment of this application. Figure 2 The diagram shows a top view of an embodiment of the electrostatic protection device provided in this application.

[0029] The structure of this electrostatic discharge (ESD) protection device is described below using an example where the first conductivity type is P-type and the second conductivity type is N-type. From... Figure 1 and Figure 2 As can be seen from the diagram, the structure of this electrostatic protection device includes: a P-type substrate 210, a P-type well region 220, a source region 230, a drain region 240, and a polysilicon gate 250.

[0030] The P-type well region 220 is formed on the upper layer of the P-type substrate 210.

[0031] In the P-type well region 220, source regions 230 and drain regions 240 are formed in a finger-like arrangement along a lateral spacing, wherein the lateral direction is... Figure 1 The X-axis is shown in the figure. Both the source region 230 and the drain region 240 are N-type.

[0032] from Figure 1 As can be seen from the diagram, the electrostatic protection device has a horizontally symmetrical structure with two drain regions 240. These two drain regions 240 are connected to lead out the electrostatic input terminal of the electrostatic protection device structure, and each of the source regions 230 leads out the electrostatic output terminal of the electrostatic protection device structure. The electrostatic output terminal is grounded.

[0033] from Figure 1 and Figure 2 It can also be seen that a P-type diffusion region 241 is formed in the drain region 240. The P-type diffusion region 241 extends downward from the upper surface of the drain region 240 and has no leads. No metal silicide is formed at the boundary between the P-type diffusion region 241 and the drain region 240. In order to reduce parasitic resistance, metal silicide can be formed on other active regions except where the polysilicon isolation structure 260 is located.

[0034] The polysilicon gate 250 is located on the spacer region between the adjacent source region 230 and the drain region 240.

[0035] In this electrostatic discharge protection device structure, the adjacent drain region 240 and source region 230, and the P-type well region 220 located between the adjacent drain region 240 and source region 230, together form a parasitic transistor. The drain region 240 serves as the collector of the parasitic transistor, the source region 230 serves as the emitter of the parasitic transistor, and the P-type well region 220 located between the adjacent drain region 240 and source region 230 serves as the base of the parasitic transistor.

[0036] In this embodiment, the formation is as follows: Figure 1 The four parasitic transistors are shown.

[0037] In this embodiment, when electrostatic charge enters the electrostatic protection device structure from the drain, the parasitic transistor in the structure creates a conductive channel between the adjacent drain region 240 and source region 230. Because a P-type diffusion region 241 is inserted into the drain region 240, the breakdown location of the parasitic transistor is not initially located in the PN junction between the drain region 240 and the P-type well region 220 near the conductive channel, but rather the PN junction between the drain region 240 and the P-type diffusion region 241 is broken down first. Since the breakdown voltage of the junction between the drain region 240 and the P-type diffusion region 241 is lower, even after breakdown, the electrostatic charge will still flow through the aforementioned conductive channel to the source region 230 and out from the source region 230, thus triggering the parasitic transistor to turn on and discharge current. Therefore, this application can effectively reduce the electrostatic protection turn-on voltage and improve its electrostatic protection capability without changing the area occupied by the electrostatic protection device structure, and can also be used in normal current output circuits.

[0038] Continue to refer to Figure 1 and Figure 2 In this embodiment, the outermost part of the electrostatic protection device structure is the source region 230, and the remaining source regions 230 and drain regions 240 are adjacent to each other and arranged alternately.

[0039] Optionally, multiple P-type well regions 220 can be formed in a drain region 240, with the multiple P-type well regions 220 being spaced apart.

[0040] Reference Figure 2 A contact hole is formed on the drain region 240, through which the drain region 240 can be led out. The P-type well region 220 does not have a contact hole.

[0041] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. An electrostatic protection device structure, characterized by, The electrostatic protection device structure comprises: a first conductive type substrate, an upper layer of the first conductive type substrate forming a first conductive type well region; in the first conductive type well region, source regions and drain regions arranged at intervals in a lateral direction, the source regions and the drain regions both being of a second conductive type; all the drain regions being connected to lead out an electrostatic input end of the electrostatic protection device structure, and each of the source regions leading out an electrostatic output end of the electrostatic protection device structure; a first conductive type diffusion region inserted into the drain regions, the first conductive type diffusion region not being provided with a leading-out end, and no metal silicide being formed at the junction of the first conductive type diffusion region and the drain region; a polysilicon gate located on an interval region between the interval-adjacent source regions and the drain regions; wherein the interval-adjacent source regions and the drain regions, and the first conductive type well region between the interval-adjacent source regions and the drain regions together form a parasitic triode.

2. The electrostatic protection device structure of claim 1, wherein, The outermost side of the electrostatic protection device structure is the source region.

3. The electrostatic protection device structure of claim 1, wherein, A plurality of first conductive type diffusion regions are formed in one of the drain regions, and the plurality of first conductive type diffusion regions are spaced apart.

4. The electrostatic protection device structure of claim 1, wherein, A contact hole is formed on the drain region, and the drain region is led out through the contact hole.

5. The electrostatic protection device structure of claim 1, wherein, No contact hole is formed on the first conductive type diffusion region.

6. The electrostatic protection device structure of claim 1, wherein, When electrostatic charges enter the electrostatic protection device structure from the drain region, the PN junction between the drain region and the first conductive type diffusion region is broken down first.

7. The electrostatic protection device structure of claim 1, wherein the first and second semiconductor regions are formed of a same material. The electrostatic output end is grounded.

Images