Rework methods for metal-oxide-semiconductor thin-film transistor array substrates

Abstract

This invention provides a rework method for a metal-oxide-semiconductor thin-film transistor array substrate, comprising: patterning a first photoresist layer above corresponding to a first via and a second via; removing a first metal layer not covered by the first photoresist layer to form a residual source and a residual drain; removing the first photoresist layer; and patterning a second metal layer on an etch stop layer, the second metal layer including a reset source and a reset drain, the reset source covering and contacting the residual source, and the reset drain covering and contacting the residual drain. This rework method for the metal-oxide-semiconductor thin-film transistor array substrate can improve product yield and reduce manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a rework method for a metal oxide semiconductor thin film transistor array substrate. Background Technology

[0002] Liquid crystal display panels have advantages such as good image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and they dominate the flat panel display field.

[0003] A liquid crystal display panel consists of an opposing thin-film transistor array substrate and a color filter substrate, with liquid crystal molecules filling the space between them. Fabricating the thin-film transistor array substrate requires multiple deposition, photolithography, and etching processes to create the gate, gate insulating layer, semiconductor layer, source / drain electrodes, pixel electrodes, and protective layers of the thin-film transistors.

[0004] In thin-film transistor array substrates with metal oxide semiconductor layers, the source / drain electrodes need to contact and connect with the metal oxide semiconductor layer through vias on the etch barrier layer. When problems occur with the source / drain electrodes and the data lines and surrounding conductors formed on the same layer, requiring film stripping and rework, the entire metal layer forming the source / drain electrodes needs to be etched away using etching solution during the stripping and rework process. The etching solution will flow into the metal oxide semiconductor layer through the vias on the etch barrier layer and etch away the metal oxide at the via locations, ultimately causing the metal oxide semiconductor layer to malfunction.

[0005] Therefore, in the process of fabricating thin-film transistor array substrates using metal oxide semiconductors, if a batch-specific anomaly occurs in the metal layer forming the source / drain during the process, the entire semi-finished product can only be stripped multiple times to restore it to a smooth glass state or be scrapped. Moreover, multiple stripping will also damage the glass body, increasing the probability of subsequent breakage, ultimately resulting in a decrease in yield and an increase in manufacturing costs. Summary of the Invention

[0006] The purpose of this invention is to provide a rework method for metal oxide semiconductor thin film transistor array substrates, which can improve product yield and reduce manufacturing costs.

[0007] This invention provides a rework method for a metal-oxide-semiconductor (MOS) thin-film transistor (TFT) array substrate. The MOS TFT array substrate includes a substrate and a MOS layer, an etch barrier layer, and a first metal layer stacked on the substrate. The first metal layer includes an initial source and an initial drain spaced apart. The etch barrier layer has a first via and a second via. The initial source is connected to the MOS layer through the first via, and the initial drain is connected to the MOS layer through the second via. The rework method includes:

[0008] A first photoresist layer is patterned and formed above the positions corresponding to the first and second through holes;

[0009] Remove the first metal layer not covered by the first photoresist layer to form a residual source and a residual drain;

[0010] Remove the first photoresist layer; and

[0011] A second metal layer is patterned on the etch barrier layer. The second metal layer includes a reset source and a reset drain. The reset source covers the remaining source and is in contact with the remaining source. The reset drain covers the remaining drain and is in contact with the remaining drain.

[0012] Further, the metal-oxide-semiconductor thin-film transistor array substrate has a display area and a non-display area; the metal-oxide-semiconductor layer is located in the display area; the metal-oxide-semiconductor thin-film transistor array substrate further includes a gate metal layer, the gate metal layer including a gate located in the display area and a first peripheral conductor located in the non-display area, the gate being located above or below the metal-oxide-semiconductor layer; the first metal layer further includes a second peripheral conductor located in the non-display area, the second peripheral conductor being contacted and connected to the first peripheral conductor through a third via; the rework method further includes:

[0013] The first photoresist layer is also formed above the position corresponding to the third via;

[0014] When the first metal layer not covered by the first photoresist layer is removed, a second peripheral conductor is also formed.

[0015] When the second metal layer is patterned, the second metal layer also includes a reset second peripheral conductor, which covers the remaining second peripheral conductor and is in contact with the remaining second peripheral conductor.

[0016] Furthermore, the first photoresist layer includes a first photoresist pattern and a second photoresist pattern. The first photoresist pattern covers a portion of the initial source and the initial drain above the metal oxide semiconductor layer, as well as a portion of the etch barrier layer located between the initial source and the initial drain. The second photoresist pattern covers the second peripheral conductor above the location of the third via.

[0017] Furthermore, the same photomask is used when patterning the first metal layer and when patterning the second metal layer.

[0018] Furthermore, the method for patterning the second metal layer includes:

[0019] A thin metal film is formed on the etch barrier layer to cover the remaining source, the remaining drain, and the remaining second peripheral conductor;

[0020] A second photoresist layer is formed by patterning the metal thin film;

[0021] Remove the metal film not covered by the second photoresist layer; and

[0022] Remove the second photoresist layer.

[0023] Furthermore, the metal oxide semiconductor thin film transistor array substrate further includes a gate insulating layer, a gate metal layer formed on the substrate, the gate insulating layer formed on the substrate and covering the gate metal layer, a metal oxide semiconductor layer formed on the gate insulating layer, an etch barrier layer formed on the gate insulating layer and covering the metal oxide semiconductor layer, and a first metal layer formed on the etch barrier layer.

[0024] Furthermore, the thickness of the first metal layer is... The thickness of the second metal layer is

[0025] Furthermore, the material of the second metal layer is the same as the material of the first metal layer.

[0026] Furthermore, the material of the metal oxide semiconductor layer is indium gallium zinc oxide, indium zinc oxide, lanthanide rare earth doped indium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide.

[0027] Furthermore, the rework method also includes:

[0028] A first passivation layer is formed on the etch barrier layer, and the first passivation layer covers the second metal layer;

[0029] A planarization layer is formed on the first passivation layer;

[0030] A first electrode layer is formed on the planarization layer;

[0031] A second passivation layer is formed on the planarization layer, and the second passivation layer covers the first electrode layer;

[0032] A fourth via is formed at the location of the reset drain corresponding to the second passivation layer, the planarization layer, and the first passivation layer to expose the reset drain; and

[0033] A second electrode layer is patterned on the second passivation layer and then filled into the fourth via to make contact with the reset drain electrode.

[0034] In the rework method for a metal-oxide-semiconductor thin-film transistor array substrate provided by this invention, when a problem occurs in the first metal layer requiring rework, the first, second, and third vias are protected by retaining a portion of the first metal layer above them. During etching of the first metal layer, this prevents the etching solution from entering the metal-oxide-semiconductor layer through the first and second vias and etching it, thus preventing functional abnormalities in the metal-oxide-semiconductor layer. It also prevents the etching solution from entering the first peripheral conductive line through the third via and etching it, thus preventing abnormal connections to subsequently formed conductive lines. This improves product yield. Furthermore, the problem can be solved by adding only one photomask without damaging the array substrate, and it eliminates the need for multiple rework processes to achieve a smooth glass surface, reducing manufacturing costs.

[0035] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make other objects, features and advantages of the above-mentioned rework method of the metal oxide semiconductor thin film transistor array substrate of the present invention more apparent, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0036] Figures 1 to 9 This is a schematic diagram of the cross-sectional structure of the metal oxide semiconductor thin film transistor array substrate in each step of the rework method of the metal oxide semiconductor thin film transistor array substrate according to a preferred embodiment of the present invention. Detailed Implementation

[0037] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of the rework method for a metal-oxide-semiconductor thin-film transistor array substrate proposed according to the present invention:

[0038] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0039] The preferred embodiment of the present invention provides a rework method for a metal-oxide-semiconductor thin-film transistor array substrate, which is used when a problem occurs in the metal layer of the metal-oxide-semiconductor thin-film transistor array substrate and rework is required. Please refer to [link to relevant documentation]. Figure 1 The metal-oxide-semiconductor thin-film transistor array substrate includes a substrate 110 and a metal-oxide-semiconductor layer 140, an etch stop layer 150, and a first metal layer 160 stacked on the substrate 110. The first metal layer 160 includes an initial source 161 and an initial drain 162 spaced apart. The etch stop layer 150 has a first via 150a and a second via 150b. The initial source 161 is contacted and connected to the metal-oxide-semiconductor layer 140 through the first via 150a, and the initial drain 162 is contacted and connected to the metal-oxide-semiconductor layer 140 through the second via 150b.

[0040] In this embodiment, the metal oxide semiconductor thin film transistor array substrate has a display area 101 and a non-display area 102, and the metal oxide semiconductor layer 140 is located in the display area 101.

[0041] The metal oxide semiconductor thin film transistor array substrate also includes a gate metal layer 120, which includes a gate 121 located in the display area 101 and a first peripheral conductor 122 located in the non-display area 102.

[0042] The gate 121 may be located above or below the metal oxide semiconductor layer 140. In this embodiment, the gate 121 is formed before the metal oxide semiconductor layer 140, and therefore is located below the metal oxide semiconductor layer 140.

[0043] Furthermore, the first metal layer 160 also includes a second peripheral conductor 163 located in the non-display area 102, which is connected to the first peripheral conductor 122 through a third through hole 150c.

[0044] Furthermore, the metal oxide semiconductor thin film transistor array substrate also includes a gate insulating layer 130, a gate metal layer 120 formed on the substrate 110, a gate insulating layer 130 formed on the substrate 110 and covering the gate metal layer 120, a metal oxide semiconductor layer 140 formed on the gate insulating layer 130, an etch stop layer 150 formed on the gate insulating layer 130 and covering the metal oxide semiconductor layer 140, and a first metal layer 160 formed on the etch stop layer 150.

[0045] Please refer to Figures 2 to 4 The rework methods for metal-oxide-semiconductor thin-film transistor array substrates specifically include:

[0046] like Figure 2 As shown, a first photoresist layer 210 is patterned and formed above the positions corresponding to the first through-hole 150a and the second through-hole 150b. The specific process of patterning and forming the first photoresist layer 210 includes photoresist coating, exposure, and development.

[0047] Furthermore, the first photoresist layer 210 is also formed above the position corresponding to the third via 150c.

[0048] Specifically, the first photoresist layer 210 includes a first photoresist pattern 211 and a second photoresist pattern 212. The first photoresist pattern 211 covers a portion of the initial source 161 and initial drain 162 above the metal oxide semiconductor layer 140, as well as a portion of the etch barrier layer 150 located between the initial source 161 and initial drain 162. The second photoresist pattern 212 covers the second peripheral conductor 163 above the location of the third via 150c.

[0049] like Figure 3 As shown, the first metal layer 160 not covered by the first photoresist layer 210 is removed to form a residual source electrode 1611 and a residual drain electrode 1621. Specifically, the first metal layer 160 not covered by the first photoresist layer 210 is etched away using an etching solution to form the residual source electrode 1611 and the residual drain electrode 1621, wherein the residual source electrode 1611 is filled in the first via 150a and the residual drain electrode 1621 is filled in the second via 150b.

[0050] Furthermore, when the first metal layer 160 not covered by the first photoresist layer 210 is removed, a second peripheral conductor 1631 is also formed.

[0051] like Figure 4 As shown, the first photoresist layer 210 is removed; and

[0052] A second metal layer 170 is patterned on the etch barrier layer 150. The second metal layer 170 includes a reset source 171 and a reset drain 172. The reset source 171 covers the remaining source 1611 and is in contact with the remaining source 1611. The reset drain 172 covers the remaining drain 1621 and is in contact with the remaining drain 1621.

[0053] Furthermore, during the patterning formation of the second metal layer 170, the second metal layer 170 also includes a reset second peripheral conductor 173, which covers the remaining second peripheral conductor 1631 and contacts and connects with the remaining second peripheral conductor 1631.

[0054] In this embodiment, the same photomask is used for both the patterning of the first metal layer 160 and the patterning of the second metal layer 170. The process for patterning the metal layer includes cleaning, applying photoresist, exposure, development, and photoresist removal.

[0055] Specifically, please refer to Figures 5 to 8 The method for patterning the second metal layer 170 includes:

[0056] like Figure 5 As shown, a metal thin film 17 is formed on the etch barrier layer 150, covering the remaining source electrode 1611, the remaining drain electrode 1621 and the remaining second peripheral conductor 1631.

[0057] like Figure 6 As shown, a second photoresist layer 220 is patterned on the metal thin film 17;

[0058] like Figure 7 As shown, the metal thin film 17 not covered by the second photoresist layer 220 is removed; and

[0059] like Figure 8 As shown, the second photoresist layer 220 is removed.

[0060] In this embodiment, the preferred thickness of the first metal layer 160 is... The preferred thickness of the second metal layer 170 is... The thickness of the first metal layer 160 and the thickness of the second metal layer 170 can be the same, so that the same process and parameters can be used when forming the first metal layer 160 and the second metal layer 170.

[0061] After the second metal layer 170 is formed, the position corresponding to the first photoresist layer 210 will be thicker than the second metal layer 170 at other positions because it simultaneously has the first metal layer 160 and the second metal layer 170. When etching the metal thin film 17 to form the second metal layer 170, adjusting the etching process parameters appropriately can prevent etching from being too fast and forming sharp corners.

[0062] Furthermore, the material of the second metal layer 170 is the same as that of the first metal layer 160. For example, both use a three-layer structure of molybdenum (Mo) / aluminum (Al) / molybdenum (Mo).

[0063] Furthermore, the metal oxide semiconductor layer 140 is made of an oxide containing at least one or more elements selected from zinc, indium, gallium, tin, aluminum, silicon, scandium, titanium, vanadium, yttrium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, and lanthanides. Examples include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), lanthanide rare earth doped indium zinc oxide (Ln-IZO), indium tin zinc oxide (ITZO), or indium gallium zinc tin oxide (IGZTO).

[0064] Furthermore, the rework method for the metal-oxide-semiconductor thin-film transistor array substrate also includes:

[0065] A first passivation layer 181 is formed on the etch barrier layer 150, and the first passivation layer 181 covers the second metal layer 170;

[0066] A planarization layer 182 is formed on the first passivation layer 181;

[0067] A first electrode layer 183 is formed on the planarization layer 182;

[0068] A second passivation layer 184 is formed on the planarization layer 182, and the second passivation layer 184 covers the first electrode layer 183;

[0069] A fourth via 184a is formed at the position corresponding to the reset drain 172 in the second passivation layer 184, planarization layer 182, and first passivation layer 181 to expose the reset drain 172; and

[0070] A second electrode layer 185 is patterned on the second passivation layer 184 and the second electrode layer 185 is filled into the fourth via 184a and makes contact with the reset drain 172.

[0071] Experiments have shown that after the planarization layer is formed in subsequent processes, no protrusions will be formed at the positions of the remaining source electrode 1611 and the remaining drain electrode 1621, which would cause height differences in the spacers (PS) within the liquid crystal layer.

[0072] The rework method for a metal-oxide-semiconductor thin-film transistor array substrate provided in this invention addresses the issue of rework required when the first metal layer 160 malfunctions and needs to be removed. By retaining a portion of the first metal layer 160 above the first vias 150a, 150b, and 150c, the method protects these vias. During etching of the first metal layer 160, this prevents the etching solution from entering the metal-oxide-semiconductor layer 140 through the first and second vias 150a and 150b, thus preventing malfunctions in the metal-oxide-semiconductor layer 140. It also prevents the etching solution from entering the first peripheral conductor 122 through the third via 150c, thus preventing abnormal connections to subsequently formed conductors. This improves product yield. Furthermore, the problem can be solved simply by adding a photomask, without damaging the array substrate. It also eliminates the need for multiple removals of the film to achieve a smooth glass finish, reducing manufacturing costs.

[0073] The rework method for the metal oxide semiconductor thin film transistor array substrate provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for reworking a metal-oxide-semiconductor thin-film transistor array substrate, the metal-oxide-semiconductor thin-film transistor array substrate comprising a substrate (110) and a metal-oxide-semiconductor layer (140), an etch stop layer (150), and a first metal layer (160) stacked on the substrate (110), the first metal layer (160) comprising an initial source (161) and an initial drain (162) spaced apart, the etch stop layer (150) having a first via (150a) and a second via (150b), the initial source (161) being contacted and connected to the metal-oxide-semiconductor layer (140) through the first via (150a), and the initial drain (162) being contacted and connected to the metal-oxide-semiconductor layer (140) through the second via (150b), characterized in that, The rework methods include: A first photoresist layer (210) is patterned above the positions corresponding to the first through hole (150a) and the second through hole (150b); Remove the first metal layer (160) that is not covered by the first photoresist layer (210) to form a residual source (1611) and a residual drain (1621); Remove the first photoresist layer (210); and A second metal layer (170) is patterned on the etch barrier layer (150). The second metal layer (170) includes a reset source (171) and a reset drain (172). The reset source (171) covers the remaining source (1611) and is in contact with the remaining source (1611). The reset drain (172) covers the remaining drain (1621) and is in contact with the remaining drain (1621).

2. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 1, characterized in that, The metal-oxide-semiconductor thin-film transistor array substrate has a display area (101) and a non-display area (102); the metal-oxide-semiconductor layer (140) is located in the display area (101); the metal-oxide-semiconductor thin-film transistor array substrate further includes a gate metal layer (120), the gate metal layer (120) includes a gate (121) located in the display area (101) and a first peripheral conductor (122) located in the non-display area (102), the gate (121) being located above or below the metal-oxide-semiconductor layer (140); the first metal layer (160) further includes a second peripheral conductor (163) located in the non-display area (102), the second peripheral conductor (163) being contacted and connected to the first peripheral conductor (122) through a third via (150c); the rework method further includes: The first photoresist layer (210) is also formed above the position corresponding to the third via (150c); When the first metal layer (160) not covered by the first photoresist layer (210) is removed, a second peripheral conductor (1631) is also formed. When the second metal layer (170) is patterned, the second metal layer (170) also includes a reset second peripheral conductor (173), which covers the remaining second peripheral conductor (1631) and is in contact with the remaining second peripheral conductor (1631).

3. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 2, characterized in that, The first photoresist layer (210) includes a first photoresist pattern (211) and a second photoresist pattern (212). The first photoresist pattern (211) covers a portion of the initial source (161) and the initial drain (162) above the metal oxide semiconductor layer (140), and a portion of the etch barrier layer (150) between the initial source (161) and the initial drain (162). The second photoresist pattern (212) covers the second peripheral conductor (163) above the location of the third via (150c).

4. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 2, characterized in that, The same photomask is used when patterning the first metal layer (160) and when patterning the second metal layer (170).

5. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 4, characterized in that, The method for patterning to form the second metal layer (170) includes: A metal thin film (17) is formed on the etching barrier layer (150) to cover the remaining source electrode (1611), the remaining drain electrode (1621) and the remaining second peripheral conductor (1631); A second photoresist layer (220) is formed by patterning the metal thin film (17); Remove the metal film (17) not covered by the second photoresist layer (220); and Remove the second photoresist layer (220).

6. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 2, characterized in that, The metal-oxide-semiconductor thin-film transistor array substrate further includes a gate insulating layer (130), a gate metal layer (120) formed on the substrate (110), the gate insulating layer (130) formed on the substrate (110) and covering the gate metal layer (120), the metal-oxide-semiconductor layer (140) formed on the gate insulating layer (130), the etch barrier layer (150) formed on the gate insulating layer (130) and covering the metal-oxide-semiconductor layer (140), and the first metal layer (160) formed on the etch barrier layer (150).

7. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 1, characterized in that, The thickness of the first metal layer (160) is The thickness of the second metal layer (170) is 8. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 1, characterized in that, The material of the second metal layer (170) is the same as that of the first metal layer (160).

9. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 1, characterized in that, The material of the metal oxide semiconductor layer (140) is indium gallium zinc oxide, indium zinc oxide, lanthanide rare earth doped indium zinc oxide, indium tin zinc oxide or indium gallium zinc tin oxide.

10. The rework method for a metal-oxide-semiconductor thin-film transistor array substrate as described in claim 1, characterized in that, Also includes: A first passivation layer (181) is formed on the etch barrier layer (150), and the first passivation layer (181) covers the second metal layer (170); A planarization layer (182) is formed on the first passivation layer (181); A first electrode layer (183) is formed on the planar layer (182); A second passivation layer (184) is formed on the planarization layer (182), and the second passivation layer (184) covers the first electrode layer (183); A fourth via (184a) is formed in the second passivation layer (184), the planarization layer (182), and the first passivation layer (181) at the position corresponding to the reset drain (172) to expose the reset drain (172); and A second electrode layer (185) is patterned on the second passivation layer (184) and the second electrode layer (185) is filled into the fourth via (184a) and makes contact with the reset drain (172).

Images