semiconductor element

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend toward a first direction. The gates include a first gate and a second gate. The first gate has a first sidewall distanced from the second gate and a second sidewall proximate to the second gate. A first extension is disposed on the first sidewall of the first gate and extends toward a second direction beyond the first sidewall. The plugs are disposed on the substrate in parallel to each other. The plugs include a first plug and a second plug. The first plug covers the first gate and the first extension. The second plug covers the second gate. A central axis of the first plug is offset from a central axis of the first gate and offset toward the second direction.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201610640986.8, application date: August 8, 2016, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a metal gate and plug structure and a method for forming the same. Background Technology

[0003] As the linewidth of semiconductor manufacturing processes continues to shrink, the size of semiconductor devices continues to miniaturize. However, as the linewidth of current semiconductor manufacturing processes has been miniaturized to a certain extent, the integration manufacturing process of semiconductor structures with metal gates has also presented more challenges and bottlenecks.

[0004] To achieve high integration and high-speed operation in miniaturized semiconductor devices, conventional techniques utilize miniaturized vias and interlayer dielectric layers to form multi-layer interconnected wiring structures. These structures electrically connect the metal gates and source / drain regions of transistors, serving as input / output terminals for external electronic signals. However, conventional techniques encounter bottlenecks due to optical limitations when combining metal gates and contact plugs in the fabrication process. For example, the poor placement of the contact plugs connecting the gates or source / drain regions can affect the overall electrical performance of the device. Therefore, effectively improving the fabrication process and architecture of semiconductor devices is a crucial issue today. Summary of the Invention

[0005] One object of the present invention is to provide a method for forming a semiconductor device, which can effectively improve the placement between the plug and the metal gate, and is beneficial to forming a semiconductor device with better reliability.

[0006] One object of the present invention is to provide a semiconductor device in which the coverage between each plug and the metal gate can reach more than 70%, thereby effectively improving the device reliability of the semiconductor device.

[0007] To achieve the above objectives, an embodiment of the present invention provides a method for forming a semiconductor device, comprising the following steps: First, a substrate is provided. Next, a plurality of gates are formed on the substrate, the gates extending toward a first direction, the gates including a first gate and a second gate, wherein the first gate includes a first extension extending toward a second direction. Then, a plurality of plugs parallel to each other are formed on the substrate, the plugs including a first plug and a second plug, wherein the first plug and the second plug respectively cover the first gate and the second gate, the central axis of the first plug being offset from the central axis of the first gate and offset toward the second direction, and the central axis of the second plug being offset from the central axis of the second gate and offset toward the second direction.

[0008] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device comprising a substrate, a plurality of gates, and a plurality of plugs. The gates are disposed on the substrate and extend toward a first direction. The gates include a first gate and a second gate, wherein the first gate includes a first extension that extends toward a second direction. The plugs are disposed parallel to each other on the substrate. The plugs include a first plug and a second plug, wherein the first plug and the second plug respectively cover the first gate and the second gate, the central axis of the first plug being offset from the central axis of the first gate and offset toward the second direction, and the central axis of the second plug being offset from the central axis of the second gate and offset toward the second direction.

[0009] The semiconductor element formation method of the present invention involves forming extensions of different sizes on the left or right side of each gate, in accordance with the offset direction and offset distance of the plug for subsequent electrical connection to the metal gate. This increases the coverage of the plug relative to each gate, achieving a coverage of 70% or more. Attached Figure Description

[0010] Figures 1 to 2 A schematic diagram illustrating a method for forming a semiconductor element according to a first embodiment of the present invention is shown, wherein:

[0011] Figure 1 A schematic diagram of a semiconductor device at the beginning of its fabrication process is shown.

[0012] Figure 2 A schematic diagram of a semiconductor device after a plug has been formed;

[0013] Figure 3 A top view schematic diagram of a semiconductor element in a second embodiment of the present invention is shown;

[0014] Figure 4 A schematic diagram illustrating the actual wiring layout of a semiconductor element according to a preferred embodiment of the present invention is shown.

[0015] Figure 5 Draw Figure 4 A cross-sectional view along the tangent A-A'.

[0016] Explanation of main component symbols

[0017] 200 interlayer dielectric layers

[0018] 300 base

[0019] 301 Fin-like structure

[0020] 302 Shallow trench isolation

[0021] 331 High Dielectric Constant Gate Dielectric Layer

[0022] 332 Work Function Layer

[0023] 333 Metal Conductive Layer

[0024] 334 Cap Layer

[0025] 335 spacer wall

[0026] 336 Source / Drain Region

[0027] Gates 340, 341, 343, 345, 347, 349

[0028] Extensions 342, 344, 346, and 348

[0029] 344a, 348a Part 1

[0030] Part 2 of 344b and 348b

[0031] 360 plug

[0032] 360a and 360b partial plugs

[0033] Plugs 380, 381, 383, 385, 387, 389

[0034] D1 First Direction

[0035] D2 Second Direction

[0036] D3 third direction

[0037] The central axis of gates G1, G2, G3, G4, and G5

[0038] H horizontal axis

[0039] Lengths of L1, L2, L3, and L4

[0040] The central axis of plugs P1, P2, P3, P4, and P5

[0041] Offset distances of S1, S2, S3, and S4

[0042] V axis of symmetry Detailed Implementation

[0043] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.

[0044] Please refer to Figures 1 to 4 The illustration shows the steps of a method for forming a semiconductor element in the first embodiment of the present invention. First, as... Figure 1 As shown, a substrate 300 is provided. The substrate 300 is, for example, a silicon substrate, an epitaxial silicon substrate, or a silicon on insulation (SOI) substrate, and a plurality of gates 340 are formed on the substrate 300.

[0045] In this embodiment, at least one fin structure 301 and an insulating layer 302 can be formed on the substrate 300 first. The fin structure 301 extends in a second direction D2 (e.g., the x-direction), and a gate 340 is formed across it. The fin structure 301 can be formed, for example, using spacer self-aligned double-patterning (SADP). A patterned mask (not shown) is formed on the substrate 300, and then an etching process is used to transfer the pattern of the patterned mask to the substrate 300. The patterned mask is then removed, forming multiple trenches (not shown) in the substrate 300. Subsequently, the insulating layer 302 is filled into these trenches, so that the substrate 300 protruding from the insulating layer 302 forms the fin structure 301, and the insulating layer 302 can form shallow trench isolation (STI). In other embodiments, if the formed transistor is a planar transistor, the fin structure can be omitted, and at least one shallow trench isolation (not shown) can be formed on the planar substrate (not shown) to define different active areas (AA, not shown) on the substrate 300, and a gate (not shown) spanning these active areas can be formed directly on the planar substrate. In one embodiment, the gate 340 is formed, for example, by first forming multiple dummy gates (not shown) on the substrate 300, and then performing a replacement metal gate (RMG) fabrication process to form the gate 340. However, those skilled in the art will readily understand that in another embodiment, the gate 340 can also be formed directly on the substrate 300.

[0046] Specifically, the gates 340 are arranged parallel to each other in a first direction D1 (e.g., the y-direction) perpendicular to the second direction D2, and preferably arranged symmetrically to each other along an axis of symmetry V. Figure 1 As shown. The two outermost gates 340 are, for example, dummy gates, but are not limited to this. It should be noted that gates 341 and 343 between the axis of symmetry V and the dummy gate on one side (e.g., the right side) have additional extensions 342 and 344. Extensions 342 and 344 extend from the right side of gates 341 and 343 toward the second direction D2, respectively. Figure 1As shown. The extension 342 of the gate 341 extends in the second direction D2 for a length L1, for example, approximately 1 nanometer to 3 nanometers; while the extension 344 of the gate 343 has a stepped structure and a length L2, for example, approximately 2 nanometers to 6 nanometers. Specifically, the size of the extension 342 is, for example, 1 / 5 to 1 / 10 of the size of the gate 341; and the extension 344 includes a first portion 344a extending from the sidewall of the gate 343, and a second portion 344b extending from the sidewall of the first portion 344a. The overall size of the first part 344a is, for example, 1 / 5 to 1 / 10 of the overall size of the gate 343, and preferably has the same length as the length L1 of the extension 342 in the first direction D1. The overall size of the second part 344b is, for example, 1 / 10 to 1 / 20 of the overall size of the gate 343, and preferably has a shorter length than the first part 344a in the first direction D1, thereby avoiding excessive stress on the gates 341 and 343.

[0047] On the other hand, gates 345 and 347, located between the axis of symmetry V and the dummy gate on the other side (e.g., the left side), also extend with extensions 346 and 348. Extensions 346 and 348 extend from the left side of gates 345 and 347 toward a third direction D3, away from the second direction D2, respectively. Figure 1 As shown. The extension 346 of the gate 345 has a length L3, for example, approximately 1 nanometer to 3 nanometers, on a third-direction D3; while the extension 348 of the gate 347 has a stepped structure and a length L4, for example, approximately 2 nanometers to 6 nanometers. Specifically, the size of the extension 346 is, for example, 1 / 5 to 1 / 10 of the size of the gate 345; and the extension 348 includes a first portion 348a extending from the sidewall of the gate 347, and a second portion 348b extending from the sidewall of the first portion 348a. The overall size of the first portion 348a is, for example, 1 / 5 to 1 / 10 of the overall size of the gate 347, and preferably has the same length as the length L3 of the extension 346 in the first direction D1. The overall size of the second portion 348b is, for example, 1 / 10 to 1 / 20 of the overall size of the gate 347, and preferably has a shorter length than the first portion 348a in the first direction D1, thereby avoiding excessive stress on the gates 345 and 347.

[0048] Next, as Figure 2As shown, multiple contact plugs 380 form the metal gates that electrically connect to the gate 340. The plugs 380 are formed within an interlayer dielectric layer (ILD, not shown) above the gate 340. Specifically, the plugs 380 are formed, for example, by first forming a patterned mask, such as a patterned photoresist layer (not shown), on the interlayer dielectric layer, and then performing an etching process, such as a dry etching process, using the patterned photoresist layer as an etching mask to form multiple contact holes (not shown) that penetrate the interlayer dielectric layer to the metal gates of each gate 340. Then, after removing the patterned photoresist layer, a cleaning process can be performed first, such as cleaning the surface of the contact hole formed above with argon (Ar) to remove etching residues. Then, a metallization process and a contact plug process are sequentially performed in the contact hole to form a plug 380 in each contact hole.

[0049] Inserts 380 are formed above gates 340, and in the projection direction perpendicular to the substrate 300, each insert 380 covers gates 341, 343, 345, 347 and their extensions 342, 344, 346, 348, and preferably covers the central axes G1, G2, G3, G4 of gates 341, 343, 345, 347. In this embodiment, each insert 380 is preferably formed parallel to each other on the same horizontal axis H, and is also arranged symmetrically to the left and right of the axis of symmetry V, such as... Figure 2 As shown. Specifically, the plugs 381 and 383, located to the right of the axis of symmetry V, each have a central axis P1 and P2 in the first direction D1, respectively. The central axes P1 and P2 of the plugs 381 and 383 are offset from the central axes G1 and G2 of the gates 341 and 343, respectively, and are all offset towards the second direction D2, as shown. Figure 2 As shown. However, it should be noted that the directions of the offset of the central axes P1 and P2 of plugs 381 and 383 are the same as the extension directions of the extensions 342 and 344 of gates 341 and 343. Therefore, plugs 381 and 383 can completely cover the gates 341 and 343 below and their extensions 342 and 344. In addition, it should be noted that the offset distance S2 between the central axis P2 of plug 383 and the central axis G2 of gate 343 is greater than the offset distance S1 between the central axis P1 of plug 381 and the central axis G1 of gate 341. However, because the extension 344 of gate 343 has a longer length L2 and a larger size than the extension 342, it can be ensured that the coverage of plug 383 relative to gate 343 is maintained at a certain level, for example, about 70%.

[0050] Similarly, the plugs 385 and 387, located on the left side of the axis of symmetry V, each have a central axis P3 and P4 in the first direction D1, respectively. The central axes P3 and P4 of the plugs 385 and 387 are offset from the central axes G3 and G4 of the gates 345 and 347, respectively, and are all offset towards the third direction D3. Figure 2 As shown. However, it should be noted that the directions of the offset of the central axes P3 and P4 of the plugs 385 and 387 are the same as the extension directions of the extensions 346 and 348 of the gates 345 and 347. Therefore, the plugs 385 and 387 can completely cover the gates 345 and 347 and their extensions 346 and 348 below. In addition, it should also be noted that the offset distance S4 between the central axis P4 of the plug 387 and the central axis G4 of the gate 347 is greater than the offset distance S3 between the central axis P3 of the plug 385 and the central axis G3 of the gate 345. However, because the extension 348 of the gate 347 has a longer length L4 and a larger size than the extension 346, it can be ensured that the coverage of the plug 387 relative to the gate 347 is maintained at a certain level, for example, about 70%.

[0051] Thus, the semiconductor element in the first preferred embodiment of the present invention is formed. The formation method of this embodiment involves sequentially forming a plurality of gates 340 and a plurality of plugs 380 on a substrate 300, with the gates 340 and plugs 380 arranged symmetrically on the substrate 300, corresponding to the axis of symmetry V. The gates 340 are formed, for example, using a spacer-wall self-aligned double-patterning method, and each gate 340 may have a small pitch. The subsequently formed plugs 380 are formed, for example, using a conventional photolithography etching process, and therefore, the plugs 380 will have a larger pitch. In this case, the placement position of some plugs 380 cannot completely correspond to the placement position of the gates 340, so that the plugs 380 covering each gate 340 often shift to the left or right of the axis of symmetry V. However, in this embodiment, the gate 340, in accordance with the offset directions D2, D3 and offset distances S1, S2, S3, S4 of the subsequent plug 380, further forms extensions 342, 344 and 346, 348 on the right side of the gates 341, 343 located on the right side of the axis of symmetry V and on the left side of the gates 345, 347 located on the left side of the axis of symmetry V, respectively. This allows the gates 341, 343 and 345, 347 to have a larger process window in the portions where the extensions 342, 344 and 346, 348 are formed. As a result, the plug 380 in the semiconductor device can have a high coverage relative to each gate 340, preferably reaching a coverage of 70% or more. Furthermore, the dimensions and structure of the extensions 342, 344, 346, and 348 can be adjusted to match the offset distances S1, S2, S3, and S4 of the plug 380. For example, the extensions 344 and 348 can have a stepped structure and a larger length L2 and L4 relative to the extensions 342 and 346.

[0052] It will be readily understood by those skilled in the art that, in this invention, the length and direction of the extension portion extending from each gate are adjusted according to the formation position of the subsequent plug or the actual manufacturing process requirements, and are not limited to the foregoing embodiments. For example, in other embodiments, other gates (not shown) may be formed to the right of gate 343, and an extension (not shown) having the same stepped structure and extending along the second direction D2 may be further formed on these gates. The extension may have a length in the second direction D2 greater than the length L2 of the extension 344, for example, it may be composed of a first part, a second part, and a third part (not shown) or a first part, a second part, a third part, and a fourth part (not shown). Alternatively, other gates (not shown) may be formed to the left of gate 347, and an extension (not shown) having the same stepped structure and extending along the third direction D3 may be further formed on these gates. The extension may have a length in the third direction D3 greater than the length L4 of the extension 348, for example, it may be composed of a first part, a second part, and a third part (not shown) or a first part, a second part, a third part, and a fourth part (not shown), but is not limited thereto.

[0053] Other embodiments of the semiconductor element of the present invention will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0054] Please refer to Figure 3 As shown, the illustration is a top view schematic diagram of a semiconductor element in a second preferred embodiment of the present invention. The semiconductor element in this embodiment is generally similar to that in the first embodiment described above. Figure 2 The same applies, and will not be repeated here. The main difference between this embodiment and the previous embodiment is that the semiconductor element in this embodiment also has a gate 349 and a plug 389 covering the gate 349 on the axis of symmetry V.

[0055] In this embodiment, the gate 349 is located between gates 341 and 345, and the plug 389 formed above the gate 349 not only completely covers the gate 349, but its central axis G5 and the central axis P5 of the plug 389 also correspond to the axis of symmetry V, as shown. Figure 3As shown. That is, the central axis P5 of the plug 389 overlaps with the central axis G5 of the gate 349, and the coverage between the plug 389 and the gate 349 reaches 100%. Therefore, the gate 349 does not need to form any additional extension. However, the plugs 381 and 383 located to the right of the axis of symmetry V have their central axes P1 and P2 offset in the second direction D2. Therefore, the gates 341 and 343 below them have additional extensions 342 and 344 extending in the second direction D2, thereby ensuring that the coverage between the gates 341 and 343 and the plugs 381 and 383 can be maintained at more than 70%. The offset distance S2 between the central axis P2 of the plug 383 and the central axis G2 of the gate 343 is larger than the offset distance S2 between the central axis P1 of the plug 381 and the central axis G1 of the gate 341. Therefore, the extension 344 formed on the gate 343 has a larger length than the extension 342. Figure 3 As shown. Similarly, the plugs 385 and 387 located to the left of the axis of symmetry V have their central axes P3 and P4 offset towards the third direction D3. Therefore, the gates 345 and 347 below them have additional extensions 346 and 348 extending towards the third direction D3, thereby ensuring that the coverage between the gates 345 and 347 and the plugs 385 and 387 can be maintained at more than 70%. The offset distance S4 between the central axis P4 of the plug 387 and the central axis G4 of the gate 347 is larger than the offset distance S3 between the central axis P3 of the plug 385 and the central axis G3 of the gate 345. Therefore, the extension 348 formed on the gate 347 has a larger length than the extension 346. Figure 3 As shown.

[0056] Therefore, the forming method of the present invention involves forming extensions of different sizes on the left or right side of each gate in accordance with the offset direction and offset distance of the plug for subsequent electrical connection to the metal gate. This increases the coverage of the plug relative to each gate, achieving a coverage of over 70%, while also improving the manufacturing process margin. Furthermore, in the semiconductor device of the present invention, the extension length and structure of the extensions formed on each gate can be adjusted in accordance with the offset distance of the plug; therefore, the extensions can have a stepped structure and gradually increasing dimensions. For example, each extension may be composed of a first portion; a first portion and a second portion; a first portion, a second portion and a third portion; ... a first portion to an Nth portion, etc., and the first portion, the second portion... to the Nth portion all have a size smaller than that of the gate to avoid the gate bearing excessive stress. In addition, each of the aforementioned portions must have a length at least greater than or equal to that of the plug in the direction parallel to the gate to ensure that the coverage of the plug relative to each gate reaches a certain level.

[0057] Furthermore, those skilled in the art will readily understand that although the foregoing embodiments of the present invention are described with the gate at the bottom and the plug at the top as implementation examples, the scope of the present invention is not limited thereto. In other embodiments, a plug-at-the-bottom, gate-at-the-top configuration may also be chosen, or other corresponding elements may be formed, such as plugs and wires, to improve the coverage of its fabrication process margin. Next, please refer to Figure 4 and Figure 5 The diagram illustrates a schematic representation of the actual wiring layout of a semiconductor element in a preferred embodiment of the present invention. The semiconductor element includes a plurality of gates 340 spanning a fin structure 301.

[0058] Each gate 340 is specifically composed of a high-dielectric-constant gate dielectric layer 331, a work function layer 332, a conductive layer 333, and a capping layer 334 sequentially stacked on the substrate 300, a spacer 335 located on both sides of these stacked layers, and a source / drain region 336 formed within the fin structure 301. Figure 5 As shown. The work function layer 332 may contain materials such as tantalum nitride (TaN), titanium nitride (TiN), titanium aluminide (TiAl), or aluminum zirconium (ZrAl); the metal conductive layer 333 may contain materials such as tungsten (W) or aluminum (Al) to serve as the metal gates of each gate 340; the cap layer 334 may contain materials such as silicon nitride (SiN) or silicon carbonitride (SiCN); the spacer wall 335 may be a single-layer or composite film structure, for example, it may contain materials with good etching resistance and coverage such as high-temperature oxide (HTO), silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride (HCD-SiN) formed using hexachlorodisilane (Si2Cl6), but is not limited thereto.

[0059] The semiconductor device further includes a plurality of contact slots 360 electrically connected to the source / drain regions 336 of the gate 340 and a plurality of contact slots 380 electrically connected to the metal gate, wherein the contact slots 360 and 380 are formed within the interlayer dielectric layer 200. In one embodiment, the contact slots 360 and 380 are formed together in the same interlayer dielectric layer 200, for example, using the same photolithography etching process; alternatively, the contact slots 360 located on both sides of the gate 340 may be formed first, followed by the contact slots 380. Preferably, the contact slot 360 is an extending strip-shaped structure parallel to the extension direction of the gate 340 (i.e., the first direction D1). That is, in this embodiment, the strip-shaped contact slot 360 extends over the source / drain regions 336 to increase its contact area with the source / drain regions 336. However, in one embodiment, to avoid the plug 360 affecting the manufacturing process of the plug 380, at least one slot cut pattern (not shown) can be pre-formed before forming the plug 360 to cut the extended strip of part of the plug 360 into two parts 360a and 360b, such as... Figure 4 As shown. However, those skilled in the art will readily understand that the size, shape, number, and layout of the plug can be adjusted according to manufacturing process requirements and are not limited to the foregoing. In other embodiments, a contact groove with a single opening may also be selected.

[0060] It should be noted that although the plug 380 covers the gates 341 and 343, it is slightly offset in the second direction D2. Therefore, the gates 341 and 343 are additionally provided with extensions 342 and 344 extending in the second direction D2 to ensure that the coverage of the plugs 381 and 383 relative to the gates 341 and 343 can be maintained at a certain level, for example, about 70%. In addition, the offset distance of the plug 383 is greater than that of the plug 381. Therefore, the extension 344 of the gate 343 has a stepped structure and has a greater length and size in the second direction D2 than the extension 342, to ensure that the plug 383 is in reliable contact with the metal gate. Figure 5 As shown.

[0061] Therefore, in accordance with the offset direction and offset distance of the plug for subsequent electrical connection to the metal gate, the present invention forms extensions of different sizes on the left or right side of each gate. This increases the coverage of the plug relative to each gate, achieving a coverage of over 70%, and also improves the manufacturing process tolerance of the plug.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that... Include: Base; A plurality of gates are disposed on the substrate and extend toward a first direction. The plurality of gates include a first gate and a second gate located on one side of the first gate in a second direction. The first gate includes a first sidewall away from the second gate and a second sidewall close to the second gate. A first extension is disposed on the first sidewall of the first gate and extends toward the second direction, protruding from the first sidewall. as well as Multiple plugs are disposed parallel to each other on the substrate. The multiple plugs include a first plug and a second plug. The first plug covers the first gate and the first extension, and the second plug covers the second gate. The central axis of the first plug is offset from the central axis of the first gate and is offset toward the second direction. The central axis of the second plug overlaps with the central axis of the second gate.

2. The semiconductor element according to claim 1, characterized in that, In this second direction, the two opposing sidewalls of the second gate are located between the two opposing sidewalls of the second plug.

3. The semiconductor element according to claim 1, characterized in that, One sidewall of the first plug overlaps with or is located between the first sidewall and the second sidewall of the first gate.

4. The semiconductor element according to claim 3, characterized in that, The other sidewall of the first plug is located on the side of the first extension away from the first gate.

5. The semiconductor element according to claim 1, characterized in that, The semiconductor device also includes a third gate, wherein the second gate is located between the first gate and the third gate. The second extension is disposed on the third sidewall of the third gate, away from the third gate, and extends and protrudes from the third sidewall in a third direction. The plurality of plugs further includes: a third plug covering the third gate and the second extension, wherein the central axis of the third plug is offset from the central axis of the third gate and is offset toward the third gate in a third direction.

6. The semiconductor element according to claim 5, characterized in that, The first gate and the third gate are symmetrical about the central axis of the second gate, and the first extension and the second extension are symmetrical about the central axis of the second gate.

7. The semiconductor element according to claim 5, characterized in that, The first plug and the third plug are symmetrical about the central axis of the second gate.

8. The semiconductor element according to claim 5, characterized in that, The first direction is perpendicular to the second direction and the third direction, and the second direction and the third direction are opposite to each other.

9. The semiconductor element according to claim 1, characterized in that, The plurality of gates have a first spacing, the plurality of plugs have a second spacing, and the second spacing is greater than the first spacing.

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