Sub-nanometer ferroelectric memory and computing integrated device and preparation method thereof

Abstract

The application provides a sub-nanometer ferroelectric memory and computing integrated device and a manufacturing method thereof. The ferroelectric memory and computing integrated device comprises a ferroelectric memory, a MOSFET transistor and an isolation layer. The ferroelectric memory comprises, from top to bottom, a metal electrode, a top electrode, a ferroelectric layer and a bottom electrode. Each layer is located above the gate of the MOSFET transistor. The bottom electrode of the ferroelectric memory is directly connected with the left side of the gate of the MOSFET transistor which is the base of the ferroelectric memory and computing integrated device. The ferroelectric memory and the gate of the MOSFET transistor are separated by the isolation layer. The bottom electrode of the ferroelectric memory is made of a low-dimensional material, and the thickness can be adjusted in a wide range. The ferroelectric memory and computing integrated device is compatible with the existing nanometer CMOS process technology of the transistor, and the size of the ferroelectric memory can reach the sub-nanometer level. The best write and read performance is achieved, and the problem of miniaturization of the ferroelectric memory is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip technology, and particularly relates to a sub-nanometer ferroelectric storage and computing integrated device and its fabrication method. Background Technology

[0002] With the advent of the artificial intelligence era, the deep processing and storage of data require higher computing speeds and lower energy consumption. The traditional von Neumann architecture separates computing and storage units, which faces speed bottlenecks and power waste. Therefore, new integrated computing and storage technologies have become an important research direction.

[0003] Ferroelectric memory-computing integrated devices possess significant application prospects due to their advantages such as high read / write speeds, outstanding fatigue resistance, low power consumption, and simple structure. Current ferroelectric memory-computing integrated devices mainly include FeFET, MFMFET, FeRAM, and FTJ. Among these, FeFET's high write voltage and non-ideal interface with the Si channel limit its cycle stability performance. FeRAM and FTJ require additional transistors for memory-computing applications, and because the device is in direct contact with the external transistor's source and drain terminals, multi-valued operations are not possible. In contrast, MFMFET inserts an additional electrode layer between the FE ferroelectric layer and the transistor gate oxide layer, which not only avoids the non-ideal interface of the Si channel and alleviates design conflicts between logic and memory, improving cycle stability performance, but also enables multi-valued operations. Furthermore, by adjusting the area ratio between the ferroelectric memory MFM (AFE) and the transistor FET (AMOS) (AR = AFE / AMOS), the voltage coupled to the ferroelectric interface can be effectively increased, thereby enabling efficient writing at low voltages.

[0004] As Moore's Law continues to advance and transistor sizes shrink, FET production lines have reached the nanometer level. Recent research indicates that an AR ratio of 1:10 achieves optimal write and read performance for integrated storage and computing. Therefore, the size of ferroelectric memory (MFM), corresponding to transistors, needs to reach the sub-nanometer level. This is difficult to achieve with existing fab process technologies and equipment, presenting challenges in compatibility with standard CMOS processes and miniaturization. Therefore, structural innovation and the selection of new materials are essential. Summary of the Invention

[0005] To address the aforementioned technical problems, the first aspect of this invention proposes a sub-nanometer-scale ferroelectric storage and computing integrated device, which includes a ferroelectric memory and a MOSFET transistor.

[0006] The ferroelectric memory serves as a data storage element, and the MOSFET transistor performs data calculation functions.

[0007] The bottom electrode 2 of the ferroelectric memory is fabricated using low-dimensional materials. The ferroelectric memory comprises, from top to bottom, a metal electrode 5, a top electrode 4, a ferroelectric layer 3, and a bottom electrode 2. Each layer is stacked on top of the gate of a MOSFET transistor according to a predetermined configuration.

[0008] The MOSFET transistor serves as the substrate of the ferroelectric memory-computing integrated device, and the bottom electrode 2 of the ferroelectric memory is directly connected to the gate of the MOSFET transistor.

[0009] The size of the effective working area 6 of the ferroelectric memory is determined solely by the thickness direction of the bottom electrode 2 relative to the width of the ferroelectric layer 3, thereby limiting the linewidth of the effective working area 6 of the ferroelectric memory to the sub-nanometer level.

[0010] As in the device of the first aspect of the present invention, the ferroelectric memory computing device further includes a stepped isolation layer 1, wherein the ferroelectric memory and the gate of the MOSFET transistor are isolated and insulated by the stepped isolation layer 1, and the left portion of the stepped isolation layer 1 located above the middle region of the gate is higher than the right portion of the stepped isolation layer 1 by a predetermined size.

[0011] As in the device of the first aspect of the present invention, the ferroelectric layer 3 located above the bottom electrode 2 and the stepped isolation layer 1 is in a convex shape, and the ferroelectric layer 3 completely covers the stepped isolation layer 1 and the bottom electrode 2;

[0012] The top electrode 4 and the metal electrode 5 are disposed only on the ferroelectric layer 3 corresponding to the step below the right side portion of the isolation layer 1.

[0013] As in the device of the first aspect of the present invention, the ratio AR of the area of ​​the ferroelectric memory to the area of ​​the MOSFET transistor is controlled to be in the range of 1:5 to 1:20.

[0014] A second aspect of the present invention provides a method for fabricating a sub-nanometer-scale ferroelectric storage and computing integrated device, the method comprising the following steps:

[0015] Step 1: Using a nanoscale metal oxide field-effect transistor (MOSFET) wafer as a substrate, the MOSFET wafer is cleaned and dried before fabricating the ferroelectric memory.

[0016] Step 2: An isolation layer 1 is fabricated on the MOSFET wafer processed in Step 1. The isolation layer 1 is subjected to multiple photolithographic patterns to form a stepped isolation layer 1 located above the MOSFET gate. The height of the upper step region of the stepped isolation layer 1 is higher than the lower step region by a predetermined size. The stepped isolation layer 1 only covers the right side portion of the MOSFET gate.

[0017] Step 3: Prepare the bottom electrode 2 layer of the ferroelectric memory on the stepped isolation layer 1; perform photolithography patterning on the bottom electrode 2 layer so that the bottom electrode 2 layer covers the area on the MOSFET gate that is not covered by the stepped isolation layer 1 and the upper step area of ​​the stepped isolation layer 1, while the lower step area is not covered by the bottom electrode 2 layer.

[0018] Step 4: After step 3 is completed, ferroelectric layer 3 is prepared. After the ferroelectric layer 3 is prepared, photolithography is performed to retain only the ferroelectric layer 3 located above the MOSFET gate and etch away the rest of the ferroelectric layer 3.

[0019] Step 5: Sequentially deposit a top electrode 4 layer and a metal electrode 5 layer on the ferroelectric layer 3. Perform photolithographic patterning on the top electrode 4 layer and the metal electrode 5 layer, retaining only the top electrode 4 layer and the metal electrode 5 layer located in the lower layer region of the stepped isolation layer 1. Etch away the excess parts of the top electrode 4 layer and the metal electrode 5 layer to form the top electrode 4 and the metal electrode 5.

[0020] Step 6: A transistor array is formed by multiple MOSFET transistors on the MOSFET wafer. The source terminals of each MOSFET transistor in the transistor array are interconnected to form a ground line. The drain terminals of each MOSFET transistor in the transistor array are interconnected to form a bit line. The metal electrodes 5 of each ferroelectric memory are interconnected to form a word line. Thus, the sub-nanometer ferroelectric memory and computing integrated device in the transistor array has both storage and multi-value computing functions.

[0021] As in the preparation method of the second aspect of the present invention, the stepped isolation layer 1 is made of a low dielectric constant material, aluminum oxide or silicon dioxide; the preparation process of the stepped isolation layer 1 adopts one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

[0022] As in the preparation method of the second aspect of the present invention, the low-dimensional material used in the bottom electrode 2 layer is selected from the following materials: two-dimensional thin film material, one-dimensional fiber material or zero-dimensional quantum dot material; the scale of the low-dimensional material is all in the nanometer scale;

[0023] In step 3, the bottom electrode layer 2 of the ferroelectric memory is prepared using the low-dimensional material wet transfer preparation method. The wet transfer preparation method adopts one of the following methods: transfer printing, spraying, spin coating or scraping coating.

[0024] The top electrode 4 is made of titanium nitride.

[0025] The material of the metal electrode 5 shall be selected from the following materials: tungsten, aluminum, nickel or platinum;

[0026] The top electrode 4 and the metal electrode 5 are prepared using one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition, physical vapor deposition, or thermal evaporation.

[0027] As in the preparation method of the second aspect of the present invention, the two-dimensional thin film material is selected from the following materials: graphene or MoS2; the one-dimensional fiber material is silver nanowire; and the zero-dimensional quantum dot material is gold quantum dot.

[0028] As in the preparation method of the second aspect of the present invention, the ferroelectric layer 3 thin film material comprises one or a mixture of the following materials: HfO2, ZrO2, HfXZr 1-X O2, lead zirconate titanate; the ferroelectric layer 3 is prepared by one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

[0029] As in the preparation method of the second aspect of the present invention, step 6 further includes rapid annealing in a nitrogen atmosphere to crystallize the ferroelectric thin film.

[0030] The method of the present invention has the following advantages:

[0031] 1. The bottom electrode of the ferroelectric memory uses low-dimensional materials to form a thickness of molecular or even atomic size in a specific dimension, and the thickness can be adjusted over a wider range. It is compatible with standard CMOS processes and can also enable the size of the ferroelectric memory MFM to reach the sub-nanometer molecular or atomic size level.

[0032] 2. A stepped distribution is formed on the isolation layer, which makes the ferroelectric memory vertically distributed. The effective electric field comes from the thickness of the bottom electrode layer, which can better match the existing transistor nanoscale process technology AR=1:10, achieving the best write and read performance while solving the problem of size miniaturization.

[0033] The ferroelectric storage and computing integrated array has advantages such as fast read and write speed, outstanding fatigue resistance, low power consumption and simple structure. It can effectively break through the separation of computing and storage units in the traditional von Neumann architecture and solve the storage wall and power consumption wall problems when processing large amounts of data in depth. Attached Figure Description

[0034] Figure 1 This is a cross-sectional view of a sub-nanometer-scale ferroelectric storage and computing integrated device proposed in this invention;

[0035] Figure 2 Cross-sectional view of a metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated for existing nanoscale technology nodes;

[0036] Figure 3 This invention involves fabricating a bottom electrode layer based on a metal-oxide-semiconductor field-effect transistor.

[0037] Figure 4 In this invention, a ferroelectric layer is prepared on the bottom electrode layer;

[0038] Figure 5 In this invention, a top electrode and a metal electrode are sequentially deposited on the ferroelectric layer;

[0039] Figure 6 This invention relates to the design of an integrated ferroelectric storage and computing array.

[0040] Figure 7 This is a schematic diagram of the ferroelectric storage computational circuit of the present invention.

[0041] Among them, 1-isolation layer, 2-bottom electrode, 3-ferroelectric layer, 4-top electrode, 5-metal electrode, and 6-effective working area. Detailed Implementation

[0042] To address the process compatibility issues of novel ferroelectric memory and computing integrated devices, this invention breaks through the traditional von Neumann architecture by innovating device structure and selecting low-dimensional materials, alleviating design conflicts between logic and memory, achieving nanoscale integration of ferroelectric memory and transistors, avoiding non-ideal interfaces of Si channels, obtaining high-efficiency write capability under low voltage, and improving cycle stability performance according to the first aspect of this invention.

[0043] We selected low-dimensional materials as the bottom electrode of the ferroelectric memory, forming a thickness at the molecular or even atomic level in a specific dimension. Simultaneously, through structural innovation, we created a stepped distribution on the isolation layer, enabling the ferroelectric memory to be vertically distributed. The effective electric field originates from the thickness of the bottom electrode layer, allowing for better compatibility with existing transistor nanoscale processes (AR = 1:10). This achieves optimal write and read performance while addressing the challenge of miniaturization, enabling the ferroelectric memory (MFM) to reach sub-nanometer molecular or atomic dimensions. The resulting ferroelectric memory-computing integrated array possesses advantages such as high read / write speeds, outstanding fatigue resistance, low power consumption, and simple structure. It effectively overcomes the traditional von Neumann architecture's separation of computing and storage units, solving the storage wall and power wall problems encountered during deep processing of large amounts of data.

[0044] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] A first aspect of the present invention provides a sub-nanometer-scale ferroelectric storage and computing integrated device, the ferroelectric storage and computing integrated device comprising a ferroelectric memory and a MOSFET transistor;

[0046] The ferroelectric memory serves as a data storage element, and the MOSFET transistor performs data calculation functions.

[0047] The bottom electrode 2 of the ferroelectric memory is fabricated using low-dimensional materials. The ferroelectric memory comprises, from top to bottom, a metal electrode 5, a top electrode 4, a ferroelectric layer 3, and a bottom electrode 2. Each layer is stacked on top of the gate of a MOSFET transistor according to a predetermined configuration.

[0048] The MOSFET transistor serves as the substrate of the ferroelectric memory-computing integrated device, and the bottom electrode 2 of the ferroelectric memory is directly connected to the gate of the MOSFET transistor.

[0049] The size of the effective working area 6 of the ferroelectric memory is determined solely by the thickness direction of the bottom electrode 2 relative to the width of the ferroelectric layer 3, thereby limiting the linewidth of the effective working area 6 of the ferroelectric memory to the sub-nanometer level.

[0050] like Figure 1 The sub-nanometer-scale ferroelectric memory-computing integrated device of the present invention is shown. The bottom electrode 2 of the ferroelectric memory is made of a low-dimensional material, 3 is a ferroelectric layer, 4 is a top electrode, and 5 is a metal electrode. The bottom electrode 2 of the ferroelectric memory is connected to the left side of the transistor gate, and the unconnected right side is separated by an isolation layer 1. The upper right half of the isolation layer is stepped, so that the effective electric field of the ferroelectric memory originates from the thickness of the bottom electrode layer, and its effective working area is 6. By controlling the layer thickness of the bottom electrode 2, the size of the ferroelectric memory MFM reaches the sub-nanometer molecular or atomic level, better matching the existing nanometer-level process technology of CMOS transistors. The area ratio AR of the ferroelectric memory to the transistor MOSFET is controlled to be AR = 1:5 to 1:20. Preferably, AR = 1:10, achieving optimal write and read performance for the integrated memory-computing technology.

[0051] As in the device of the first aspect of the present invention, the ferroelectric memory computing integrated device further includes a stepped isolation layer 1, wherein the ferroelectric memory and the gate of the MOSFET transistor are isolated and insulated by the stepped isolation layer 1, and the left portion of the stepped isolation layer 1 located above the middle region of the gate is higher than the right portion of the stepped isolation layer 1 by a predetermined dimension. See Appendix Figure 3 As shown.

[0052] As in the device of the first aspect of the present invention, the ferroelectric layer 3 located above the bottom electrode 2 and the stepped isolation layer 1 is convex in shape, and the ferroelectric layer 3 completely covers the stepped isolation layer 1 and the bottom electrode 2; as shown in the appendix Figure 5 As shown.

[0053] The top electrode 4 and the metal electrode 5 are disposed only on the ferroelectric layer 3 corresponding to the step below the right side portion of the isolation layer 1. (See attached image) Figure 6 As shown.

[0054] As in the device of the first aspect of the present invention, the ratio AR of the area of ​​the ferroelectric memory to the area of ​​the MOSFET transistor is controlled to be in the range of 1:5 to 1:20.

[0055] Appendix Figure 2 This is a cross-sectional view of a MOSFET transistor structure used to fabricate sub-nanometer ferroelectric memory and computing devices. The diagram shows a typical MOSFET transistor, where S is the source, D is the drain, and G is the gate. Under current process conditions, the width of MOSFET transistor electrodes is greater than 5-7 nanometers; the electrode width cannot yet be achieved at the sub-nanometer level. The dimensions of each electrode in the transistor shown are all greater than the sub-nanometer level.

[0056] However, it is possible to deposit semiconductor or metal layers at the sub-nanometer level using processes such as sputtering and vapor deposition. (See attached image) Figure 1 As shown, the ferroelectric memory includes: a metal electrode 5, a top electrode 4, a ferroelectric layer 3, and a bottom electrode 2; wherein the ferroelectric layer 3, which serves as the two plates of the ferroelectric memory, is vertically arranged between the top electrode 4 and the bottom electrode 2, and their effective working area 6 is determined solely by the thickness of the ferroelectric layer 3. Since the thicknesses of the top electrode 4, the ferroelectric layer 3, and the bottom electrode 2 of the ferroelectric memory can all be achieved at the sub-nanometer level, the effective size of the ferroelectric memory is limited to the sub-nanometer level.

[0057] Appendix Figure 7 This is the equivalent electrical schematic diagram of a ferroelectric memory-computing integrated device. The source (S) of the MOSFET transistor is connected to ground (Gnd), the drain (D) is connected to the bit line, and the gate is connected to the bottom electrode of the ferroelectric memory (MFM). The metal electrode (5) of the ferroelectric memory (MFM) is connected to the word line. The ferroelectric memory (MFM) with storage function serves as the data storage element, while the MOSFET transistor is used as the computing element.

[0058] A second aspect of the present invention provides a method for fabricating a sub-nanometer-scale ferroelectric storage and computing integrated device, the method comprising the following steps:

[0059] Step 1: Using a nanoscale metal oxide field-effect transistor (MOSFET) wafer as a substrate, the MOSFET wafer is cleaned and dried before fabricating the ferroelectric memory.

[0060] Step 2: An isolation layer 1 is fabricated on the MOSFET wafer processed in Step 1. The isolation layer 1 is subjected to multiple photolithographic patterns to form a stepped isolation layer 1 located above the MOSFET gate. The height of the upper step region of the stepped isolation layer 1 is higher than the lower step region by a predetermined size. The stepped isolation layer 1 only covers the right side portion of the MOSFET gate.

[0061] Step 3: Fabricate the bottom electrode 2 layer of the ferroelectric memory on the stepped isolation layer 1; perform photolithography patterning on the bottom electrode 2 layer so that the bottom electrode 2 layer covers the area on the MOSFET gate not covered by the stepped isolation layer 1 and the upper layer region of the stepped isolation layer 1, while the lower layer region of the step is not covered by the bottom electrode 2 layer; see [reference needed]. Figure 4 As shown;

[0062] Step 4: After step 3 is completed, ferroelectric layer 3 is prepared. After the ferroelectric layer 3 is prepared, photolithography is performed to retain only the ferroelectric layer 3 located above the MOSFET gate and etch away the rest of the ferroelectric layer 3.

[0063] Step 5: Sequentially deposit a top electrode 4 layer and a metal electrode 5 layer on the ferroelectric layer 3. Perform photolithographic patterning on the top electrode 4 layer and the metal electrode 5 layer, retaining only the top electrode 4 layer and the metal electrode 5 layer located in the lower layer region of the stepped isolation layer 1. Etch away the excess parts of the top electrode 4 layer and the metal electrode 5 layer to form the top electrode 4 and the metal electrode 5.

[0064] Step 6: A transistor array is formed by multiple MOSFET transistors on the MOSFET wafer. The source terminals of each MOSFET transistor in the transistor array are interconnected to form a ground line. The drain terminals of each MOSFET transistor in the transistor array are interconnected to form a bit line. The metal electrodes 5 of each ferroelectric memory are interconnected to form a word line. Thus, the sub-nanometer ferroelectric memory and computing integrated device in the transistor array has both storage and multi-value computing functions.

[0065] As in the preparation method of the second aspect of the present invention, the stepped isolation layer 1 is made of a low dielectric constant material, aluminum oxide or silicon dioxide; the preparation process of the stepped isolation layer 1 adopts one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

[0066] As in the preparation method of the second aspect of the present invention, the low-dimensional material used in the bottom electrode 2 layer is selected from the following materials: two-dimensional thin film material, one-dimensional fiber material or zero-dimensional quantum dot material; the scale of the low-dimensional material is all in the nanometer scale;

[0067] In step 3, the bottom electrode layer 2 of the ferroelectric memory is prepared using the low-dimensional material wet transfer preparation method. The wet transfer preparation method adopts one of the following methods: transfer printing, spraying, spin coating or scraping coating.

[0068] The top electrode 4 is made of titanium nitride.

[0069] The material of the metal electrode 5 shall be selected from the following materials: tungsten, aluminum, nickel or platinum;

[0070] The top electrode 4 and the metal electrode 5 are prepared using one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition, physical vapor deposition, or thermal evaporation.

[0071] As in the preparation method of the second aspect of the present invention, the two-dimensional thin film material is selected from the following materials: graphene or MoS2; the one-dimensional fiber material is silver nanowire; and the zero-dimensional quantum dot material is gold quantum dot.

[0072] As in the preparation method of the second aspect of the present invention, the ferroelectric layer 3 thin film material comprises one or a mixture of the following materials: HfO2, ZrO2, HfXZr 1-X O2, lead zirconate titanate; the ferroelectric layer 3 is prepared by one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

[0073] As in the preparation method of the second aspect of the present invention, step 6 further includes rapid annealing in a nitrogen atmosphere to crystallize the ferroelectric thin film.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention and are not intended to limit them. Although the embodiments of the present invention have been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the embodiments of the present invention should not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A sub-nanometer-scale ferroelectric storage and computing integrated device, characterized in that, The ferroelectric storage and computing integrated device includes a ferroelectric memory and a MOSFET transistor; The ferroelectric memory serves as a data storage element, and the MOSFET transistor performs data calculation functions. The bottom electrode (2) of the ferroelectric memory is made of low-dimensional material. The ferroelectric memory includes, from top to bottom, a metal electrode (5), a top electrode (4), a ferroelectric layer (3) and a bottom electrode (2). Each layer is stacked on top of the gate of the MOSFET transistor according to a predetermined configuration. The MOSFET transistor serves as the substrate of the ferroelectric memory computing device, and the bottom electrode (2) of the ferroelectric memory is directly connected to the gate of the MOSFET transistor. The size of the effective working area (6) of the ferroelectric memory is determined only by the thickness direction of the bottom electrode (2) relative to the width of the ferroelectric layer (3), so as to limit the linewidth size of the effective working area (6) of the ferroelectric memory to the sub-nanometer level.

2. The device as described in claim 1, characterized in that, The ferroelectric memory computing device further includes a stepped isolation layer (1). The ferroelectric memory and the gate of the MOSFET transistor are isolated and insulated by the stepped isolation layer (1). The left side of the stepped isolation layer (1) located above the middle region of the gate is higher than the right side of the stepped isolation layer (1) by a predetermined size.

3. The device as described in claim 2, characterized in that, The ferroelectric layer (3) located above the bottom electrode (2) and the stepped isolation layer (1) is convex in shape, and the ferroelectric layer (3) completely covers the stepped isolation layer (1) and the bottom electrode (2); The top electrode (4) and the metal electrode (5) are disposed only on the ferroelectric layer (3) corresponding to the step below the right side of the isolation layer (1).

4. The device as claimed in claim 1, characterized in that, The ratio AR of the area of ​​the ferroelectric memory to the area of ​​the MOSFET transistor is controlled to be between 1:5 and 1:

20.

5. A method for fabricating a sub-nanometer-scale ferroelectric storage and computing integrated device, characterized in that, The preparation method includes the following steps: Step 1: Using a nanoscale metal oxide field-effect transistor (MOSFET) wafer as a substrate, the MOSFET wafer is cleaned and dried before fabricating the ferroelectric memory. Step 2: An isolation layer (1) is prepared on the MOSFET wafer processed in Step 1. The isolation layer (1) is subjected to multiple photolithographic patterns to form a stepped isolation layer (1) located above the MOSFET gate. The height of the upper step region of the stepped isolation layer (1) is higher than the lower step region by a predetermined size. The stepped isolation layer (1) only covers the right side portion of the MOSFET gate. Step 3: Prepare the bottom electrode (2) layer of the ferroelectric memory on the stepped isolation layer (1); perform photolithography patterning on the bottom electrode (2) layer so that the bottom electrode (2) layer covers the area on the MOSFET gate that is not covered by the stepped isolation layer (1) and the upper step area of ​​the stepped isolation layer (1), while the lower step area is not covered by the bottom electrode (2) layer; Step 4: After step 3 is completed, a ferroelectric layer (3) is prepared. After the ferroelectric layer (3) is prepared, photolithography is performed to retain only the ferroelectric layer (3) located above the MOSFET gate and etch away the rest of the ferroelectric layer (3). Step 5: Sequentially deposit a top electrode (4) layer and a metal electrode (5) layer on the ferroelectric layer (3). Perform photolithographic patterning on the top electrode (4) layer and the metal electrode (5) layer, retaining only the top electrode (4) layer and the metal electrode (5) layer located in the lower layer region of the stepped isolation layer (1), and etch away the excess parts of the top electrode (4) layer and the metal electrode (5) layer to form the top electrode (4) and the metal electrode (5). Step 6: A transistor array is formed by multiple MOSFET transistors on the MOSFET wafer. The source terminals of each MOSFET transistor in the transistor array are interconnected to form a ground line. The drain terminals of each MOSFET transistor in the transistor array are interconnected to form a bit line. The metal electrodes (5) of each ferroelectric memory are interconnected to form a word line. Thus, the sub-nanometer ferroelectric storage and computing integrated device in the transistor array has both storage and multi-value computing functions.

6. The preparation method according to claim 5, characterized in that, The stepped isolation layer (1) is made of a low dielectric constant material, aluminum oxide or silicon dioxide; the step-shaped isolation layer (1) is prepared by one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

7. The preparation method according to claim 5, characterized in that, The low-dimensional material used in the bottom electrode (2) layer is selected from the following materials: two-dimensional thin film material, one-dimensional fiber material or zero-dimensional quantum dot material; the scale of the low-dimensional material is all in the nanometer scale; In step 3, the bottom electrode (2) layer of the ferroelectric memory is prepared using the low-dimensional material wet transfer preparation method. The wet transfer preparation method adopts one of the following methods: transfer printing, spraying, spin coating or scraping coating. The top electrode (4) is made of titanium nitride; The metal electrode (5) material is selected from the following materials: tungsten, aluminum, nickel or platinum; The top electrode (4) and the metal electrode (5) are prepared by one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition, physical vapor deposition or thermal evaporation.

8. The preparation method according to claim 7, characterized in that, The two-dimensional thin film material is selected from the following materials: graphene or MoS2; the one-dimensional fiber material is silver nanowire; and the zero-dimensional quantum dot material is gold quantum dot.

9. The preparation method according to claim 5, characterized in that, The ferroelectric layer (3) thin film material includes one or a mixture of the following materials: HfO2, ZrO2, HfXZr 1-X O2, lead zirconate titanate; the ferroelectric layer (3) is prepared by one of the following methods: sputtering, atomic-size thickness deposition, chemical vapor deposition or physical vapor deposition.

10. The preparation method according to claim 5, characterized in that, Step 6 also includes rapid annealing in a nitrogen atmosphere to crystallize the ferroelectric thin film.

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