A planar SiC MOSFET device structure and method of manufacture thereof

Abstract

The application relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof. The device structure comprises a substrate, an epitaxial layer located on the substrate, a doped region and a JFET region located on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are located on the same set surface, and the set surface is a concave surface; the concave part of the concave surface covers the specified region of the JFET region and the doped region, and the specified region is a region containing at least a channel of the doped region. Through the device structure, the on-resistance of the device is effectively reduced under the premise of guaranteeing the performance of the device except the on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a planar SiC MOSFET device structure and its manufacturing method. Background Technology

[0002] SiC MOSFET devices possess significant advantages in high-voltage, high-temperature, and high-frequency applications due to their large bandgap, high critical breakdown electric field, fast electron saturation drift velocity, and high thermal conductivity, particularly in emerging fields such as new energy vehicles, photovoltaic energy storage, and charging piles. Due to limitations in process technology and equipment, domestic wafer fabs primarily employ planar-gate silicon carbide SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device structures. Compared to trench-gate SiC MOSFET devices, planar-gate SiC MOSFETs are easier to manufacture, have higher yields, do not suffer from the high electric field concentration issues of trench-gate SiC MOSFETs, and offer superior avalanche resistance. However, the rough surface and lower mobility of planar-gate SiC MOSFETs, along with the large JFET region and cell size inherent in SiC MOSFET structures, result in significantly higher on-resistance and parasitic capacitance compared to trench-gate SiC MOSFETs. In particular, the on-resistance, a key parameter, affects both the product cost and practical application of the device, and is currently a pain point for planar gate SiC MOSFET devices.

[0003] To address this pain point, existing SiC MOSFET devices employ the following methods to reduce on-resistance:

[0004] 1. Optimize the doping concentration in the JFET region to reduce the JFET resistance, thereby reducing the device's on-resistance. However, when the doping concentration in the JFET region increases to a certain extent, the drain-source leakage current of the device will increase significantly, and the gate oxide reliability will be greatly reduced.

[0005] 2. Reduce the channel length of the device to lower the channel resistance, which accounts for a significant portion of the on-resistance. However, this method can lead to short-channel effects and increase the likelihood of drain-source punch-through when the channel length is reduced to a certain extent.

[0006] 3. Reduce the cell size of the device, increase the channel density, and reduce the channel resistance and JFET resistance. However, when the cell size is reduced to a certain extent, the yield will be greatly reduced due to equipment limitations, and the increase in the resistance of the JFET region will also offset the benefits brought by the reduction in cell size.

[0007] While existing SiC MOSFET devices can reduce on-resistance to some extent, once the structural optimization for reducing on-resistance exceeds a certain point, the performance gains of existing SiC MOSFET devices significantly decrease, and other device parameters are severely affected. Therefore, existing SiC MOSFET devices suffer from the problem of impacting other device parameters besides on-resistance while attempting to reduce it. Summary of the Invention

[0008] This application provides a planar SiC MOSFET device structure and its manufacturing method, which solves the technical problem in the prior art of affecting other device parameters besides on-resistance while reducing on-resistance. It achieves the technical effect of effectively reducing the conduction electrons of the device while ensuring the performance of other device parameters besides on-resistance.

[0009] In a first aspect, embodiments of the present invention provide a planar SiC MOSFET device structure, comprising: a substrate, an epitaxial layer located on the substrate, a doped region and a JFET region located on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate and the epitaxial layer is a SiC epitaxial layer;

[0010] The JFET region is located between the doped regions, and the JFET region is in contact with the doped regions;

[0011] The upper surface of the JFET region, the upper surface of the doped region, and the upper surface of the epitaxial layer are located on the same set surface, which is a concave surface.

[0012] The concave portion of the concave surface covers a designated area of ​​the JFET region and the doped region to reduce the on-resistance of the device structure through the concave surface and the concave portion, wherein the designated area is a region that at least includes the channel of the doped region.

[0013] Optionally, the angle of the recess is 1° to 4°.

[0014] Optionally, the depth of the recess is in the range of 0.05um to 0.2um.

[0015] Optionally, the maximum opening width of the recess is not less than the sum of the width of the JFET region and the channel width in the doped region.

[0016] Optionally, the mask used in the manufacturing process of the recess is the same mask used in the manufacturing process of the JFET region.

[0017] Optionally, the doped region includes: a P-type well region, an N+ region, and a P+ region;

[0018] The N+ region and the P+ region are located in the P-type well region, and the upper surface of the N+ region, the upper surface of the P+ region, and the upper surface of the P-type well region are located on the same designated surface;

[0019] One side of the N+ region is close to the JFET region, and the other side of the N+ region is in contact with the P+ region.

[0020] Optionally, the method further includes: a gate region located above the epitaxial layer, the gate region covering a portion of the JFET region and the doped region;

[0021] The gate region includes: a gate dielectric layer and a gate polysilicon;

[0022] The gate dielectric layer is located above the epitaxial layer, and the gate dielectric layer covers a portion of the JFET region and the doped region.

[0023] The gate polysilicon is located on top of the gate dielectric layer.

[0024] Optionally, it may also include: an interlayer dielectric layer; the interlayer dielectric layer is located above the epitaxial layer and encloses the gate region.

[0025] Optionally, it also includes: a source metal layer and a drain metal layer;

[0026] The source metal layer is located above the epitaxial layer and covers the interlayer dielectric layer, the gate region, and the doped region;

[0027] The drain metal layer is located beneath the substrate.

[0028] Based on the same inventive concept, in a second aspect, the present invention also provides a method for manufacturing a planar SiC MOSFET device structure, for manufacturing the planar SiC MOSFET device structure as described in the first aspect; the manufacturing method includes:

[0029] An epitaxial layer is formed on a substrate, wherein the substrate is a silicon carbide (SiC) substrate and the epitaxial layer is a SiC epitaxial layer;

[0030] A doped region and a JFET region are formed on the epitaxial layer, wherein the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region, and the upper surface of the epitaxial layer are located on the same defined surface, which is a concave surface; the concave portion of the concave surface covers a designated area of ​​the JFET region and the doped region, so as to reduce the on-resistance of the device structure through the concave surface and the concave portion, wherein the designated area is a region that at least includes the channel of the doped region.

[0031] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0032] In this embodiment of the invention, the upper surface of the epitaxial layer of the planar gate SiC MOSFET device is configured as a concave surface, with the concave portion covering a designated area of ​​the JFET region and the doped region. The designated area is the region containing at least the channel of the doped region. This changes the crystal plane of the original channel, thereby optimizing or increasing the current density of the channel, accumulation layer, and JFET region below the gate. Furthermore, by setting the concave portion, the change in the surface crystal plane guided by the concave portion and the formation of tensile stress can also optimize the surface mobility of the device, thereby increasing the current density and reducing the on-resistance of the device. Attached Figure Description

[0033] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 A schematic diagram of a planar SiC MOSFET device structure in an embodiment of the present invention is shown;

[0035] Figure 2 A schematic diagram of a conventional SiC MOSFET device structure is shown in an embodiment of the present invention;

[0036] Figure 3 The diagram illustrates the structure of the device structure in the embodiment of the present invention and the structure of the mask in the JFET region during the manufacturing process of a conventional device.

[0037] Figure 4 A schematic diagram of the manufacturing process of the concave surface and recess in an embodiment of the present invention is shown;

[0038] Figure 5a The current distribution diagram of a conventional device structure in an embodiment of the present invention is shown;

[0039] Figure 5b The current distribution diagram of the device structure in an embodiment of the present invention is shown;

[0040] Figure 6 The diagram shows the current density curves along the C1 tangent position of the device structure in the embodiment of the present invention and the conventional device structure;

[0041] Figure 7 The diagram shows the current density curves along the C2 tangent position of the device structure in the embodiment of the present invention and the conventional device structure;

[0042] Figure 8a The stress distribution diagram of a conventional device structure in an embodiment of the present invention is shown;

[0043] Figure 8b A stress distribution diagram of the device structure in an embodiment of the present invention is shown;

[0044] Figure 9a The electric field intensity distribution diagram of the conventional device structure in the embodiment of the present invention is shown;

[0045] Figure 9b The electric field intensity distribution diagram of the device structure in the embodiment of the present invention is shown;

[0046] Figure 10 A schematic diagram of an epitaxial layer, a concave surface, and a recess is shown in an embodiment of the present invention.

[0047] Figure 11 This diagram illustrates a structure in which a P-type well region and an N+ region are formed on an epitaxial layer according to an embodiment of the present invention.

[0048] Figure 12 This diagram illustrates a structure in which a P+ region is formed in a P-type well region according to an embodiment of the present invention.

[0049] Figure 13 This diagram illustrates a structure in which a JFET region is formed between doped regions according to an embodiment of the present invention.

[0050] Figure 14 This diagram illustrates a structure in which a gate dielectric layer and a gate polysilicon are formed on an epitaxial layer in an embodiment of the present invention.

[0051] Figure 15 A schematic diagram of the structure of the interlayer dielectric layer in an embodiment of the present invention is shown;

[0052] Figure 16 A schematic flowchart of the manufacturing method of a planar SiC MOSFET device structure according to an embodiment of the present invention is shown.

[0053] In the attached figures, 110 is the substrate; 120 is the epitaxial layer; 130 is the doped region; 140 is the JFET region; 150 is the concave surface; 151 is the recess; 160 is the gate region; 170 is the interlayer dielectric layer; 180 is the source metal layer; and 190 is the drain metal layer.

[0054] 131. P-type well region; 132. N+ region; 133. P+ region;

[0055] 161. Gate dielectric layer; 162. Gate polysilicon. Detailed Implementation

[0056] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0057] Example 1

[0058] The first embodiment of the present invention provides a planar SiC MOSFET device structure, such as... Figure 1 As shown, it includes: a substrate 110, an epitaxial layer 120 situated on the substrate 110, a doped region 130 situated on the epitaxial layer 120, and a JFET region 140. The substrate 110 is a silicon carbide (SiC) substrate, such as a 4H-SiC substrate, and the epitaxial layer 120 is a SiC epitaxial layer. Both the substrate 110 and the epitaxial layer 120 are N-type conductive. The substrate 110 is a heavily doped N-type substrate, and the doping concentration of the epitaxial layer 120 is lower than that of the substrate 110.

[0059] JFET region 140 is located between doped regions 130 and is in contact with doped regions 130. The upper surface of JFET region 140, the upper surface of doped region 130, and the upper surface of epitaxial layer 120 are located on the same defined surface, which is a concave surface 150. The recess 151 of concave surface 150 covers a designated area of ​​JFET region 140 and doped region 130 to reduce the on-resistance of the device structure through concave surface 150 and recess 151. The designated area is the region that at least includes the channel of doped region 130.

[0060] It should be noted that the SiC MOSFET device structure in this embodiment is a planar gate structure, or simply a planar SiC MOSFET device.

[0061] In this embodiment, the upper surface of the epitaxial layer 120 of the planar gate SiC MOSFET device is configured as a concave surface 150, and the recess 151 of the concave surface 150 covers a designated area of ​​the JFET region 140 and the doped region 130. The designated area is the region that at least includes the channel of the doped region 130. This changes the crystal plane where the original channel is located, thereby optimizing or increasing the current density of the channel, accumulation layer, and JFET region 140 below the gate. Furthermore, by setting the recess 151 of the concave surface 150, the change in the surface crystal plane guided by the recess 151 and the formation of tensile stress can also optimize the surface mobility of the device, thereby increasing the current density and reducing the on-resistance of the device.

[0062] Below, in conjunction with Figure 1 The structure and principle of the planar SiC MOSFET device in this embodiment are explained in detail:

[0063] The device structure in this embodiment is modified from the conventional planar gate MOSFET device (hereinafter referred to as the conventional device). Specifically, the channel is changed by altering the horizontal upper surface of the epitaxial layer 120 and the JFET region 140 of the conventional planar gate MOSFET device. To better understand the structure and principle of the planar SiC MOSFET device in this embodiment, it is necessary to first describe the structure of the conventional planar gate MOSFET device.

[0064] like Figure 2 As shown, in a conventional planar gate MOSFET device structure, a JFET region 140 is formed on an epitaxial layer 120, with the upper surface of the epitaxial layer 120 and the upper surface of the JFET region 140 located on the same horizontal plane. Doped regions 130 are formed within the JFET region 140, and the doped regions 130 are spaced apart. The upper surface of the doped regions 130 and the upper surface of the JFET region 140 are on the same horizontal plane; that is, the upper surface of the epitaxial layer 120, the upper surface of the JFET region 140, and the upper surface of the doped region 130 are all on the same horizontal plane. Other structures of the conventional planar gate MOSFET device are consistent with those of this embodiment and will not be described again. For example, in both the conventional device and the device of this embodiment, the gate region 160 is located above the epitaxial layer 120, and the gate region 160 covers a portion of the doped region 130 and the JFET region 140 between the doped regions 130. The channel of the conventional device is called the original channel.

[0065] In this embodiment, the concave surface 150 is a plane with a recess 151. The recess 151 is a gently sloping micro-trench, i.e., a flat curved surface. The angle of the recess 151 is 1° to 4°, so that the channel is located on the crystal plane position after the (0001) crystal plane is deflected by 1° to 2° from the

[0001] crystal plane (i.e., the c-axis). This not only increases the current density of the channel, accumulation layer, and JFET region 140 under the gate, but also reduces the interface state density, improves the surface carrier mobility, and introduces tensile stress, reducing scattering and decreasing the effective electron mass, further improving mobility. The angle of the recess 151 is the angle between the edge of the recess 151 and the plane of the bottom of the recess 151. Thus, based on these three factors, the on-resistance of the device is reduced. The depth of the recess 151 ranges from 0.05µm to 0.2µm. As the depth of the recess 151 increases, the angle of the recess 151 also increases, resulting in a better reduction in on-resistance.

[0066] exist Figure 3 In the diagram, the device on the left is a conventional device, and the device on the right is the device of this embodiment. For example... Figure 3As shown, in the manufacturing process of a conventional planar gate MOSFET device, before the doped region 130 is implanted into the epitaxial layer 120, an entire mask is typically used for the implantation of the JFET region 140. This means the entire mask is set as the open area of ​​the JFET region 140, effectively opening the active region of the conventional device and realizing the implantation area of ​​the JFET region 140. The JFET region 140 of the conventional device completely encloses the doped region 130, allowing the JFET region 140 beneath the doped region 130 to form a current spreading layer.

[0067] In the fabrication process of the planar SiC MOSFET device structure in this embodiment, the mask for the recess 151 and the mask for the JFET region 140 are the same mask, achieving multiple uses from a single mask to reduce costs, increase efficiency, and ensure compatibility with existing processes. Figure 3 As shown, in the manufacturing process of the device in this embodiment, before the doped region 130 is implanted into the epitaxial layer 120, a mask for the JFET region 140 (hereinafter referred to as the original mask) of the conventional device manufacturing process can still be used. Only the open area of ​​the JFET region 140 of the original mask is set as the open area of ​​the JFET region 140 of the device in this embodiment, thus achieving the implantation of the JFET region 140 of the device in this embodiment. It can be seen that the open area of ​​the JFET region 140 of the device in this embodiment is significantly smaller than that of the conventional JFET region 140. Based on the original mask, partial design optimization of the active region is performed to achieve the goals of cost reduction, efficiency improvement, and compatibility with existing processes.

[0068] Typically, the mask design for JFET region 140 is such that the active region is fully open, as in the mask design for a conventional JFET region 140. The typical design of JFET region 140 simplifies the layout, and by changing the injection energy of JFET region 140, a current spreading layer structure can be introduced to slightly reduce the on-resistance of the device, such as... Figure 3 As shown in the traditional device. This embodiment optimizes the design of the active region based on the existing JFET region 140 mask, achieving multiple uses for a single mask without affecting the JFET region 140 injection while also meeting the mask requirements for the recess 151 process. Figure 3 The device shown in this embodiment is an example of a device structure that cannot form a current spreading layer structure. However, the optimization of the channel and JFET region 140 by the concave surface 150 and the concave portion 151 can further reduce the on-resistance of the device.

[0069] And, as Figure 4As shown, in the fabrication process of the device in this embodiment, before the doped region 130 is implanted into the epitaxial layer 120, the surface of the epitaxial layer 120 is subjected to multiple exposures and wet etching processes using different exposure energies and focal lengths through a mask of the JFET region 140 of the device in this embodiment, with the opening width (i.e., the open area of ​​the mask) increasing linearly. Figure 4 In this diagram, the mask for the first JFET region 140 above the epitaxial layer 120 serves as a schematic mask for the photoresist dimensions during the first exposure of the surface of the epitaxial layer 120. The aperture width of the mask for the first JFET region 140 is the same as the aperture width for the first exposure. The mask for the second JFET region 140 above the epitaxial layer 120 serves as a schematic mask for the photoresist dimensions during the second exposure of the surface of the epitaxial layer 120. The aperture width of the mask for the second JFET region 140 is the same as the aperture width for the second exposure. And so on, the mask for the Nth JFET region 140 above the epitaxial layer 120 serves as a schematic mask for the photoresist dimensions during the Nth exposure of the surface of the epitaxial layer 120. The aperture width of the mask for the Nth JFET region 140 is the same as the aperture width for the Nth exposure. N can be set according to actual requirements. The same mask is used for all N photoresist exposures. One of the JFET region 140 mask opening widths is the same as the opening width of the mask used to manufacture JFET region 140, such as... Figure 4 The mask is shown within the dashed frame. In the epitaxial layer 120, the opening width of each exposure corresponds to a schematic structure of wet etching. Thus, a smooth micro-trench, i.e., a recess 151, isotropically etched onto the surface of the epitaxial layer 120, deflecting the (0001) crystal plane of the original channel towards the

[0001] crystal plane (c-axis) by 1°~2°. Furthermore, the mask for the recess 151 is the same as the mask for the JFET region 140, achieving multiple uses from a single mask, further reducing costs and increasing efficiency, and ensuring compatibility with existing processes.

[0070] The maximum opening width of the recess 151 is not less than the sum of the width of the JFET region 140 and the channel width in the doped region 130. The maximum opening width of the recess 151 is the maximum opening width of the mask of the recess 151. This allows the recess 151 to cover the channels of the JFET region 140 and the doped region 130, increasing the current density of the channel, accumulation layer, and JFET region 140 under the gate, thereby reducing the on-resistance of the device.

[0071] like Figure 1As shown, the smallest unit cell structure of the device in this embodiment has two doped regions 130. Each doped region 130 has the same structure. Each doped region 130 includes a P-type well region 131, an N+ region 132, and a P+ region 133. The N+ region 132 and the P+ region 133 are located within the P-type well region 131. The upper surfaces of the N+ region 132, the P+ region 133, and the P-type well region 131 are located on the same defined surface. One side of the N+ region 132 is close to the JFET region 140, and the other side of the N+ region 132 is in contact with the P+ region 133.

[0072] Specifically, in each doped region 130, N+ region 132 and P+ region 133 are located in P-type well region 131, with the upper surfaces of N+ region 132, P+ region 133, and P-type well region 131 located on this defined surface. The right side of N+ region 132 in the left-hand doped region 130 is adjacent to JFET region 140, and the left side of N+ region 132 in the left-hand doped region 130 is in contact with P+ region 133 in the left-hand doped region 130. The left side of N+ region 132 in the right-hand doped region 130 is adjacent to JFET region 140, and the right side of N+ region 132 in the right-hand doped region 130 is in contact with P+ region 133 in the right-hand doped region 130. In each doped region 130, the region between the side of N+ region 132 adjacent to JFET region 140 and the side of P-type well region 131 adjacent to JFET region 140 forms a channel. In the left-hand doped region 130, a channel is formed between the right side of the N+ region 132 and the right side of the P-type well region 131. In the right-hand doped region 130, a channel is formed between the left side of the N+ region 132 and the left side of the P-type well region 131. The designated region is the area that at least contains the channel of the doped region 130; that is, the designated region must contain the channel of the doped region 130.

[0073] JFET region 140 is disposed between the doped region 130 on the left and the doped region 130 on the right, and each side of JFET region 140 contacts one doped region 130. During device turn-on, a thin accumulation layer is formed above JFET region 140 and below gate region 160.

[0074] like Figure 1 As shown, the device structure of this embodiment further includes a gate region 160. The gate region 160 forms a gate. The gate region 160 is located above the epitaxial layer 120, and the gate region 160 covers a portion of the JFET region 140 and the doped region 130. The portion of the doped region 130 is at least the region containing the channel of the doped region 130, and may also include a portion of the N+ region 132 in addition to the region containing the channel of the doped region 130.

[0075] Gate region 160 includes a gate dielectric layer 161 and a gate polysilicon layer 162. The gate dielectric layer 161 is located above the epitaxial layer 120 and covers a portion of the JFET region 140 and the doped region 130. The gate polysilicon layer 162 is located above the gate dielectric layer 161.

[0076] like Figure 1 As shown, the device structure in this embodiment further includes an interlayer dielectric layer 170, i.e., an ILD (Inter Layer Dielectric) dielectric layer. The interlayer dielectric layer 170 is located above the epitaxial layer 120 and encloses the gate region 160.

[0077] like Figure 1 As shown, the device structure in this embodiment further includes a source metal layer 180 and a drain metal layer 190. The source metal layer 180 is located above the epitaxial layer 120 and covers the interlayer dielectric layer 170, the gate region 160, and the doped region 130. The drain metal layer 190 is located below the substrate 110. The source metal layer 180 forms the source, and the drain metal layer 190 forms the drain.

[0078] The principle of the planar SiC MOSFET device structure in this embodiment:

[0079] Compared to traditional devices, the planar SiC MOSFET device structure in this embodiment undergoes multiple exposures and wet etching processes with linearly increasing aperture widths on the upper surface of the epitaxial layer 120 before the formation of the doped region 130, i.e., before the implantation of the P-type well region 131. For example... Figure 4 As shown, a smooth micro-trench, or recess 151, is isotropically etched on the upper surface of the epitaxial layer 120, deflecting the (0001) crystal plane of the original channel towards the

[0001] crystal plane (c-axis) by 1°~2°, thereby changing the horizontal upper surface of the epitaxial layer 120 into the concave surface 150 of this embodiment. Through the provision of the recess 151 and the concave surface 150, the current density of the channel, accumulation layer, and JFET region 140 below the gate (i.e., gate region 160) can be optimized.

[0080] Figure 5a This is a current distribution diagram for a traditional device structure. Figure 5b This is a current distribution diagram of the device structure in this embodiment. Figure 6 This is a current density curve along the C1 tangent position for the device structure in this embodiment and the conventional device structure. Figure 7 This is a current density curve along the C2 tangent position for the device structure in this embodiment and the conventional device structure. Figure 8a This is a stress distribution diagram of a traditional device structure. Figure 8b This is a stress distribution diagram of the device structure in this embodiment. Figure 9a This is a diagram showing the electric field intensity distribution of a traditional device structure. Figure 9b This is a diagram showing the electric field distribution of the device structure in this embodiment. In the diagram, the Y-axis represents the width of the device structure, and the X-axis represents the height or depth of the device structure.

[0081] like Figure 5a and Figure 5b As shown, C1 is the tangent along the central axis of the JFET region 140, and C2 is the tangent along the upper surface of the epitaxial layer 120. Figure 6 In the current density curves shown by cutting the device structure of this embodiment and the conventional device structure along C1, the peak value of the curve represents the current density formed by the accumulation layer, the JEFT region, and the epitaxial layer 120. Regarding the peak value, the current density at the accumulation layer, the JEFT region, and the epitaxial layer 120 of the device structure of this embodiment is greater than that of the conventional device structure. The region where the peak value gradually decreases downwards represents the area gradually moving from the accumulation layer and the JEFT region towards the bottom of the epitaxial layer 120. Regarding this region where the peak value gradually decreases downwards, the current density in this region of the device structure of this embodiment is also greater than that of the conventional device. The flat region of the curve represents the region of the epitaxial layer 120. Regarding this region, the current density in this region of the device structure of this embodiment is also significantly greater than that of the conventional device. Therefore, the current density of the device structure of this embodiment is superior to that of the conventional device.

[0082] exist Figure 7 In the current density curves shown by cutting the device structure of this embodiment along C2 and the conventional device structure, the curve region with a Y-axis coordinate range of -1 to 1 represents the current density formed by the channel, accumulation layer, and JEFT region. Regarding the curve region with a Y-axis coordinate range of -1 to 1, the current density at the channel, accumulation layer, and JEFT region locations of the device structure of this embodiment is significantly greater than that at the channel, accumulation layer, and JEFT region locations of the conventional device structure. The curve region with a Y-axis coordinate range of -1 to -3 represents the current density of the left-side doped region 130. The curve region with a Y-axis coordinate range of 1 to 3 represents the current density of the right-side doped region 130. Regarding the current density distribution of the doped region 130, the current density of the doped region 130 in the device structure of this embodiment is slightly greater than that in the conventional device structure. From... Figure 8a and Figure 8b It can be intuitively seen that tensile stress is introduced at the channel, accumulation layer and JEFT region (i.e., the recess) of the device structure in this embodiment. This indicates that the current density at the channel, accumulation layer and JEFT region of the device structure in this embodiment is significantly greater than the current density at the channel, accumulation layer and JEFT region of the conventional device structure, thereby reducing the on-resistance of the device.

[0083] Therefore, as Figures 5a-8b As shown, by providing the recess 151 and the concave surface 150, the recess 151 structure can optimize the current density of the channel, accumulation layer, and JFET region 140 below the gate. Specifically, the change in surface crystal plane and the formation of tensile stress caused by the recess 151 can also optimize the surface mobility of the SiC MOSFET device structure, thereby increasing the current density and reducing the on-resistance of the device.

[0084] The principle behind improving mobility through crystal orientation is as follows: In mainstream planar 4H-SiC MOSFET devices, the channel is almost entirely fabricated on the (0001) crystal plane. This is the most commonly used and easily obtained substrate 110 epitaxial layer 120 orientation, but it also has the highest interface state density, resulting in very poor mobility. The recess 151 transforms the channel region from a purely (0001) plane into one that incorporates some of the desirable characteristics of the a-plane. This reduces interface state scattering and improves the carrier mobility on the surface; furthermore, the slight deflection directs electron transport into a valley with lower effective mass, reducing the effective electron mass.

[0085] The principle behind tensile stress improving mobility: Tensile stress is introduced through the recess 151. This tensile stress reduces the bandgap and causes valley splitting. The reduced bandgap can shield scattering from interface defects, while valley splitting reduces inter-valley scattering. Furthermore, the tensile stress in the device structure of this embodiment also leads to a decrease in the effective electron mass. All of these mechanisms demonstrate that the introduction of tensile stress can effectively improve the mobility of SiC MOSFET devices.

[0086] like Figure 9a and Figure 9b As shown, D1 is the gate oxide region above the JFET region 140 in a conventional device structure, and D2 is the gate oxide region above the JFET region 140 in the device structure of this embodiment. The maximum electric field strength of D1 is 3.6 V / cm, and the maximum electric field strength of D2 is 3.8 V / cm. It can be seen that the gate oxide strength of the device structure in this embodiment is consistent with that of the conventional device structure, which can also ensure the reliability of the gate oxide, thereby improving the reliability of the device.

[0087] Single-variable simulation results show that, compared with the traditional planar gate SiC MOSFET device structure, the device structure with the 2° micro-trench structure (i.e., recess 151) in this embodiment exhibits a 6.2% reduction in on-resistance. Due to the shielding effect of the JFET region 140, the gate oxide electric field strength does not significantly increase, ensuring the long-term reliability of the device. Figure 9a and Figure 9bAs shown. Therefore, the device structure of this embodiment has good compatibility with traditional device structures. It not only eliminates the need for additional masks, but also ensures that the device performance (such as the electric field strength of the gate oxide) other than the on-resistance will not be affected, and will not affect key parameters such as the breakdown voltage of the device. Furthermore, it can be combined with existing manufacturing processes to significantly reduce the on-resistance of the planar gate SiC MOSFET of this embodiment, thereby improving the performance, reliability, and practicality of the device in this embodiment.

[0088] The fabrication process of the planar SiC MOSFET device structure in this embodiment:

[0089] Step 1: As Figure 10 As shown, an epitaxial layer 120 is formed on the substrate 110. Wet etching is performed multiple times on the epitaxial layer 120 using the area defined by the photolithographic mask of the JFET region 140 to form a recess 151 and a concave surface 150. The depth of the recess 151 ranges from 0.05 μm to 0.2 μm. The angle of the recess 151 ranges from 1° to 4°.

[0090] Step Two: As Figure 11 As shown, a P-type well region 131 is formed on the epitaxial layer 120 by defining a region using a photolithographic mask and photoresist, followed by multiple high-temperature aluminum ion implantations. Then, an N+ region 132 is formed within the P-type well region 131 by defining a region using a self-aligned process and performing multiple high-temperature nitrogen ion implantations. The implantation dose range for the P-type well region 131 is 2E13~5E15 cm⁻¹. -2 The junction depth of the P-type well region 131 ranges from 0.6 μm to 1.4 μm. The injection dose range of the N+ region 132 is 2E15~4E16 cm. -2 The junction depth of N+ region 132 ranges from 0.2um to 0.5um.

[0091] Step 3: As Figure 12 As shown, a region is defined on the epitaxial layer 120 using a mask and a hard mask for the P+ region 133, and multiple high-temperature aluminum ion implantations are performed to form the P+ region 133 in the P-type well region 131, on the side of the N+ region 132 away from the JFET region 140. The implantation dose range of the P+ region 133 is 1E14~1E17 cm⁻¹. -2 The junction depth of P+ region 133 ranges from 0.3um to 0.8um.

[0092] Step Four: As Figure 13As shown, the JFET region 140 is formed on the epitaxial layer 120 by defining the region using a photolithographic mask and photoresist, and then undergoing multiple high-temperature nitrogen ion implantations. Subsequently, a carbon layer is deposited on the surface of the epitaxial layer 120 and subjected to high-temperature activation annealing to activate the implanted ions while preventing the high-temperature volatilization of silicon atoms. The implantation dose range of the JFET region 140 is 1E11~1E13 cm⁻¹. -2 The junction depth ranges from 0.4µm to 1.4µm. The annealing temperature is 1700℃ to 2000℃, and the annealing time is 10 min to 60 min.

[0093] Step 5: As Figure 14 As shown, a gate dielectric layer 161 is grown on the surface of the epitaxial layer 120 using thermal oxidation. Introducing a small amount of NO into the oxidizing atmosphere can significantly improve the SiO2 / SiC interface quality. A gate polysilicon 162 is chemically deposited on the gate dielectric layer 161, and photolithography and etching are performed at designated locations using a mask of the gate polysilicon 162 to form the gate region 160 structure. The material of the gate dielectric layer 161 includes, but is not limited to, SiO2, and the thickness of the gate dielectric layer 161 ranges from 0.02 μm to 0.12 μm. The thickness of the gate polysilicon 162 ranges from 0.3 μm to 1 μm.

[0094] Step Six: As Figure 15 As shown, an ILD dielectric layer is deposited on the surface of the epitaxial layer 120 and the gate region 160, forming an interlayer dielectric layer 170. Ohmic contact holes are formed at designated locations using a contact hole mask through photolithography and dielectric layer etching. Subsequently, metallic nickel is sputtered via physical vapor deposition and annealed to form ohmic contacts at the opening locations. The width of the ohmic electrode contact holes ranges from 0.3 μm to 1.2 μm. The materials of the ILD dielectric layer include, but are not limited to, silicon dioxide and borosilicate glass, with a thickness ranging from 0.4 μm to 1.2 μm.

[0095] Step Seven: As Figure 1 As shown, a source metal layer 180 is formed above the ILD dielectric layer, and a drain metal layer 190 is formed below the substrate 110. The metal layer material includes, but is not limited to, aluminum and copper, with a thickness of 2µm to 5µm. This ultimately forms the complete planar gate SiC MOSFET structure of this embodiment.

[0096] In the manufacturing process of the device structure in this embodiment, the device structure has extremely high compatibility with existing technologies such as traditional device structures, eliminating the need for additional photomasks and achieving cost reduction and efficiency improvement. Furthermore, without conflicting with existing technologies, the on-resistance of SiC MOSFET devices can be further reduced based on existing technologies, while also ensuring other performance characteristics of SiC MOSFET devices, thereby improving device performance, reliability, and practicality.

[0097] Example 2

[0098] Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a planar SiC MOSFET device structure, such as... Figure 16 As shown, the method for manufacturing a planar SiC MOSFET device structure as described in Example 1 includes:

[0099] S201, an epitaxial layer is formed on a substrate, wherein the substrate is a silicon carbide (SiC) substrate and the epitaxial layer is a SiC epitaxial layer;

[0100] S202, a doped region and a JFET region are formed on the epitaxial layer, wherein the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region, and the upper surface of the epitaxial layer are located on the same defined surface, which is a concave surface; the concave portion of the concave surface covers a designated area of ​​the JFET region and the doped region, so as to reduce the on-resistance of the device structure through the concave surface and the concave portion, wherein the designated area is a region that at least includes the channel of the doped region.

[0101] Since the manufacturing method of the planar SiC MOSFET device structure described in this embodiment is the same manufacturing method used to implement the planar SiC MOSFET device structure in Embodiment 1 of this application, those skilled in the art can understand the specific implementation methods and various variations of the manufacturing method of the planar SiC MOSFET device structure in this embodiment based on the planar SiC MOSFET device structure described in Embodiment 1 of this application. Therefore, how the manufacturing method of the planar SiC MOSFET device structure implements the planar SiC MOSFET device structure in Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the manufacturing method used to implement the planar SiC MOSFET device structure in Embodiment 1 of this application, it falls within the scope of protection of this application.

[0102] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0103] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A planar SiC MOSFET device structure, characterized in that, include: The substrate, the epitaxial layer on the substrate, the doped region and the JFET region on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate and the epitaxial layer is a SiC epitaxial layer; The JFET region is located between the doped regions, and the JFET region is in contact with the doped regions; The upper surface of the JFET region, the upper surface of the doped region, and the upper surface of the epitaxial layer are located on the same set surface, which is a concave surface. The concave portion of the concave surface covers a designated area of ​​the JFET region and the doped region, thereby reducing the on-resistance of the device structure through the concave surface and the concave portion, wherein the designated area is a region that at least includes the channel of the doped region; The angle of the recess is 1°~4° to increase the current density of the channel, accumulation layer and JFET region below the gate, reduce the interface state density, improve the carrier mobility on the surface, and introduce tensile stress to reduce scattering and reduce the effective electron mass, thereby further improving mobility. The depth of the recess ranges from 0.05um to 0.2um; the recess is a flat curved surface.

2. The planar SiC MOSFET device structure as described in claim 1, characterized in that, The maximum opening width of the recess is not less than the sum of the width of the JFET region and the channel width in the doped region.

3. The planar SiC MOSFET device structure as described in claim 2, characterized in that, The mask used in the manufacturing process of the recess is the same mask used in the manufacturing process of the JFET region.

4. The planar SiC MOSFET device structure as described in any one of claims 1 to 3, characterized in that, The doped region includes: a P-type well region, an N+ region, and a P+ region; The N+ region and the P+ region are located in the P-type well region, and the upper surface of the N+ region, the upper surface of the P+ region, and the upper surface of the P-type well region are located on the same designated surface; One side of the N+ region is close to the JFET region, and the other side of the N+ region is in contact with the P+ region.

5. The planar SiC MOSFET device structure as described in claim 4, characterized in that, Also includes: A gate region, located above the epitaxial layer, covering a portion of the JFET region and the doped region; The gate region includes: a gate dielectric layer and a gate polysilicon; The gate dielectric layer is located above the epitaxial layer, and the gate dielectric layer covers a portion of the JFET region and the doped region. The gate polysilicon is located on top of the gate dielectric layer.

6. The planar SiC MOSFET device structure as described in claim 5, characterized in that, Also includes: Interlayer dielectric layer; the interlayer dielectric layer is located above the epitaxial layer and encloses the gate region.

7. The planar SiC MOSFET device structure as described in claim 6, characterized in that, Also includes: Source metal layer and drain metal layer; The source metal layer is located above the epitaxial layer and covers the interlayer dielectric layer, the gate region, and the doped region; The drain metal layer is located beneath the substrate.

8. A method for manufacturing a planar SiC MOSFET device structure, characterized in that, A method for manufacturing a planar SiC MOSFET device structure as described in any one of claims 1-7; the manufacturing method includes: An epitaxial layer is formed on a substrate, wherein the substrate is a silicon carbide (SiC) substrate and the epitaxial layer is a SiC epitaxial layer; A doped region and a JFET region are formed on the epitaxial layer, wherein the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region, and the upper surface of the epitaxial layer are located on the same defined surface, which is a concave surface; the concave portion of the concave surface covers a designated area of ​​the JFET region and the doped region, so as to reduce the on-resistance of the device structure through the concave surface and the concave portion, wherein the designated area is a region that at least includes the channel of the doped region.

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