Video data transmission method, device and system

Abstract

Embodiments of the present invention provide a method, device, and system for transmitting video data. The method comprises: upon determining that a first processor is in an abnormal state, receiving first video data from M of N first data interfaces; and transmitting the first video data to a second processor via M second data interfaces, wherein the second processor is a normal processor and is configured to transmit the first video data to a storage device. This invention solves the problem of video data loss in related technologies and achieves the effect of completely storing video data.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a method, device and system for transmitting video data. Background Art

[0002] Digital Video Recorders (DVRs) evolved alongside multimedia technology, starting in the late 1990s and experiencing rapid growth in the early 2000s. DVRs are computer systems that integrate multiple functions, including video capture, encoding and compression, video storage, and network transmission. However, with the advancement of high-definition DVRs, the performance requirements for the codec's central processing unit (CPU) have become increasingly stringent, necessitating the use of two cascaded CPUs. If one of the two CPUs fails, the DVR device will be unable to start. If the DVR device's abnormality is not detected promptly, the video during that period cannot be recorded, resulting in video data loss. Summary of the Invention

[0003] The embodiments of the present invention provide a method, device and system for transmitting video data, so as to at least solve the problem of video data loss existing in the related art.

[0004] According to one embodiment of the present invention, a method for transmitting video data is provided, comprising: when it is determined that a first processor is in an abnormal state, receiving first video data from M first data interfaces out of N first data interfaces, wherein the above-mentioned first data interface is used to transmit the above-mentioned first video data to the above-mentioned first processor, and the above-mentioned first processor is used to transmit the above-mentioned first video data to a storage device, the above-mentioned N is a natural number greater than 1, and the above-mentioned M is a natural number less than or equal to the above-mentioned N; transmitting the above-mentioned first video data to a second processor through M second data interfaces, wherein the above-mentioned second processor is a processor in a normal state, and the above-mentioned second processor is used to transmit the above-mentioned first video data to the above-mentioned storage device.

[0005] According to another embodiment of the present invention, a video data transmission device is also provided, including: a first receiving module, used to receive first video data from M first data interfaces among N first data interfaces when it is determined that the first processor is in an abnormal state, wherein the above-mentioned first data interface is used to transmit the above-mentioned first video data to the above-mentioned first processor, and the above-mentioned first processor is used to transmit the above-mentioned first video data to a storage device, the above-mentioned N is a natural number greater than 1, and the above-mentioned M is a natural number less than or equal to the above-mentioned N; a first transmission module, used to transmit the above-mentioned first video data to the second processor through M second data interfaces, wherein the above-mentioned second processor is a processor in a normal state, and the above-mentioned second processor is used to transmit the above-mentioned first video data to the above-mentioned storage device.

[0006] In an exemplary embodiment, the above-mentioned device determines that the above-mentioned first processor is in an abnormal state in the following manner: when an abnormality occurs in the communication between the above-mentioned first processor and the complex programmable logic device, it is determined that the above-mentioned first processor is in an abnormal state; the above-mentioned first receiving module includes: a first determination unit, used to determine the data interface in the N above-mentioned first data interfaces that is in an open state, obtain M above-mentioned first data interfaces, and receive the above-mentioned first video data from the M above-mentioned first data interfaces.

[0007] In an exemplary embodiment, the above-mentioned first determination unit includes: a first connection sub-unit, used to determine the first data interface among the N above-mentioned first data interfaces that is connected to the above-mentioned complex programmable logic device and is in a data transmission state as a data interface in the above-mentioned open state, and obtain M above-mentioned first data interfaces, wherein the connection between the above-mentioned complex programmable logic device and the M above-mentioned first data interfaces is set by the above-mentioned first processor.

[0008] In an exemplary embodiment, the above-mentioned device also includes: a first determination module, which is used to determine the second data interface in the P second data interfaces included in the above-mentioned second processor that is in a high-impedance state before transmitting the above-mentioned first video data to the above-mentioned second processor through the M second data interfaces, so as to obtain the M above-mentioned second data interfaces, wherein the high-impedance state of the M above-mentioned second data interfaces is set by the above-mentioned second processor, and the other second data channels among the P above-mentioned second data channels except the M above-mentioned second data channels are used to transmit the second video data to the above-mentioned second processor, and the above-mentioned second processor is also used to transmit the above-mentioned second video data to the above-mentioned storage device, and the above-mentioned P is a natural number greater than or equal to the above-mentioned N; a first connection module, which is used to establish a connection with the M above-mentioned second data interfaces.

[0009] In an exemplary embodiment, the above-mentioned device also includes: a first sending module, which is used to send an on instruction to the switching device to control the on of the above-mentioned switching device after the above-mentioned first video data is transmitted to the above-mentioned second processor through M second data interfaces; a first indication module, which is used to instruct the above-mentioned switching device to send on information to the above-mentioned second processor when the above-mentioned switching device is in the on state, wherein the above-mentioned on information is used to instruct the above-mentioned second processor to transmit the above-mentioned first video data to the above-mentioned storage device.

[0010] According to another embodiment of the present invention, a video data transmission device is also provided, including: a second receiving module, used to receive first video data from M second data interfaces among P second data interfaces when it is determined that the first processor is in an abnormal state, wherein the above-mentioned first video data is the video data transmitted from the M first data interfaces in the above-mentioned first processor to the first processor, and the above-mentioned first processor is used to transmit the above-mentioned first video data to a storage device, the above-mentioned P is a natural number greater than 1, and the above-mentioned M is a natural number less than or equal to the above-mentioned P; the second transmission module is used to transmit the above-mentioned first video data to the above-mentioned storage device.

[0011] In an exemplary embodiment, the above-mentioned device also includes: a first setting module, which is used to set the data transmission status of the M second data interfaces among the P second data interfaces to a high-impedance state before receiving the first video data from the M second data interfaces when it is determined that the first processor is in an abnormal state.

[0012] In an exemplary embodiment, the second transmission module includes: a first receiving unit for receiving the start-up information sent by the switching device, wherein the start-up information is used to indicate that the switching device is in the on state; and a first response unit for responding to the start-up information and transmitting the first video data to the storage device.

[0013] In an exemplary embodiment, the above-mentioned device also includes: a third receiving module, used to receive the second video data transmitted by other above-mentioned second data interfaces, wherein the other above-mentioned second data interfaces are data interfaces other than the M above-mentioned second data interfaces among the P above-mentioned second data interfaces; a third transmission module, used to transmit the above-mentioned second video data to the above-mentioned storage device.

[0014] According to another embodiment of the present invention, a video data transmission system is provided, comprising: a complex programmable logic device, wherein the complex programmable logic device comprises the above-mentioned video data transmission device; a first processor, a second processor, wherein the above-mentioned second processor comprises the above-mentioned video data transmission device.

[0015] In an exemplary embodiment, the system further includes: K first data acquisition devices, connected to the first processor, for acquiring the first video data; wherein each of the first data acquisition devices includes a first data interface, the first data interface is used to send the first video data to the first processor, or to transmit the first video data to the complex programmable logic device when the first processor is in an abnormal state, the complex programmable logic device is used to transmit the first video data to the second processor through M first data interfaces, and K is a natural number greater than or equal to 1.

[0016] In an exemplary embodiment, the system further includes: K second data acquisition devices, connected to the second processor, for acquiring second video data; wherein each of the second data acquisition devices includes a second data interface, and the second data interface is used to send the second video data to the second processor, or to transmit the second video data to the complex programmable logic device when the second processor is in an abnormal state, and the complex programmable logic device is used to transmit the second video data to the first processor through M second data interfaces, wherein K is a natural number greater than or equal to 1.

[0017] In an exemplary embodiment, the system further includes: a first integrated circuit bus, used to connect the first processor and the complex programmable logic device, and used to determine the state of the first data interface when the first processor is in an abnormal state; a second integrated circuit bus, used to connect the second processor and the complex programmable logic device, and used to determine the state of the second data interface when the second processor is in an abnormal state.

[0018] In an exemplary embodiment, the system further includes: a device bus for connecting the first processor and the second processor.

[0019] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0020] According to another embodiment of the present invention, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0021] With the present invention, if the first processor experiences an anomaly and is unable to transmit video data, the first video data is received from M of the N first data interfaces, transmitted to the second processor via M second data interfaces, and then promptly transferred to a storage device for storage by the second processor. This prevents video data loss due to the anomaly in the first processor. Therefore, the problem of video data loss in the related art is resolved, achieving complete storage of video data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of two CPUs cascaded to implement video data storage in the related art;

[0023] Figure 2 This is a hardware structure block diagram of a mobile terminal for an image processing method according to an embodiment of the present invention;

[0024] Figure 3 is a flowchart of a method for transmitting video data according to an embodiment of the present invention (I);

[0025] Figure 4 1 is a schematic diagram of the operation of the AD chip according to an embodiment of the present invention (I);

[0026] Figure 5 2 is a schematic diagram of the operation of the AD chip according to an embodiment of the present invention;

[0027] Figure 6 3 is a working schematic diagram of the AD chip according to an embodiment of the present invention;

[0028] Figure 7 is a flowchart (II) of a method for transmitting video data according to an embodiment of the present invention;

[0029] Figure 8 is a schematic diagram of the normal operation of the master CPU and the slave CPU according to an embodiment of the present invention;

[0030] Figure 9 is a schematic diagram of abnormal operation of a main CPU according to an embodiment of the present invention;

[0031] Figure 10 is a schematic diagram of operation from a CPU according to an embodiment of the present invention;

[0032] Figure 11 is a schematic diagram of abnormal operation of a slave CPU according to an embodiment of the present invention;

[0033] Figure 12 is an implementation flow chart according to a specific embodiment of the present invention;

[0034] Figure 131 is a structural block diagram of a video data transmission device according to an embodiment of the present invention (I);

[0035] Figure 14 2 is a structural block diagram of a video data transmission device according to an embodiment of the present invention;

[0036] Figure 15 FIG. 4 is a structural block diagram of a video data transmission system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0038] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0039] First, the related technologies involved in the present invention are described:

[0040] The high definition of video recording equipment requires two CPUs to be cascaded to process video data. For example, a video recording device that supports 16-channel 1080P@30 frames (supporting 4 million @30 frames) video access and 16-channel 1080P@30 frames (supporting 4 million @15 frames encoding) encoding capabilities needs to be implemented through two CPUs cascaded, such as Figure 1 As shown, it is a schematic diagram of video data storage achieved by cascading two CPUs, including a master CPU and a slave CPU. The slave CPU transmits the acquired video data to the master CPU, and the master CPU transmits the video data acquired from the slave CPU and the video data acquired by the master CPU to the storage module for storage.

[0041] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 2 FIG. 1 is a hardware structure diagram of a mobile terminal according to an image processing method of an embodiment of the present invention. Figure 2 As shown, the mobile terminal may include one or more ( Figure 2 Only one is shown) a processor 202 (the processor 202 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 204 for storing data, wherein the mobile terminal may also include a transmission device 206 and an input and output device 208 for communication functions. It will be understood by those skilled in the art that Figure 2 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 2More or fewer components than shown, or with Figure 2 Different configurations shown.

[0042] The memory 204 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the image processing method in the embodiment of the present invention. The processor 202 executes various functional applications and data processing by running the computer program stored in the memory 204, that is, implementing the above-mentioned method. The memory 204 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 204 may further include a memory remotely located relative to the processor 202, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0043] The transmission device 206 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, the transmission device 206 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 206 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0044] This embodiment provides a method for transmitting video data. Figure 3 Flowchart (1) of the video data transmission method according to an embodiment of the present invention, Figure 3 As shown, the process includes the following steps:

[0045] Step S302: When it is determined that the first processor is in an abnormal state, first video data is received from M first data interfaces among the N first data interfaces, where the first data interface is used to transmit the first video data to the first processor, and the first processor is used to transmit the first video data to a storage device, where N is a natural number greater than 1, and M is a natural number less than or equal to N.

[0046] Step S304: The first video data is transmitted to the second processor through M second data interfaces, wherein the second processor is a processor in a normal state, and the second processor is used to transmit the first video data to a storage device.

[0047] In this embodiment, the first processor and the second processor may be mutually active and standby processors. For example, the first processor is a master CPU, the second processor is a slave CPU, and the master CPU and the slave CPU may be connected via a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, abbreviated as PCIE).

[0048] In this embodiment, the first data interface may be a View Object (VO) interface provided in an analog-to-digital converter (ADC) chip. The values of N and M can be flexibly set based on the actual application scenario or the performance of the AD chip. For example, the two AD chips connected to the first processor include eight VO interfaces. The second processor may have the same number of AD chips and VO interfaces as the first processor, or a different number.

[0049] In this embodiment, an AO chip includes 4 analog inputs and 4 digital BT656 outputs. When the analog input interface and the output of the VO interface are one-to-one, up to 4 400M@30 frames or 4 800M@15 frames video sources can be connected. Figure 4 This scenario can be applied when the first processor and the second processor are both in normal working state, and the VO interfaces in the AO chips provided in the first processor and the second processor are all open. When two analog channels are time-division multiplexed and output through the same set of VO interfaces (for example, the four VO interfaces included in the AD chip are opened and two VO interfaces are opened for video data transmission), up to 4 channels of 1080P video sources can be connected, such as Figure 5 This scenario can be applied to the case where the first processor or the second processor is abnormal, and the VO interface in the AO chip set in the first processor and the second processor is half-open. When four-way analog time division multiplexing is used and output through the same group of VO interfaces (for example, the four-way VO interfaces included in the AD chip are opened and one VO interface is opened for video data transmission), up to four 720P video sources can be connected, such as Figure 6 This scenario can be applied to the case where the first processor or the second processor is malfunctioning, and a VO interface is enabled in the AO chip provided in the first processor and the second processor to transmit video data.

[0050] Among them, the execution subject of the above steps can be a server, a terminal or a specific processor set in the server, or a processor or processing device set relatively independently from the terminal or server, such as a complex programmable logic device (CPLD), but is not limited to this.

[0051] Through the above steps, if the first processor encounters an anomaly and is unable to transmit video data, the first video data is received from M of the N first data interfaces, transmitted to the second processor via the M second data interfaces, and then promptly transferred to the storage device for storage by the second processor. This prevents video data loss due to the anomaly of the first processor. Therefore, the problem of video data loss in the related art is resolved, achieving complete storage of video data.

[0052] In an exemplary embodiment, determining that the first processor is in an abnormal state includes: determining that the first processor is in an abnormal state when an abnormality occurs in communication between the first processor and the complex programmable logic device;

[0053] In this embodiment, a complex programmable logic device (CPLD) is connected to the first processor via an inter-integrated circuit (IIC) bus. If the first processor fails, the IIC interface transmits fault information of the first processor to the CPLD, and the CPLD detects the failure of the first processor from the fault information.

[0054] In an exemplary embodiment, receiving first video data from M first data interfaces among N first data interfaces includes: determining data interfaces that are in an open state among the N first data interfaces, obtaining M first data interfaces, and receiving first video data from the M first data interfaces.

[0055] In this embodiment, when M and N are equal, the N first data interfaces in the AD chip connected to the first processor are all open, and the transmitted video resolution is the maximum, for example, Figure 4 As shown, the 4 data channels in the analog input interface and the outputs of the 4 VO interfaces correspond one to one, and can transmit 4 channels of 400M@30 frames or 4 channels of 800M@15 frames of video data. It should be noted that when the VO interfaces in the first processor are fully open, the second processor needs to open N second data interfaces to receive the video data transmitted by the N first data interfaces. The second processor needs to set P second data interfaces greater than N to use the remaining second data interfaces to transmit the video data in the second processor, thereby achieving the purpose of ensuring the continuity of the video data without reducing the video resolution in the first processor. When M is less than N, a part of the N first data interfaces in the AD chip connected to the first processor is opened, for example, Figure 5As shown, two VO interfaces are enabled to access four 1080P video sources. The second processor then needs to configure N second data interfaces to receive video data transmitted by N first data interfaces, and use the remaining second data interfaces to transmit video data within the second processor. This ensures continuous video data transmission by reducing video resolution.

[0056] In an exemplary embodiment, determining the data interfaces in the N first data interfaces that are in an enabled state to obtain M first data interfaces includes:

[0057] S1. Determine the first data interface among N first data interfaces that is connected to the complex programmable logic device and is in a data transmission state as a data interface in an open state, and obtain M first data interfaces, wherein the connection between the complex programmable logic device and the M first data interfaces is set by the first processor.

[0058] In this embodiment, when both the first processor and the second processor are in normal state, the number of first data interfaces to be enabled in the first processor and the number of second data interfaces to be enabled in the second processor are negotiated through the PCIE interface when the first processor fails. Alternatively, the number of second data interfaces to be enabled and the number of first data interfaces to be enabled are negotiated through the PCIE interface when the second processor fails.

[0059] In an exemplary embodiment, before transmitting the first video data to the second processor through the M second data interfaces, the method further includes:

[0060] S1, determining a second data interface in a high-impedance state among P second data interfaces included in a second processor, obtaining M second data interfaces, wherein the high-impedance state of the M second data interfaces is set by the second processor, the other second data channels among the P second data channels except the M second data channels are used to transmit second video data to the second processor, and the second processor is further used to transmit the second video data to a storage device, and P is a natural number greater than or equal to N;

[0061] S2: Establish connections with M second data interfaces.

[0062] In this embodiment, P can be greater than N or less than or equal to N. For example, when P is greater than N, the purpose of ensuring the continuity of video data can be achieved without reducing the video resolution in the first processor. When P is less than or equal to N, the purpose of ensuring the continuity of video data transmission can be achieved by reducing the video resolution. In addition, after the M second data interfaces are set to a high-impedance state, the M second data interfaces no longer transmit the second video data transmitted by the data channel in the AD chip in the second processor, but instead receive the first video data transmitted by the CPLD, thereby achieving the goal of taking over the video data of the first processor by the second processor.

[0063] In an exemplary embodiment, after transmitting the first video data to the second processor through the M second data interfaces, the method further includes:

[0064] S1, sending an opening instruction to the switch device to control the opening of the switch device;

[0065] S2: When the switch device is in the on state, instruct the switch device to send an on message to the second processor, wherein the on message is used to instruct the second processor to transmit the first video data to the storage device.

[0066] In this embodiment, the CPLD is connected to the storage device via a switch device. After receiving the first video data from the M first data interfaces, the CPLD sends an enable instruction to the switch device to control the switch device to be enabled. Both the first processor and the second processor are connected to the storage device via the switch device. Only when the switch device is enabled are the first processor and the second processor allowed to transmit video data to the storage device. This enhances control over video data transmission between the first and second processors.

[0067] This embodiment provides a method for transmitting video data. Figure 7 Flowchart (II) of the video data transmission method according to an embodiment of the present invention, as shown in FIG. Figure 7 As shown, the process includes the following steps:

[0068] Step S702: When it is determined that the first processor is in an abnormal state, first video data is received from M second data interfaces among the P second data interfaces, wherein the first video data is video data transmitted from the M first data interfaces among the first processor to the first processor, and the first processor is configured to transmit the first video data to a storage device, where P is a natural number greater than 1, and M is a natural number less than or equal to P.

[0069] Step S704: Transmit the first video data to the storage device.

[0070] The execution subject of the above steps may be a specific processor provided in the server, or a processor or processing device provided relatively independently from the terminal or server, for example, the second processor in this embodiment, but not limited thereto.

[0071] Through the above steps, if the first processor encounters an abnormality and cannot transmit video data, the first video data is received from M of the N first data interfaces, and the first video data is transmitted to the second processor via the M second data interfaces. The second processor then promptly transmits the first video data to the storage device for storage, preventing video data loss due to the abnormality of the first processor. Therefore, the problem of video data loss existing in the related art is solved, and the effect of complete storage of video data is achieved.

[0072] In an exemplary embodiment, when it is determined that the first processor is in an abnormal state, the method further includes:

[0073] S1 , before receiving first video data from M second data interfaces among P second data interfaces, setting the data transmission states of the M second data interfaces to a high impedance state.

[0074] In an exemplary embodiment, transferring the first video data to a storage device includes:

[0075] S1, receiving a start-up message sent by a switch device, wherein the start-up message is used to indicate that the switch device is in an on state;

[0076] S2: In response to the start-up information, transmit the first video data to the storage device.

[0077] In an exemplary embodiment, the method further comprises:

[0078] S1, receiving second video data transmitted by other second data interfaces, wherein the other second data interfaces are data interfaces other than the M second data interfaces among the P second data interfaces;

[0079] S2: Transmit the second video data to the storage device.

[0080] In this embodiment, when P is greater than N, M of the P second data interfaces can be set to a high-impedance state to transmit the first video data. This can achieve the purpose of ensuring the continuity of video data without reducing the video resolution in the first processor and the video resolution in the second processor. When P is less than or equal to N, M of the P second data interfaces can be set to a high-impedance state to transmit the first video data. This can achieve the purpose of ensuring the continuity of video data transmission by reducing the video resolution in the first processor and the video resolution in the second processor. In addition, after the M second data interfaces are set to a high-impedance state, the M second data interfaces no longer transmit the second video data transmitted by the data channel in the AD chip in the second processor, but instead receive the first video data transmitted by the CPLD, thereby achieving the video data of the first processor being taken over by the second processor.

[0081] Obviously, the embodiments described above are only part of the embodiments of the present invention, rather than all the embodiments.

[0082] The present invention will be specifically described below in conjunction with embodiments:

[0083] This embodiment is described using a master CPU and a slave CPU as an example. When one of the CPUs fails, the other CPU takes over all video access and video storage services to ensure continuity of the video service.

[0084] In this embodiment, both the master and slave CPUs acquire video data via the AD chip, i.e., coaxial communication via the AD chip. Coaxial communication refers to the transmission of control signals over a coaxial cable, which transmits both video and 485 signals. Coaxial communication enables data communication between the backend DVR and the frontend camera, supporting both forward and reverse communication: forward communication from camera to DVR and reverse communication from DVR to camera.

[0085] This embodiment, based on the AD video access feature and the coaxial reverse control feature, uses dual CPUs to work together. When one CPU malfunctions, the video access resolution is reduced to allow the other CPU to take over all core services. This mainly includes the following embodiments:

[0086] Example 1: When the master CPU and slave CPU are operating normally, the access and storage paths of video data are as follows: Figure 8As shown, the bold path represents the video data transmission path. The maximum video access and encoding capabilities remain at the advertised capacity, for example, 16 channels of 400M@30 video access and 16 channels of 1080P encoding and storage access. In this case, the four VO interfaces corresponding to the four AD chips are all configured as outputs, and the eight digital signals connected to the CPLD are all configured as inputs.

[0087] Example 2: When the main CPU is working abnormally and the slave CPU is working normally, the video access and storage path is as follows: Figure 9 As shown, the bold path represents the transmission path of the video data. At this time, the maximum video access capability and encoding capability are maintained at half of the declared capability, for example, 16-channel 1080@30 video access and 8-channel 1080P encoding storage access; in this case, the VO3 interface and VO4 interface of the AD chip hanging from the CPU are synchronously set to input high-impedance state, and the remaining VO interfaces maintain their original output state unchanged. Of the 8 groups of signals of the CPLD, the 4 groups connected to the main CPU are set to input, and the 4 groups connected to the slave CPU are set to output. In this embodiment, the VO3 interface and VO4 interface of the AD chip hanging from the CPU are synchronously set to input high-impedance state for the following reasons: Figure 10 As shown in the figure, the bold path goes from the CPLD output to the slave CPU, and the AD chip outputs to the slave CPU. If the VO interface status of the AD chip is not set, all VO interfaces will output to the slave CPU, causing signal conflict. In this case, the AD chip has switched from 4-channel output to 2-channel time-division multiplexing mode. The corresponding V03 and V04 interfaces are set to high-impedance input, which does not affect the CPLD output signal. This allows the AD chip under the master CPU to normally collect video data, and the slave CPU retains and stores the video data collected by the AD chip under the master CPU as intact as possible.

[0088] Example 3: When the slave CPU is working abnormally and the master CPU is working normally, the video access and storage path is as follows: Figure 11 As shown in the figure, the bold path represents the video data transmission path. In this case, the maximum video data access and encoding capabilities are reduced to half of the advertised capabilities. For example, 16 channels of 1080@30 video are accessed, and 8 channels of 1080P encoding and storage are accessed. In this case, the VO3 and VO4 interfaces of the AD chip under the master CPU are simultaneously set to input high-impedance, while the remaining VO interfaces remain in their original output states. Of the eight signal groups of the CPLD, four connected to the master CPU are set to output, and the four connected to the slave CPUs are set to input. This allows the AD chip under the slave CPU to normally acquire video data, and the master CPU to preserve and store the video data captured by the AD chip under the slave CPU as intact as possible.

[0089] like Figure 12FIG. 1 is a flowchart of an implementation in this embodiment, which includes the following steps:

[0090] S1201: The device starts and operates in state 1, where state 1 indicates that both the master CPU and the slave CPU in Example 1 are in normal operation.

[0091] S1202, determining whether the CPLD is communicating normally with the master and slave CPUs, and determining whether the master CPU and the slave CPU are communicating normally;

[0092] S1203: If the CPLD communicates normally with the master and slave CPUs, and the master CPU and the slave CPU communicate normally, then the operation in state 1 is maintained.

[0093] S1204, determining whether the communication between the CPLD and the slave CPU is abnormal;

[0094] S1205: If the communication between the CPLD and the slave CPU is normal, determine whether the communication between the CPLD and the master CPU is abnormal.

[0095] S1206: If the CPLD and the master CPU communicate abnormally, the CPLD switches to state 2 and triggers an alarm. State 2 indicates that the master CPU is abnormal and the slave CPU is normal in Example 2.

[0096] S1207, determining whether the current video access has a resolution exceeding 1080P;

[0097] S1208: For channels that exceed the resolution, reverse 485 and switch the camera resolution to 1080P;

[0098] S1209, keep the configuration unchanged;

[0099] S1210, determining whether the communication between the CPLD and the main CPU is abnormal;

[0100] S1211, maintain the default state 1 operation and trigger the alarm at the same time;

[0101] S1212, switching to operation state 3 and triggering an alarm at the same time, wherein state 3 is used to indicate that the slave CPU in Example 3 is abnormal and the master CPU is normal;

[0102] S1213, determining whether the current video access has a resolution exceeding 1080P;

[0103] S1214: For channels that exceed the resolution, reverse 485 and switch the camera resolution to 1080P;

[0104] S1215, keep the configuration unchanged.

[0105] In summary, in this embodiment, when one of the CPUs fails, the other CPU takes over all core services of video access and video storage, and outputs an alarm to indicate the failure, thereby enhancing the reliability of the device.

[0106] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0107] This embodiment also provides a video data transmission device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented using software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0108] Figure 13 1 is a structural block diagram of a video data transmission device according to an embodiment of the present invention (I), as shown in FIG. Figure 13 As shown, the device includes:

[0109] a first receiving module 1302, configured to, when determining that the first processor is in an abnormal state, receive first video data from M first data interfaces among the N first data interfaces, wherein the first data interfaces are configured to transmit the first video data to the first processor, and the first processor is configured to transmit the first video data to a storage device, wherein N is a natural number greater than 1, and M is a natural number less than or equal to N;

[0110] The first transmission module 1304 is used to transmit the above-mentioned first video data to the second processor through M second data interfaces, wherein the above-mentioned second processor is a processor in a normal state, and the above-mentioned second processor is used to transmit the above-mentioned first video data to the above-mentioned storage device.

[0111] In an exemplary embodiment, the apparatus determines that the first processor is in an abnormal state by: determining that the first processor is in an abnormal state when an abnormality occurs in communication between the first processor and the complex programmable logic device;

[0112] The first receiving module includes:

[0113] The first determining unit is configured to determine an open data interface among the N first data interfaces, obtain the M first data interfaces, and receive the first video data from the M first data interfaces.

[0114] In an exemplary embodiment, the first determining unit includes:

[0115] The first connection subunit is used to determine the first data interface among the N first data interfaces that is connected to the complex programmable logic device and is in a data transmission state as the data interface in the above-mentioned open state, and obtain M first data interfaces, wherein the connection between the complex programmable logic device and the M first data interfaces is set by the above-mentioned first processor.

[0116] In an exemplary embodiment, the apparatus further comprises:

[0117] a first determining module, configured to, before transmitting the first video data to the second processor via the M second data interfaces, determine which second data interfaces among the P second data interfaces included in the second processor are in a high-impedance state, thereby obtaining the M second data interfaces, wherein the high-impedance state of the M second data interfaces is set by the second processor, and the other second data channels among the P second data channels except the M second data channels are used to transmit the second video data to the second processor, and the second processor is further configured to transmit the second video data to the storage device, and the P is a natural number greater than or equal to the N;

[0118] The first connection module is used to establish connections with the M second data interfaces.

[0119] In an exemplary embodiment, the apparatus further comprises:

[0120] a first sending module, configured to send an opening instruction to the switch device to control the opening of the switch device after transmitting the first video data to the second processor through the M second data interfaces;

[0121] The first instruction module is used to instruct the switching device to send an activation message to the second processor when the switching device is in an on state, wherein the activation message is used to instruct the second processor to transmit the first video data to the storage device.

[0122] Figure 14 FIG. 2 is a block diagram of a video data transmission device according to an embodiment of the present invention. Figure 14 As shown, the device includes:

[0123] a second receiving module 1402, configured to, when determining that the first processor is in an abnormal state, receive first video data from M second data interfaces among the P second data interfaces, wherein the first video data is video data transmitted from the M first data interfaces among the first processor to the first processor, and the first processor is configured to transmit the first video data to a storage device, wherein P is a natural number greater than 1, and M is a natural number less than or equal to P;

[0124] The second transmission module 1404 is configured to transmit the first video data to the storage device.

[0125] In an exemplary embodiment, the above-mentioned device also includes: a first setting module, which is used to set the data transmission status of the M second data interfaces among the P second data interfaces to a high-impedance state before receiving the first video data from the M second data interfaces when it is determined that the first processor is in an abnormal state.

[0126] In an exemplary embodiment, the second transmission module includes:

[0127] A first receiving unit is configured to receive the opening information sent by the switch device, wherein the opening information is used to indicate that the switch device is in an open state;

[0128] The first responding unit is configured to respond to the start-up information and transmit the first video data to the storage device.

[0129] In an exemplary embodiment, the apparatus further comprises:

[0130] A third receiving module is configured to receive the second video data transmitted by the other second data interfaces, wherein the other second data interfaces are data interfaces other than the M second data interfaces among the P second data interfaces;

[0131] The third transmission module is used to transmit the second video data to the storage device.

[0132] Figure 15 FIG. 1 is a structural block diagram of a video data transmission system according to an embodiment of the present invention. Figure 15 As shown, the system includes:

[0133] Complex programmable logic device 1502, wherein the complex programmable logic device includes Figure 13 A transmission device for video data in;

[0134] The first processor 1504,

[0135] The second processor 1506 includes Figure 14 A device for transmitting video data in.

[0136] In an exemplary embodiment, the system further comprises:

[0137] K first data acquisition devices, connected to the first processor, for acquiring the first video data;

[0138] Among them, each of the above-mentioned first data acquisition devices includes a first data interface, and the above-mentioned first data interface is used to send the above-mentioned first video data to the above-mentioned first processor, or to transmit the above-mentioned first video data to the above-mentioned complex programmable logic device when the above-mentioned first processor is in an abnormal state. The above-mentioned complex programmable logic device is used to transmit the above-mentioned first video data to the above-mentioned second processor through M above-mentioned first data interfaces, and the above-mentioned K is a natural number greater than or equal to 1.

[0139] In an exemplary embodiment, the system further comprises:

[0140] K second data acquisition devices, connected to the second processor, for acquiring second video data;

[0141] Among them, each of the above-mentioned second data acquisition devices includes a second data interface, and the above-mentioned second data interface is used to send the above-mentioned second video data to the above-mentioned second processor, or to transmit the above-mentioned second video data to the above-mentioned complex programmable logic device when the above-mentioned second processor is in an abnormal state, and the above-mentioned complex programmable logic device is used to transmit the above-mentioned second video data to the above-mentioned first processor through M above-mentioned second data interfaces, wherein the above-mentioned K is a natural number greater than or equal to 1.

[0142] In an exemplary embodiment, the system further comprises:

[0143] a first integrated circuit bus, configured to connect the first processor and the complex programmable logic device, and to determine a state of the first data interface when the first processor is in an abnormal state;

[0144] The second integrated circuit bus is used to connect the second processor and the complex programmable logic device, and is used to determine the state of the second data interface when the second processor is in an abnormal state.

[0145] In an exemplary embodiment, the system further comprises:

[0146] The device bus is used to connect the first processor and the second processor.

[0147] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0148] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0149] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0150] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0151] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0152] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0153] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0154] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for transmitting video data, characterized in that: include: In a case where it is determined that the first processor is in an abnormal state, receiving first video data from M first data interfaces among N first data interfaces, wherein the first data interface is used to transmit the first video data to the first processor, and the first processor is used to transmit the first video data to a storage device, wherein N is a natural number greater than 1, and M is a natural number less than or equal to N; Transmitting the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state, and the second processor is used to transmit the first video data to the storage device; Before transmitting the first video data to the second processor through M second data interfaces, the method also includes: determining the second data interface in a high-impedance state among the P second data interfaces included in the second processor to obtain M second data interfaces, wherein the high-impedance state of the M second data interfaces is set by the second processor, and the other second data channels among the P second data channels except the M second data channels are used to transmit the second video data to the second processor, and the second processor is also used to transmit the second video data to the storage device, and P is a natural number greater than or equal to N; establishing a connection with the M second data interfaces.

2. The method according to claim 1, characterized in that Determining that the first processor is in an abnormal state includes: determining that the first processor is in an abnormal state when communication between the first processor and the complex programmable logic device is abnormal; Receiving first video data from M first data interfaces among N first data interfaces includes: determining a data interface that is in an open state among the N first data interfaces, obtaining M first data interfaces, and receiving the first video data from the M first data interfaces.

3. The method according to claim 2, characterized in that Determining a data interface that is in an open state among the N first data interfaces to obtain M first data interfaces includes: The first data interface among the N first data interfaces that is connected to the complex programmable logic device and is in a data transmission state is determined as the data interface in the open state, to obtain M first data interfaces, wherein the connection between the complex programmable logic device and the M first data interfaces is set by the first processor.

4. The method according to claim 1, wherein After transmitting the first video data to the second processor through the M second data interfaces, the method further includes: Sending an opening instruction to the switch device to control the opening of the switch device; When the switch device is in the on state, the switch device is instructed to send an on message to the second processor, wherein the on message is used to instruct the second processor to transmit the first video data to the storage device.

5. A method for transmitting video data, characterized in that: include: In a case where it is determined that the first processor is in an abnormal state, receiving first video data from M second data interfaces among the P second data interfaces, wherein the first video data is video data transmitted from the M first data interfaces among the first processor to the first processor, and the first processor is configured to transmit the first video data to a storage device, wherein P is a natural number greater than 1, and M is a natural number less than or equal to P; transmitting the first video data to the storage device; Among them, the M second data interfaces are second data interfaces in a high-impedance state among the P second data interfaces included in the second processor, the high-impedance state of the M second data interfaces is set by the second processor, and the other second data channels among the P second data channels except the M second data channels are used to transmit second video data to the second processor, and the second processor is also used to transmit the second video data to the storage device, and P is a natural number greater than or equal to N.

6. The method according to claim 5, characterized in that In the case where it is determined that the first processor is in an abnormal state, the method further includes: Before receiving the first video data from M second data interfaces among the P second data interfaces, the data transmission states of the M second data interfaces are set to a high impedance state.

7. The method according to claim 5, characterized in that The step of transmitting the first video data to a storage device includes: receiving a start message sent by a switch device, wherein the start message is used to indicate that the switch device is in an on state; In response to the start-up information, the first video data is transmitted to the storage device.

8. The method according to claim 5, characterized in that The method further comprises: receiving second video data transmitted by other second data interfaces, wherein the other second data interfaces are data interfaces other than the M second data interfaces among the P second data interfaces; The second video data is transferred to the storage device.

9. A video data transmission device, characterized in that: include: a first receiving module, configured to, when determining that the first processor is in an abnormal state, receive first video data from M first data interfaces among the N first data interfaces, wherein the first data interfaces are configured to transmit the first video data to the first processor, and the first processor is configured to transmit the first video data to a storage device, wherein N is a natural number greater than 1, and M is a natural number less than or equal to N; A first transmission module, configured to transmit the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state, and the second processor is configured to transmit the first video data to the storage device; a first determining module, configured to, before transmitting the first video data to the second processor through the M second data interfaces, determine which second data interfaces among the P second data interfaces included in the second processor are in a high-impedance state, thereby obtaining the M second data interfaces, wherein the high-impedance state of the M second data interfaces is set by the second processor, and the other second data channels among the P second data channels except the M second data channels are used to transmit the second video data to the second processor, and the second processor is further configured to transmit the second video data to the storage device, where P is a natural number greater than or equal to N; A first connection module is configured to establish connections with M second data interfaces.

10. A video data transmission device, characterized in that: include: a second receiving module, configured to, when determining that the first processor is in an abnormal state, receive first video data from M second data interfaces among the P second data interfaces, wherein the first video data is video data transmitted from the M first data interfaces among the first processors to the first processor, and the first processor is configured to transmit the first video data to a storage device, wherein P is a natural number greater than 1, and M is a natural number less than or equal to P; a second transmission module, configured to transmit the first video data to the storage device; Among them, the M second data interfaces are second data interfaces in a high-impedance state among the P second data interfaces included in the second processor, the high-impedance state of the M second data interfaces is set by the second processor, and the other second data channels among the P second data channels except the M second data channels are used to transmit second video data to the second processor, and the second processor is also used to transmit the second video data to the storage device, and P is a natural number greater than or equal to N.

11. A video data transmission system, characterized in that: include: A complex programmable logic device, wherein the complex programmable logic device comprises the video data transmission device according to claim 9; First processor, The second processor comprises the video data transmission device according to claim 10.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 4 are implemented, or when the computer program is executed by a processor, the steps of the method described in any one of claims 5 to 8 are implemented.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 4 are implemented; or when the processor executes the computer program, the steps of the method described in any one of claims 5 to 8 are implemented.

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