Display panel and display device

Abstract

A display panel (100) comprises a substrate (1), a plurality of sub-pixels (2), and a gate drive circuit (3). The sub-pixel (2) comprises a pixel drive circuit (21). The gate drive circuit (3) comprises a plurality of cascaded shift registers (31), and one shift register (31) is electrically connected with a plurality of pixel drive circuits (21) in one row of sub-pixels (2). The gate drive circuit (3) further comprises a plurality of cascaded input signal lines (34) and a plurality of cascaded display reset signal lines (35). The cascaded input signal line (34) is configured to connect a shift signal end (CR <n>) and an input signal end (Iput) of another stage shift register (31); a cascade display reset signal line (35) is configured to connect a shift signal end (CR <n>) and a display reset signal terminal (STD) of another stage shift register. The display panel (100) has a plurality of sub-pixel regions (S) for setting a plurality of sub-pixels (2), and a first gap region (D) between two adjacent column sub-pixel regions (S); the cascade display reset signal line (35) and the cascade input signal line (34) are both arranged in the first gap region (D), and are arranged in different first gap regions (D).< / n> < / n>

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] A gate driving circuit (also referred to as a scan driving circuit) is an important component in a display device. The gate driving circuit can include multiple cascaded shift registers, and each shift register is electrically connected to a row of gate lines in the display device. The gate driving circuit can input a scan signal (also referred to as a gate signal) to each row of gate lines in the display device, respectively drive each row of sub-pixels in the display device to perform display scanning, and thus enable the display device to perform picture display.

[0003] The gate driving circuit disposed in the display device can effectively reduce the cost and improve the yield. SUMMARY

[0004] In one aspect, a display panel is provided. The display panel includes a substrate, a plurality of sub-pixels disposed on one side of the substrate, and a gate driving circuit disposed on the same side of the substrate as the plurality of sub-pixels. The plurality of sub-pixels are arranged in multiple rows along a first direction and multiple columns along a second direction. A sub-pixel includes a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. The gate driving circuit includes multiple cascaded shift registers, and each shift register is electrically connected to multiple pixel driving circuits in a row of sub-pixels. The shift register includes multiple device groups, and each device group is located in a region between two adjacent sub-pixels in a corresponding row of sub-pixels. Each device group includes at least one transistor and / or at least one capacitor. The gate driving circuit further includes multiple cascaded input signal lines and multiple cascaded display reset signal lines. The cascaded input signal lines are configured to connect a shift signal terminal of a shift register and an input signal terminal of another shift register. The cascaded display reset signal lines are configured to connect a shift signal terminal of a shift register and a display reset signal terminal of another shift register. The display panel has multiple sub-pixel regions for disposing the plurality of sub-pixels, and a first gap region between two adjacent columns of sub-pixel regions. The cascaded display reset signal lines and the cascaded input signal lines are both disposed in the first gap region, and are disposed in different first gap regions.

[0005] In some embodiments, the plurality of cascaded input signal lines are divided into groups, each group of cascaded input signal lines includes at least one cascaded input signal line, and at least one group of cascaded input signal lines is arranged in each of the first gap regions. The plurality of cascaded display reset signal lines are divided into groups, each group of cascaded display reset signal lines includes at least one cascaded display reset signal line, and at least one group of cascaded display reset signal lines is arranged in each of the first gap regions.

[0006] In some embodiments, at least one column of sub-pixels is arranged between two groups of cascaded input signal lines located in different first gap regions and adjacent to each other. At least one column of sub-pixels is arranged between two groups of cascaded display reset signal lines located in different first gap regions and adjacent to each other.

[0007] In some embodiments, a plurality of groups of cascaded input signal lines are arranged in each of the first gap regions, and at least one row of sub-pixels is arranged between two groups of cascaded input signal lines located in the same first gap region and adjacent to each other. A plurality of groups of cascaded display reset signal lines are arranged in each of the first gap regions, and at least one row of sub-pixels is arranged between two groups of cascaded display reset signal lines located in the same first gap region and adjacent to each other.

[0008] In some embodiments, the display panel further includes a plurality of data lines extending in the second direction. One data line is electrically connected to a plurality of pixel driving circuits in one column of sub-pixels. The plurality of cascaded input signal lines, the plurality of cascaded display reset signal lines, and the plurality of data lines are made of the same material and arranged in the same layer.

[0009] In some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit includes at least three sub-pixels arranged in sequence in the first direction, the plurality of pixel units are arranged into a plurality of rows in the first direction and a plurality of columns in the second direction. The region between any two adjacent columns of pixel units is the first gap region.

[0010] In some embodiments, each sub-pixel region comprises a sub-pixel circuit area arranged along the second direction and used for setting a corresponding pixel driving circuit, and a sub-pixel light-emitting area used for setting a corresponding light-emitting device. Along the second direction, any three adjacent rows of sub-pixel regions are a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions, respectively. The area between the first row of sub-pixel regions and the second row of sub-pixel regions is a second gap region, and the area between the second row of sub-pixel regions and the third row of sub-pixel regions is a third gap region. In the first row of sub-pixel regions and the second row of sub-pixel regions, the sub-pixel light-emitting area is closer to the second gap region than the sub-pixel circuit area. In the second row of sub-pixel regions and the third row of sub-pixel regions, the sub-pixel circuit area is closer to the third gap region than the sub-pixel light-emitting area.

[0011] In some embodiments, the gate driving circuit further comprises a plurality of transmission signal lines located in the second gap region and extending along the first direction. Two-stage shift registers electrically connected to sub-pixels located in the first row of sub-pixel regions and sub-pixels located in the second row of sub-pixel regions share at least one transmission signal line of the plurality of transmission signal lines.

[0012] In some embodiments, the gate driving circuit further comprises a first voltage signal line electrically connected to a first voltage signal end of the two-stage shift register, a second voltage signal line electrically connected to a second voltage signal end of the two-stage shift register, and a third voltage signal line electrically connected to a third voltage signal end of the two-stage shift register. The transmission signal line is the first voltage signal line, the second voltage signal line, or the third voltage signal line.

[0013] In some embodiments, at least one cascaded input signal line comprises a first sub-input signal line and a second sub-input signal line located in different first gap regions; the gate driving circuit further comprises an input signal connection line located in the second gap region and electrically connected to the first sub-input signal line and the second sub-input signal line; and the transmission signal line is the input signal connection line. And / or, at least one cascaded display reset signal line comprises a first sub-display reset signal line and a second sub-display reset signal line located in different first gap regions; the gate driving circuit further comprises a display reset connection line located in the second gap region and electrically connected to the first sub-display reset signal line and the second sub-display reset signal line; and the transmission signal line is the display reset connection line.

[0014] In some embodiments, the gate driving circuit further comprises a plurality of node voltage transmission lines in the second gap region. In the same stage shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line. In the two-stage shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line. The transmission signal line is the node voltage transmission line.

[0015] In some embodiments, the shift register comprises: a first input circuit electrically connected to an input signal terminal, a pull-up node and an anti-leakage node; the first input circuit is configured to, in a display period of a frame display stage, transmit an input signal received at the input signal terminal to the pull-up node in response to the input signal; an output circuit electrically connected to the pull-up node, a first clock signal terminal and a first output signal terminal; the output circuit is configured to, in a display period of a frame display stage, transmit a first clock signal received at the first clock signal terminal to the first output signal terminal under the control of the voltage of the pull-up node; and an anti-leakage circuit electrically connected to the pull-up node, a first voltage signal terminal and the anti-leakage node; the anti-leakage circuit is configured to, under the control of the voltage of the pull-up node, transmit a first voltage signal received at the first voltage signal terminal to the anti-leakage node to prevent the pull-up node from leaking. The first input circuit, the output circuit and the anti-leakage circuit each comprise at least one device group. The device group in the first input circuit for electrical connection with the pull-up node and the device group in the output circuit for electrical connection with the pull-up node are electrically connected to the pull-up node through a node voltage transmission line. The device group in the first input circuit for electrical connection with the anti-leakage node and the device group in the anti-leakage circuit for electrical connection with the anti-leakage node are electrically connected to the anti-leakage node through a node voltage transmission line.

[0016] In some embodiments, the gate driving circuit further comprises: a plurality of blanking input circuits; one blanking input circuit is electrically connected with at least two adjacent stages of shift registers; the blanking input circuit is configured to, in a blanking period of a frame display stage, control the corresponding shift register to input a blanking control signal to the pixel driving circuit of the corresponding row, so that the pixel driving circuit obtains a sensing signal. The blanking input circuit comprises: a selection control circuit, which is electrically connected with a selection control signal end, a shift signal end, a second voltage signal end and a first blanking node; the selection control circuit is configured to, under the control of a selection control signal transmitted by the selection control signal end, transmit a shift signal received at the shift signal end to the first blanking node; a second input circuit, which is electrically connected with the first blanking node, a second blanking node and a second clock signal end or a first voltage signal end; the second input circuit is configured to, under the control of the voltage of the first blanking node, transmit a second clock signal received at the second clock signal end or a first voltage signal received at the first voltage signal end to the second blanking node; and at least two transmission circuits, one transmission circuit being electrically connected with the pull-up node of one stage of shift registers; the transmission circuit is further electrically connected with the second blanking node and the second clock signal end; the transmission circuit is configured to, under the control of a second clock signal transmitted by the second clock signal end, transmit the second clock signal or the first voltage signal received at the second blanking node to the pull-up node. The second input circuit and the transmission circuit each comprise at least one device group; each device group comprised by the second input circuit and the transmission circuit is respectively located in a row of sub-pixels where the corresponding shift register is located, in a region between two adjacent sub-pixels. The device group in the second input circuit for electrical connection with the second blanking node, and the device group in the at least two transmission circuits for electrical connection with the second blanking node, are electrically connected with the second blanking node through a node voltage transmission line.

[0017] In some embodiments, the display panel further comprises: a plurality of gate lines extending along the first direction; one gate line is electrically connected with a plurality of pixel driving circuits in a row of sub-pixels. The plurality of transmission signal lines and the plurality of gate lines are of the same material and are disposed in the same layer.

[0018] In some embodiments, the pixel driving circuit comprises: a first sensing signal line located in the third gap region and extending along the first direction. In the case where the plurality of sub-pixels are divided into a plurality of pixel units, and one pixel unit comprises at least three sub-pixels arranged in sequence along the first direction, among the sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions, two pixel units opposite along the second direction share the first sensing signal line.

[0019] In some embodiments, the sub-pixel further comprises: a light shielding layer disposed on the side of the pixel driving circuit close to the substrate. The first sensing signal line and the light shielding layer are made of the same material and are disposed in the same layer.

[0020] In some embodiments, the pixel driving circuit further comprises: a second sensing signal line extending along the second direction. The second sensing signal line is located in the region between the adjacent two columns of sub-pixels in the two pixel units opposite in the second direction. The first sensing signal line is electrically connected to the second sensing signal line through a via.

[0021] In some embodiments, in the case that the display panel further comprises a plurality of data lines, the second sensing signal line and the plurality of data lines are made of the same material and are disposed in the same layer.

[0022] In some embodiments, the gate driving circuit further comprises: a plurality of control signal lines extending along the second direction. A stage shift register is electrically connected to at least part of the plurality of control signal lines; the shift register is configured to provide an output signal to a plurality of pixel driving circuits in a corresponding row under the control of at least part of the control signal lines electrically connected to the shift register.

[0023] In some embodiments, at least one of the plurality of control signal lines is located in the first gap region.

[0024] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the product related to the embodiments of the present disclosure.

[0026] Figure 1 FIG. 1 is a structural diagram of a display panel according to the related art;

[0027] Figure 2 FIG. 2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0028] Figure 3 FIG. 3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0029] Figure 4A circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0030] Figure 5 A circuit diagram of a shift register according to some embodiments of the present disclosure;

[0031] Figure 6 A circuit diagram of two adjacent stages of a shift register according to some embodiments of the present disclosure;

[0032] Figure 7 A structural diagram of a gate driving circuit according to some embodiments of the present disclosure;

[0033] Figure 8 A circuit diagram of another two adjacent stages of a shift register according to some embodiments of the present disclosure;

[0034] Figures 9a to 9h A structural diagram of a sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0035] Figure 10 A structural diagram of another sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0036] Figure 11 A partial enlarged view of a sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0037] Figure 12 A partial enlarged view of another sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0038] Figure 13 A partial enlarged view of a sub-pixel according to some embodiments of the present disclosure;

[0039] Figure 14 A structural diagram of a gate driving circuit according to some embodiments of the present disclosure; Figure 13 A sectional view along M-M' of the structural diagram shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0041] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an open, inclusive sense as "including, but not limited to." As used throughout this description and the claims, the term "one embodiment" or "the embodiment" means an implementation or implementation example. Any implementation or implementation example used or described herein can include one or more embodiments or implementation examples. Separate embodiments or implementation examples can also be provided by combinations of elements and / or limitations of the described embodiments or implementation examples. Words using the singular or plural number also include the plural or singular number respectively. Words using the singular or plural number also include the plural or singular number respectively. The terms "about" and "substantially" used herein in reference to a given value or range of values mean that the value or range of values need not be achieved exactly, but that deviations or variations, whether positive or negative, are expected and are within acceptable limits. The terms "first", "second", and the like, do not denote any order, quantity, combination, or importance, but are used to identify one of the features described. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0042] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood to indicate or imply relative importance or to imply the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0043] In describing some embodiments, the term "connected" and / or derivatives thereof can be used. For example, the term "connected" can be used to mean that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the context.

[0044] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0045] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0046] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected" is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0047] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0048] Additionally, the use of "based on" means open and inclusive, as the process, step, calculation, or other action based on a stated condition or value can actually be based on additional conditions or values beyond those stated.

[0049] As used herein, "about" or "approximately" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement at issue and the error in measurement associated with the particular quantity measured (i.e., the limitations of the measurement system).

[0050] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer and regions are shown in each figure nor is every structure necessarily shown. For the most part, details that would be apparent to one of ordinary skill in the art and which do not factor into the disclosure have been omitted in the interest of clarity. For example, while the exemplary embodiments are described herein with reference to a number of specific embodiments, alternative embodiments will become apparent to those of ordinary skill in the art from this disclosure. Accordingly, the exemplary embodiments are not limited to the specific embodiments described herein, but include all alternatives falling within the scope of the exemplary embodiments. In the drawings: like reference numerals refer to like elements throughout.

[0051] The transistors employed in the circuits provided by embodiments of the present disclosure can be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices of the same character, and embodiments of the present disclosure are described with reference to thin film transistors.

[0052] In some embodiments, the control electrode of each transistor employed by the shift register is the gate of the transistor, the first electrode is one of the source and the drain of the transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and the drain of a transistor can be symmetric in structure, the source and the drain of a transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of a transistor in embodiments of the present disclosure can be indistinguishable in structure. For example, in the case of a P-type transistor, the first electrode of the transistor is the source and the second electrode of the transistor is the drain; for example, in the case of an N-type transistor, the first electrode of the transistor is the drain and the second electrode of the transistor is the source.

[0053] In the circuit provided by embodiments of the present disclosure, the first pull-up node, the second pull-up node, the first pull-down node, the second pull-down node, and the like are not actual components, but are the convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are equivalent to the convergence points of relevant electrical connections in a circuit diagram.

[0054] In embodiments of the present disclosure, the term "pull up" means charging a node or an electrode of a transistor to increase the absolute value of the level of the node or the electrode, thereby realizing the operation (for example, turning on) of the corresponding transistor. The term "pull down" means discharging a node or an electrode of a transistor to decrease the absolute value of the level of the node or the electrode, thereby realizing the operation (for example, turning off) of the corresponding transistor.

[0055] In the following, in the circuit provided by embodiments of the present disclosure, each transistor is taken as an N-type transistor for example.

[0056] Some embodiments of the present disclosure provide a display panel 100 and a display device 1000, which are introduced as follows.

[0057] Some embodiments of the present disclosure provide a display device 1000, which is as follows. Figure 2As shown. The display device 1000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0058] In some examples, the aforementioned display device 1000 includes a frame, a display panel 100 disposed within the frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0059] In some examples, the display panel 100 may be non-rectangular. For instance, when the display panel 100 is applied to a building, its shape can be customized according to the shape of the building and the requirements of the application environment.

[0060] For example, the shape of the display panel 100 can be circular, elliptical, arc-shaped, or rhomboid, etc.

[0061] The aforementioned display panel 100 may be, for example, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, etc., and this disclosure does not specifically limit it.

[0062] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0063] In some embodiments, such as Figure 3 As shown, the display panel 100 may include: a substrate 1, a plurality of sub-pixels 2, and a gate driving circuit 3.

[0064] The type of the substrate 1 can be various, and can be selected according to actual needs.

[0065] For example, the substrate 1 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0066] For example, the substrate 1 can be a flexible substrate. The flexible substrate can be, for example, a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate or a PI (Polyimide) substrate, etc. In this case, the display panel 100 can be a flexible display panel.

[0067] In some examples, as shown in FIG. 1, the plurality of sub-pixels 2 can be arranged on one side of the substrate 1. For example, the plurality of sub-pixels 2 can be arranged in a plurality of rows along a first direction X and in a plurality of columns along a second direction Y. Each row of sub-pixels 2 can include a plurality of sub-pixels 2, and each column of sub-pixels 2 can include a plurality of sub-pixels 2. Figure 3

[0068] Here, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected according to actual needs. For example, the included angle between the first direction X and the second direction Y can be 85°, 89° or 90°, etc.

[0069] For example, the shape of the substrate 1 can be the same as the shape of the display panel 100, i.e., the shape of the substrate 1 can be a non-rectangular shape. Based on this, the number of sub-pixels 2 included in a column of sub-pixels (i.e., a certain column of sub-pixels 2 arranged along the second direction Y) located at different positions of the substrate 1 can be different, and the number of sub-pixels 2 included in a row of sub-pixels (i.e., a certain row of sub-pixels 2 arranged along the first direction X) located at different positions of the substrate 1 can be different.

[0070] In some examples, as shown in FIG. 1, the display panel 100 can include a plurality of gate lines GL arranged on one side of the substrate 1 and extending along the first direction X, and a plurality of data lines DL arranged on one side of the substrate 1 and extending along the second direction Y. For example, the plurality of data lines DL can be located away from the plurality of gate lines GL on one side of the substrate 1, and the plurality of data lines DL and the plurality of gate lines GL can be insulated from each other. Figure 3

[0071] In some examples, as shown in FIG. 1, the display panel 100 can include a plurality of gate lines GL arranged on one side of the substrate 1 and extending along the first direction X, and a plurality of data lines DL arranged on one side of the substrate 1 and extending along the second direction Y. For example, the plurality of data lines DL can be located away from the plurality of gate lines GL on one side of the substrate 1, and the plurality of data lines DL and the plurality of gate lines GL can be insulated from each other. Figure 4 ​​As shown, each of the plurality of sub-pixels 2 can include a pixel driving circuit 21 and a light emitting device 22 electrically connected to the pixel driving circuit 21.

[0072] For example, as shown in FIG. 1, a display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 3 and Figure 4 As shown, one gate line GL can be electrically connected to a plurality of pixel driving circuits 21 in the same row of sub-pixels 2, and one data line DL can be electrically connected to a plurality of pixel driving circuits 21 in the same column of sub-pixels 2. The number of gate lines GL electrically connected to the plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can be determined according to the structure of the pixel driving circuit 21.

[0073] The structure of the pixel driving circuit 21 can be selected according to actual needs. For example, the structure of the pixel driving circuit 21 can include a "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C" structure. Here, "T" represents a thin film transistor, the number before "T" represents the number of thin film transistors, "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors. The pixel driving circuit 21 can include one switching transistor and one driving transistor.

[0074] Here, during use of the display panel 100, the stability of the thin film transistor in the pixel driving circuit 21 and the light emitting device 22 can decrease (for example, threshold voltage drift of the driving transistor), affecting the display effect of the display panel 100, so that the sub-pixel 2 needs to be compensated.

[0075] The compensation method for the sub-pixel 2 can include a plurality of methods, which can be selected according to actual needs. For example, a pixel compensation circuit can be provided in the sub-pixel 2 to internally compensate the sub-pixel 2 by using the pixel compensation circuit. For another example, the driving transistor or the light emitting device 22 can be sensed by the thin film transistor inside the sub-pixel 2, and the sensed data can be transmitted to an external sensing circuit to calculate the driving voltage value to be compensated and feedback, thereby realizing external compensation of the sub-pixel 2.

[0076] The present disclosure takes the method of external compensation (sensing the driving transistor) and the structure of the pixel driving circuit 21 as an example to illustrate the structure and working process of the sub-pixel 2.

[0077] For example, as shown in FIG. 1, a display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 4 As shown, the pixel driving circuit 21 can include a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

[0078] For example, as shown in FIG. 1, a display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 4As shown, the control terminal of the switching transistor T1 is electrically connected to the first gate signal terminal G1, the first terminal of the switching transistor T1 is electrically connected to the data signal terminal Data, and the second terminal of the switching transistor T1 is electrically connected to the first node G. The switching transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to a first gate signal received at the first gate signal terminal G1.

[0079] Here, data signals include, for example, detection data signals and display data signals.

[0080] For example, such as Figure 4 As shown, the control terminal of driving transistor T2 is electrically connected to the first node G, the first terminal of driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD, and the second terminal of driving transistor T2 is electrically connected to the second node S. Driving transistor T2 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal ELVDD to the second node S under the control of the voltage at node G.

[0081] For example, such as Figure 4 As shown, the first terminal of the storage capacitor Cst is electrically connected to the first node G, and the second terminal of the storage capacitor Cst is electrically connected to the second node S. The switching transistor T1 charges the storage capacitor Cst simultaneously while charging the first node G.

[0082] For example, such as Figure 4 As shown, the anode of the light-emitting device 22 is electrically connected to the second node S, and the cathode of the light-emitting device 22 is electrically connected to the fifth voltage signal terminal ELVSS. The light-emitting device 22 is configured to emit light in cooperation with the fourth voltage signal from the second node S and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

[0083] Here, the level range of the first voltage signal can be, for example, -5V to 5V. The second voltage signal is, for example, a fixed voltage signal, the level of which can be, for example, less than or equal to 0V.

[0084] For example, such as Figure 4 As shown, the control terminal of sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first terminal of sensing transistor T3 is electrically connected to the second node S, and the second terminal of sensing transistor T3 is electrically connected to the sensing signal terminal Sense. Sensing transistor T3 is configured to detect the electrical characteristics of driving transistor T2 in response to a second gate signal received at the second gate signal terminal G2 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of driving transistor T2.

[0085] Here, the sensing signal terminal Sense can provide a reset signal for resetting the second node S or a sensing signal for obtaining a threshold voltage of the driving transistor T2.

[0086] Based on the structure of the pixel driving circuit 21, multiple pixel driving circuits 21 in the same row of sub-pixels 2 can be electrically connected with two gate lines GL (i.e., a first gate line and a second gate line). For example, each first gate signal terminal G1 can be electrically connected with the first gate line and receive a first gate signal transmitted by the first gate line; and each second gate signal terminal G2 can be electrically connected with the second gate line and receive a second gate signal transmitted by the second gate line.

[0087] In the present example, a display phase of one frame can include a display period and a blanking period in sequence, for example.

[0088] In the display period in the display phase of one frame, the working process of the sub-pixel 2 can include a reset phase, a data writing phase, and a light emitting phase, for example.

[0089] In the reset phase, the second gate signal provided by the second gate signal terminal G2 has a high level, and the sensing signal terminal Sense provides a reset signal (which has a low level, for example). The sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.

[0090] In the data writing phase, the first gate signal provided by the first gate signal terminal G1 has a high level, and the display data signal provided by the data signal terminal Data has a high level. The switching transistor T1 is turned on under the control of the first gate signal, receives the display data signal, and transmits the display data signal to the first node G, while charging the storage capacitor Cst.

[0091] In the light emitting phase, the first gate signal provided by the first gate signal terminal G1 has a low level, the second gate signal provided by the second gate signal terminal G2 has a low level, and the fourth voltage signal provided by the fourth voltage signal terminal ELVDD has a high level. The switching transistor T1 is turned off under the control of the first gate signal, and the sensing transistor T3 is turned off under the control of the second gate signal. The storage capacitor Cst starts to discharge, so that the voltage of the first node G remains at a high level. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the second node S, so that the light emitting device 22 emits light under the cooperation of the fourth voltage signal and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

[0092] The operation of the sub-pixel 2 may, for example, include a first stage and a second stage during a blanking period in a frame display stage.

[0093] In the first stage, the first gate signal provided by the first gate signal terminal G1 and the second gate signal provided by the second gate signal terminal G2 are both at a high level, and the detection data signal provided by the data signal terminal Data is also at a high level. The switch transistor T1 is turned on under the control of the first gate signal, receives the detection data signal, and transmits the detection data signal to the first node G, thereby charging the first node G. The sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal provided by the sensing signal terminal Sense, and transmits the reset signal to the second node S.

[0094] In the second stage, the sensing signal terminal Sense is in a floating state. The drive transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal provided by the fourth voltage signal terminal ELVDD, and transmits the fourth voltage signal to the second node S, thereby charging the second node S and raising the voltage of the second node S until the drive transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the drive transistor T2.

[0095] Since the sensing transistor T3 is in a turned-on state and the sensing signal terminal Sense is in a floating state, the sensing signal terminal Sense is also charged during the charging of the second node S by the drive transistor T2. By voltage sampling (i.e., obtaining the sensing signal) of the sensing signal terminal Sense, the threshold voltage Vth of the drive transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal.

[0096] After the threshold voltage Vth of the drive transistor T2 is calculated, the threshold voltage Vth can be compensated into the display data signal in the display period of the next frame display stage, thereby completing the external compensation of the sub-pixel 2.

[0097] In some examples, the gate driving circuit 3 and the plurality of sub-pixels 2 are located on the same side of the substrate 1. The gate driving circuit 3 can include a plurality of cascaded shift registers 31, and one shift register 31 can be electrically connected to the plurality of pixel driving circuits 21 in one row of sub-pixels 2.

[0098] It should be noted that in the display stage of a frame, the first gate signal transmitted by the first gate signal terminal G1 and the second gate signal transmitted by the second gate signal terminal G2 are both provided by the gate drive circuit 3. That is, each stage of the shift register 31 in the gate drive circuit 3 can be electrically connected with the first gate signal terminal G1 through a first gate line, transmit the first gate signal to the first gate signal terminal G1 through the first gate line, and be electrically connected with the second gate signal terminal G2 through a second gate line, transmit the second gate signal to the second gate signal terminal G2 through the second gate line.

[0099] The structure of the shift register 31 described above includes multiple structures, which can be selected and set according to actual needs. The structures of two kinds of shift registers 31 are schematically described below, but the shift register 31 in the present disclosure is not limited to the two kinds.

[0100] In some examples, as shown in Figure 5 and Figure 6 , the shift register 31 can include a first input circuit 3101, an anti-leakage circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109.

[0101] For example, as shown in Figure 5 and Figure 6 , the first input circuit 3101 is electrically connected with an input signal terminal Input (simplified as Iput in the drawings and hereinafter), a pull-up node Q <n>and an electric leakage prevention node OFF <n>The first input circuit 3101 is configured to, in a display period in a frame display stage, transmit the input signal to the pull-up node Q in response to the input signal received at the input signal end Iput <n>N is a positive integer, and represents the number of rows of sub-pixels.

[0102] For example, during a display period in a frame display stage, when the level of the input signal is high, the first input circuit 3101 can be turned on under the action of the input signal, and transmit the input signal to the pull-up node Q <n>Q <n>Charging is performed so that the pull-up node Q <n>the voltage of the input signal terminal Iput is raised.

[0103] Optionally, as shown in Figure 5 and Figure 6 The first input circuit 3101 can include a first transistor M1 and a second transistor M2.

[0104] For example, as shown in Figure 5 and Figure 6 The control electrode of the first transistor M1 is electrically connected with the input signal terminal Iput, the first electrode of the first transistor M1 is electrically connected with the input signal terminal Iput, and the second electrode of the first transistor M1 is electrically connected with the first electrode of the second transistor M2 and the first leakage prevention node OFF1. The control electrode of the second transistor M2 is electrically connected with the input signal terminal Iput, and the second electrode of the second transistor M2 is electrically connected with the first pull-up node Q1.

[0105] Here, in a display period in a frame display stage, in the case that the level of the input signal transmitted by the input signal terminal Iput is high, the first transistor M1 and the second transistor M2 can be turned on simultaneously under the action of the input signal. The first transistor M1 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode of the second transistor M2 and the leakage prevention node OFF1. The second transistor M2 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first pull-up node Q1. <n>The second transistor M2 can transmit the received input signal to the pull-up node Q <n>Q <n>Charging is performed so that the pull-up node Q <n>The voltage increases.

[0106] For example, such as Figure 5 and Figure 6 As shown, the leakage protection circuit 3102 and the pull-up node Q <n>, a first voltage signal terminal VDD and an anti-leakage node OFF <n>The electrical connection. Wherein the leakage protection circuit 3102 is configured to, in response to the pull-up node Q <n>transmit the first voltage signal transmitted by the first voltage signal terminal VDD to the leakage prevention node OFF under the control of the voltage of the second voltage signal terminal VSS <n>to prevent the pull-up node Q <n>Leakage. The first voltage signal is for example a constant high voltage signal.

[0107] For example, in the pull-up node Q <n>When the voltage is high, the leakage protection circuit 3102 can pull up the Q node. <n>under control of the voltage of the first voltage signal, and transmit the first voltage signal to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>the voltage of the power supply.

[0108] Optionally, as shown in Figure 5 and Figure 6 The leakage prevention circuit 3102 can include a third transistor M3.

[0109] For example, as shown in Figure 5 and Figure 6 The control electrode of the third transistor M3 is connected to the pull-up node Q <n>The first electrode of the third transistor M3 is electrically connected with the first voltage signal terminal VDD, and the second electrode of the third transistor M3 is electrically connected with the anti-leakage node OFF <n>Electrically connected.

[0110] Here, the pull-up node Q <n>The third transistor M3 can pull up the voltage at the pull-up node Q <n>under control of the voltage of the first voltage signal, the first voltage signal being transmitted to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>the voltage of the pull-up node Q rises, and the voltage difference between the control electrode and the first electrode of the second transistor M2 is less than zero, ensuring that the second transistor M2 is completely or relatively completely turned off. In this way, the pull-up node Q <n>Leakage occurs through the first input circuit 3101, causing the pull-up node Q <n>It can maintain a relatively high and stable voltage.

[0111] For example, such as Figure 5 and Figure 6 As shown, the output circuit 3103 and the pull-up node Q <n>, a first clock signal terminal CLKE_1 and a first output signal terminal Output1 <n>(both the figure and the text below are abbreviated as Oput1 <n>) electrically connected. Wherein the output circuit 3103 is configured to, in a display period in a frame display stage, pull up the pull-up node Q <n>the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 under the control of the voltage of the first control signal terminal CTRL1 <n>.

[0112] Of course, such as Figure 6 As shown, the output circuit 3103 can also be connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR. <n>The output circuit 3103 is further configured to, in the display period in the frame display stage, pull up the pull-up node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR under the control of the voltage of the second clock signal terminal CLKD_2 <n>.

[0113] Of course, such as Figure 6 As shown, the output circuit 3103 can also be connected to the fourth clock signal terminal CLKF_1 and the second output signal terminal Output2. <n>(both the figure and the text below are abbreviated as Oput2 <n>) electrically connected. Wherein the output circuit 3103 is further configured to, in a blanking period in a frame display stage, pull up the pull-up node Q <n>the fourth clock signal received at the fourth clock signal terminal CLKF_1 is transmitted to the second output signal terminal Oput2 under the control of the voltage of the second control signal terminal CTRL2 <n>.

[0114] For example, during a display period in a frame display phase, the pull-up node Q <n>In a case where the voltage of the output circuit 3103 rises, the output circuit 3103 can pull up the node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is used as a shift signal from the shift signal terminal CR under the control of the voltage of the control signal terminal CTRL. The shift signal is shifted by one bit at each clock cycle, and the third clock signal is output from the third clock signal terminal CLKD_2. <n>output; the first clock signal received at the first clock signal terminal CLKE_1 is taken as a first output signal, from the first output signal terminal Oput1 <n>output. During a blanking period in a frame display phase, the pull-up node Q <n>In a case where the voltage of the output circuit 3103 rises, the output circuit 3103 can pull up the node Q <n>be turned on under the control of the voltage of the fourth clock signal received at the fourth clock signal terminal CLKF_1 as the second output signal from the second output signal terminal Oput2 <n>Output.

[0115] In this example, the first output signal terminal Oput1 <n>The first gate line can be electrically connected with the first output signal terminal Oput1 <n>The first output signal outputted can be transmitted to the pixel driving circuit 21 as the first gate signal through the first gate line and the first gate signal terminal G1 in sequence. The second output signal terminal Oput2 <n>The second gate line can be electrically connected with the second output signal terminal Oput2 <n>The output second output signal can be transmitted to the pixel driving circuit 21 as the second gate signal through the second gate line and the second gate signal terminal G2 in sequence.

[0116] Optionally, as shown in Figure 6 The output circuit 3103 can include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1 and a second capacitor C2.

[0117] For example, as shown in Figure 6 The control electrode of the fourth transistor M4 is connected with the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected with the third clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected with the shift signal terminal CR <n>Electrically connected.

[0118] During a display period in a frame display period, the first input circuit 3101 is turned on, so that the pull-up node Q <n>The fourth transistor M4 can pull up the voltage at the pull-up node Q <n>The third clock signal is transmitted to the shift signal end CR under the control of the high voltage of the high-voltage control end <n>and the third clock signal is taken as a shift signal from a shift signal terminal CR <n>Output.

[0119] For example, as Figure 6 shown, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected with the first clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected with the first output signal terminal Oput1 <n>The first end of the first capacitor CI is electrically connected to the pull-up node Q <n>electrical connection, a second end of the first capacitor C1 and the first output signal terminal Oput1 <n>Electrically connected.

[0120] During a display period in a frame display phase, the first input circuit 3101 is turned on, so that the pull-up node Q <n>the voltage of the first input circuit 3101 is raised, the first capacitor C1 is charged. In the case where the first input circuit 3101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>The first clock signal is transmitted to the first output signal terminal Oputl through the fifth transistor M5 which is kept in the on state <n>and outputs the first clock signal as a first output signal from a first output signal terminal Oputl <n>Output.

[0121] For example, such as Figure 6 As shown, the control electrode of the sixth transistor M6 is connected to the pull-up node Q. <n>The first electrode of the sixth transistor M6 is electrically connected with the fourth clock signal terminal CLKF_1, and the second electrode of the sixth transistor M6 is electrically connected with the second output signal terminal Oput2 <n>The first end of the second capacitor C2 is connected to the pull-up node Q <n>electrical connection, a second end of the second capacitor C2 is connected to the second output signal terminal Oput2 <n>Electrical connection.

[0122] During a blanking period in a frame display phase, the pull-up node Q <n>The voltage of the second capacitor C2 can be charged at the same time as the voltage of the first capacitor C1 is raised. At the corresponding stage, the second capacitor C2 can be discharged so that the pull-up node Q <n>Maintaining a high level allows the sixth transistor M6 to remain on, transmitting the fourth clock signal to the second output signal terminal Oput2. <n>and the fourth clock signal is outputted from the second output signal terminal Oput2 as a second output signal <n>Output.

[0123] Here, after the plurality of stages of shift registers 31 are cascaded to constitute the gate drive circuit 3, the shift signal terminal CR <n>For example, the input signal terminal Iput in the N+1th shift register 31 can be electrically connected, and then the shift signal terminal CR of the Nth shift register 31 is electrically connected. <n>The output shift signal is inputted into the N+1th shift register 31. Of course, the cascade relationship of the multi-stage shift register 31 is not limited to this.

[0124] In addition, the input signal terminal Iput of a part of the shift registers 31 can be electrically connected with the start signal terminal STU, so as to receive the start signal transmitted by the start signal terminal STU as the input signal. The part of the shift registers 31 can be, for example, the first stage shift register 31 in the gate driving circuit 3, or can be, for example, the first stage shift register 31 and the second stage shift register 31, etc.

[0125] Here, the number of the shift registers 31 electrically connected with the start signal terminal STU is not limited, and can be selected and set according to actual needs.

[0126] For example, as shown in Figure 5 and Figure 6 The control circuit 3104 is electrically connected with the pull-up node Q <n>The sixth voltage signal terminal VDD_A, the pull-down node QB_A, and the second voltage signal terminal VGL1 are electrically connected. The control circuit 3104 is configured to, in response to the pull-up node Q <n>The voltage of the pull-down node QB_A is controlled under the control of a fifth voltage signal transmitted by a fifth voltage signal terminal VGL2 and a sixth voltage signal transmitted by a sixth voltage signal terminal VDD_A. The level of the sixth voltage signal can be constant during the display stage of a frame, for example. The second voltage signal terminal VGL1 can be configured to transmit a direct current low level signal (e.g. lower than or equal to the low level part of the clock signal). The second voltage signal terminal VGL1 can be grounded, for example.

[0127] For example, the voltage of the pull-up node QB_A is controlled under the control of a third voltage signal transmitted by a third voltage signal terminal VGL3 and a fourth voltage signal transmitted by a fourth voltage signal terminal VDD_B. The level of the fourth voltage signal can be constant during the display stage of a frame, for example. The third voltage signal terminal VGL3 can be configured to transmit a direct current low level signal (e.g. lower than or equal to the low level part of the clock signal). The third voltage signal terminal VGL3 can be grounded, for example. <n>When the voltage rises, the control circuit 3104 can transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the pull-down node QB_A, pulling the voltage of the pull-down node QB_A down to a low voltage. At the pull-up node Q... <n>When the voltage of the pull-down node QB_A is low voltage, the control circuit 3104 can transmit the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A to the pull-down node QB_A, and pull up the voltage of the pull-down node QB_A to high level.

[0128] Optionally, as shown in Figure 5 and Figure 6 The control circuit 3104 can include a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

[0129] For example, as shown in Figure 5 and Figure 6 The control electrode of the seventh transistor M7 is electrically connected with the sixth voltage signal terminal VDD_A, the first electrode of the seventh transistor M7 is electrically connected with the sixth voltage signal terminal VDD_A, and the second electrode of the seventh transistor M7 is electrically connected with the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The first electrode of the eighth transistor M8 is electrically connected with the sixth voltage signal terminal VDD_A, and the second electrode of the eighth transistor M8 is electrically connected with the pull-down node QB_A and the first electrode of the tenth transistor M10. The control electrode of the ninth transistor M9 is electrically connected with the pull-up node Q <n>The second electrode of the ninth transistor M9 is electrically connected with the second voltage signal terminal VGL1. The control electrode of the tenth transistor M10 is electrically connected with the pull-up node Q <n>The second electrode of the tenth transistor M10 is electrically connected with a second voltage signal terminal VGL1.

[0130] When the level of the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A is high, the seventh transistor M7 can be turned on under the action of the sixth voltage signal, receive and transmit the sixth voltage signal to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The eighth transistor M8 can be turned on under the action of the sixth voltage signal, receive and transmit the sixth voltage signal to the pull-down node QB_A and the first electrode of the tenth transistor M10.

[0131] The pull-up node Q <n>The ninth transistor M9 and the tenth transistor M10 can be turned on in the case where the voltage of the second node N2 is a high level <n>The ninth transistor M9 can be turned on under the control of the voltage of the pull-up node QP, and the ninth transistor M9 can transmit the second voltage signal transmitted by the second voltage signal end VGL1 to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off, and the tenth transistor M10 can transmit the second voltage signal to the pull-down node QB_A, and the voltage of the pull-down node QB_A is pulled low to the low level.

[0132] The pull-up node QP <n>The ninth transistor M9 and the tenth transistor M10 can pull up the voltage of the pull-up node Q <n>The eighth transistor M8 can transmit the received sixth voltage signal to the pull-down node QB_A, and pull up the voltage of the pull-down node QB_A to a high level under the control of the voltage of the first reset circuit 3105.

[0133] As shown in the example of FIG. 3, the first reset circuit 3105 can be configured to output a first reset signal to the pull-down node QB_A and the pull-up node QB_B. Figure 5 and Figure 6 As shown in the example of FIG. 3, the first reset circuit 3105 can be configured to output a first reset signal to the pull-down node QB_A and the pull-up node QB_B. <n>a second voltage signal terminal VGL1 and an anti-creeping node OFF <n>The first reset circuit 3105 is configured to, under the control of the voltage of the pull-down node QB_A, control the voltage of the pull-up node Q <n>A reset is performed.

[0134] For example, in a case where the voltage of the pull-down node QB_A is high, the first reset circuit 3105 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node QB_A <n>Q <n>A pull-down reset is performed.

[0135] Optionally, as shown in Figure 5 and Figure 6 The first reset circuit 3105 can include an eleventh transistor M11 and a twelfth transistor M12.

[0136] For example, as shown in Figure 5 and Figure 6 The control electrode of the eleventh transistor M11 is electrically connected with the pull-down node QB_A, the first electrode of the eleventh transistor M11 is electrically connected with the pull-up node Q <n>an electric connection between the second electrode of the eleventh transistor Ml 1 and the first electrode of the twelfth transistor M12 and the leakage-preventing node OFF <n>The control electrode of the twelfth transistor M12 is electrically connected with the pull-down node QB_A, and the second electrode of the twelfth transistor M12 is electrically connected with the second voltage signal terminal VGL1.

[0137] In the case that the voltage of the pull-down node QB_A is high, the eleventh transistor M11 and the twelfth transistor M12 can be turned on simultaneously under the action of the voltage of the pull-down node QB_A, and the twelfth transistor M12 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF <n>, the eleventh transistor M11 can pass the voltage from the leakage prevention node OFF <n>a second voltage signal of the first voltage signal is transmitted to the pull-up node Q <n>Q <n>A reset is performed.

[0138] Here, the pull-up node Q <n>The potential of the third transistor M3 is high, and the first reset circuit 3105 is in an inactive state. In this case, the third transistor M3 can pull up the pull-up node Q <n>under control of the voltage of the first voltage signal, the first voltage signal being transmitted to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>the voltage of the pull-up node Q is raised, and then the voltage difference between the control electrode and the second electrode of the eleventh transistor Ml 1 is less than zero, ensuring that the eleventh transistor Ml 1 is completely or relatively completely turned off. In this way, the pull-up node Q <n>Leakage occurs through the first reset circuit 3105, causing the pull-up node Q <n>It can maintain a relatively high and stable voltage.

[0139] For example, such as Figure 5 and Figure 6 As shown, the second reset circuit 3106 is connected to the display reset signal terminal STD and the pull-up node Q. <n>a second voltage signal terminal VGL1 and an anti-creeping node OFF <n>The second reset circuit 3106 is configured to, under the control of a display reset signal transmitted by a display reset signal terminal STD, reset the pull-up node Q <n>A reset is performed.

[0140] For example, in the case where the level of the display reset signal is high, the second reset circuit 3106 can be turned on under the action of the display reset signal, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-up node Q <n>Q <n>A pull-down reset is performed.

[0141] Optionally, as shown in Figure 5 and Figure 6 The second reset circuit 3106 can include a thirteenth transistor M13 and a fourteenth transistor M14.

[0142] For example, as shown in Figure 5 and Figure 6 The control electrode of the thirteenth transistor M13 is electrically connected with a display reset signal terminal STD, the first electrode of the thirteenth transistor M13 is electrically connected with the pull-up node Q <n>An electric connection is made between the second electrode of the thirteenth transistor M13 and the first electrode of the fourteenth transistor M14 and the leakage prevention node OFF <n>The control electrode of the fourteenth transistor M14 is electrically connected with a display reset signal terminal STD, and the second electrode of the fourteenth transistor M14 is electrically connected with a second voltage signal terminal VGL1.

[0143] In the case that the voltage of the display reset signal is high, the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on at the same time under the action of the display reset signal, and the fourteenth transistor M14 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF <n>, the thirteenth transistor M13 can pass the voltage from the leakage prevention node OFF <n>a second voltage signal of the first voltage signal is transmitted to the pull-up node Q <n>Q <n>A reset is performed.

[0144] Here, the pull-up node Q <n>The potential of the second reset circuit 3106 is high, and the third transistor M3 can pull up the potential of the pull-up node Q <n>under control of the voltage of the first voltage signal, the first voltage signal being transmitted to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>The voltage rises, causing the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 to be less than zero, ensuring that the thirteenth transistor M13 is completely or partially turned off. This avoids the need for the pull-up node Q. <n>Leakage occurs through the second reset circuit 3106, causing the pull-up node Q <n>A relatively high and stable voltage can be maintained.

[0145] Here, after the gate drive circuit 3 is formed by cascading the multi-stage shift registers 31, the display reset signal terminal STD of the Nth shift register 31 can be connected to the shift signal terminal CR of the N+4th shift register 31, for example. <n>The electrical connection, in turn, shifts the signal terminal CR of the N+4th stage shift register 31 <n>The output shift signal is the display reset signal of the Nth stage shift register 31. Of course, the relationship of the cascade of the multi-stage shift register 31 is not limited to this.

[0146] As shown in the example, Figure 5 and Figure 6 The third reset circuit 3107 is connected with the global reset signal terminal TRST, the pull-up node Q <n>a second voltage signal terminal VGL1 and an anti-creeping node OFF <n>The third reset circuit 3107 is configured to control the pull-up node Q <n>A reset is performed.

[0147] For example, in the case where the level of the global reset signal is high, the third reset circuit 3107 can be turned on under the action of the global reset signal, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-up node Q <n>Q <n>A pull-down reset is performed.

[0148] Optionally, as shown in Figure 5 and Figure 6 The third reset circuit 3107 can include a fifteenth transistor M15 and a sixteenth transistor M16.

[0149] For example, as shown in Figure 5 and Figure 6 The control electrode of the fifteenth transistor M15 is electrically connected with the global reset signal terminal TRST, the first electrode of the fifteenth transistor M15 is electrically connected with the pull-up node Q <n>An electric connection is made between the second electrode of the fifteenth transistor M15 and the first electrode of the sixteenth transistor M16 and the leakage prevention node OFF <n>The control electrode of the sixteenth transistor M16 is electrically connected with a global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected with a second voltage signal terminal VGL1.

[0150] In the case that the voltage of the global reset signal is high, the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on at the same time under the action of the global reset signal, and the sixteenth transistor M16 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF <n>, the fifteenth transistor M15 can couple the voltage from the leakage prevention node OFF <n>a fifth voltage signal of the first voltage signal transmission to the pull-up node Q <n>Q <n>A reset is performed.

[0151] Here, the pull-up node Q <n>The potential of the third transistor M3 is high potential, and the third reset circuit 3107 is in the non-working state, the third transistor M3 can pull up the node Q <n>under control of the voltage of the first voltage signal, the first voltage signal being transmitted to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>the voltage of the pull-up node Q rises, and the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 is less than zero, ensuring that the fifteenth transistor M15 is completely or relatively completely turned off. In this way, the pull-up node Q <n>Leakage occurs through the third reset circuit 3107, causing the pull-up node Q <n>A relatively high and stable voltage can be maintained.

[0152] For example, as Figure 6 As shown, the fourth reset circuit 3108 is connected to the pull-down node QB_A, the shift signal terminal CR <n>, a first output signal terminal Oput1 <n>, a second output signal terminal Oput2 <n>The fourth reset circuit 3108 is configured to, under the control of the voltage of the pull-down node QB_A, output a reset signal to the shift signal end CR <n>, a first output signal terminal Oput1 <n>and a second output signal terminal Oput2 <n>The reset is performed. The third voltage signal terminal VGL2 is configured to transmit a direct current low level signal (for example, lower than or equal to the low level part of the clock signal). The third voltage signal terminal VGL2 may, for example, be grounded. The low level signals transmitted by the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 may or may not be equal.

[0153] For example, in the case where the voltage of the pull-down node QB_A is a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first output signal terminal Oputl through a pull-down reset <n>to the first output signal terminal Oputl <n>A third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the second output signal terminal Oput2 through the pull-down reset <n>to the second output signal terminal Oput2 <n>A pull-down reset is performed.

[0154] Optionally, as shown in Figure 6 The fourth reset circuit 3108 can include a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19.

[0155] For example, as shown in Figure 6 The control electrode of the seventeenth transistor M17 is electrically connected with the pull-down node QB_A, the first electrode of the seventeenth transistor M17 is electrically connected with the shift signal end CR <n>The second electrode of the seventeenth transistor M17 is electrically connected with the second voltage signal terminal VGL1.

[0156] In the case that the voltage of the pull-down node QB_A is high, the seventeenth transistor M17 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed.

[0157] For example, as shown in Figure 6 The control electrode of the eighteenth transistor M18 is electrically connected with the pull-down node QB_A, the first electrode of the eighteenth transistor M18 is electrically connected with the first output signal end Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected with the third voltage signal terminal VGL2.

[0158] In the case that the voltage of the pull-down node QB_A is high, the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>to the first output signal terminal Oputl <n>A pull-down reset is performed.

[0159] For example, as shown in Figure 6 The control electrode of the nineteenth transistor M19 is electrically connected with the pull-down node QB_A, the first electrode of the nineteenth transistor M19 is electrically connected with the second output signal terminal Oput2 <n>The second electrode of the nineteenth transistor M19 is electrically connected with the third voltage signal terminal VGL2.

[0160] In the case that the voltage of the pull-down node QB_A is high, the nineteenth transistor M19 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2 <n>to the second output signal terminal Oput2 <n>The pull-down reset is performed.

[0161] As shown in Figure 5 and Figure 6 , the fifth reset circuit 3109 is electrically connected with the input signal terminal Iput, the pull-down node QB_A and the second voltage signal terminal VGL1. The fifth reset circuit 3109 is configured to reset the pull-down node QB_A under the control of the input signal transmitted by the input signal terminal Iput.

[0162] For example, when the level of the input signal is high, the fifth reset circuit 3109 can be turned on under the action of the input signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, so as to perform the pull-down reset on the pull-down node QB_A.

[0163] Optionally, as shown in Figure 5 and Figure 6 , the fifth reset circuit 3109 can include a twentieth transistor M20.

[0164] For example, as shown in Figure 5 and Figure 6 , the control electrode of the twentieth transistor M20 is electrically connected with the input signal terminal Iput, the first electrode of the twentieth transistor M20 is electrically connected with the pull-down node QB_A, and the second electrode of the twentieth transistor M20 is electrically connected with the second voltage signal terminal VGL1.

[0165] When the level of the input signal is high, the twentieth transistor M20 can be turned on under the action of the input signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, so as to perform the pull-down reset on the pull-down node QB_A.

[0166] It should be noted that, as shown in Figure 6 , the gate drive circuit 3 can further include a plurality of blanking input circuits 32. One blanking input circuit 32 can be electrically connected with at least two adjacent stages of shift registers 31. That is, at least two stages of shift registers 31 share one blanking input circuit 32. The blanking input circuit 32 is configured to control the corresponding shift register 31 to input a blanking control signal to the pixel drive circuit 21 of the corresponding row during the blanking period of a frame display stage, so that the pixel drive circuit 21 acquires a sensing signal.

[0167] Here, as shown in Figure 6 , the blanking input circuit 32 can include, for example, a selection control circuit 3201, a second input circuit 3202 and at least two transmission circuits 3203.

[0168] As shown in Figure 6 As shown, the selection control circuit 3201 is connected with the selection control signal terminal OE, the shift signal terminal CR <n>The first voltage signal terminal VGL1 and the first blanking node H are electrically connected. The selection control circuit 3201 is configured to, under the control of a selection control signal transmitted by a selection control signal terminal OE, transmit a selection control signal to the first voltage signal terminal VGL1 and the first blanking node H. <n>The received shift signal is transmitted to the first blanking node H.

[0169] For example, in a case where the level of the selection control signal is high, the selection control circuit 3201 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H, charge the first blanking node H, so that the voltage of the first blanking node H rises.

[0170] In the blanking period of a frame display stage, in a case where the sensing signal needs to be acquired, the waveform timing of the selection control signal and the waveform timing of the input signal can be made the same, and then the selection control circuit 3201 is turned on.

[0171] Optionally, as shown in Figure 6 The selection control circuit 3201 can include a twenty-first transistor M21, a twenty-second transistor M22 and a third capacitor C3.

[0172] For example, as shown in Figure 6 The control electrode of the twenty-first transistor M21 is electrically connected with the selection control signal end OE, the first electrode of the twenty-first transistor M21 is electrically connected with the shift signal end CR <n>The second electrode of the twenty-first transistor M21 is electrically connected with the first electrode of the twenty-second transistor M22. The control electrode of the twenty-second transistor M22 is electrically connected with the selection control signal terminal OE, and the second electrode of the twenty-second transistor M22 is electrically connected with the first blanking node H.

[0173] In the case that the level of the selection control signal transmitted by the selection control signal terminal OE is high, the twenty-first transistor M21 and the twenty-second transistor M22 can be turned on at the same time under the action of the selection control signal, and the twenty-first transistor M21 can transmit the shift signal terminal CR <n>The transmitted shift signal is transmitted to the first electrode of the twenty-second transistor M22, and the twenty-second transistor M22 can receive and transmit the shift signal to the first blanking node H to charge the first blanking node H.

[0174] For example, as shown in Figure 6 The first end of the third capacitor C3 is electrically connected with the first blanking node H, and the second end of the third capacitor C3 is electrically connected with the second voltage signal end VGL1.

[0175] In the process of charging the first blanking node H by the selection control circuit 3201, the third capacitor C3 is also charged. In this way, the first blanking node H can be kept at a high level by discharging the third capacitor C3 when the selection control circuit 3201 is turned off.

[0176] In addition, as shown in Figure 6 The selection control circuit 3201 can further include, for example, a twenty-third transistor M23. The control electrode of the twenty-third transistor M23 is electrically connected with the first blanking node H, the first electrode of the twenty-third transistor M23 is electrically connected with the first voltage signal end VDD, and the second electrode of the twenty-third transistor M23 is electrically connected with the first electrode of the twenty-second transistor M22.

[0177] When the voltage of the first blanking node H is at a high level and the twenty-first transistor M21 and the twenty-second transistor M22 are not working, the twenty-third transistor M23 can be turned on under the control of the voltage of the first blanking node H to transmit the first voltage signal transmitted by the first voltage signal end VDD to the first electrode of the twenty-second transistor M22, so that the voltage of the first electrode of the twenty-second transistor M22 is raised, and then the voltage difference between the control electrode and the first electrode of the twenty-second transistor M22 is less than zero, ensuring that the twenty-second transistor M22 is completely or relatively completely cut off. In this way, the first blanking node H can be prevented from leaking through the twenty-second transistor M22, so that the first blanking node H can maintain a relatively high and stable voltage.

[0178] For example, as shown in Figure 6 The second input circuit 3202 is electrically connected with the first blanking node H, the second blanking node N, and the second clock signal end CLKA or the first voltage signal end VDD. The second input circuit 3202 is configured to transmit the second clock signal received at the second clock signal end CLKA or the first voltage signal received at the first voltage signal end VDD to the second blanking node N under the control of the voltage of the first blanking node H.

[0179] For example, when the selection control circuit 3201 is turned on so that the voltage of the first blanking node H is raised, the second input circuit 3202 can be turned on under the control of the voltage of the first blanking node H, receive the second clock signal transmitted by the second clock signal terminal CLKA, and transmit the second clock signal to the second blanking node N.

[0180] Optionally, as shown in Figure 6 the second input circuit 3202 can include a twenty-fourth transistor M24.

[0181] For example, as shown in Figure 6 the control electrode of the twenty-fourth transistor M24 is electrically connected with the first blanking node H, the first electrode of the twenty-fourth transistor M24 is electrically connected with the second clock signal terminal CLKA or the first voltage signal terminal VDD, and the second electrode of the twenty-fourth transistor M24 is electrically connected with the second blanking node N.

[0182] When the voltage of the first blanking node H is high, the twenty-fourth transistor M24 can be turned on under the control of the voltage of the first blanking node H, and transmit the fourth clock signal received at the fourth clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N.

[0183] For example, as shown in Figure 6 the above-mentioned at least two transmission circuits 3203 can be electrically connected with the at least two shift registers 31 one by one. One transmission circuit 3203 is electrically connected with the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q <n>The electric connection, wherein the transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q under the control of the second clock signal transmitted by the second clock signal terminal CLKA <n>.

[0184] For example, in the case that the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, transmit the received second clock signal or the first voltage signal to the pull-up node Q <n>such that the pull-up node Q <n>the voltage of the second output signal terminal Oput2 of the output circuit 3103 is raised, and the output circuit 3103 is turned on, so that the second output signal terminal Oput2 of the output circuit 3103 <n>output a second output signal.

[0185] Optionally, as Figure 6 shown in FIG. 32, the transmission circuit 3203 can include a twenty-fifth transistor M25 and a twenty-sixth transistor M26.

[0186] For example, as Figure 6 shown in FIG. 32, a control electrode of the twenty-fifth transistor M25 is electrically connected with the second clock signal terminal CLKA, a first electrode of the twenty-fifth transistor M25 is electrically connected with the second blanking node N, and a second electrode of the twenty-fifth transistor M25 is electrically connected with a first electrode of the twenty-sixth transistor M26. A control electrode of the twenty-sixth transistor M26 is electrically connected with the second clock signal terminal CLKA, a second electrode of the twenty-sixth transistor M26 is electrically connected with the pull-up node Q <n>The electrical connection.

[0187] In a case where the level of the second clock signal transmitted by the second clock signal terminal CLKA is a high level, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 can be turned on simultaneously under the action of the second clock signal, the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the first electrode of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive and transmit the second clock signal or the first voltage signal to the pull-up node Q <n>Q <n>Charging is performed. The sixth transistor M6 in the output circuit 3103 can pull up the pull-up node Q <n>under the control of the voltage of the second output signal terminal Oput2, receives the fourth clock signal, and outputs the fourth clock signal as the second output signal from the second output signal terminal Oput2 <n>Output.

[0188] The transmission circuit 3203 is also connected to the leakage prevention node OFF <n>In the case of electrical connection, as shown in Figure 6 The first electrode of the twenty-sixth transistor M26 can be connected to the leakage prevention node OFF <n>The second electrode of the twenty-fifth transistor M25 is electrically connected to the first electrode of the twenty-fourth transistor M24.

[0189] Here, the pull-up node Q <n>The potential of the third transistor M3 is high, and the transmission circuit 3203 is in an inactive state. In this case, the third transistor M3 can pull up the pull-up node Q <n>under control of the voltage of the first voltage signal, the first voltage signal being transmitted to the leakage prevention node OFF <n>making the leakage prevention node OFF <n>The voltage rises, causing the voltage difference between the control electrode and the first electrode of the 26th transistor M26 to be less than zero, ensuring that the 26th transistor M26 is completely or partially turned off. This avoids pulling up the Q node. <n>Leakage occurs through the transmission circuit 3203, causing the pull-up node Q <n>It can maintain a relatively high and stable voltage.

[0190] For example, such as Figure 6 As shown, when the gate drive circuit 3 further includes a blanking input circuit 32, the shift register 31 may also include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A, and the second voltage signal terminal VGL1. The sixth reset circuit 3110 is configured to reset the pull-down node QB_A during the blanking period of a frame display phase, under the combined control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H.

[0191] For example, during the blanking period of a frame display phase, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the joint control of the second clock signal and the voltage of the first blanking node H, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, and perform a pull-down reset on the pull-down node QB_A.

[0192] Optional, such as Figure 6 As shown, the sixth reset circuit 3110 may include: the thirty-second transistor M32 and the thirty-third transistor M33.

[0193] For example, such as Figure 6 As shown, the control terminal of the thirty-second transistor M32 is electrically connected to the second clock signal terminal CLKA, the first terminal of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A, and the second terminal of the thirty-second transistor M32 is electrically connected to the first terminal of the thirty-third transistor M33. The control terminal of the thirty-third transistor M33 is electrically connected to the first blanking node H, and the second terminal of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1.

[0194] When the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the voltage of the first blanking node H, transmitting the second voltage signal to the first terminal of the thirty-third transistor M33. The thirty-second transistor M32 can be turned on under the control of the second clock signal, transmitting the second voltage signal from the first terminal of the thirty-third transistor M33 to the pull-down node QB_A, and performing a pull-down reset on the pull-down node QB_A.

[0195] like Figure 6 As shown, taking the example of two adjacent shift registers 31 sharing a single blanking input circuit 32, the structure of the gate drive circuit 3 is schematically illustrated. Furthermore, N represents a positive odd number.

[0196] Here, as shown in Figure 6 In the two adjacent shift registers 31, the fourth transistor M4 can not be arranged in the output circuit 3103 in the latter shift register 31, and the third clock signal end CLKD_1 is not electrically connected.

[0197] Based on this, the shift signal end CR <n>The input signal terminal Iput in the N+2th and N+3th shift registers 31 can be electrically connected, and then the shift signal terminal CR of the Nth shift register 31 is electrically connected to the output signal terminal Out of the N+1th shift register 31. <n>The output shift signal is inputted into the N+2th and N+3th shift registers 31. The display reset signal terminal STD of the Nth and N+1th shift registers 31 can be electrically connected to the shift signal terminal CR

[0198] For example, the shift signal terminal CR <n>The input signal terminal Iput in the third and fourth stage shift registers 31 can be electrically connected. The shift signal terminal CR in the fifth stage shift register 31 can be electrically connected to the output signal terminal Out of the fourth stage shift register 31. <n>The display reset signal end STD in the first-stage and second-stage shift registers 31 can be electrically connected.

[0199] This is conducive to simplifying the structure of the gate drive circuit 3 and reducing the space ratio of the gate drive circuit 3 in the display panel 100.

[0200] For example, as shown in FIG. 3, the first-stage and second-stage shift registers 31 can be divided into two adjacent scanning units 31a and 31b. Figure 6 At this time, the pull-up node Q <n>referred to as a first pull-up node Q <n>pull-up node Q in the second scanning unit 31b is set to the high level <n>The node is called the second pull-up node Q<N+1>. The pull-down node QB_A in the first scan unit 31a can be called the first pull-down node QB_A, and the pull-down node QB_A in the second scan unit 31b can be called the second pull-down node QB_B. The anti-leakage node OFF <n>referred to as a first leakage prevention node OFF <n>The anti-leakage node OFF in the second scanning unit 31b is connected to the anti-leakage node OFF in the first scanning unit 31a. <n>called the second anti-leakage node OFF<N+1>. The first clock signal CLKE_1 in the second scan unit 31b can be called the fifth clock signal CLKE_2, and the fourth clock signal CLKF_1 in the second scan unit 31b can be called the sixth clock signal CLKF_2. The first output signal terminal Oput1 <n>referred to as a first sub output signal terminal Oput1 <n>The second output signal terminal Oput2 in the first scanning unit 31a is connected to the first input signal terminal Sinl in the second scanning unit 31b. <n>referred to as a second sub output signal terminal Oput2 <n>The first output signal terminal Oput1 in the second scanning unit 31b <n>The second output signal terminal Oput2 in the second scan unit 31b is called a third sub-output signal terminal Oputl<N+1> and is connected to the third sub-output signal terminal Oputl<N+1> in the first scan unit 31a. <n>The fourth sub output signal terminal Oput2<N+1> is also referred to as a fourth output signal terminal Oput2.

[0201] As shown in Figure 6 The control circuit 3104 in the second scanning unit 31b can be electrically connected with the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. In the display stage of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are complementary signals.

[0202] As shown in Figure 6 The first reset circuit 3105 in the first scanning unit 31a can also be electrically connected with the second pull-down node QB_B. The first reset circuit 3105 is further configured to, under the control of the voltage of the second pull-down node QB_B, control the voltage of the first pull-up node Q <n>A reset is performed.

[0203] For example, in a case where the voltage of the second pull-down node QB_B is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first pull-up node Q <n>To the first pull-up node Q <n>Perform a pull-down reset.

[0204] Optional, such as Figure 6 As shown, the first reset circuit 3105 in the first scanning unit 31a may further include: the twenty-seventh transistor M27 and the twenty-eighth transistor M28.

[0205] For example, such as Figure 6 As shown, in the first scanning unit 31a, the control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-seventh transistor M27 is connected to the first pull-up node Q. <n>an electric connection between a second electrode of the twenty-seventh transistor M27 and a first electrode of the twenty-eighth transistor M28 and the first leakage-preventing node OFF <n>The control electrode of the twenty-eighth transistor M28 is electrically connected with the second pull-down node QB B, and the second electrode of the twenty-eighth transistor M28 is electrically connected with the second voltage signal terminal VGL1.

[0206] In the case that the voltage of the second pull-down node QB B is high, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 can be turned on at the same time under the action of the voltage of the second pull-down node QB B, and the twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first anti-leakage node OFF <n>, the twenty-seventh transistor M27 can couple the first leakage prevention node OFF <n>a second voltage signal of the first pull-up node Q <n>Q <n>Reset is performed.

[0207] As shown in Figure 6 the first reset circuit 3105 in the second scan unit 31b can also be electrically connected with the first pull-down node QB_A. The first reset circuit 3105 is further configured to reset the second pull-up node Q

[0208] For example, when the voltage of the first pull-down node QB_A is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second pull-up node Q

[0209] Optionally, as shown in Figure 6 the first reset circuit 3105 in the second scan unit 31b can further include a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0210] For example, as shown in Figure 6 in the second scan unit 31b, the control electrode of the twenty-seventh transistor M27 is electrically connected with the first pull-down node QB_A, the first electrode of the twenty-seventh transistor M27 is electrically connected with the second pull-up node Q

[0211] When the voltage of the first pull-down node QB_A is at a high level, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 can be turned on at the same time under the action of the voltage of the first pull-down node QB_A, the twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second anti-leakage node OFF

[0212] As shown in Figure 6 the fourth reset circuit 3108 in the first scan unit 31a can also be electrically connected with the second pull-down node QB_B. The fourth reset circuit 3108 is further configured to reset the shift signal terminal CR <n>, a first sub output signal terminal Oput1 <n>and a second sub-output signal terminal Oput2 <n>A reset is performed.

[0213] For example, in a case where the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed, and a third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oputl <n>and a second sub-output signal terminal Oput2 <n>to the first sub output signal terminal Oputl <n>and a second sub-output signal terminal Oput2 <n>A pull-down reset is performed.

[0214] Optionally, as shown in Figure 6 The fourth reset circuit 3108 in the first scanning unit 31a can further include a twenty-ninth transistor M29, a thirtieth transistor M30 and a thirty-first transistor M31.

[0215] For example, as shown in Figure 6 The control electrode of the twenty-ninth transistor M29 is electrically connected with the second pull-down node QB_B, the first electrode of the twenty-ninth transistor M29 is electrically connected with the shift signal end CR <n>The second electrode of the twenty-ninth transistor M29 is electrically connected with the second voltage signal terminal VGL1.

[0216] In the case that the voltage of the second pull-down node QB_B is high, the twenty-ninth transistor M29 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed.

[0217] For example, as shown in Figure 6 The control electrode of the thirtieth transistor M30 is electrically connected with the second pull-down node QB_B, the first electrode of the thirtieth transistor M30 is electrically connected with the first sub output signal end Oput1 <n>The second electrode of the thirtieth transistor M30 is electrically connected with the third voltage signal terminal VGL2.

[0218] When the voltage of the second pull-down node QB_B is high, the thirtieth transistor M30 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub output signal terminal Oput1 <n>to the first sub output signal terminal Oputl <n>A pull-down reset is performed.

[0219] For example, as shown in Figure 6 The control electrode of the thirty-first transistor M31 is electrically connected with the second pull-down node QB_B, the first electrode of the thirty-first transistor M31 is electrically connected with the second sub output signal terminal Oput2 <n>The second electrode of the thirty-first transistor M31 is electrically connected with the third voltage signal terminal VGL2.

[0220] When the voltage of the second pull-down node QB_B is high, the thirty-first transistor M31 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub output signal terminal Oput2 <n>to the second sub output signal terminal Oput2 <n>The pull-down reset is performed.

[0221] As shown in Figure 6 the fourth reset circuit 3108 in the second scan unit 31b can also be electrically connected with the first pull-down node QB_A. The fourth reset circuit 3108 is further configured to reset the third sub-output signal terminal Oput1<N+1> and the fourth sub-output signal terminal Oput2<N+1> under the control of the voltage of the first pull-down node QB_A.

[0222] For example, when the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1<N+1>, perform pull-down reset on the third sub-output signal terminal Oput1<N+1>, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N+1>, and perform pull-down reset on the fourth sub-output signal terminal Oput2<N+1>.

[0223] Optionally, as shown in Figure 6 the fourth reset circuit 3108 in the second scan unit 31b can further include a thirtieth transistor M30 and a thirty-first transistor M31.

[0224] For example, as shown in Figure 6 the control electrode of the thirtieth transistor M30 is electrically connected with the first pull-down node QB_A, the first electrode of the thirtieth transistor M30 is electrically connected with the third sub-output signal terminal Oput1<N+1>, and the second electrode of the thirtieth transistor M30 is electrically connected with the third voltage signal terminal VGL2.

[0225] When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1<N+1>, and perform pull-down reset on the third sub-output signal terminal Oput1<N+1>.

[0226] For example, as shown in Figure 6 the control electrode of the thirty-first transistor M31 is electrically connected with the first pull-down node QB_A, the first electrode of the thirty-first transistor M31 is electrically connected with the fourth sub-output signal terminal Oput2<N+1>, and the second electrode of the thirty-first transistor M31 is electrically connected with the third voltage signal terminal VGL2.

[0227] In a case where the voltage of the first pull-down node QB_A is at a high level, the thirty-first transistor M31 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N+1>, and pull down and reset the fourth sub-output signal terminal Oput2<N+1>.

[0228] In some other examples, as shown in Figure 5 and Figure 8 , the shift register 31 can include a first input circuit 3101, a leakage prevention circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109.

[0229] For example, the structure and function of the first input circuit 3101 in the present example can be the same as those of the first input circuit 3101 in some of the above examples, the structure and function of the leakage prevention circuit 3102 in the present example can be the same as those of the leakage prevention circuit 3102 in some of the above examples, the structure and function of the control circuit 3104 in the present example can be the same as those of the control circuit 3104 in some of the above examples, the structure and function of the first reset circuit 3105 in the present example can be the same as those of the first reset circuit 3105 in some of the above examples, the structure and function of the second reset circuit 3106 in the present example can be the same as those of the second reset circuit 3106 in some of the above examples, the structure and function of the third reset circuit 3107 in the present example can be the same as those of the third reset circuit 3107 in some of the above examples, and the structure and function of the fifth reset circuit 3109 in the present example can be the same as those of the fifth reset circuit 3109 in some of the above examples. For the same structure and function of the circuit, details are not repeated here.

[0230] For example, as shown in Figure 5 and Figure 8 , the output circuit 3103 can include a pull-up node Q <n>, a first clock signal terminal CLKE_1 and a first output signal terminal Oput1 <n>The output circuit 3103 is configured to, in the display period in the frame display stage, pull up the pull-up node Q <n>the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 under the control of the voltage of the first control signal terminal CTRL1 <n>; and, during a blanking period in a frame display phase, pulling up the node Q <n>the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 under the control of the voltage of the first control signal terminal CTRL1 <n>.

[0231] Of course, such as Figure 5 and Figure 8 As shown, the output circuit 3103 can also be connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR. <n>The output circuit 3103 is further configured to, in the display period in the frame display stage, pull up the pull-up node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR under the control of the voltage of the second clock signal terminal CLKD_2 <n>.

[0232] For example, during a display period in a frame display phase, the pull-up node Q <n>In a case where the voltage of the output circuit 3103 rises, the output circuit 3103 can pull up the node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is used as a shift signal from the shift signal terminal CR under the control of the voltage of the control signal terminal CTRL. The shift signal is shifted by one bit at each clock cycle, and the third clock signal is output from the third clock signal terminal CLKD_2. <n>output; output the first clock signal received at the first clock signal terminal CLKE_1 as an output signal (i.e. the first gate signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>output. During a blanking period in a frame display phase, the pull-up node Q <n>In a case where the voltage of the output circuit 3103 is raised, the output circuit 3103 can pull up the pull-up node Q <n>The first clock signal received at the first clock signal terminal CLKE_1 is outputted as an output signal (i.e. the second gate signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 under the control of the voltage of the first control signal terminal CTRL1. <n>Output.

[0233] In this example, for instance, the first output signal Oput1 of shift register 31 <n>The first output signal terminal Oput1 of the shift register 31 can be electrically connected with the first gate line and the second gate line, so as to shift the first output signal terminal Oput1 of the shift register 31 in the display period in a frame display stage <n>The first gate signal can be transmitted to the pixel driving circuit 21 through the first gate line and the first gate signal terminal G1 in sequence, and the first output signal terminal Oputl of the shift register 31 is shifted during the blanking period in a frame display stage <n>The second gate signal can be transmitted to the pixel driving circuit 21 in sequence via the second gate line and the second gate signal terminal G2. Also, the first output signal terminal Oputl of the shift register 31 can be connected to the second gate signal terminal G2 of the pixel driving circuit 21. <n>The first gate signal terminal G1 and the second gate signal terminal G2 can be electrically connected with one of the gate lines respectively, so that the first output signal terminal Oput1 of the shift register 31 is electrically connected with one of the gate lines respectively during the display period in a frame display stage <n>The first gate signal can be transmitted to the pixel driving circuit 21 through the gate line and the first gate signal terminal G1 in sequence, and the first output signal terminal Oputl of the shift register 31 is shifted during the blanking period in a frame display stage <n>The second gate signal can be transmitted to the pixel driving circuit 21 in sequence via the gate line and the second gate signal terminal G2.

[0234] Optionally, as shown in Figure 5 and Figure 8 The output circuit 3103 can include a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.

[0235] For example, as shown in Figure 5 and Figure 8 The control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected with the third clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected with the shift signal terminal CR <n>Electrically connected.

[0236] During a display period in a frame display stage, the first input circuit 3101 is turned on so that the pull-up node Q <n>The fourth transistor M4 can pull up the voltage at the pull-up node Q <n>The third clock signal is transmitted to the shift signal end CR under the control of the high voltage of the high-voltage control end <n>and the third clock signal is taken as a shift signal from a shift signal terminal CR <n>Output.

[0237] For example, as Figure 5 and Figure 8 illustrated, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected with the first clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected with the first output signal terminal Oput1 <n>The first end of the first capacitor C1 is electrically connected to the pull-up node Q <n>electrical connection, the second end of the first capacitor C1 and the first output signal terminal Oput1 <n>Electrically connected.

[0238] During a display period in a frame display stage, the first input circuit 3101 is turned on, so that the pull-up node Q <n>the voltage of the first input circuit 3101 is raised, the first capacitor C1 is charged. In the case where the first input circuit 3101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>The first clock signal is transmitted to the first output signal terminal Oputl through the fifth transistor M5 which is kept in the on state <n>and outputs the first clock signal as an output signal (i.e., the first gate signal received by the pixel driving circuit 21) from a first output signal terminal Oputl <n>Output.

[0239] During the blanking period in a frame display phase, the pull-up node Q <n>The voltage of the first capacitor C1 can be charged at the same time as the voltage of the second capacitor C2 is raised. At the corresponding stage, the first capacitor C1 can be discharged so that the pull-up node Q <n>The first clock signal is transmitted to the first output signal terminal Oputl through the fifth transistor M6 which is kept in the on state <n>and outputs the first clock signal as an output signal (i.e., a second gate signal received by the pixel driving circuit 21) from a first output signal terminal Oputl <n>Output.

[0240] For example, such as Figure 5 and Figure 8 As shown, the fourth reset circuit 3108 is connected to the pull-down node QB_A and the shift signal terminal CR. <n>, a first output signal terminal Oput1 <n>The fourth reset circuit 3108 is configured to, under the control of the voltage of the pull-down node QB_A, output a reset signal to the shift signal end CR <n>and a first output signal terminal Oputl <n>A reset is performed.

[0241] For example, in a case where the voltage of the pull-down node QB_A is high, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal end VGL1 to the shift signal end CR <n>To the shift signal terminal CR <n>A third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first output signal terminal Oputl by performing a pull-down reset <n>to the first output signal terminal Oputl <n>A pull-down reset is performed.

[0242] Optionally, as shown in Figure 5 and Figure 8 The fourth reset circuit 3108 can include a seventeenth transistor M17 and an eighteenth transistor M18.

[0243] For example, as shown in Figure 5 and Figure 8 The control electrode of the seventeenth transistor M17 is electrically connected with the pull-down node QB_A, the first electrode of the seventeenth transistor M17 is electrically connected with the shift signal end CR <n>The second electrode of the seventeenth transistor M17 is electrically connected with the second voltage signal terminal VGL1.

[0244] In the case that the voltage of the pull-down node QB_A is high, the seventeenth transistor M17 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed.

[0245] For example, as Figure 5 and Figure 8 shown, a control electrode of the eighteenth transistor M18 is electrically connected with the pull-down node QB_A, a first electrode of the eighteenth transistor M18 is electrically connected with the first output signal end Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected with the third voltage signal terminal VGL2.

[0246] When the voltage of the pull-down node QB_A is high, the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>to the first output signal terminal Oputl <n>A pull-down reset is performed.

[0247] It should be noted that, as shown in Figure 8 The gate drive circuit 3 can further include a plurality of blanking input circuits 32. One blanking input circuit 32 can be electrically connected with at least two adjacent stages of shift registers 31. That is, at least two stages of shift registers 31 share one blanking input circuit 32. The blanking input circuit 32 is configured to control the corresponding shift register 31 to input a blanking control signal to the pixel drive circuit 21 of the corresponding row to obtain a sensing signal during a blanking period of a frame display stage.

[0248] Here, as shown in Figure 8 The blanking input circuit 32 can include, for example, a selection control circuit 3201, a second input circuit 3202, and at least two transmission circuits 3203.

[0249] For example, the selection control circuit 3201 in the blanking input circuit 32 in this example can have the same structure and function as the selection control circuit 3201 in the blanking input circuit 32 in some of the above examples. The second input circuit 3202 in the blanking input circuit 32 in this example can have the same structure and function as the second input circuit 3202 in the blanking input circuit 32 in some of the above examples. The structure and function of the same circuits will not be described here.

[0250] For example, as shown in Figure 8 The at least two transmission circuits 3203 can be electrically connected with the at least two shift registers 31 in a one-to-one correspondence. One transmission circuit 3203 is electrically connected with the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q <n>The electric connection, wherein the transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q under the control of the second clock signal transmitted by the second clock signal end CLKA during a blanking period in a frame display stage <n>.

[0251] For example, in the blanking period in a frame display stage, in the case that the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or the first voltage signal to the pull-up node Q <n>such that the pull-up node Q <n>the voltage of the output signal terminal Out of the output circuit 3103 is raised, and the output circuit 3103 is turned on, so that the output signal terminal Out of the output circuit 3103 outputs a signal of the voltage of the output signal terminal Out of the output circuit 3103 <n>Output signal.

[0252] Optionally, as Figure 8 shown in FIG. 32, the transmission circuit 3203 can include a twenty-fifth transistor M25.

[0253] For example, as Figure 8 shown in FIG. 32, a control electrode of the twenty-fifth transistor M25 is electrically connected with a second clock signal terminal CLKA, a first electrode of the twenty-fifth transistor M25 is electrically connected with the second blanking node N, and a second electrode of the twenty-fifth transistor M25 is electrically connected with the pull-up node Q <n>Electrically connected.

[0254] During the blanking period in a frame display stage, in the case that the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the twenty-fifth transistor M25 can be turned on under the action of the second clock signal, and the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the pull-up node Q <n>Q <n>Charging is performed. The fifth transistor M5 in the output circuit 3103 can pull up the pull-up node Q <n>under the control of the voltage of the first output signal terminal Oputl, receives the first clock signal, and outputs the first clock signal as an output signal from the first output signal terminal Oputl <n>Output.

[0255] For example, such as Figure 8 As shown, when the gate drive circuit 3 further includes a blanking input circuit 32, the shift register 31 may also include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A, and the second voltage signal terminal VGL1. The sixth reset circuit 3110 is configured to reset the pull-down node QB_A during the blanking period of a frame display phase, under the combined control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H.

[0256] For example, during the blanking period of a frame display phase, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the joint control of the second clock signal and the voltage of the first blanking node H, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, and perform a pull-down reset on the pull-down node QB_A.

[0257] Optional, such as Figure 8 As shown, the sixth reset circuit 3110 may include: the thirty-second transistor M32 and the thirty-third transistor M33.

[0258] For example, such as Figure 8 As shown, the control terminal of the thirty-second transistor M32 is electrically connected to the first blanking node H, the first terminal of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A, and the second terminal of the thirty-second transistor M32 is electrically connected to the first terminal of the thirty-third transistor M33. The control terminal of the thirty-third transistor M33 is electrically connected to the second clock signal terminal CLKA, and the second terminal of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1.

[0259] When the level of the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the second clock signal, transmitting the second voltage signal to the first terminal of the thirty-third transistor M33. The thirty-second transistor M32 can be turned on under the control of the voltage of the first blanking node H, transmitting the second voltage signal from the first terminal of the thirty-third transistor M33 to the pull-down node QB_A, and performing a pull-down reset on the pull-down node QB_A.

[0260] like Figure 8 As shown, taking the example of two adjacent shift registers 31 sharing a single blanking input circuit 32, the structure of the gate drive circuit 3 is schematically illustrated. Furthermore, N represents a positive odd number.

[0261] Here, as shown in Figure 8 In the two adjacent shift registers 31, the fourth transistor M4 can not be arranged in the output circuit 3103 in the latter shift register 31, and the third clock signal end CLKD_1 is not electrically connected.

[0262] Exemplarily, the cascade relationship of the multi-stage shift register 31 in this example can be the same as that of the multi-stage shift register 31 in some examples described above, which will not be described herein again.

[0263] Exemplarily, the former stage (i.e., the Nth stage) shift register 31 in the two adjacent shift registers 31 can be referred to as a first scan unit 31a, and the latter stage (i.e., the N+1th stage) shift register 31 can be referred to as a second scan unit 31b. At this time, the pull-up node Q <n>referred to as a first pull-up node Q <n>pull-up node Q in the second scanning unit 31b is set to the high level <n>The node is called the second pull-up node Q<N+1>. The pull-down node QB_A in the first scan unit 31a can be called the first pull-down node QB_A, and the pull-down node QB_A in the second scan unit 31b can be called the second pull-down node QB_B. The anti-leakage node OFF <n>referred to as a first leakage prevention node OFF <n>The anti-leakage node OFF in the second scanning unit 31b is connected to the anti-leakage node OFF in the first scanning unit 31a. <n>called the second anti-leakage node OFF<N+1>. The first clock signal CLKE_1 in the second scan unit 31b can be called the fifth clock signal CLKE_2. The first output signal terminal Oput1 in the first scan unit 31a can be called the sixth output signal terminal Oput2. <n>referred to as a first sub output signal terminal Oput1 <n>The first output signal terminal Oput1 in the second scanning unit 31b <n>The second sub-output signal terminal Oput1<N+1> is also referred to as the second output signal terminal Oput1.

[0264] As shown in Figure 8 The control circuit 3104 in the second scanning unit 31b can be electrically connected with the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. In the display stage of a frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are complementary signals.

[0265] In the present example, the structure and function of the first reset circuit 3105 in the first scanning unit 31a can be the same as those in some of the above examples, and the structure and function of the first reset circuit 3105 in the second scanning unit 31b can be the same as those in some of the above examples. The structure and function of the same circuit are not described here.

[0266] As shown in Figure 8 The fourth reset circuit 3108 in the first scanning unit 31a can also be electrically connected with the second pull-down node QB_B. The fourth reset circuit 3108 is further configured to, under the control of the voltage of the second pull-down node QB_B, output a fourth reset signal CR <n>and a first sub-output signal terminal Oputl <n>A reset is performed.

[0267] For example, in a case where the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed, and a third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oputl <n>to the first sub output signal terminal Oputl <n>A pull-down reset is performed.

[0268] Optionally, as shown in Figure 8 The fourth reset circuit 3108 in the first scanning unit 31a can further include a twenty-ninth transistor M29 and a thirtieth transistor M30.

[0269] For example, as shown in Figure 8 The control electrode of the twenty-ninth transistor M29 is electrically connected with the second pull-down node QB_B, the first electrode of the twenty-ninth transistor M29 is electrically connected with the shift signal end CR <n>The second electrode of the twenty-ninth transistor M29 is electrically connected with the second voltage signal terminal VGL1.

[0270] In the case that the voltage of the second pull-down node QB_B is high, the twenty-ninth transistor M29 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>To the shift signal terminal CR <n>A pull-down reset is performed.

[0271] For example, as shown in Figure 8 The control electrode of the thirtieth transistor M30 is electrically connected with the second pull-down node QB_B, the first electrode of the thirtieth transistor M30 is electrically connected with the first sub output signal end Oput1 <n>The second electrode of the thirtieth transistor M30 is electrically connected with the third voltage signal terminal VGL2.

[0272] When the voltage of the second pull-down node QB_B is high, the thirtieth transistor M30 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>to the first sub output signal terminal Oputl <n>The pull-down reset is performed.

[0273] As shown in Figure 8 The fourth reset circuit 3108 in the second scan unit 31b can also be electrically connected with the first pull-down node QB_A. The fourth reset circuit 3108 is configured to reset the second sub-output signal terminal Oput1<N+1> under the control of the voltage of the first pull-down node QB_A.

[0274] For example, when the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1<N+1>, thereby performing pull-down reset on the second sub-output signal terminal Oput1<N+1>.

[0275] Optionally, as shown in Figure 8 The fourth reset circuit 3108 in the second scan unit 31b can further include a thirtieth transistor M30.

[0276] For example, as shown in Figure 8 The control electrode of the thirtieth transistor M30 is electrically connected with the first pull-down node QB_A, the first electrode of the thirtieth transistor M30 is electrically connected with the second sub-output signal terminal Oput2<N+1>, and the second electrode of the thirtieth transistor M30 is electrically connected with the third voltage signal terminal VGL2.

[0277] When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1<N+1>, thereby performing pull-down reset on the second sub-output signal terminal Oput1<N+1>.

[0278] Next, taking the structure of the shift register 31 shown in the first example as an example, the structure of the gate drive circuit 3 is further described.

[0279] In some examples, as shown in Figure 7 The gate drive circuit 3 can further include a plurality of control signal lines 33 extending along the second direction Y. At least part of the plurality of control signal lines 33 is electrically connected with the first shift register 31. The shift register 31 is configured to provide an output signal to the plurality of pixel drive circuits 21 in a corresponding row under the control of at least part of the control signal lines 33 electrically connected with the shift register 31.

[0280] Here, at least part of the plurality of control signal lines 33 can refer to some of the plurality of control signal lines 33.

[0281] Exemplary, Figure 7 A1, A2, A3, …, A6 shown in the drawing respectively represent the first-stage shift register 31, the second-stage shift register 31, the third-stage shift register 31, …, the sixth-stage shift register 31, and are respectively electrically connected with the pixel driving circuit 21 of the first row of sub-pixels 2, the pixel driving circuit 21 of the second row of sub-pixels 2, the pixel driving circuit 21 of the third row of sub-pixels 2, …, the pixel driving circuit 21 of the sixth row of sub-pixels 2 in the display panel 100.

[0282] Among them, A1, A3, A5 can be respectively through the first sub-output signal end Oput1 <n>The first gate signal end G1 in the corresponding row pixel driving circuit 21 is electrically connected through the second sub-output signal end Oput2 <n>A1, A3, A5 can be electrically connected to the first gate signal end G1 in the corresponding row pixel driving circuit 21 through the third sub-output signal end Oput1<N+1>, and electrically connected to the second gate signal end G2 in the corresponding row pixel driving circuit 21 through the fourth sub-output signal end Oput2<N+1>.

[0283] Here, A1, A3, A5 can be respectively referred to as the first scanning unit 31a, and A2, A4, A6 can be respectively referred to as the second scanning unit 31b.

[0284] For example, as shown in FIG. 3, the plurality of control signal lines 33 can include a first clock signal line CLK_1, a second clock signal line CLK_2, and a third clock signal line CLK_3. Figure 7

[0285] The third clock signal end CLKD_1 in the first stage shift register 100 is electrically connected to the first clock signal line CLK_1 to receive the third clock signal. The third clock signal end CLKD_1 in the third stage shift register 100 is electrically connected to the second clock signal line CLK_2 to receive the third clock signal. The third clock signal end CLKD_1 in the fifth stage shift register 100 is electrically connected to the third clock signal line CLK_3 to receive the third clock signal.

[0286] For example, as shown in FIG. 3, the plurality of control signal lines 33 can include a first clock signal line CLK_1, a second clock signal line CLK_2, and a third clock signal line CLK_3. Figure 7

[0287] The first clock signal end CLKE_1 in the first stage shift register 100 is electrically connected to the fourth clock signal line CLK_4 to receive the first clock signal, and the fourth clock signal end CLKF_1 is electrically connected to the fifth clock signal line CLK_5 to receive the fourth clock signal.

[0288] The fifth clock signal end CLKE_2 in the second stage shift register 100 is electrically connected to the sixth clock signal line CLK_6 to receive the fifth clock signal, and the sixth clock signal end CLKE_2 is electrically connected to the seventh clock signal line CLK_7 to receive the sixth clock signal.

[0289] ​​The first clock signal end CLKE_1 in the third stage shift register 100 is electrically connected with the eighth clock signal line CLK_8 to receive a first clock signal, and the fourth clock signal end CLKF_1 is electrically connected with the ninth clock signal line CLK_9 to receive a fourth clock signal.

[0290] The fifth clock signal end CLKE_2 in the fourth stage shift register 100 is electrically connected with the tenth clock signal line CLK_10 to receive a fifth clock signal, and the sixth clock signal end CLKE_2 is electrically connected with the eleventh clock signal line CLK_11 to receive a sixth clock signal.

[0291] The first clock signal end CLKE_1 in the fifth stage shift register 100 is electrically connected with the twelfth clock signal line CLK_12 to receive a first clock signal, and the fourth clock signal end CLKF_1 is electrically connected with the thirteenth clock signal line CLK_13 to receive a fourth clock signal.

[0292] The fifth clock signal end CLKE_2 in the sixth stage shift register 100 is electrically connected with the fourteenth clock signal line CLK_14 to receive a fifth clock signal, and the sixth clock signal end CLKE_2 is electrically connected with the fifteenth clock signal line CLK_15 to receive a sixth clock signal.

[0293] As shown in Figure 7 The above plurality of control signal lines 33 can further include a sixteenth clock signal line CLK_16.

[0294] The global reset signal end TRST in each stage shift register 31 is electrically connected with the sixteenth clock signal line CLK_16 to receive a global reset signal.

[0295] As shown in Figure 7 The above plurality of control signal lines 33 can further include a seventeenth clock signal line CLK_17 and an eighteenth clock signal line CLK_18.

[0296] The selection control signal end OE of each blanking input circuit 32 is electrically connected with the seventeenth clock signal line CLK_17 to receive a selection control signal.

[0297] The second clock signal end CLKA of each blanking input unit 5 is electrically connected with the eighteenth clock signal line CLK_18 to receive a second clock signal.

[0298] As shown in Figure 7 The above plurality of control signal lines 33 can further include a nineteenth clock signal line CLK_19 and a twentieth clock signal line CLK_20.

[0299] The sixth voltage signal end VDD_A in the first stage shift register 31, the sixth voltage signal end VDD_A in the third stage shift register 31 and the sixth voltage signal end VDD_A in the fifth stage shift register 31 are all electrically connected with the nineteenth clock signal line CLK_19 to receive the sixth voltage signal.

[0300] The seventh voltage signal end VDD_B in the second stage shift register 31, the seventh voltage signal end VDD_B in the fourth stage shift register 31 and the seventh voltage signal end VDD_B in the sixth stage shift register 31 are all electrically connected with the twentieth clock signal line CLK_20 to receive the seventh voltage signal.

[0301] As shown in the example of FIG. 6, the plurality of control signal lines 33 can further include a twenty-first clock signal line CLK_21. Figure 7

[0302] The input signal end Iput in the first stage shift register 31 and the input signal end Iput in the second stage shift register 31 can both be electrically connected with the twenty-first clock signal line CLK_21 to receive a start signal as an input signal.

[0303] As shown in the example of FIG. 6, the plurality of control signal lines 33 can further include a twenty-second clock signal line CLK_22. Figure 7

[0304] The display reset signal end STD of the last four stage shift registers 31 in the gate drive circuit 3 can all be electrically connected with the twenty-second clock signal line CLK_22 to receive a display reset signal.

[0305] As shown in the example of FIG. 6, in the gate drive circuit 3, the shift signal end CR in the Nth stage shift register 31 in the other stage shift registers 31 except the first stage shift register 31 and the second stage shift register 31 can be electrically connected with the twenty-third clock signal line CLK_23 to receive a shift signal. <n>The input signal terminal Iput in the N+2th and N+3th shift registers 31 can be electrically connected, and then the shift signal terminal CR of the Nth shift register 31 is electrically connected to the output signal terminal Out of the N+1th shift register 31. <n>The output shift signal serves as the input signal in the (N+2)th and (N+3)th stage shift registers 31. In the other stages of shift registers 31 besides the last four, the display reset signal STD of the Nth and (N+1)th stage shift registers 31 can, for example, be connected to the shift signal CR of the (N+4)th stage shift register 31.<N+4> Electrical connection, thereby enabling the shift signal terminal CR of the (N+4)th stage shift register 31.<N+4> The output shift signal serves as the display reset signal for the Nth and N+1th shift registers 31.

[0306] In related technologies, a display panel PNL typically has a display area A and a bezel area B surrounding the display area A. Sub-pixels P in the display panel PNL are typically located within the display area A, and gate drive circuits 3' electrically connected to the sub-pixels P are typically located within the bezel area B, situated on one side of the extension direction of the gate line GL.

[0307] As display panel resolutions increase, narrow bezels and even borderless designs have become the current trend. In the display field, especially in large-size OLED displays, the method of placing the gate driving circuit 3' within the bezel area B of the display panel PNL makes it difficult to achieve narrow or borderless bezels. Furthermore, the shape of current display panel PNLs is often non-rectangular, making it even more difficult to achieve narrow or borderless bezels with the aforementioned gate driving circuit 3' placement.

[0308] Based on this, such as Figure 3 As shown, the display panel 100 provided in some embodiments of this disclosure can divide the multiple transistors and capacitors included in each level shift register 31 into multiple device groups 311. A device group 311 can be located in the area between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2.

[0309] For example, such as Figures 9a to 9h As shown, each device group 311 may include at least one transistor and / or at least one capacitor. Wherein, Figures 9a to 9h The structure shown is a sequentially connected structure. Because it is difficult to show this structure in one figure, it has been divided into multiple figures.

[0310] Here, the method of dividing the multiple transistors and capacitors included in the shift register 31 can be selected and set according to actual needs, so that the space ratio of the divided device group 311 is small and the complexity of the connection relationship between each device group 311 is low.

[0311] For example, such as Figure 9b As shown in FIG. 10, one device group 311 can include a first transistor Ml and a second transistor M2 in the first input circuit 3101.

[0312] For example, as shown in FIG. 10, one device group 311 can include a third transistor M3 in the leakage prevention circuit 3102. Figure 9a

[0313] For example, as shown in FIG. 10, one device group 311 can include a first capacitor Cl in the output circuit 3103. Figure 9g

[0314] For example, as shown in FIG. 10, one device group 311 can include a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10 in the control circuit 3104. Figure 9d

[0315] For example, as shown in FIG. 10, one device group 311 can include an eleventh transistor Ml 1 in the first reset circuit 3105. Another device group 311 can include a twelfth transistor M12 in the first reset circuit 3105. Figure 9c It should be noted that,

[0316] The circuit diagram of the shift register 31 shown in FIG. 10 is an equivalent circuit diagram of the shift register 31 in the actual product. In the actual product, multiple parallel transistors are included in some circuits, and only one is shown in the circuit diagram of the shift register 31 shown in FIG. 10. Figures 9a to 9h Figures 9a to 9h For example, the first transistor Ml and the second transistor M2 included in the first input circuit 3101 are only one shown in FIG. 10. In the actual product, the first input circuit 3101 can include multiple parallel first transistors Ml and second transistors M2. Among them, each first transistor Ml and a second transistor M2 can constitute a device group 311, which is arranged in the area between the adjacent two sub-pixels 2 in the corresponding row of sub-pixels 2.

[0317] For example, the fifth transistor M5 included in the output circuit 3103 is only one shown in FIG. 10. In the actual product, the output circuit 3103 can include multiple parallel fifth transistors M5. Among them, each fifth transistor M5 can constitute a device group 311, which is arranged in the area between the adjacent two sub-pixels 2 in the corresponding row of sub-pixels 2. Figure 9b

[0318] For example, the fifth transistor M5 included in the output circuit 3103 is only one shown in FIG. 10. In the actual product, the output circuit 3103 can include multiple parallel fifth transistors M5. Among them, each fifth transistor M5 can constitute a device group 311, which is arranged in the area between the adjacent two sub-pixels 2 in the corresponding row of sub-pixels 2. Figure 9h

[0319] ​​​​​​For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0320] For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. Figures 9a to 9h For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0321] For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0322] For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0323] For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. Figures 9a to 9h For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0324] Figure 9a For example, as shown in FIG. 6, the device group 311 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. That is, at least part of the device groups 311 included in the first-stage shift register 31 can be arranged in the area between the two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2. Figure 9c ​As shown, in shift registers 31 of different levels, multiple device groups 311, each including the eleventh transistor M11, can be located in the region between two adjacent columns of sub-pixels 2.

[0325] This helps to reduce the difficulty of the layout design of the display panel 100 and improve the regularity of the layout of the display panel 100.

[0326] Of course, the division method of the multiple device groups 311 included in different levels of shift register 31 can be different, and the arrangement order of the multiple device groups 311 included in different levels of shift register 31 and their setting positions in the corresponding row sub-pixels 2 can also be different. The specific settings can be selected according to actual needs.

[0327] In some examples, such as Figure 3 , Figure 9f and Figure 10 As shown, after cascading the multi-stage shift registers 31 to form the gate drive circuit 3, the gate drive circuit 3 further includes: multiple cascaded input signal lines 34 and multiple cascaded display reset signal lines 35. Each cascaded input signal line 34 is configured to connect to the shift signal terminal CR of the first-stage shift register 31. <n>and the input signal terminal Iput of the other stage shift register 31. Each cascaded display reset signal line 35 is configured to connect the shift signal terminal CR of the one stage shift register 31 <n>a display reset signal terminal STD of another stage shift register 31.

[0328] For example, the cascade relationship of the gate drive circuit 3 shown in Figure 3 , Figure 9f and Figure 10 is taken as an example.

[0329] That is, in the shift signal terminal CR of the Nth stage shift register 31 among the shift registers 31 other than the first stage shift register 31 and the second stage shift register 31, the shift signal terminal CR of the (N-1)th stage shift register 31 is connected. <n>The input signal line 34 is electrically connected to the input signal terminal Iput of the N+2th stage shift register 31 and is electrically connected to the input signal terminal Iput of the N+3th stage shift register 31.

[0330] For example, as shown in Fig. 3, the output circuit 3103 of the Nth stage shift register 31 is electrically connected to the first input circuit 3101 and the fifth reset circuit 3109 of the N+2th stage shift register 31 through the cascade input signal line 34, and is electrically connected to the first input circuit 3101 and the fifth reset circuit 3109 of the N+3th stage shift register 31 through the cascade input signal line 34. Figure 10

[0331] Thus, the shift signal terminal CR of the output circuit 3103 of the Nth stage shift register 31 is electrically connected to the shift signal terminal CR of the first input circuit 3101 of the N+2th stage shift register 31 and the shift signal terminal CR of the first input circuit 3101 of the N+3th stage shift register 31 through the cascade input signal line 34. <n>The shift signal output by the shift signal terminal CR<N+4> of the output circuit 3103 in the N+4th shift register 31 can be transmitted to the second reset circuit 3106 in the Nth shift register 31 through the cascaded display reset signal line 35 as a display reset signal of the second reset circuit 3106, and can be transmitted to the second reset circuit 3106 in the N+1th shift register 31 through the cascaded display reset signal line 35 as a display reset signal of the second reset circuit 3106.

[0332] The shift signal terminal CR<N+4> of the N+4th shift register 31 in the shift register 31 other than the last four shift registers 31 can be electrically connected to the display reset signal terminal STD of the Nth shift register 31 through the cascaded display reset signal line 35, and can be electrically connected to the display reset signal terminal STD of the N+1th shift register 31 through the cascaded display reset signal line 35.

[0333] For example, as shown in FIG. 6, the output circuit 3103 in the N+4th shift register 31 can be electrically connected to the second reset circuit 3106 of the Nth shift register 31 through the cascaded display reset signal line 35, and can be electrically connected to the second reset circuit 3106 of the N+1th shift register 31 through the cascaded display reset signal line 35. Figure 10

[0334] Thus, the shift signal output by the shift signal terminal CR<N+4> of the output circuit 3103 in the N+4th shift register 31 can be transmitted to the second reset circuit 3106 in the Nth shift register 31 through the cascaded display reset signal line 35 as a display reset signal of the second reset circuit 3106, and can be transmitted to the second reset circuit 3106 in the N+1th shift register 31 through the cascaded display reset signal line 35 as a display reset signal of the second reset circuit 3106.

[0335] In some examples, as shown in FIG. 7, the display panel 100 has a plurality of sub-pixel regions S. The plurality of sub-pixel regions S are configured to include a plurality of sub-pixels 2. For example, the plurality of sub-pixel regions S and the plurality of sub-pixels 2 can be one-to-one correspondingly configured. Figure 9a In some examples, as shown in FIG. 8, the display panel 100 further has a first gap region D located between two adjacent columns of sub-pixel regions S. Since the number of sub-pixels 2 included in different columns of sub-pixels 2 included in the display panel 100 can be different, the size of different first gap regions D in the second direction Y can be different.

[0336] Figure 9a In some examples, as shown in FIG. 8, the display panel 100 further has a first gap region D located between two adjacent columns of sub-pixel regions S. Since the number of sub-pixels 2 included in different columns of sub-pixels 2 included in the display panel 100 can be different, the size of different first gap regions D in the second direction Y can be different. ​​

[0337] For example, the "adjacent two column sub-pixel region S" described above can refer to any adjacent two column sub-pixel region S of the plurality of column sub-pixel regions S of the display panel 100, or can refer to adjacent two column sub-pixel region S in a part of the plurality of column sub-pixel regions S of the display panel 100.

[0338] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 9a For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form.

[0339] For example, one pixel unit 2a can include three sub-pixels 2 or four sub-pixels 2 arranged in the first direction X in sequence, and so on. In the case where one pixel unit 2a includes three sub-pixels 2 arranged in the first direction X in sequence, the three sub-pixels 2 can include a red sub-pixel, a green sub-pixel and a blue sub-pixel. In the case where one pixel unit 2a includes four sub-pixels 2 arranged in the first direction X in sequence, the four sub-pixels 2 can include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.

[0340] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 9a For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form.

[0341] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form.

[0342] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form.

[0343] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form.

[0344] For example, as shown in FIG. 2, the display panel 100 can include a plurality of sub-pixels 2 arranged in a matrix form. Figure 3 、 Figure 9f 、 Figure 10 and Figure 11 As shown, the cascade display reset signal line 34 and the cascade input signal line 35 are both arranged in the first gap region D, and are arranged in different first gap regions D. That is, the first gap region D in which the cascade display reset signal line 34 is arranged is different from the first gap region D in which the cascade input signal line 35 is arranged, and the two do not overlap.

[0345] For example, in the first gap region D in which the cascade display reset signal line 34 or the cascade input signal line 35 is arranged, no device group 311 is arranged.

[0346] It should be noted that since the gate drive circuit 3 includes a plurality of stages of shift registers 31, after cascading, the number of cascade display reset signal lines 34 and cascade input signal lines 35 in the gate drive circuit 3 is relatively large. If the cascade display reset signal line 34 and the cascade input signal line 35 are arranged in the same first gap region D, the size of the first gap region D in the first direction X is relatively large, which reduces the space ratio of the sub-pixel 2, and thus easily leads to a reduction in the PPI of the display panel 100.

[0347] The display panel 100 provided by some embodiments of the present disclosure can effectively improve the PPI of the display panel 100 by arranging the cascade display reset signal line 34 and the cascade input signal line 35 in different first gap regions D, so that the size of each first gap region D in the first direction X is relatively small, the space ratio of the first gap region D is reduced, and the space ratio of the sub-pixel 2 is increased. It has been verified that arranging the cascade display reset signal line 34 and the cascade input signal line 35 in different first gap regions D can improve the PPI by about one time compared with arranging the cascade display reset signal line 34 and the cascade input signal line 35 in the same first gap region D.

[0348] Therefore, the display panel 100 provided by some embodiments of the present disclosure can effectively utilize the area between the two adjacent sub-pixels 2 by dividing each stage of shift registers 31 into a plurality of device groups 311 and arranging the plurality of device groups 311 in the area between the two adjacent sub-pixels 2 in the corresponding row, thereby reducing the space ratio of the part of the gate drive circuit 3 in the frame area, so that the display panel 100 can realize a narrow-frame design or even a frameless design.

[0349] Furthermore, the display panel 100 provided by some embodiments of the present disclosure can further reduce the space ratio of the part of the gate drive circuit 3 in the frame area while reducing the size of the first gap region D in the first direction X by arranging the cascade display reset signal line 34 and the cascade input signal line 35 in different first gap regions D, thereby increasing the space ratio of the sub-pixel 2 and effectively improving the PPI of the display panel 100.

[0350] In some embodiments, as shown in Figure 9b , Figure 9d , Figure 9e , Figure 9f , Figure 9h and Figure 10 , at least one of the plurality of control signal lines 33 included in the gate drive circuit 3 is located in the first gap region D.

[0351] That is, a part of the plurality of control signal lines 33 can be located in the first gap region D. Alternatively, all of the plurality of control signal lines 33 can be located in the first gap region D.

[0352] In this way, a part or even all of the gate drive circuit 3 can be arranged in the region between the plurality of sub-pixels 2 included in the display panel 100, reducing the space ratio of the part of the gate drive circuit 3 in the frame region, so that the display panel 100 can realize a narrow frame design or even a frameless design.

[0353] In some examples, as shown in Figure 9b , Figure 9d , Figure 9e , Figure 9f , Figure 9h and Figure 10 , in the case where the plurality of control signal lines 33 are arranged in the first gap region D, one first gap region D can be provided with one control signal line 33, and at least one column of sub-pixels 2 is arranged between the adjacent two control signal lines 33.

[0354] Since the size of the control signal line 33 in the first direction X is large, by arranging only one control signal line 33 in one first gap region D, the size of the first gap region D in the first direction X can be avoided from being increased, thereby avoiding affecting the PPI of the display panel 100.

[0355] It should be noted that in the first gap region D provided with the control signal line 33, the device group 311, the cascade input signal line 34 and the cascade display reset signal line 35 are not arranged. In this way, the size of the first gap region D in the first direction X can be avoided from being increased, thereby avoiding affecting the PPI of the display panel 100.

[0356] Here, in the case where the plurality of sub-pixels 2 are divided into a plurality of pixel units 2a, and the first gap region D is the region between any two adjacent columns of pixel units 2a, at least one column of pixel units 2a can be arranged between the two control signal lines 33.

[0357] In some examples, the plurality of control signal lines 33 can be arranged in the same layer and made of the same material as the plurality of data lines DL.

[0358] It should be noted that the "same layer" mentioned herein refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form the layer structure by one patterning process. According to different specific patterns, the one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and the specific patterns can also be at different heights or have different thicknesses. In this way, the plurality of control signal lines 33 and the plurality of data lines DL can be prepared at the same time in the one patterning process, which is beneficial to simplify the preparation process of the display panel 100.

[0359] For example, the material of the data line DL can be a metal material. The metal material can be molybdenum, titanium, copper, silver or aluminum, etc. The structure of the data line DL can be a single-layer structure or a laminated structure.

[0360] The arrangement mode of the cascade input signal lines 34 and the cascade display reset signal lines 35 can include multiple modes, which can be selected according to actual needs.

[0361] In some embodiments, the plurality of cascade input signal lines 34 can be divided into multiple groups. Each group of cascade input signal lines 34 can include at least one cascade input signal line 34.

[0362] For example, each group of cascade input signal lines 34 can include one cascade input signal line 34, or can include multiple cascade input signal lines 34.

[0363] Here, the grouping mode of the plurality of cascade input signal lines 34 can be selected according to actual needs. For example, for the cascade input signal lines 34 located in the same first gap region D, there is partial overlap in the first direction X, and then the cascade input signal lines 34 with partial overlap can be divided into a group.

[0364] For example, for the two cascade input signal lines 34 located in the same first gap region D, there is partial overlap in the first direction X, and then the two cascade input signal lines 34 can be divided into a group.

[0365] For example, as shown in FIG. 6, for the three cascade input signal lines 34 located in the same first gap region D, the first two cascade input signal lines 34 have partial overlap in the first direction X, and the last two cascade input signal lines 34 have partial overlap in the first direction X, and then the three cascade input signal lines 34 can be divided into a group. Figure 10

[0366] ​In some examples, at least one set of cascaded input signal lines 34 is arranged in one first gap region D. That is, the multiple sets of cascaded input signal lines 34 can be arranged in multiple first gap regions D, and one first gap region D can be arranged with one set of cascaded input signal lines 34, or one first gap region D can be arranged with two sets of cascaded input signal lines 34. Alternatively, one first gap region D can be arranged with all the cascaded input signal lines 34.

[0367] In some examples, at least one column of sub-pixels 2 is arranged between two adjacent sets of cascaded input signal lines 34 which are arranged in different first gap regions D. That is, there can be no first gap region D between two adjacent sets of cascaded input signal lines 34, or there can be at least one first gap region D between two adjacent sets of cascaded input signal lines 34.

[0368] This means that the multiple sets of cascaded input signal lines 34 can be arranged in multiple first gap regions D, which is conducive to further reducing the size of the first gap region D in the first direction X, and is conducive to improving the PPI of the display panel 100.

[0369] For example, in the multiple first gap regions D arranged with cascaded input signal lines 34, each first gap region D is arranged with multiple sets of cascaded input signal lines 34. In this case, two adjacent sets of cascaded input signal lines 34 can refer to any set of cascaded input signal lines 34 in one first gap region D and any set of cascaded input signal lines 34 in another first gap region D, and the two first gap regions D in which the two sets of cascaded input signal lines 34 are arranged are adjacent to each other, or at least one first gap region D is arranged between the two first gap regions D in which the two sets of cascaded input signal lines 34 are arranged, and the at least one first gap region D is not arranged with cascaded input signal lines 34.

[0370] For example, in the first direction X, the two adjacent sets of cascaded input signal lines 34 can partially overlap or can not overlap.

[0371] Here, in the case where the multiple sub-pixels 2 are divided into multiple pixel units 2a, and the first gap region D is the region between any two adjacent columns of pixel units 2a, at least one column of pixel units 2a is arranged between the two adjacent sets of cascaded input signal lines 34.

[0372] In some examples, multiple sets of cascaded input signal lines 34 are arranged in one first gap region D, and at least one row of sub-pixels is arranged between two adjacent sets of cascaded input signal lines 34 which are arranged in the same first gap region D.

[0373] For example, one row, two rows, three rows or even more rows of sub-pixels 2 can be arranged between the two adjacent groups of cascaded input signal lines 34. As the number of rows of sub-pixels arranged between the two adjacent groups of cascaded input signal lines 34 increases, the difference in the number of stages of the shift registers 31 corresponding to the two adjacent groups of cascaded input signal lines 34 increases.

[0374] This means that, in the first direction X, the remaining groups of cascaded input signal lines 34 that partially overlap the two adjacent groups of cascaded input signal lines 34 are located in other first gap regions D. The number of cascaded input signal lines 34 that are located in the same first gap region D and partially overlap in the first direction X is small. This effectively reduces the size of the first gap region D in the first direction X, which is conducive to improving the PPI of the display panel 100.

[0375] In some embodiments, the plurality of cascaded display reset signal lines 35 can be divided into a plurality of groups. Each group of cascaded display reset signal lines 35 includes at least one cascaded display reset signal line 35.

[0376] For example, each group of cascaded display reset signal lines 35 can include one cascaded display reset signal line 35, or can include a plurality of cascaded display reset signal lines 35.

[0377] In this embodiment, the manner in which the plurality of cascaded display reset signal lines 35 are grouped can refer to the manner in which the plurality of cascaded input signal lines 34 are grouped in some of the above embodiments, which will not be described again here.

[0378] In some examples, at least one group of cascaded display reset signal lines 35 can be arranged in one first gap region D. That is, the plurality of groups of cascaded display reset signal lines 35 can be arranged in a plurality of first gap regions D, and one group of cascaded display reset signal lines 35 can be arranged in one first gap region D, or two groups of cascaded display reset signal lines 35 can be arranged in one first gap region D. Alternatively, all of the cascaded display reset signal lines 35 can be arranged in one first gap region D.

[0379] In some examples, at least one column of sub-pixels 2 is arranged between two adjacent groups of cascaded display reset signal lines 35 located in different first gap regions D. That is, there can be no first gap region D between the two adjacent groups of cascaded display reset signal lines 35, or there can be at least one first gap region D between the two adjacent groups of cascaded display reset signal lines 35.

[0380] This means that the plurality of groups of cascaded display reset signal lines 35 can be arranged in a plurality of first gap regions D, which is conducive to further reducing the size of the first gap region D in the first direction X and improving the PPI of the display panel 100.

[0381] For example, in the plurality of first gap regions D provided with the cascade display reset signal lines 35, in the case that each first gap region D is provided with a plurality of groups of the cascade display reset signal lines 35, the two adjacent groups of the cascade display reset signal lines 35 can refer to any group of the cascade display reset signal lines 35 in one first gap region D and any group of the cascade display reset signal lines 35 in another first gap region D, and the two first gap regions D in which the two groups of the cascade display reset signal lines 35 are located are adjacent to each other, or at least one first gap region D is provided between the two first gap regions D in which the two groups of the cascade display reset signal lines 35 are located, and the at least one first gap region D is not provided with the cascade display reset signal lines 35.

[0382] For example, in the first direction X, the two adjacent groups of the cascade display reset signal lines 35 can have partial overlap or no overlap.

[0383] Here, in the case that the plurality of sub-pixels 2 are divided into a plurality of pixel units 2a, and the first gap region D is a region between any two adjacent columns of pixel units 2a, at least one column of pixel units 2a is provided between the two adjacent groups of the cascade display reset signal lines 35.

[0384] In some examples, a plurality of groups of the cascade display reset signal lines 35 are provided in one first gap region D, and at least one row of sub-pixels 2 is provided between the two adjacent groups of the cascade display reset signal lines 35 located in the same first gap region D.

[0385] For example, the two adjacent groups of the cascade display reset signal lines 35 can be provided with one row, two rows, three rows or even more rows of sub-pixels 2. As the number of rows of sub-pixels 2 provided between the two adjacent groups of the cascade display reset signal lines 35 increases, the difference in the number of stages of the shift registers 31 corresponding to the two adjacent groups of the cascade display reset signal lines 35 increases.

[0386] This means that, in the first direction X, the remaining groups of the cascade display reset signal lines 35 having partial overlap with the two adjacent groups of the cascade display reset signal lines 35 are located in other first gap regions D. The number of the cascade display reset signal lines 35 located in the same first gap region D and having partial overlap in the first direction X is small. This can effectively reduce the size of the first gap region D in the first direction X, and is beneficial to improve the PPI of the display panel 100.

[0387] In some embodiments, the plurality of cascade input signal lines 34 and the plurality of cascade display reset signal lines 35 can be made of the same material as the plurality of data lines DL and provided in the same layer.

[0388] In this way, multiple input signal lines 34, multiple cascaded display reset signal lines 35, multiple control signal lines 33, and multiple data lines DL can be fabricated simultaneously in a single patterning process, which helps to simplify the fabrication process of the display panel 100.

[0389] In some embodiments, such as Figure 9a As shown, each sub-pixel region S may include a sub-pixel circuit region Sa and a sub-pixel light-emitting region Sb arranged sequentially along the second direction Y. The sub-pixel circuit region Sa is used to house the pixel driving circuit 21 in the corresponding sub-pixel 2, and the sub-pixel light-emitting region Sb is used to house the light-emitting device 22 in the corresponding sub-pixel 2.

[0390] In some examples, such as Figures 9a to 9h As shown, along the second direction Y, any three adjacent rows of sub-pixel regions S can be designated as the first row of sub-pixel regions S1, the second row of sub-pixel regions S2, and the third row of sub-pixel regions S3.

[0391] For example, such as Figures 9a to 9h As shown, the area between the first row of sub-pixel region S1 and the second row of sub-pixel region S2 is the second gap region E, and the area between the second row of sub-pixel region S2 and the third row of sub-pixel region S3 is the third gap region F.

[0392] Among them, such as Figures 9a to 9h As shown, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, the sub-pixel light-emitting areas Sb are both closer to the second gap region E than the sub-pixel circuit areas Sa. For example, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, each sub-pixel region S is symmetrically arranged with respect to the second gap region E, and the sub-pixel light-emitting areas Sb in each sub-pixel region S are closer to the second gap region E, while the sub-pixel circuit areas Sa in each sub-pixel region S are farther away from the second gap region E.

[0393] like Figures 9a to 9h As shown, in the second row of sub-pixel regions S2 and the third row of sub-pixel regions S3, the sub-pixel circuit region Sa is closer to the third gap region F than the sub-pixel light-emitting region Sb. For example, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, each sub-pixel region S is symmetrically arranged with respect to the third gap region F, and the sub-pixel light-emitting region Sb in each sub-pixel region S is farther away from the third gap region F, while the sub-pixel circuit region Sa in each sub-pixel region S is closer to the third gap region F.

[0394] It should be noted that the present example only limits the positions of the sub-pixel circuit region Sa and the sub-pixel light-emitting region Sb in each sub-pixel region S, and does not limit whether the structures of the pixel driving circuit 21 arranged in the sub-pixel circuit region Sa and the light-emitting device 22 arranged in the sub-pixel light-emitting region Sb are symmetrical. Since the pixel driving circuit 21 and the light-emitting device 22 each include a plurality of film layers, in the process of preparing the plurality of film layers, there may be differences between the sizes of the film layers included in different pixel driving circuits 21 or differences between the sizes of the film layers included in different light-emitting devices 22 due to inevitable reasons such as process errors. In this way, the pixel driving circuits 21 in the first row of sub-pixel regions S1 and the pixel driving circuits 21 in the second row of sub-pixel regions S2 cannot be strictly symmetrically arranged about the second gap region E, the light-emitting devices 22 in the first row of sub-pixel regions S1 and the light-emitting devices 22 in the second row of sub-pixel regions S2 cannot be strictly symmetrically arranged about the second gap region E, the pixel driving circuits 21 in the second row of sub-pixel regions S2 and the pixel driving circuits 21 in the third row of sub-pixel regions S2 cannot be strictly symmetrically arranged about the third gap region F, and the light-emitting devices 22 in the second row of sub-pixel regions S2 and the light-emitting devices 22 in the third row of sub-pixel regions S2 cannot be strictly symmetrically arranged about the third gap region F.

[0395] In some embodiments, as shown in FIG. 3, the gate driving circuit 3 can further include a plurality of transmission signal lines 36 extending along the first direction X and located in the second gap region E. Figures 9a to 9h

[0396] In some examples, as shown in FIG. 3, the two-stage shift register 31 electrically connected to the sub-pixel 2 located in the first row of sub-pixel regions S1 and the sub-pixel 2 located in the second row of sub-pixel regions S2 can share at least one transmission signal line 36 of the plurality of transmission signal lines 36. Figures 9a to 9h

[0397] For example, the two-stage shift register 31 can share one transmission signal line 36, two transmission signal lines 36, three transmission signal lines 36, or even the plurality of transmission signal lines 36.

[0398] ​​By arranging the sub-pixel circuit regions Sa and the sub-pixel light-emitting regions Sb in the first row of sub-pixel regions S1, the second row of sub-pixel regions S2, and the third row of sub-pixel regions S3 in the above manner, the sub-pixel circuit regions Sa in the second row of sub-pixel regions S2 and the sub-pixel circuit regions Sa in the third row of sub-pixel regions S3 can be arranged closely together (i.e., the third gap region F has a smaller size in the second direction Y), the second gap region E between the sub-pixel light-emitting regions Sb in the first row of sub-pixel regions S1 and the sub-pixel light-emitting regions Sb in the second row of sub-pixel regions S2 has a larger size in the second direction Y (the size of the second gap region E in the second direction Y is larger than the size of the third gap region F in the second direction Y), and the spacing between the sub-pixel light-emitting regions Sb in each row of sub-pixel regions S can be equal or approximately equal, thereby ensuring the uniformity of light emission of the display panel 100.

[0399] On this basis, the required wiring inside each stage of shift registers 31 and the required wiring between the shift registers 31 and the control signal lines 33 can be arranged in the second gap region E adjacent to the shift registers 31. The plurality of transmission signal lines 36 can include, for example, the required wiring inside two stages of shift registers 31 electrically connected to the sub-pixels 2 in the first row of sub-pixel regions S1 and the sub-pixels 2 in the second row of sub-pixel regions S2 and the required wiring between the two stages of shift registers 31 and the control signal lines 33.

[0400] The present disclosure can reduce the number of transmission signal lines 36 arranged in the second gap region E and reduce the spatial proportion of the transmission signal lines 36 in the second gap region E by using at least one of the plurality of transmission signal lines 36 for the two stages of shift registers 31. This can reduce the size of the second gap region E in the second direction Y, allow more sub-pixels 2 to be arranged to increase the PPI of the display panel 100, or increase the area of the sub-pixel light-emitting regions Sb to increase the aperture ratio of the display panel 100.

[0401] In some embodiments, the plurality of transmission signal lines 36 and the plurality of gate lines GL can be made of the same material and arranged in the same layer.

[0402] In this way, the plurality of transmission signal lines 36 and the plurality of gate lines GL can be formed simultaneously in one patterning process, which is conducive to simplifying the manufacturing process of the display panel 100. Moreover, since the transmission signal lines 36 extend along the first direction X, by arranging the transmission signal lines 36 in the same layer as the gate lines GL, the transmission signal lines 36 can be prevented from being short-circuited with the control signal lines 33, the cascade input signal lines 34, the cascade display reset signal lines 35, and the like extending along the second direction Y, and the display panel 100 can also be prevented from being increased in thickness and the manufacturing process of the display panel 100 from being increased due to the separate formation of the transmission signal lines 36.

[0403] Here, the type of the plurality of transmission signal lines 36 can include various types, which can be selected and arranged according to actual needs.

[0404] In some examples, as shown in Figures 9a to 9g The gate drive circuit 3 can further include a first voltage signal line 36a, a second voltage signal line 36b, and a third voltage signal line 36c.

[0405] For example, as shown in Figure 9a The first voltage signal line 36a can be electrically connected to the first voltage signal end VDD of the two-stage shift register 31.

[0406] Since each of the anti-leakage circuits 3102 in the two-stage shift register 31 is electrically connected to the first voltage signal end VDD, the first voltage signal line 36a can be electrically connected to the anti-leakage circuits 3102 in the two-stage shift register 31. During the operation of each anti-leakage circuit 3102, the first voltage signal can be transmitted to the corresponding anti-leakage circuit 3102 through the first voltage signal line 36a.

[0407] For example, as shown in Figures 9a to 9f and Figure 12 The second voltage signal line 36b can be electrically connected to the second voltage signal end VGL1 of the two-stage shift register 31.

[0408] Since the control circuit 3104, the first reset circuit 3105, the second reset circuit 3106, the third reset circuit 3107, the fourth reset circuit 3108, and the fifth reset circuit 3109 in the two-stage shift register 31 are electrically connected to the second voltage signal line 36b, the second voltage signal line 36b can be electrically connected to the control circuit 3104 and each reset circuit in the two-stage shift register 31. In this way, during the operation of each control circuit 3104 and each reset circuit, the second voltage signal can be transmitted to the corresponding control circuit 3104 or reset circuit through the second voltage signal line 36b.

[0409] For example, as shown in Figure 9g As shown, the third voltage signal line 36c can be electrically connected with the third voltage signal terminal VGL2 of the above-mentioned two-stage shift register 31.

[0410] Since the fourth reset circuit 3108 in the above-mentioned two-stage shift register 31 is electrically connected with the third voltage signal terminal VGL2, the third voltage signal line 36c can be electrically connected with the fourth reset circuit 3108 in the two-stage shift register 31. During the operation of each fourth reset circuit 3108, the third voltage signal can be transmitted to the corresponding fourth reset circuit 3108 through the third voltage signal line 36c.

[0411] Based on this, the above-mentioned two-stage shift register 31 can share at least one of the first voltage signal line 36a, the second voltage signal line 36b and the third voltage signal line 36c. The transmission signal line 36 can be the first voltage signal line 36a, the second voltage signal line 36b or the third voltage signal line 36c.

[0412] In addition, in the case where the gate drive circuit 3 adopts the structure as shown in Figures 9a to 9h and Figure 10 , the input signal terminal Iput in the first-stage shift register 31 and the input signal terminal Iput in the second-stage shift register 31 can be electrically connected with the twenty-first clock signal line CLK_21 in the control signal line 33. At this time, the first-stage shift register 31 and the second-stage shift register 31 can share one transmission signal line 36, and the input signal terminal Iput in the two-stage shift register 31 and the twenty-first clock signal line CLK_21 are connected so that the twenty-first clock signal line CLK_21 can transmit the start signal (i.e. the input signal) to the first input circuit 3101 or the fifth reset circuit 3109 in the corresponding shift register 31 through one transmission signal line 36.

[0413] In the case where the gate drive circuit 3 adopts the structure as shown in Figures 9a to 9h and Figure 10 , the display reset signal terminal SDT in the last four-stage shift register 31 can be electrically connected with the twenty-second clock signal line CLK_22. At this time, the shift register 31 corresponding to the first row of sub-pixel regions S1 and the shift register 31 corresponding to the second row of sub-pixels S2 in the last four-stage shift register 31 can share one transmission signal line 36, and the display reset signal terminal SDT in the two-stage shift register 31 and the twenty-second clock signal line CLK_22 are connected so that the twenty-second clock signal line CLK_22 can transmit the display reset signal to the second reset circuit 3106 in the corresponding shift register 31 through one transmission signal line 36.

[0414] In some other examples, as shown in Figures 9a to 9g As shown, the gate drive circuit can further include a plurality of node voltage transmission lines 36d located in the second gap region E. The transmission signal lines 36 can be the node voltage transmission lines 36d.

[0415] Here, the node voltage transmission lines 36d can be used to connect device groups 311 in the same stage shift register 31, or can be used to connect device groups 311 in different stage shift registers 31.

[0416] For example, as shown in FIG. 3, in the same stage shift register 31, at least two device groups 311 are electrically connected to the same node through a node voltage transmission line 36d. Figures 9a to 9g

[0417] The first input circuit 3101, the output circuit 3103, and the leakage prevention circuit 3102 in the same stage shift register 31 each include at least one device group 311.

[0418] For example, the first input circuit 3101 includes six device groups 311, the leakage prevention circuit 3102 includes one device group 311, and the output circuit 3103 includes thirteen device groups 311. The six device groups 311 included in the first input circuit 3101 are connected in parallel, and each device group 311 includes a first transistor M1 and a second transistor M2. The one device group 311 included in the leakage prevention circuit 3102 includes a third transistor M3. The thirteen device groups 311 included in the output circuit 3103 include a fourth transistor M4 in one device group 311, a first capacitor C1 in each of two parallel device groups 311, and a fifth transistor M5 in each of ten parallel device groups 311.

[0419] Since the first input circuit 3101 and the output circuit 3103 are both connected to the pull-up node Q <n>The first input circuit 3101 is electrically connected to the pull-up node Q <n>The device group 311 connected electrically, and the output circuit 3103 for the pull-up node Q <n>The group of devices 311 electrically connected, can be pulled up to the node Q <n>The first input circuit 3101 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1. The first input circuit 3101 is configured to receive an input signal IN and output a signal to the output circuit 3103. The first input circuit 3101 is configured to output a signal to the output circuit 3103 via a node voltage transmission line 36a.

[0420] For example, the second electrode of the second transistor M2 included in the sixth device group 311 of the first input circuit 3101, the control electrode of the third transistor M3 included in one device group 311 of the leakage prevention circuit 3102, and the control electrode of the fourth transistor M4, the control electrode of the fifth transistor M5, the first terminal of the first capacitor C1 included in the thirteen device groups 311 of the output circuit 3103 can be connected to the same node voltage transmission line 36d and the pull-up node Q <n>Electrical connection.

[0421] Of course, in the same stage shift register 31, the control circuit 3104 for the pull-up node Q <n>The device group 311 electrically connected, the first reset circuit 3105 in the node Q <n>The device group 311 electrically connected, the second reset circuit 3106 in the node Q <n>The device group 311 connected electrically and the third reset circuit 3107 for the pull-up node Q <n>The group of devices 311 electrically connected, also to the pull-up node Q <n>The electrical connection.

[0422] Since the first input circuit 3101 and the leakage prevention circuit 3102 are both connected to the leakage prevention node OFF <n>The first input circuit 3101 is electrically connected to the anti-leakage node OFF <n>The device group 311 connected electrically, and the leakage prevention circuit 3102 for the leakage prevention node OFF <n>The device group 311 electrically connected can be connected to the anti-creeping node OFF through the same node voltage transmission line 36d <n>Electrical connection.

[0423] For example, the first terminal of the second transistor M2 in the six device groups 311 included in the first input circuit 3101 and the second terminal of the third transistor M3 in one device group 311 included in the leakage protection circuit 3102 can be connected to the leakage protection node OFF through the same node voltage transmission line 36d. <n>Electrically connected.

[0424] Of course, in the same stage shift register 31, the first reset circuit 3105 in the first reset circuit 3105 for the anti-leakage node OFF <n>The device group 311 electrically connected, the second reset circuit 3106 for preventing electric leakage node OFF <n>The device group 311 connected electrically and the third reset circuit 3107 in the device group 311 for connection with the anti-creeping node OFF <n>The group of devices 311 electrically connected, also to the anti-leakage node OFF <n>Electrical connection.

[0425] As shown in FIG. 1, the two-stage shift register 31 is electrically connected with the sub-pixels 2 located in the first row of sub-pixel regions S1 and the sub-pixels 2 located in the second row of sub-pixel regions S2. Figure 9a As shown in FIG. 1, at least two device groups 311 in the two-stage shift register 31 are electrically connected with the same node through a node voltage transmission line 36d.

[0426] As shown in FIG. 1, the gate driving circuit 3 adopts the structure as shown in FIG. 1, and one blanking input circuit 32 is electrically connected with the above-mentioned two-stage shift register 31. Figures 9a to 9h

[0427] As shown in FIG. 1, the selection control circuit 3201, the second input circuit 3202 and the two transmission circuits 3203 in the blanking input circuit 32 each include at least one device group 311. Each device group 311 is located in the region between the adjacent two sub-pixels 2 in the row of sub-pixels 2 where the corresponding shift register 31 is located.

[0428] For example, as shown in FIG. 1, the selection control circuit 3201 can include two device groups 311. One device group 311 includes the twenty-first transistor M21, the twenty-second transistor M22 and the twenty-third transistor M23, and is located in the region between the adjacent two sub-pixels 2 in the first row of sub-pixel regions S1. The other device group 311 includes the third capacitor C3, and is located in the region between the adjacent two sub-pixels 2 in the second row of sub-pixel regions S1. Figure 9a For example, as shown in FIG. 1, the second input circuit 3202 can include one device group 311. The device group 311 includes the twenty-fourth transistor M4, and is located in the region between the adjacent two sub-pixels 2 in the first row of sub-pixel regions S1.

[0429] Figure 9a For example, as shown in FIG. 1, each of the above-mentioned two transmission circuits 3203 includes one device group 311. The device group 311 includes the twenty-fifth transistor M25 and the twenty-sixth transistor M26. The device group 311 included in one transmission circuit 3203 is located in the region between the adjacent two sub-pixels 2 in the first row of sub-pixel regions S1. The device group 311 included in the other transmission circuit 3203 is located in the region between the adjacent two sub-pixels 2 in the second row of sub-pixel regions S1.

[0430] Figure 9a

[0431] ​​​​Since the second input circuit 3202 and the two transmission circuits 3203 are electrically connected with the second blanking node N, the device group 311 in the second input circuit 3202 for electrical connection with the second blanking node N and the device group 311 in the two transmission circuits 3203 for electrical connection with the second blanking node N can be electrically connected with the second blanking node N through the same node voltage transmission line 36d.

[0432] For example, the second electrode of the twenty-fourth transistor M24 in the device group 311 included in the second input circuit 3202 and the first electrode of the twenty-fifth transistor M25 in the device group included in the two transmission circuits 3203 can be electrically connected with the second blanking node N through the same node voltage transmission line 36d.

[0433] In yet some examples, as shown in Figure 10 The gate drive circuit 3 can further include an input signal connection line 36e located in the second gap region E and electrically connected with the first sub-input signal line 341 and the second sub-input signal line 342. The transmission signal line 36 can be the input signal connection line 36e.

[0434] For example, as shown in Figure 10 In the different stage shift registers 31, the device groups 311 with the same structure can be located in the same first gap region D so as to reduce the difficulty of layout design of the display panel 100.

[0435] For example, as shown in Figure 10 In the different stage shift registers 31, the device groups 311 including the first input circuit 3101 (including the first transistor M1) are located in the same first gap region D. In addition, in the different stage shift registers 31, the device groups 311 including the output circuit 3103 (including the fourth transistor M4) are located in the same first gap region D. The first gap region D where the first input circuit 3101 is located and the first gap region D where the output circuit 3103 is located in the different stage shift registers 31 are not the same.

[0436] Based on this, for example, as shown in Figure 10 In the one cascade input signal line 34, the first sub-input signal line 341 can be electrically connected with the shift signal end CR of the output circuit 3103 in the one stage shift register 31, and the second sub-input signal line 342 can be electrically connected with the shift signal end CR of the output circuit 3103 in the other stage shift register 31. <n>The second sub-input signal line 342 can be electrically connected with the input signal end Iput of the first input circuit 3101 in the other stage of the shift register 31, and located in the same first gap region D with the first input circuit 3101. Wherein, the first gap region D where the first input circuit 3101 is located and the first gap region D where the first sub-input signal line 341 is located are not the same, thus, the input signal connection line 36e can be arranged to connect the first sub-input signal line 341 and the second sub-input signal line 342 located in different first gap regions D.

[0437] Here, since the shift signal end CR <n>The input signal line 36e is electrically connected to the input signal terminals Iput of the (N+2)th level shift register 31 (e.g., corresponding to the first row sub-pixel region S1) and the (N+3)th level shift register 31 (e.g., corresponding to the second row sub-pixel region S2). Therefore, the input signal connection line 36e can be set within the second gap region E, allowing the two levels of shift registers 31 to share a single input signal connection line 36e, thus achieving electrical connection with the Nth level shift register 31. Furthermore, the two levels of shift registers 31 can also share a single second sub-input signal line 342.

[0438] For example, such as Figure 10 As shown, for the output circuit 3103 in the first-stage shift register 31, the first input circuit 3101 in the third-stage shift register 31, and the first input circuit 3101 in the fourth-stage shift register 31, the first sub-input signal line 341 can be connected to the shift signal terminal CR of the output circuit 3103. <1> Electrically connected, the second sub-input signal line 342 can be located within the same first gap region D as the two first input circuits 3101, and electrically connected to the input signal terminals Iput of the two first input circuits 3101. The input signal connection line 36e can be located within the second gap region E between the third-stage shift register 31 and the fourth-stage shift register 31, and electrically connected to both the first sub-input signal line 341 and the second sub-input signal line 342. This enables the two-stage shift register 31 to share the same input signal connection line 36e.

[0439] In some other examples, such as Figure 10 As shown, at least one cascaded display reset signal line 35 includes a first sub-display reset signal line 351 and a second sub-display reset signal line 352 located in different first gap regions D. The gate drive circuit 3 may further include a display reset connection line 36f located in the second gap region E and electrically connected to the first sub-display reset signal line 351 and the second sub-display reset signal line 352. The transmission signal line 36 may be the display reset connection line 36f.

[0440] For example, in different levels of shift registers 31, the device groups 311 with the same structure can be located in the same first gap region D, so as to reduce the difficulty of the layout design of the display panel 100.

[0441] For example, in the different stage shift register 31, the device group 311 including the first input circuit 3101 (including the first transistor M1) is located in the same first gap region D. For another example, in the different stage shift register 31, the device group 311 of the second reset circuit 3106 (including the thirteenth transistor M13 and the fourteenth transistor M14) is located in the same first gap region D. Wherein, in the different stage shift register 31, the first gap region D where the output circuit 3103 is located and the first gap region D where the second reset circuit 3106 is located are not the same.

[0442] Based on this, for example, as shown in Figure 10 In a cascade display reset signal line 35, the first sub-display reset signal line 351 can be connected to the shift signal end CR of the output circuit 3103 in the first stage shift register 31. <n>The second sub-display reset signal line 352 is electrically connected with the display reset signal end STD of the second reset circuit 3106 in the other stage of the shift register 31, and is located in the same first gap region D as the second reset circuit 3106. The first gap region D where the output circuit 3103 is located is different from the first gap region D where the first sub-display reset signal line 351 is located, and thus a display reset connection line 36f can be arranged to connect the first sub-display reset signal line 351 and the second sub-display reset signal line 352 located in different first gap regions D.

[0443] Here, the shift signal end CR of the N+4th stage of the shift register 31 is electrically connected with the display reset signal end STD of the second reset circuit 3106 in the other stage of the shift register 31, and is located in the same first gap region D as the second reset circuit 3106. <n>The display reset signal line 36f is electrically connected to the STD terminal of the Nth-level shift register 31 (e.g., corresponding to the first row sub-pixel region S1) and the N+1th-level shift register 31 (e.g., corresponding to the second row sub-pixel region S2). Therefore, the display reset connection line 36f can be set within the second gap region E, allowing the two shift registers 31 to share a single display reset connection line 36f, thus achieving electrical connection with the N+4th-level shift register 31. Furthermore, the two shift registers 31 can also share a single second sub-display reset signal line 352.

[0444] For example, such as Figure 10 As shown, for the output circuit 3103 in the fifth-stage shift register 31, the second reset circuit 3106 in the first-stage shift register 31, and the second reset circuit 3106 in the second-stage shift register 31, the first sub-display reset signal line 351 can be located in the same first gap region D as the output circuit 3103, and connected to the shift signal terminal CR of the output circuit 3103. <n>The second sub display reset signal line 352 can be electrically connected with the two second reset circuits 3106 in the same first gap region D, and the display reset signal end STD of the two second reset circuits 3106. The display reset connection line 36f can be located in the second gap region E between the first stage shift register 31 and the second stage shift register 31, and electrically connected with the first sub display reset signal line 351 and the second sub display reset signal line 352. In this way, the two stage shift registers 31 share the same display reset connection line 36f.

[0445] In some embodiments, as shown in Figures 9a-9h and Figure 13 The pixel driving circuit 21 can further include a first sensing signal line 211 located in the third gap region F and extending along the first direction X. The first sensing signal line 211 can be electrically connected with the sensing signal end Sense in the pixel driving circuit 21, and electrically connected with the sensing transistor T3 in the pixel driving circuit 21 through the sensing signal end Sense.

[0446] In some examples, as shown in Figures 9a-9h In the case where the plurality of sub-pixels 2 included in the display panel 100 are divided into a plurality of pixel units 2a, and one pixel unit 2a includes at least three sub-pixels 2 arranged in sequence along the first direction X, among the sub-pixels 2 located in the second row sub-pixel region S2 and the third row sub-pixel region S3, two pixel units 2a opposite along the second direction Y share the first sensing signal line 211.

[0447] For example, the two pixel units 2a opposite along the second direction Y can be electrically connected with the same first sensing signal line 211.

[0448] Since one row of pixel units 2a includes a plurality of pixel units 2a, the number of two pixel units 2a opposite along the second direction Y among the sub-pixels 2 located in the second row sub-pixel region S2 and the third row sub-pixel region S3 can be multiple, and the number of the first sensing signal lines 211 located in the third gap region F can also be multiple.

[0449] The two pixel units 2a opposite along the second direction Y share the first sensing signal line 211, that is, the sensing transistors T3 of the at least six sub-pixels 2 included in the two pixel units 2a can be electrically connected with the same first sensing signal line 211.

[0450] By arranging the first sensing signal line 211 in the third gap region F, the extending direction of the first sensing signal line 211 is the same as the arrangement direction of the plurality of sub-pixels 2 included in each pixel unit 2a, which can make the pixel driving circuit 21 in the plurality of sub-pixels 2 electrically connected with the same first sensing signal line 211, reduce the number of first sensing signal lines 211, and further simplify the structure of the pixel driving circuit 21.

[0451] By arranging the two pixel units 2a in the sub-pixels 2 in the second row sub-pixel region S2 and the third row sub-pixel region S3, which are opposite in the second direction Y, to share the first sensing signal line 211, not only can the spacing between the two pixel units 2a opposite in the second direction Y be reduced, the size of the third gap region F in the second direction Y can be reduced, but also the space ratio of the pixel driving circuit 21 can be reduced. In this way, the minimum line width spacing of the sub-pixels 2 can be avoided, which is beneficial to arranging more sub-pixels 2 to increase the PPI of the display panel 100, or increasing the area of the sub-pixel light emitting region Sb to increase the aperture ratio of the display panel 100.

[0452] In some examples, as shown in Figures 9a-9h and Figure 13 , the pixel driving circuit 21 can further include a second sensing signal line 212 extending in the second direction Y. The second sensing signal line 212 is arranged in the region between the two adjacent columns of sub-pixels 2 in the two pixel units 2a opposite in the second direction Y.

[0453] For example, as shown in Figures 9a-9h and Figure 13 , taking the example that the pixel unit 2a includes four sub-pixels 2, the four sub-pixels 2 arranged in the first direction X in sequence can be referred to as a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel. The data line DL electrically connected with the pixel driving circuit 21 in the first sub-pixel and the data line DL electrically connected with the pixel driving circuit 21 in the second sub-pixel can be arranged in the region between the first sub-pixel and the second sub-pixel. The data line DL electrically connected with the pixel driving circuit 21 in the third sub-pixel and the data line DL electrically connected with the pixel driving circuit 21 in the fourth sub-pixel can be arranged in the region between the third sub-pixel and the fourth sub-pixel. The second sensing signal line 212 electrically connected with the first sensing signal line 211 can be arranged in the region between the second sub-pixel and the third sub-pixel. The data line DL and the second sensing signal line 212 are arranged in the above manner, which is beneficial to reasonably utilizing the space of the display panel 100 and reducing the complexity of the circuit.

[0454] For example, as shown in Figure 13 , the first sensing signal line 211 is electrically connected with the second sensing signal line 212 through the via G. The second sensing signal line 212 is further electrically connected with the external sensing circuit, for example.

[0455] That is, the first sensing signal line 211 and the second sensing signal line 212 are connected alternately, so as to realize the electrical connection between the pixel driving circuit 21 and the external sensing circuit. In this way, the layout design of the display panel 100 can be simplified, and the space proportion of the pixel driving circuit 21 can be reduced.

[0456] For example, one second sensing signal line 212 can be located in the region between the adjacent yield sub-pixels 2 in one column of pixel units 2a. One column of pixel units 2a includes a plurality of two pixel units 2a opposite in the second direction Y, so that one second sensing signal line 212 can be electrically connected with a plurality of first sensing signal lines 211.

[0457] For example, in the process of the pixel driving circuit 21 working, in the reset stage in the display period, the reset signal can be transmitted to the sensing transistor T3 through the second sensing signal line 212, the first sensing signal line 211 and the sensing signal terminal Sense in sequence; in the first stage in the blanking period, the reset signal can be transmitted to the sensing transistor T3 through the second sensing signal line 212, the first sensing signal line 211 and the sensing signal terminal Sense in sequence; in the second stage in the blanking period, in the process of the driving transistor T2 charging the second node S, the driving transistor T2 can also charge the first sensing signal line 211 and the second sensing signal line 212 through the sensing transistor T3 and the sensing signal terminal Sense in sequence, and in the process of voltage sampling, the second sensing signal line 212 can be voltage sampled, and the voltage sampling result can be transmitted to the external sensing circuit.

[0458] In some examples, as shown in Figure 13 The second sensing signal line 212 is made of the same material as the above-mentioned plurality of data lines GL and is arranged in the same layer.

[0459] In this way, the second sensing signal line 212 and the plurality of data lines DL can be prepared simultaneously in one patterning process, which is beneficial to simplify the preparation process of the display panel 100.

[0460] In some examples, as shown in Figure 13 and Figure 14 The sub-pixel 2 further includes an optical shielding layer 23 arranged on the side of the pixel driving circuit 21 close to the substrate 1.

[0461] The material of the above-mentioned optical shielding layer 23 is, for example, an optical shielding material. The optical shielding material is, for example, a black matrix material or a metal material.

[0462] The active layer of the switch transistor T1 and the driving transistor T2 is located in the projection range of the light shielding layer 23 on the substrate 1. In this way, the light shielding layer 23 can shield the light incident from the substrate 1 to the active layer of the switch transistor T1 and the driving transistor T2, so as to avoid affecting the performance of the switch transistor T1 and the driving transistor T2.

[0463] Figure 14 The light shielding layer 23 is taken as an example of a metal material. The light shielding layer 23 can be electrically connected with the source-drain conductive layer in the switch transistor T1, the driving transistor T2 and the sensing transistor T3, so as to form a structure similar to a double-channel structure, and improve the electrical performance of the transistor. The source-drain conductive layer includes the first and second poles of each transistor, and a plurality of data lines DL and the like.

[0464] The structure of the light shielding layer 23 can be a single-layer structure, or a multi-layer structure formed by a plurality of thin films stacked in sequence.

[0465] For example, as shown in FIG. 2, the first sensing signal 211 can be formed by a material same as that of the light shielding layer 23 and in the same layer. Figure 14 In this way, the first sensing signal 211 and the light shielding layer 23 can be simultaneously prepared in one patterning process, which is beneficial to simplify the preparation process of the display panel 100.

[0466] The light emitting device 22 includes an anode, a light emitting layer and a cathode layer which are sequentially stacked. The anode is electrically connected with the second pole of the driving transistor T2.

[0467] For example, at least one of the anode and the cathode is a light-transmitting layer. That is, at least one of the anode and the cathode can be prepared by using a conductive material with high light transmittance.

[0468] For example, the conductive material with high light transmittance can be indium tin oxide (ITO).

[0469] In the case where the anode is a light-transmitting layer, the light emitted by the light emitting device 22 can be emitted in the direction of the substrate 1, and in this case, the display panel 100 can be a bottom emission display panel. In the case where the cathode is a light-transmitting layer, the light emitted by the light emitting device 22 can be emitted in the direction away from the substrate 1, and in this case, the display panel 100 can be a top emission display panel. In the case where both the anode and the cathode are light-transmitting layers, the display panel 100 can emit light from both sides.

[0470]

[0471] ​The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> ​< / n> ​< / n> < / n> < / n> < / n> < / n> ​​< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a plurality of sub-pixels arranged on one side of the substrate; the plurality of sub-pixels are arranged into multiple rows along a first direction and multiple columns along a second direction; each sub-pixel comprises a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit; and a gate driving circuit located on the same side of the substrate as the plurality of sub-pixels; the gate driving circuit comprises a plurality of cascaded shift registers, one shift register is electrically connected to a plurality of pixel driving circuits in one row of sub-pixels; the shift register comprises a plurality of device groups, one device group is located in a region between two adjacent sub-pixels in a corresponding row of sub-pixels; each device group comprises at least one transistor and / or at least one capacitor; wherein the gate driving circuit further comprises a plurality of cascaded input signal lines and a plurality of cascaded display reset signal lines; the cascaded input signal lines are configured to connect a shift signal terminal of one shift register and an input signal terminal of another shift register; the cascaded display reset signal lines are configured to connect a shift signal terminal of one shift register and a display reset signal terminal of another shift register; the shift signal terminal connected to the cascaded input signal lines is different from the shift signal terminal connected to the cascaded display reset signal lines; the display panel has a plurality of sub-pixel regions for arranging the plurality of sub-pixels, and a first gap region between two adjacent columns of sub-pixel regions; the cascaded display reset signal lines and the cascaded input signal lines are both arranged in the first gap region, and are arranged in different first gap regions; no device group is arranged in the first gap region in which the cascaded display reset signal lines or the cascaded input signal lines are arranged; each sub-pixel region comprises a sub-pixel circuit region arranged along the second direction and used for arranging a corresponding pixel driving circuit, and a sub-pixel light-emitting region used for arranging a corresponding light-emitting device; along the second direction, any three adjacent rows of sub-pixel regions are a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions, respectively; a region between the first row of sub-pixel regions and the second row of sub-pixel regions is a second gap region, and a region between the second row of sub-pixel regions and the third row of sub-pixel regions is a third gap region; wherein in the first row of sub-pixel regions and the second row of sub-pixel regions, the sub-pixel light-emitting regions are closer to the second gap region than the sub-pixel circuit regions; in the second row of sub-pixel regions and the third row of sub-pixel regions, the sub-pixel circuit regions are closer to the third gap region than the sub-pixel light-emitting regions.

2. The display panel of claim 1, wherein, the plurality of cascaded input signal lines are divided into a plurality of groups, each group of cascaded input signal lines comprises at least one cascaded input signal line, and at least one group of cascaded input signal lines is arranged in one first gap region; the plurality of cascaded display reset signal lines are divided into a plurality of groups, each group of cascaded display reset signal lines comprises at least one cascaded display reset signal line, and at least one group of cascaded display reset signal lines is arranged in one first gap region.

3. The display panel of claim 2, wherein, At least one column of sub-pixels is arranged between two groups of cascaded input signal lines located in different first gap regions and adjacent to each other; At least one column of sub-pixels is arranged between two groups of cascaded display reset signal lines located in different first gap regions and adjacent to each other.

4. The display panel of claim 2, wherein, A plurality of groups of cascaded input signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two groups of cascaded input signal lines located in the same first gap region and adjacent to each other; A plurality of groups of cascaded display reset signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two groups of cascaded display reset signal lines located in the same first gap region and adjacent to each other.

5. The display panel of claim 1, wherein, Further comprising: a plurality of data lines extending in the second direction; one data line is electrically connected with a plurality of pixel driving circuits in one column of sub-pixels; The plurality of cascaded input signal lines, the plurality of cascaded display reset signal lines and the plurality of data lines are made of the same material and arranged in the same layer.

6. The display panel of claim 1, wherein, The plurality of sub-pixels are divided into a plurality of pixel units; one pixel unit comprises at least three sub-pixels arranged in the first direction in sequence; the plurality of pixel units are arranged into a plurality of rows in the first direction and a plurality of columns in the second direction; The region between any two adjacent columns of pixel units is the first gap region.

7. The display panel of claim 1, wherein, The gate drive circuit further comprises a plurality of transmission signal lines located in the second gap region and extending in the first direction; Two stages of shift registers electrically connected with sub-pixels located in the first row of sub-pixel regions and sub-pixels located in the second row of sub-pixel regions share at least one transmission signal line of the plurality of transmission signal lines.

8. The display panel of claim 7, wherein, The gate drive circuit further comprises: a first voltage signal line electrically connected with a first voltage signal end of the two stages of shift registers; a second voltage signal line electrically connected with a second voltage signal end of the two stages of shift registers; and a third voltage signal line electrically connected with a third voltage signal end of the two stages of shift registers; The transmission signal line is the first voltage signal line, the second voltage signal line or the third voltage signal line.

9. The display panel of claim 7, wherein, At least one cascaded input signal line comprises a first sub-input signal line and a second sub-input signal line located in different first gap regions; The gate drive circuit further comprises an input signal connection line located in the second gap region and electrically connected with the first sub-input signal line and the second sub-input signal line; The transmission signal line is the input signal connection line; and / or At least one cascaded display reset signal line comprises a first sub-display reset signal line and a second sub-display reset signal line located in different first gap regions; The gate drive circuit further comprises a display reset connection line located in the second gap region and electrically connected with the first sub-display reset signal line and the second sub-display reset signal line; The transmission signal line is the display reset connection line.

10. The display panel of claim 7, wherein, The gate drive circuit further comprises a plurality of node voltage transmission lines located in the second gap region; In the same stage of shift registers, at least two groups of devices are electrically connected with the same node through one node voltage transmission line; The two-stage shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line; The transmission signal line is the node voltage transmission line.

11. The display panel of claim 10, wherein, The shift register comprises: The first input circuit is electrically connected to the input signal end, the pull-up node and the anti-leakage node; the first input circuit is configured to, in a display period of a frame display stage, transmit the input signal received at the input signal end to the pull-up node in response to the input signal received at the input signal end; The output circuit is electrically connected to the pull-up node, the first clock signal end and the first output signal end; the output circuit is configured to, in a display period of a frame display stage, transmit the first clock signal received at the first clock signal end to the first output signal end under the control of the voltage of the pull-up node; and, The anti-leakage circuit is electrically connected to the pull-up node, the first voltage signal end and the anti-leakage node; the anti-leakage circuit is configured to, under the control of the voltage of the pull-up node, transmit the first voltage signal received at the first voltage signal end to the anti-leakage node to prevent the pull-up node from leaking electricity; The first input circuit, the output circuit and the anti-leakage circuit each comprise at least one device group; The device group in the first input circuit for electrical connection with the pull-up node and the device group in the output circuit for electrical connection with the pull-up node are electrically connected to the pull-up node through a node voltage transmission line; The device group in the first input circuit for electrical connection with the anti-leakage node and the device group in the anti-leakage circuit for electrical connection with the anti-leakage node are electrically connected to the anti-leakage node through a node voltage transmission line.

12. The display panel of claim 11, wherein, The gate drive circuit further comprises: a plurality of blanking input circuits; one blanking input circuit is electrically connected to at least two adjacent shift registers; The blanking input circuit is configured to, in a blanking period of a frame display stage, control the corresponding shift register to input a blanking control signal to the pixel drive circuit of the corresponding row, so that the pixel drive circuit acquires a sensing signal; The blanking input circuit comprises: The selection control circuit is electrically connected to the selection control signal end, the shift signal end, the second voltage signal end and the first blanking node; the selection control circuit is configured to, under the control of the selection control signal transmitted by the selection control signal end, transmit the shift signal received at the shift signal end to the first blanking node; The second input circuit is electrically connected to the first blanking node, the second blanking node and the second clock signal end or the first voltage signal end; the second input circuit is configured to, under the control of the voltage of the first blanking node, transmit the second clock signal received at the second clock signal end or the first voltage signal received at the first voltage signal end to the second blanking node; and, At least two transmission circuits, one of which is electrically connected with the pull-up node of the first-stage shift register; the transmission circuit is also electrically connected with the second blanking node and the second clock signal terminal; the transmission circuit is configured to, under the control of the second clock signal transmitted by the second clock signal terminal, transmit the second clock signal or the first voltage signal received at the second blanking node to the pull-up node; The second input circuit and the transmission circuit each include at least one device group; each device group included in the second input circuit and the transmission circuit is located in a row of sub-pixels where the corresponding shift register is located, in a region between two adjacent sub-pixels; The device group in the second input circuit for electrical connection with the second blanking node and the device group in the at least two transmission circuits for electrical connection with the second blanking node are electrically connected with the second blanking node through a node voltage transmission line.

13. The display panel of claim 7, wherein, Further comprising: A plurality of gate lines extending in the first direction; one gate line is electrically connected with a plurality of pixel driving circuits in a row of sub-pixels; The plurality of transmission signal lines and the plurality of gate lines are of the same material and are arranged in the same layer.

14. The display panel of claim 1, wherein, The pixel driving circuit includes a first sensing signal line located in the third gap region and extending in the first direction; In the case where the plurality of sub-pixels are divided into a plurality of pixel units, and one pixel unit includes at least three sub-pixels arranged in the first direction in sequence, Among the sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions, two pixel units opposite in the second direction share the first sensing signal line.

15. The display panel of claim 14, wherein, The sub-pixel further includes an optical shielding layer arranged on the side of the pixel driving circuit close to the substrate; The first sensing signal line and the optical shielding layer are of the same material and are arranged in the same layer.

16. The display panel of claim 14, wherein, The pixel driving circuit further includes a second sensing signal line extending in the second direction; The second sensing signal line is located in a region between two adjacent columns of sub-pixels in the two pixel units opposite in the second direction; The first sensing signal line is electrically connected with the second sensing signal line through a via hole.

17. The display panel of claim 16, wherein, In the case where the display panel further includes a plurality of data lines, The second sensing signal line and the plurality of data lines are of the same material and are arranged in the same layer.

18. The display panel of any one of claims 1-6, wherein, The gate drive circuit further includes a plurality of control signal lines extending in the second direction; at least a part of the plurality of control signal lines is electrically connected with the first-stage shift register; the shift register is configured to, under the control of at least a part of the control signal lines electrically connected with the shift register, provide an output signal to a plurality of pixel driving circuits in a corresponding row.

19. The display panel of claim 18, wherein, At least one control signal line in the plurality of control signal lines is located in the first gap region.

20. A display device comprising: Comprise: The display panel according to any one of claims 1-19. The display panel according to any one of claims 1-19.

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